coreboot May 2010

coreboot@coreboot.org

59 participants
300 discussions

[patch] DDR3 support of AMD Family 10
by Bao, Zheng 11 Aug '10

11 Aug '10

DDR3 supporting is added. More testing need to be done. But we don't have boards that cover all the options. Features that have been tested. The socket AM3 and ASB2. Single rank and double rank DIMM. Features that need to be tested. Socket C32 and G34, I don't know if it is DDR3. Quad rank. Registered DIMM, which is quite complicated and I am not confident about. The tilapia board is the demo that shows the way to use DDR3. It is quite close to mahogany, except tilapia uses AM3. For a new board, just specify the socket type in Kconfig the devicetree.cb. Signed-off-by: Zheng Bao <zheng.bao(a)amd.com>

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#154: Flashing BIOSes from Fujitsu/Siemens is not supported
by coreboot 25 Jul '10

25 Jul '10

#154: Flashing BIOSes from Fujitsu/Siemens is not supported ---------------------------------------+------------------------------------ Reporter: johannesobermayr@… | Owner: carldani Type: enhancement | Status: new Priority: major | Milestone: Component: flashrom | Version: Keywords: | Dependencies: Patchstatus: there is no patch | ---------------------------------------+------------------------------------ As summary says I cannot flash BIOSes provided by Fujitsu/Siemens. You can see BIOS architecture from Fujitsu/Siemens if you download for example this BIOS package (for D1326): http://dl- extern3.treiberupdate.de/download2/123525.EXE I also could not find a suitable converter... -- Ticket URL: <http://tracker.coreboot.org/trac/coreboot/ticket/154> coreboot <http://www.coreboot.org/>

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#134: flashrom crashes acer aspire one laptop
by coreboot 23 Jul '10

23 Jul '10

#134: flashrom crashes acer aspire one laptop -----------------------------------------------------------+---------------- Reporter: Timo Juhani Lindfors <timo.lindfors@…> | Owner: somebody Type: defect | Status: new Priority: minor | Milestone: Component: flashrom | Version: v2 Keywords: aspire laptop | Dependencies: Patchstatus: there is no patch | -----------------------------------------------------------+---------------- I ran the "flashrom" command on my acer aspire one laptop. The display turned black and the system did not respond to even sysrq after that. (Fortunately the system boots after powercycling.) This is debian stable with flashrom package that has version "0.0+r3397-1". -- Ticket URL: <http://tracker.coreboot.org/trac/coreboot/ticket/134> coreboot <http://www.coreboot.org/>

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[RFC] Network console for coreboot
by Rudolf Marek 16 Jul '10

16 Jul '10

-----BEGIN PGP SIGNED MESSAGE----- Hash: SHA1 Hello all, Maybe this story should be for coreboot blog ;) I have a very short serial cable and therefore I had to always connect the coreboot machine to the notebook which is bit annoying if I use my workstation for development. You may ask how send packets if we have no RAM? Good question so far I know two answers: 1) use some card with internal SRAM I know only one... RTL 8029AS which is a NE 2000 compatible PCI card. It has like 16kb SRAM which is only accessible through PIO. 2) Use some other PCI card with a memory space for packet descriptors, maybe the sideport memory could work - this is just an idea not tested Rest was relatively simple. I took the PCI NE2000 driver from gpxe sources, made it bit more simple (b.c) all routines takes as an argument the IO address of the card. How it works: 1) before uart init call net_init() which just setup the BAR0 on card to IOport 0xe00 enable the IO decoding of the card 2) in uart_tx_byte write the byte to card SRAM 3) after the print is done, construct the packet, with fixed MAC and fixed IP, variable length. The IP payload is UDP packet (src port 6667 dest 6666) The UDP payload is our text which is already there. Thefore invoke the transmit jut to transmit it ;) 4) If the PCI slot with the card is bellow some bridge, then situation does not differ too much. In my case, the first part of the boot is the card on BUS0 but later the PCI slot bus is moved to separate bus (chipset has some bit for this). Because the bridge has subtractive decoding, the output still works regardless of the IO forwarding range. The only problem is if coreboot wants to write new address to BAR0. I solved that by simple hack - I did small PCI driver which just tells coreboot the card has fixed and assigned IO resource. Here is how it looks in linux: 00:13.1 PCI bridge: VIA Technologies, Inc. VT8237A PCI to PCI Bridge (prog-if 01 [Subtractive decode]) Bus: primary=00, secondary=05, subordinate=05, sec-latency=0 I/O behind bridge: 00001000-00001fff Memory behind bridge: f1200000-f12fffff 05:06.0 Ethernet controller: Realtek Semiconductor Co., Ltd. RTL-8029(AS) Flags: medium devsel, IRQ 16 I/O ports at 0e00 [size=32] Kernel driver in use: ne2k-pci Kernel modules: ne2k-pci And here how it looks if I catch the output with netcat: $nc -u -l -p 6666 TEST coreboot-4.0-r5577M Sun May 30 20:21:52 CEST 2010 starting... now booting... INIT detected from --- { APICID = 00 NODEID = 00 COREID = 00} --- Issuing SOFT_RESET... soft reset TEST coreboot-4.0-r5577M Sun May 30 20:21:52 CEST 2010 starting... now booting... Enabling routing table for node 00 done. Enabling UP settings Disabling read/write/fill probes for UP... done. coherent_ht_finalize done <---- snip ----> Post relocation: addr: 0x00000000000eca00 memsz: 0x0000000000013600 filesz: 0x0000000000009a8e using LZMA [ 0x00000000000eca00, 0000000000100000, 0x0000000000100000) <- 00000000fff97c70 dest 000eca00, end 00100000, bouncebuffer 1def0000 Loaded segments Jumping to boot code at fdfae entry = 0x000fdfae lb_start = 0x00100000 lb_size = 0x00080000 adjust = 0x1de70000 buffer = 0x1def0000 elf_boot_notes = 0x00118ab0 adjusted_boot_notes = 0x1df88ab0 It goes allright through the boot. Now some questions: 5) The b.c file is from GPXE project and this particular file is under two Clause BSD license which is compatible with GPL. Can we include this or some other rewrite needs to be done? 6) SMP? I think we will need some locking ? 7) In case you are wondering where to get RTL8029AS pci card. I asked one big czech ISP and they found like 20 of this cards. If some of coreboot developers wants some I can mail it to you with a price of the mail and paypal fee. 8) Someone has free time to fix this patch to something more pretty? Thanks, Rudolf -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.10 (GNU/Linux) Comment: Using GnuPG with Mozilla - http://enigmail.mozdev.org iEYEARECAAYFAkwCvaEACgkQ3J9wPJqZRNWngQCePOCPktBDBv2VP4SDSrLxFa/N 44MAoJe+hgnp8ZJicifwfFgnZSkJw+dW =BQN9 -----END PGP SIGNATURE-----

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[PATCH] resource maps
by Myles Watson 10 Jun '10

10 Jun '10

I think there's too much duplication in the resource map code. resourcemaps.diff tries to address it by: Creating clear_resource_map() for k8 and fam10. This sets all the routing registers to a known state. Calling clear_resource_map() and then only setting the specific registers that are non-zero in board-specific code. Adding util.c for fam10, so that it can be customized for fam10. I didn't update all of the resourcemap.c files, yet. I wanted to see what the reaction would be. sublinks.diff marks that bit as not reserved for all fam10 boards, so that it can be cleared. Signed-off-by: Myles Watson <mylesgw(a)gmail.com> Thanks, Myles

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i840 coreboot challenge
by Joseph Smith 08 Jun '10

08 Jun '10

Hello, I want to propose a "coreboot challenge" to first port coreboot to the i840 chpset, second port coreboot to support a very rare i840 dual cpu board, third instead of RAMBUS (which i840 is designed for) this board uses SDRAM. I think this would be a very interesting port for coreboot. The board is a AMI Megatrends MegaDual. The user manual can be found here: http://www.ami.com/support/doc/MegaDual_mb_man.PDF I have four of these rare boards and am willing to donate three of them (one person each, less shipping costs of course) to anyone who is willing to take on this challenge. Let me know if your interested. P.S.: the first person to boot to a Linux command line gets the grand prize, a big fat cookie :-) -- Thanks, Joseph Smith Set-Top-Linux www.settoplinux.org

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SIS630ET coreboot challenge
by Keith Hui 05 Jun '10

05 Jun '10

Hi all, After hours spent yesterday, some Chipquik, one heatgun pass, and a dead board scare later, I managed to solder a PLCC socket on my TUSI-M board. SIS630ET is still on my radar, but I'm going to need some help. In the spirit of the "coreboot challenge" below, let me propose another one: Port coreboot v4 to SIS630ET, then to Asus TUSI-M. This is a challenge because most if not all of the SIS chipsets have no public documentation, and so far from reversing my factory BIOS I don't recognize any of the registers the TUSI-M factory BIOS programs, after reading what's available from coreboot v1. To be legally safe, I would like one person/team to reverse the factory BIOS of a number of 630ET boards, then produce a documentation. Then another person/team (can be myself) do the port to that documentation. And one interesting bit: I noticed a special check for "CentaurHauls" CPUID in the factory BIOS, which also uses CAR. Cheers Keith On Tue, Apr 27, 2010 at 10:17 AM, Joseph Smith <joe(a)settoplinux.org> wrote: > > > > On Tue, 27 Apr 2010 10:01:28 -0400, Keith Hui <buurin(a)gmail.com> wrote: >>>> Hello, >>>> I want to propose a "coreboot challenge" to first port coreboot to the >>>> i840 chpset, second port coreboot to support a very rare i840 dual cpu >>>> board, third instead of RAMBUS (which i840 is designed for) this board >>>> uses SDRAM. I think this would be a very interesting port for coreboot. >>>> >>>> The board is a AMI Megatrends MegaDual. The user manual can be found >>>> here: http://www.ami.com/support/doc/MegaDual_mb_man.PDF >>>> >>>> I have four of these rare boards and am willing to donate three of them >>>> (one person each, less shipping costs of course) to anyone who is >>>> willing to take on this challenge. Let me know if your interested. >>>> >> >> Sounds like some sort of reference board for workstations/servers. >> >> i840+SDRAM means this board has one or two MTHs. This is going to be > epic. >> > Yes it should be interesting :-) > >> (No I won't be able to attempt it - I still have 440BX and SIS630ET in >> my pipeline.) >> > That's OK Keith. I actually have allot of other i8xx boards that are a > higher priority than this one. I knew I was not going to be able to get to > it for a while that is why I am offering up my 3 spare boards for free so > others could hack along if they want. > > I am actually suprised no one has jumped for the oppritunity to get a free > motherboard. > > I do have a few SIS 630's kicking around so I will be looking forward to > your work on that :-) > > -- > Thanks, > Joseph Smith > Set-Top-Linux > www.settoplinux.org > >

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Nokia IP530 finally fully working
by mbertens 02 Jun '10

02 Jun '10

hi all, i was to fast on the send button, the Nokia IP530 is now finally fully working. - the four on-board NICs (22143PD) - the 2 PCMCIA-Cardbus slots - the 3 compact PCI expansion slots (with 12 NICs) I got it working with 16 ethernet controller (all 21143PD), two HDDs on the primary IDE controller and two HDD's on the secondary controller. The on-board CF slot works as master on the primary IDE controller. very nice for silent running (hihi, with those 4 fan's in the back). for the NICs i added a driver to the src/drivers/dec/21143. for the pcmcia-cardbus controller i added a driver to the src/drivers/ti/pcmcia-cardbus. these where required to get the devices proberly working. These are added as drivers so that other can use then in there configuration to. the parameters can be set in the configuration "menuconfig", "xconfig" or "gconfig". all this depends still on a patch to the 'src/arch/i386/boot/pirq_routing.c' to get the interrupt routing correct working. i will look into this to fix in the near future. I find the coreboot project a great project and i have a lot of fun working on it. and i will do so. Next on mylist is the Nokia-IP330, yes again a Nokia piece of hardware. "That's all folks" Marc

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addition to getpir
by mbertens 01 Jun '10

01 Jun '10

hi all, i make an addition to getpir, getpir works are before without any commandline parameters. when applying for example build\coreboot_ram as parameter it looks in the file for the PIRQ table prints it to stdout and shows if the checksum is correct. THis is very handy for developing a PIRQ table. Marc PS this patch was send before, but was not applied to svn.

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Selfboot error checking fix
by Myles Watson 01 Jun '10

01 Jun '10

Check the return value of ulzma, and quit instead of loading the next segment if there's an error. Size pointers 8 characters instead of 16 to beautify the common case where selfboot is loading something into memory below 4GB. Signed-off-by: Myles Watson <mylesgw(a)gmail.com> Thanks, Myles

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coreboot May 2010