March 2010 - coreboot - mail.coreboot.org

by repository service

Author: myles Date: Wed Mar 31 16:57:55 2010 New Revision: 5343 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5343 Log: Consolidate ifdefs in src/lib/cbmem.c for readability. Signed-off-by: Myles Watson <mylesgw(a)gmail.com> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/src/lib/cbmem.c Modified: trunk/src/lib/cbmem.c ============================================================================== --- trunk/src/lib/cbmem.c Wed Mar 31 16:47:43 2010 (r5342) +++ trunk/src/lib/cbmem.c Wed Mar 31 16:57:55 2010 (r5343) @@ -44,6 +44,9 @@ #ifndef __PRE_RAM__ struct cbmem_entry *bss_cbmem_toc; +#define get_cbmem_toc() bss_cbmem_toc +#else +#define get_cbmem_toc() (struct cbmem_entry *)(get_top_of_ram() - HIGH_MEMORY_SIZE) #endif /** @@ -99,11 +102,7 @@ { struct cbmem_entry *cbmem_toc; int i; -#ifdef __PRE_RAM__ - cbmem_toc = (struct cbmem_entry *)(get_top_of_ram() - HIGH_MEMORY_SIZE); -#else - cbmem_toc = bss_cbmem_toc; -#endif + cbmem_toc = get_cbmem_toc(); if (cbmem_toc == NULL) { return NULL; @@ -155,11 +154,7 @@ { struct cbmem_entry *cbmem_toc; int i; -#ifdef __PRE_RAM__ - cbmem_toc = (struct cbmem_entry *)(get_top_of_ram() - HIGH_MEMORY_SIZE); -#else - cbmem_toc = bss_cbmem_toc; -#endif + cbmem_toc = get_cbmem_toc(); if (cbmem_toc == NULL) return NULL; @@ -201,11 +196,7 @@ { struct cbmem_entry *cbmem_toc; int i; -#ifdef __PRE_RAM__ - cbmem_toc = (struct cbmem_entry *)(get_top_of_ram() - HIGH_MEMORY_SIZE); -#else - cbmem_toc = bss_cbmem_toc; -#endif + cbmem_toc = get_cbmem_toc(); if (cbmem_toc == NULL) return;

9 years, 8 months

1
0
0 0

build service results for r5341

by coreboot information

Dear coreboot readers! This is the automatic build system of coreboot. The developer "stepan" checked in revision 5341 to the coreboot repository. This caused the following changes: Change Log: This patch drops arch/i386/lib/console.c and arch/i386/lib/console_print.c and makes include/console/console.h and console/console.c usable both in __PRE_RAM__ and coreboot_ram stages. While debugging this, I removed an indirection from the e7520 ram init code (same as we did on a couple of other chipsets, removes some register pressure from romcc) Also, drop remainders of CONFIG_USE_INIT (except the one odd piece of dead code in cache_as_ram.inc) Then some ap_romstage.c fixes, at least the nvidia/l1_2pvv compiled for me with CONFIG_AP_CODE_IN_CAR set in Kconfig which it did not before. Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Myles Watson <mylesgw(a)gmail.com> Build Log: Compilation of asus:p2b-d has been fixed Compilation of asus:p2b-ds has been fixed If something broke during this checkin please be a pain in stepan's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

9 years, 8 months

1
0
0 0

[commit] r5342 - in trunk/src: console cpu/amd/car cpu/amd/dualcore cpu/amd/model_fxx cpu/amd/model_lx cpu/amd/quadcore cpu/amd/sc520 cpu/intel/microcode cpu/intel/model_106cx drivers/ati/ragexl dr...

by repository service

Author: stepan Date: Wed Mar 31 16:47:43 2010 New Revision: 5342 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5342 Log: Drop \r\n and \n\r as both print_XXX and printk now do this internally. Only some assembler files still have \r\n ... Can we move that part to C completely? Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/src/console/console.c trunk/src/cpu/amd/car/post_cache_as_ram.c trunk/src/cpu/amd/dualcore/amd_sibling.c trunk/src/cpu/amd/model_fxx/fidvid.c trunk/src/cpu/amd/model_fxx/init_cpus.c trunk/src/cpu/amd/model_lx/cpureginit.c trunk/src/cpu/amd/quadcore/amd_sibling.c trunk/src/cpu/amd/sc520/raminit.c trunk/src/cpu/intel/microcode/microcode.c trunk/src/cpu/intel/model_106cx/cache_as_ram_disable.c trunk/src/drivers/ati/ragexl/xlinit.c trunk/src/drivers/generic/debug/debug_dev.c trunk/src/drivers/i2c/adm1027/adm1027.c trunk/src/include/assert.h trunk/src/include/cpu/x86/bist.h trunk/src/lib/debug.c trunk/src/lib/generic_dump_spd.c trunk/src/lib/generic_sdram.c trunk/src/lib/ramtest.c trunk/src/mainboard/amd/dbm690t/romstage.c trunk/src/mainboard/amd/mahogany/romstage.c trunk/src/mainboard/amd/pistachio/romstage.c trunk/src/mainboard/amd/rumba/romstage.c trunk/src/mainboard/amd/serengeti_cheetah/ap_romstage.c trunk/src/mainboard/amd/serengeti_cheetah/romstage.c trunk/src/mainboard/arima/hdama/debug.c trunk/src/mainboard/arima/hdama/romstage.c trunk/src/mainboard/asus/a8n_e/romstage.c trunk/src/mainboard/asus/a8v-e_se/romstage.c trunk/src/mainboard/asus/m2v-mx_se/romstage.c trunk/src/mainboard/bcom/winnetp680/romstage.c trunk/src/mainboard/broadcom/blast/romstage.c trunk/src/mainboard/dell/s1850/debug.c trunk/src/mainboard/dell/s1850/watchdog.c trunk/src/mainboard/digitallogic/msm586seg/romstage.c trunk/src/mainboard/gigabyte/ga_2761gxdk/ap_romstage.c trunk/src/mainboard/gigabyte/ga_2761gxdk/romstage.c trunk/src/mainboard/gigabyte/m57sli/ap_romstage.c trunk/src/mainboard/gigabyte/m57sli/romstage.c trunk/src/mainboard/hp/dl145_g3/romstage.c trunk/src/mainboard/ibm/e325/romstage.c trunk/src/mainboard/ibm/e326/romstage.c trunk/src/mainboard/intel/eagleheights/debug.c trunk/src/mainboard/intel/jarrell/debug.c trunk/src/mainboard/intel/jarrell/jarrell_fixups.c trunk/src/mainboard/intel/jarrell/power_reset_check.c trunk/src/mainboard/intel/jarrell/watchdog.c trunk/src/mainboard/intel/xe7501devkit/romstage.c trunk/src/mainboard/iwill/dk8_htx/romstage.c trunk/src/mainboard/iwill/dk8s2/romstage.c trunk/src/mainboard/iwill/dk8x/romstage.c trunk/src/mainboard/jetway/j7f24/romstage.c trunk/src/mainboard/kontron/kt690/romstage.c trunk/src/mainboard/lippert/frontrunner/romstage.c trunk/src/mainboard/lippert/spacerunner-lx/romstage.c trunk/src/mainboard/msi/ms7135/romstage.c trunk/src/mainboard/msi/ms7260/ap_romstage.c trunk/src/mainboard/msi/ms7260/romstage.c trunk/src/mainboard/msi/ms9185/romstage.c trunk/src/mainboard/msi/ms9282/romstage.c trunk/src/mainboard/newisys/khepri/romstage.c trunk/src/mainboard/nvidia/l1_2pvv/ap_romstage.c trunk/src/mainboard/nvidia/l1_2pvv/romstage.c trunk/src/mainboard/olpc/btest/romstage.c trunk/src/mainboard/olpc/rev_a/romstage.c trunk/src/mainboard/pcengines/alix1c/romstage.c trunk/src/mainboard/sunw/ultra40/romstage.c trunk/src/mainboard/supermicro/h8dme/ap_romstage.c trunk/src/mainboard/supermicro/h8dme/romstage.c trunk/src/mainboard/supermicro/h8dmr/ap_romstage.c trunk/src/mainboard/supermicro/h8dmr/romstage.c trunk/src/mainboard/supermicro/x6dai_g/debug.c trunk/src/mainboard/supermicro/x6dai_g/watchdog.c trunk/src/mainboard/supermicro/x6dhe_g/debug.c trunk/src/mainboard/supermicro/x6dhe_g/watchdog.c trunk/src/mainboard/supermicro/x6dhe_g2/debug.c trunk/src/mainboard/supermicro/x6dhe_g2/watchdog.c trunk/src/mainboard/supermicro/x6dhr_ig/debug.c trunk/src/mainboard/supermicro/x6dhr_ig/watchdog.c trunk/src/mainboard/supermicro/x6dhr_ig2/debug.c trunk/src/mainboard/supermicro/x6dhr_ig2/watchdog.c trunk/src/mainboard/technexion/tim5690/romstage.c trunk/src/mainboard/technexion/tim8690/romstage.c trunk/src/mainboard/technologic/ts5300/romstage.c trunk/src/mainboard/tyan/s2735/romstage.c trunk/src/mainboard/tyan/s2850/romstage.c trunk/src/mainboard/tyan/s2875/romstage.c trunk/src/mainboard/tyan/s2880/romstage.c trunk/src/mainboard/tyan/s2881/romstage.c trunk/src/mainboard/tyan/s2882/romstage.c trunk/src/mainboard/tyan/s2885/romstage.c trunk/src/mainboard/tyan/s2891/romstage.c trunk/src/mainboard/tyan/s2912/ap_romstage.c trunk/src/mainboard/tyan/s2912/romstage.c trunk/src/mainboard/tyan/s4880/romstage.c trunk/src/mainboard/tyan/s4882/romstage.c trunk/src/mainboard/via/epia-cn/romstage.c trunk/src/mainboard/via/epia-m/romstage.c trunk/src/mainboard/via/epia-m700/romstage.c trunk/src/mainboard/via/epia-n/romstage.c trunk/src/mainboard/via/vt8454c/debug.c trunk/src/mainboard/via/vt8454c/romstage.c trunk/src/northbridge/amd/amdk8/amdk8_f.h trunk/src/northbridge/amd/amdk8/coherent_ht.c trunk/src/northbridge/amd/amdk8/incoherent_ht.c trunk/src/northbridge/amd/amdk8/northbridge.c trunk/src/northbridge/amd/amdk8/raminit_f_dqs.c trunk/src/northbridge/amd/amdk8/raminit_test.c trunk/src/northbridge/amd/amdk8/setup_resource_map.c trunk/src/northbridge/amd/gx1/raminit.c trunk/src/northbridge/amd/gx2/pll_reset.c trunk/src/northbridge/amd/gx2/raminit.c trunk/src/northbridge/amd/lx/pll_reset.c trunk/src/northbridge/amd/lx/raminit.c trunk/src/northbridge/intel/e7501/debug.c trunk/src/northbridge/intel/e7501/raminit.c trunk/src/northbridge/intel/e7520/memory_initialized.c trunk/src/northbridge/intel/e7520/raminit.c trunk/src/northbridge/intel/e7525/raminit.c trunk/src/northbridge/intel/i3100/raminit.c trunk/src/northbridge/intel/i3100/raminit_ep80579.c trunk/src/northbridge/intel/i440bx/debug.c trunk/src/northbridge/intel/i440bx/raminit.c trunk/src/northbridge/intel/i440lx/raminit.c trunk/src/northbridge/intel/i82810/debug.c trunk/src/northbridge/intel/i82810/raminit.c trunk/src/northbridge/intel/i82830/raminit.c trunk/src/northbridge/intel/i855/debug.c trunk/src/northbridge/intel/i855/raminit.c trunk/src/northbridge/via/cn400/raminit.c trunk/src/northbridge/via/cn700/raminit.c trunk/src/northbridge/via/cx700/cx700_early_smbus.c trunk/src/northbridge/via/vt8601/raminit.c trunk/src/northbridge/via/vt8623/raminit.c trunk/src/northbridge/via/vx800/examples/romstage.c trunk/src/northbridge/via/vx800/vga.c trunk/src/northbridge/via/vx800/vx800_early_smbus.c trunk/src/southbridge/amd/amd8111/amd8111_early_smbus.c trunk/src/southbridge/amd/cs5535/cs5535_early_setup.c trunk/src/southbridge/amd/cs5536/cs5536_early_setup.c trunk/src/southbridge/amd/cs5536/cs5536_early_smbus.c trunk/src/southbridge/amd/sb600/sb600_early_setup.c trunk/src/southbridge/amd/sb700/sb700_early_setup.c trunk/src/southbridge/broadcom/bcm5785/bcm5785_early_smbus.c trunk/src/southbridge/broadcom/bcm5785/bcm5785_lpc.c trunk/src/southbridge/broadcom/bcm5785/bcm5785_sata.c trunk/src/southbridge/intel/esb6300/esb6300_early_smbus.c trunk/src/southbridge/intel/i3100/i3100_early_smbus.c trunk/src/southbridge/intel/i82371eb/i82371eb_early_smbus.c trunk/src/southbridge/intel/i82371eb/i82371eb_smbus.h trunk/src/southbridge/intel/i82801ax/i82801ax_early_smbus.c trunk/src/southbridge/intel/i82801ax/i82801ax_smbus.h trunk/src/southbridge/intel/i82801ax/i82801ax_watchdog.c trunk/src/southbridge/intel/i82801bx/i82801bx_early_smbus.c trunk/src/southbridge/intel/i82801bx/i82801bx_smbus.h trunk/src/southbridge/intel/i82801bx/i82801bx_watchdog.c trunk/src/southbridge/intel/i82801cx/i82801cx_early_smbus.c trunk/src/southbridge/intel/i82801dx/i82801dx_early_smbus.c trunk/src/southbridge/intel/i82801ex/i82801ex_early_smbus.c trunk/src/southbridge/intel/i82801ex/i82801ex_watchdog.c trunk/src/southbridge/intel/i82801gx/i82801gx_early_smbus.c trunk/src/southbridge/intel/i82801gx/i82801gx_watchdog.c trunk/src/southbridge/nvidia/ck804/ck804_early_smbus.c trunk/src/southbridge/nvidia/ck804/ck804_lpc.c trunk/src/southbridge/nvidia/ck804/ck804_sata.c trunk/src/southbridge/nvidia/mcp55/mcp55_early_setup_car.c trunk/src/southbridge/nvidia/mcp55/mcp55_early_smbus.c trunk/src/southbridge/sis/sis966/sis966_aza.c trunk/src/southbridge/sis/sis966/sis966_ide.c trunk/src/southbridge/sis/sis966/sis966_nic.c trunk/src/southbridge/sis/sis966/sis966_sata.c trunk/src/southbridge/sis/sis966/sis966_usb.c trunk/src/southbridge/sis/sis966/sis966_usb2.c trunk/src/southbridge/via/vt8231/vt8231_early_serial.c trunk/src/southbridge/via/vt8231/vt8231_early_smbus.c trunk/src/southbridge/via/vt8235/vt8235_early_smbus.c trunk/src/southbridge/via/vt8237r/vt8237r_early_smbus.c trunk/src/southbridge/via/vt82c686/vt82c686_early_serial.c trunk/src/superio/ite/it8716f/superio.c trunk/src/superio/serverengines/pilot/pilot_early_init.c trunk/src/superio/smsc/lpc47b272/superio.c trunk/src/superio/smsc/lpc47b397/superio.c trunk/src/superio/smsc/lpc47m10x/superio.c trunk/src/superio/smsc/lpc47n217/superio.c trunk/src/superio/winbond/w83627ehg/superio.c trunk/src/superio/winbond/w83627hf/superio.c Modified: trunk/src/console/console.c ============================================================================== --- trunk/src/console/console.c Wed Mar 31 16:34:40 2010 (r5341) +++ trunk/src/console/console.c Wed Mar 31 16:47:43 2010 (r5342) @@ -100,12 +100,12 @@ void console_init(void) { static const char console_test[] = - "\r\n\r\ncoreboot-" + "\n\ncoreboot-" COREBOOT_VERSION COREBOOT_EXTRA_VERSION " " COREBOOT_BUILD - " starting...\r\n"; + " starting...\n"; print_info(console_test); } @@ -115,7 +115,7 @@ #if CONFIG_SERIAL_POST==1 print_emerg("POST: 0x"); print_emerg_hex8(value); - print_emerg("\r\n"); + print_emerg("\n"); #endif outb(value, 0x80); #endif Modified: trunk/src/cpu/amd/car/post_cache_as_ram.c ============================================================================== --- trunk/src/cpu/amd/car/post_cache_as_ram.c Wed Mar 31 16:34:40 2010 (r5341) +++ trunk/src/cpu/amd/car/post_cache_as_ram.c Wed Mar 31 16:47:43 2010 (r5342) @@ -5,7 +5,7 @@ static inline void print_debug_pcar(const char *strval, uint32_t val) { - printk(BIOS_DEBUG, "%s%08x\r\n", strval, val); + printk(BIOS_DEBUG, "%s%08x\n", strval, val); } /* from linux kernel 2.6.32 asm/string_32.h */ @@ -86,10 +86,10 @@ /* We can put data to stack again */ /* only global variable sysinfo in cache need to be offset */ - print_debug("Done\r\n"); + print_debug("Done\n"); print_debug_pcar("testx = ", testx); - print_debug("Disabling cache as ram now \r\n"); + print_debug("Disabling cache as ram now \n"); disable_cache_as_ram_bsp(); print_debug("Clearing initial memory region: "); @@ -99,7 +99,7 @@ #else memset((void*)0, 0, ((CONFIG_RAMTOP) - CONFIG_DCACHE_RAM_SIZE)); #endif - print_debug("Done\r\n"); + print_debug("Done\n"); // dump_mem((CONFIG_RAMTOP) - 0x8000, (CONFIG_RAMTOP) - 0x7c00); @@ -115,5 +115,5 @@ copy_and_run(); /* We will not return */ - print_debug("should not be here -\r\n"); + print_debug("should not be here -\n"); } Modified: trunk/src/cpu/amd/dualcore/amd_sibling.c ============================================================================== --- trunk/src/cpu/amd/dualcore/amd_sibling.c Wed Mar 31 16:34:40 2010 (r5341) +++ trunk/src/cpu/amd/dualcore/amd_sibling.c Wed Mar 31 16:47:43 2010 (r5342) @@ -109,7 +109,7 @@ if((apicid_base+ioapic_num-1)>0xf) { // We need to enable APIC EXT ID - printk(BIOS_INFO, "if the IO APIC device doesn't support 256 apic id, \r\n you need to set CONFIG_ENABLE_APIC_EXT_ID in romstage.c so you can spare 16 id for ioapic\r\n"); + printk(BIOS_INFO, "if the IO APIC device doesn't support 256 apic id, \n you need to set CONFIG_ENABLE_APIC_EXT_ID in romstage.c so you can spare 16 id for ioapic\n"); enable_apic_ext_id(nodes); } Modified: trunk/src/cpu/amd/model_fxx/fidvid.c ============================================================================== --- trunk/src/cpu/amd/model_fxx/fidvid.c Wed Mar 31 16:34:40 2010 (r5341) +++ trunk/src/cpu/amd/model_fxx/fidvid.c Wed Mar 31 16:47:43 2010 (r5342) @@ -15,21 +15,21 @@ static inline void print_debug_fv(const char *str, unsigned val) { #if K8_SET_FIDVID_DEBUG == 1 - printk(BIOS_DEBUG, "%s%x\r\n", str, val); + printk(BIOS_DEBUG, "%s%x\n", str, val); #endif } static inline void print_debug_fv_8(const char *str, unsigned val) { #if K8_SET_FIDVID_DEBUG == 1 - printk(BIOS_DEBUG, "%s%02x\r\n", str, val); + printk(BIOS_DEBUG, "%s%02x\n", str, val); #endif } static inline void print_debug_fv_64(const char *str, unsigned val, unsigned val2) { #if K8_SET_FIDVID_DEBUG == 1 - printk(BIOS_DEBUG, "%s%x%x\r\n", str, val, val2); + printk(BIOS_DEBUG, "%s%x%x\n", str, val, val2); #endif } @@ -131,7 +131,7 @@ apicidx = lapicid(); if (apicid != apicidx) { - printk(BIOS_ERR, "wrong apicid, we want change %x, but it is %x\r\n", apicid, apicidx); + printk(BIOS_ERR, "wrong apicid, we want change %x, but it is %x\n", apicid, apicidx); return fidvid; } @@ -328,10 +328,10 @@ if (showmessage) { if (vid_new != vid_cur) { - print_err("set vid failed for apicid ="); print_err_hex8(apicidx); print_err("\r\n"); + print_err("set vid failed for apicid ="); print_err_hex8(apicidx); print_err("\n"); } if (fid_new != fid_cur) { - print_err("set fid failed for apicid ="); print_err_hex8(apicidx); print_err("\r\n"); + print_err("set fid failed for apicid ="); print_err_hex8(apicidx); print_err("\n"); } } Modified: trunk/src/cpu/amd/model_fxx/init_cpus.c ============================================================================== --- trunk/src/cpu/amd/model_fxx/init_cpus.c Wed Mar 31 16:34:40 2010 (r5341) +++ trunk/src/cpu/amd/model_fxx/init_cpus.c Wed Mar 31 16:47:43 2010 (r5342) @@ -16,7 +16,7 @@ static inline void print_initcpu8 (const char *strval, unsigned val) { - printk(BIOS_DEBUG, "%s%02x\r\n", strval, val); + printk(BIOS_DEBUG, "%s%02x\n", strval, val); } static inline void print_initcpu8_nocr (const char *strval, unsigned val) @@ -27,12 +27,12 @@ static inline void print_initcpu16 (const char *strval, unsigned val) { - printk(BIOS_DEBUG, "%s%04x\r\n", strval, val); + printk(BIOS_DEBUG, "%s%04x\n", strval, val); } static inline void print_initcpu(const char *strval, unsigned val) { - printk(BIOS_DEBUG, "%s%08x\r\n", strval, val); + printk(BIOS_DEBUG, "%s%08x\n", strval, val); } typedef void (*process_ap_t)(unsigned apicid, void *gp); @@ -155,7 +155,7 @@ static inline __attribute__((always_inline)) void print_apicid_nodeid_coreid(unsigned apicid, struct node_core_id id, const char *str) { - printk(BIOS_DEBUG, "%s --- { APICID = %02x NODEID = %02x COREID = %02x} ---\r\n", str, apicid, id.nodeid, id.coreid); + printk(BIOS_DEBUG, "%s --- { APICID = %02x NODEID = %02x COREID = %02x} ---\n", str, apicid, id.nodeid, id.coreid); } @@ -201,7 +201,7 @@ { print_debug("started ap apicid: "); for_each_ap(bsp_apicid, 2 , wait_ap_started, (void *)0); - print_debug("\r\n"); + print_debug("\n"); } static void allow_all_aps_stop(unsigned bsp_apicid) @@ -286,8 +286,8 @@ #endif if (cpu_init_detectedx) { - print_apicid_nodeid_coreid(apicid, id, "\r\n\r\n\r\nINIT detected from "); - print_debug("\r\nIssuing SOFT_RESET...\r\n"); + print_apicid_nodeid_coreid(apicid, id, "\n\n\nINIT detected from "); + print_debug("\nIssuing SOFT_RESET...\n"); soft_reset(); } @@ -351,7 +351,7 @@ while(!is_core0_started(i)) {} print_initcpu8_nocr(" ", i); } - print_debug("\r\n"); + print_debug("\n"); } Modified: trunk/src/cpu/amd/model_lx/cpureginit.c ============================================================================== --- trunk/src/cpu/amd/model_lx/cpureginit.c Wed Mar 31 16:34:40 2010 (r5341) +++ trunk/src/cpu/amd/model_lx/cpureginit.c Wed Mar 31 16:47:43 2010 (r5342) @@ -209,9 +209,9 @@ print_debug_hex32(msr.hi); print_debug(" and lo "); print_debug_hex32(msr.lo); - print_debug("\r\n"); + print_debug("\n"); wrmsr(GLCP_DELAY_CONTROLS, msr); - print_debug("SetDelayControl done\r\n"); + print_debug("SetDelayControl done\n"); return; } @@ -225,7 +225,7 @@ /* Castle 2.0 BTM periodic sync period. */ /* [40:37] 1 sync record per 256 bytes */ - print_debug("Castle 2.0 BTM periodic sync period.\r\n"); + print_debug("Castle 2.0 BTM periodic sync period.\n"); msrnum = CPU_PF_CONF; msr = rdmsr(msrnum); msr.hi |= (0x8 << 5); @@ -235,7 +235,7 @@ * LX performance setting. * Enable Quack for fewer re-RAS on the MC */ - print_debug("Enable Quack for fewer re-RAS on the MC\r\n"); + print_debug("Enable Quack for fewer re-RAS on the MC\n"); msrnum = GLIU0_ARB; msr = rdmsr(msrnum); msr.hi &= ~ARB_UPPER_DACK_EN_SET; @@ -251,25 +251,25 @@ /* GLIU port active enable, limit south pole masters * (AES and PCI) to one outstanding transaction. */ - print_debug(" GLIU port active enable\r\n"); + print_debug(" GLIU port active enable\n"); msrnum = GLIU1_PORT_ACTIVE; msr = rdmsr(msrnum); msr.lo &= ~0x880; wrmsr(msrnum, msr); /* Set the Delay Control in GLCP */ - print_debug("Set the Delay Control in GLCP\r\n"); + print_debug("Set the Delay Control in GLCP\n"); SetDelayControl(); /* Enable RSDC */ - print_debug("Enable RSDC\r\n"); + print_debug("Enable RSDC\n"); msrnum = CPU_AC_SMM_CTL; msr = rdmsr(msrnum); msr.lo |= SMM_INST_EN_SET; wrmsr(msrnum, msr); /* FPU imprecise exceptions bit */ - print_debug("FPU imprecise exceptions bit\r\n"); + print_debug("FPU imprecise exceptions bit\n"); msrnum = CPU_FPU_MSR_MODE; msr = rdmsr(msrnum); msr.lo |= FPU_IE_SET; @@ -277,14 +277,14 @@ /* Power Savers (Do after BIST) */ /* Enable Suspend on HLT & PAUSE instructions */ - print_debug("Enable Suspend on HLT & PAUSE instructions\r\n"); + print_debug("Enable Suspend on HLT & PAUSE instructions\n"); msrnum = CPU_XC_CONFIG; msr = rdmsr(msrnum); msr.lo |= XC_CONFIG_SUSP_ON_HLT | XC_CONFIG_SUSP_ON_PAUSE; wrmsr(msrnum, msr); /* Enable SUSP and allow TSC to run in Suspend (keep speed detection happy) */ - print_debug("Enable SUSP and allow TSC to run in Suspend\r\n"); + print_debug("Enable SUSP and allow TSC to run in Suspend\n"); msrnum = CPU_BC_CONF_0; msr = rdmsr(msrnum); msr.lo |= TSC_SUSP_SET | SUSP_EN_SET; @@ -302,10 +302,10 @@ #endif /* Setup throttling delays to proper mode if it is ever enabled. */ - print_debug("Setup throttling delays to proper mode\r\n"); + print_debug("Setup throttling delays to proper mode\n"); msrnum = GLCP_TH_OD; msr.hi = 0; msr.lo = 0x00000603C; wrmsr(msrnum, msr); - print_debug("Done cpuRegInit\r\n"); + print_debug("Done cpuRegInit\n"); } Modified: trunk/src/cpu/amd/quadcore/amd_sibling.c ============================================================================== --- trunk/src/cpu/amd/quadcore/amd_sibling.c Wed Mar 31 16:34:40 2010 (r5341) +++ trunk/src/cpu/amd/quadcore/amd_sibling.c Wed Mar 31 16:47:43 2010 (r5342) @@ -114,7 +114,7 @@ if((apicid_base+ioapic_num-1)>0xf) { // We need to enable APIC EXT ID - printk(BIOS_SPEW, "if the IO APIC device doesn't support 256 apic id, \r\n you need to set CONFIG_ENABLE_APIC_EXT_ID in MB Option.lb so you can spare 16 id for ioapic\r\n"); + printk(BIOS_SPEW, "if the IO APIC device doesn't support 256 apic id, \n you need to set CONFIG_ENABLE_APIC_EXT_ID in MB Option.lb so you can spare 16 id for ioapic\n"); enable_apic_ext_id(sysconf.nodes); } Modified: trunk/src/cpu/amd/sc520/raminit.c ============================================================================== --- trunk/src/cpu/amd/sc520/raminit.c Wed Mar 31 16:34:40 2010 (r5341) +++ trunk/src/cpu/amd/sc520/raminit.c Wed Mar 31 16:47:43 2010 (r5342) @@ -248,14 +248,14 @@ static void dumpram(void){ - print_err("ctl "); print_err_hex8(*drcctl); print_err("\r\n"); - print_err("mctl "); print_err_hex8(*drcmctl); print_err("\r\n"); - print_err("cfg "); print_err_hex8(*drccfg); print_err("\r\n"); - - print_err("bendadr0 "); print_err_hex8(*drcbendadr); print_err("\r\n"); - print_err("bendadr1 "); print_err_hex8(*drcbendadr); print_err("\r\n"); - print_err("bendadr2 "); print_err_hex8(*drcbendadr); print_err("\r\n"); - print_err("bendadr3"); print_err_hex8(*drcbendadr); print_err("\r\n"); + print_err("ctl "); print_err_hex8(*drcctl); print_err("\n"); + print_err("mctl "); print_err_hex8(*drcmctl); print_err("\n"); + print_err("cfg "); print_err_hex8(*drccfg); print_err("\n"); + + print_err("bendadr0 "); print_err_hex8(*drcbendadr); print_err("\n"); + print_err("bendadr1 "); print_err_hex8(*drcbendadr); print_err("\n"); + print_err("bendadr2 "); print_err_hex8(*drcbendadr); print_err("\n"); + print_err("bendadr3"); print_err_hex8(*drcbendadr); print_err("\n"); } /* there is a lot of silliness in the amd code, and it is @@ -311,11 +311,11 @@ print_err("NOP\n"); /* 100? 200? */ udelay(100); - print_err("after sc520_udelay\r\n"); + print_err("after sc520_udelay\n"); /* issue all banks precharge */ *drcctl=0x02; - print_err("set *drcctl to 2 \r\n"); + print_err("set *drcctl to 2 \n"); dummy_write(); print_err("PRE\n"); @@ -334,7 +334,7 @@ *drcctl=0x04; for (i=0; i<8; i++) /* refresh 8 times */{ dummy_write(); - print_err("dummy write\r\n"); + print_err("dummy write\n"); } print_err("8 dummy writes\n"); @@ -342,18 +342,18 @@ *drcctl=0x00; print_err("normal\n"); - print_err("HI done normal\r\n"); + print_err("HI done normal\n"); print_err("sizemem\n"); for(bank = 3; bank >= 0; bank--) { - print_err("Try to assign to l\r\n"); + print_err("Try to assign to l\n"); *lp = 0xdeadbeef; - print_err("assigned l ... \r\n"); + print_err("assigned l ... \n"); if (*lp != 0xdeadbeef) { print_err(" no memory at bank "); // print_err_hex8(bank); // print_err(" value "); print_err_hex32(*lp); - print_err("\r\n"); + print_err("\n"); // continue; } *drcctl = 2; @@ -362,7 +362,7 @@ l = *drcbendadr; l >>= 8; *drcbendadr = l; - print_err("loop around\r\n"); + print_err("loop around\n"); *drcctl = 0; dummy_write(); } @@ -386,11 +386,11 @@ print_err("NOP\n"); /* 100? 200? */ //sc520_udelay(100); - print_err("after sc520_udelay\r\n"); + print_err("after sc520_udelay\n"); /* issue all banks precharge */ *drcctl=0x02; - print_err("set *drcctl to 2 \r\n"); + print_err("set *drcctl to 2 \n"); dummy_write(); print_err("PRE\n"); @@ -409,7 +409,7 @@ *drcctl=0x04; for (i=0; i<8; i++) /* refresh 8 times */{ dummy_write(); - print_err("dummy write\r\n"); + print_err("dummy write\n"); } print_err("8 dummy writes\n"); @@ -417,7 +417,7 @@ *drcctl=0x00; print_err("normal\n"); - print_err("HI done normal\r\n"); + print_err("HI done normal\n"); bank = 3; @@ -558,7 +558,7 @@ al -= i&3; *drcbendaddr = rows >> al; print_err("computed ending_adr = "); print_err_hex8(ending_adr); - print_err("\r\n"); + print_err("\n"); */ bad_reinit: @@ -592,7 +592,7 @@ return bank; bad_ram: - print_info("bad ram!\r\n"); + print_info("bad ram!\n"); /* you are here because the read-after-write failed, * in most cases because: no ram in that bank! * set badbank to 1 and go to reinit @@ -600,7 +600,7 @@ ending_adr = 0; goto bad_reinit; while(1) - print_err("DONE NEXTBANK\r\n"); + print_err("DONE NEXTBANK\n"); #endif } @@ -628,27 +628,27 @@ /* two autorefreshes */ *drcctl = 4; *zero = 0; - print_debug("one zero out on refresh\r\n"); + print_debug("one zero out on refresh\n"); *zero = 0; - print_debug("two zero out on refresh\r\n"); + print_debug("two zero out on refresh\n"); /* load mode register */ *drcctl = 3; *zero = 0; - print_debug("DONE the load mode reg\r\n"); + print_debug("DONE the load mode reg\n"); /* normal mode */ *drcctl = 0x0; *zero = 0; - print_debug("DONE one last write and then turn on refresh etc\r\n"); + print_debug("DONE one last write and then turn on refresh etc\n"); *drcctl = 0x18; *zero = 0; - print_debug("DONE the normal\r\n"); + print_debug("DONE the normal\n"); *zero = 0xdeadbeef; if (*zero != 0xdeadbeef) - print_debug("NO LUCK\r\n"); + print_debug("NO LUCK\n"); else - print_debug("did a store and load ...\r\n"); + print_debug("did a store and load ...\n"); //print_err_hex32(*zero); - // print_err(" zero is now "); print_err_hex32(*zero); print_err("\r\n"); + // print_err(" zero is now "); print_err_hex32(*zero); print_err("\n"); } Modified: trunk/src/cpu/intel/microcode/microcode.c ============================================================================== --- trunk/src/cpu/intel/microcode/microcode.c Wed Mar 31 16:34:40 2010 (r5341) +++ trunk/src/cpu/intel/microcode/microcode.c Wed Mar 31 16:47:43 2010 (r5342) @@ -82,7 +82,7 @@ print_debug_hex32(pf); print_debug(" rev = 0x"); print_debug_hex32(rev); - print_debug("\r\n"); + print_debug("\n"); m = microcode_updates; for(c = microcode_updates; m->hdrver; m = (const struct microcode *)c) { @@ -99,7 +99,7 @@ print_debug_hex32(new_rev); print_debug(" from revision "); print_debug_hex32(rev); - print_debug("\r\n"); + print_debug("\n"); break; } if (m->total_size) { Modified: trunk/src/cpu/intel/model_106cx/cache_as_ram_disable.c ============================================================================== --- trunk/src/cpu/intel/model_106cx/cache_as_ram_disable.c Wed Mar 31 16:34:40 2010 (r5341) +++ trunk/src/cpu/intel/model_106cx/cache_as_ram_disable.c Wed Mar 31 16:47:43 2010 (r5342) @@ -40,10 +40,10 @@ "movl %%esp, %0\n\t" : "=a" (v_esp) ); - printk(BIOS_SPEW, "v_esp=%08x\r\n", v_esp); + printk(BIOS_SPEW, "v_esp=%08x\n", v_esp); } - printk(BIOS_SPEW, "cpu_reset = %08x\r\n",cpu_reset); + printk(BIOS_SPEW, "cpu_reset = %08x\n",cpu_reset); if(cpu_reset == 0) { print_spew("Clearing initial memory region: "); @@ -83,12 +83,12 @@ #ifdef CONFIG_DEACTIVATE_CAR print_debug("Deactivating CAR"); #include CONFIG_DEACTIVATE_CAR_FILE - print_debug(" - Done.\r\n"); + print_debug(" - Done.\n"); #endif /* Copy and execute coreboot_ram */ copy_and_run(new_cpu_reset); /* We will not return */ } - print_debug("sorry. parachute did not open.\r\n"); + print_debug("sorry. parachute did not open.\n"); } Modified: trunk/src/drivers/ati/ragexl/xlinit.c ============================================================================== --- trunk/src/drivers/ati/ragexl/xlinit.c Wed Mar 31 16:34:40 2010 (r5341) +++ trunk/src/drivers/ati/ragexl/xlinit.c Wed Mar 31 16:47:43 2010 (r5342) @@ -541,7 +541,7 @@ #endif #if 0 - printk(BIOS_DEBUG, "ati_regbase = 0x%08x, frame_buffer = 0x%08x\r\n", info->ati_regbase, info->frame_buffer); + printk(BIOS_DEBUG, "ati_regbase = 0x%08x, frame_buffer = 0x%08x\n", info->ati_regbase, info->frame_buffer); #endif chip_id = aty_ld_le32(CONFIG_CHIP_ID, info); @@ -561,7 +561,7 @@ return ; found: - printk(BIOS_INFO, "ati_ragexl_init: %s [0x%04x rev 0x%02x]\r\n", chipname, type, rev); + printk(BIOS_INFO, "ati_ragexl_init: %s [0x%04x rev 0x%02x]\n", chipname, type, rev); #if 0 if (M64_HAS(INTEGRATED)) { /* for many chips, the mclk is 67 MHz for SDRAM, 63 MHz otherwise */ Modified: trunk/src/drivers/generic/debug/debug_dev.c ============================================================================== --- trunk/src/drivers/generic/debug/debug_dev.c Wed Mar 31 16:34:40 2010 (r5341) +++ trunk/src/drivers/generic/debug/debug_dev.c Wed Mar 31 16:47:43 2010 (r5342) @@ -92,16 +92,16 @@ unsigned char byte; status = smbus_read_byte(dev, j); if (status < 0) { - // printk(BIOS_DEBUG, "bad device status= %08x\r\n", status); + // printk(BIOS_DEBUG, "bad device status= %08x\n", status); break; } if ((j & 0xf) == 0) { - printk(BIOS_DEBUG, "\r\n%02x: ", j); + printk(BIOS_DEBUG, "\n%02x: ", j); } byte = status & 0xff; printk(BIOS_DEBUG, "%02x ", byte); } - printk(BIOS_DEBUG, "\r\n"); + printk(BIOS_DEBUG, "\n"); } static void print_smbus_regs_all(struct device *dev) Modified: trunk/src/drivers/i2c/adm1027/adm1027.c ============================================================================== --- trunk/src/drivers/i2c/adm1027/adm1027.c Wed Mar 31 16:34:40 2010 (r5341) +++ trunk/src/drivers/i2c/adm1027/adm1027.c Wed Mar 31 16:47:43 2010 (r5342) @@ -26,7 +26,7 @@ result = smbus_read_byte(dev, ADM1027_REG_CONFIG1); if (!(result & CFG1_RDY)) { - printk(BIOS_DEBUG, "ADM1027: monitoring not ready\r\n"); + printk(BIOS_DEBUG, "ADM1027: monitoring not ready\n"); return; } result = (result | CFG1_STRT); @@ -34,9 +34,9 @@ result = smbus_read_byte(dev, ADM1027_REG_CONFIG1); if (!(result & CFG1_STRT)) { - printk(BIOS_DEBUG, "ADM1027: monitoring would not enable\r\n"); + printk(BIOS_DEBUG, "ADM1027: monitoring would not enable\n"); } - printk(BIOS_DEBUG, "ADM1027: monitoring enabled\r\n"); + printk(BIOS_DEBUG, "ADM1027: monitoring enabled\n"); } static void adm1027_init(device_t dev) Modified: trunk/src/include/assert.h ============================================================================== --- trunk/src/include/assert.h Wed Mar 31 16:34:40 2010 (r5341) +++ trunk/src/include/assert.h Wed Mar 31 16:47:43 2010 (r5342) @@ -29,7 +29,7 @@ print_emerg(__FILE__); \ print_emerg("', line 0x"); \ print_debug_hex32(__LINE__); \ - print_emerg("\r\n"); \ + print_emerg("\n"); \ /* die(""); */ \ } \ } @@ -39,7 +39,7 @@ print_emerg(__FILE__); \ print_emerg("', line 0x"); \ print_debug_hex32(__LINE__); \ - print_emerg("\r\n"); \ + print_emerg("\n"); \ /* die(""); */ \ } Modified: trunk/src/include/cpu/x86/bist.h ============================================================================== --- trunk/src/include/cpu/x86/bist.h Wed Mar 31 16:34:40 2010 (r5341) +++ trunk/src/include/cpu/x86/bist.h Wed Mar 31 16:47:43 2010 (r5342) @@ -10,7 +10,7 @@ print_emerg("BIST failed: "); print_emerg_hex32(bist); #endif - die("\r\n"); + die("\n"); } } Modified: trunk/src/lib/debug.c ============================================================================== --- trunk/src/lib/debug.c Wed Mar 31 16:34:40 2010 (r5341) +++ trunk/src/lib/debug.c Wed Mar 31 16:47:43 2010 (r5342) @@ -23,7 +23,7 @@ continue; } print_debug_pci_dev(dev); - print_debug("\r\n"); + print_debug("\n"); } } @@ -31,7 +31,7 @@ { int i; print_debug_pci_dev(dev); - print_debug("\r\n"); + print_debug("\n"); for(i = 0; i <= 255; i++) { unsigned char val; @@ -43,7 +43,7 @@ print_debug_char(' '); print_debug_hex8(val); if ((i & 0x0f) == 0x0f) { - print_debug("\r\n"); + print_debug("\n"); } } } Modified: trunk/src/lib/generic_dump_spd.c ============================================================================== --- trunk/src/lib/generic_dump_spd.c Wed Mar 31 16:34:40 2010 (r5341) +++ trunk/src/lib/generic_dump_spd.c Wed Mar 31 16:47:43 2010 (r5342) @@ -6,7 +6,7 @@ static void dump_spd_registers(const struct mem_controller *ctrl) { int i; - print_debug("\r\n"); + print_debug("\n"); for(i = 0; i < 4; i++) { unsigned device; device = ctrl->channel0[i]; @@ -20,20 +20,20 @@ int status; unsigned char byte; if ((j & 0xf) == 0) { - print_debug("\r\n"); + print_debug("\n"); print_debug_hex8(j); print_debug(": "); } status = spd_read_byte(device, j); if (status < 0) { - print_debug("bad device\r\n"); + print_debug("bad device\n"); break; } byte = status & 0xff; print_debug_hex8(byte); print_debug_char(' '); } - print_debug("\r\n"); + print_debug("\n"); } device = ctrl->channel1[i]; if (device) { @@ -46,20 +46,20 @@ int status; unsigned char byte; if ((j & 0xf) == 0) { - print_debug("\r\n"); + print_debug("\n"); print_debug_hex8(j); print_debug(": "); } status = spd_read_byte(device, j); if (status < 0) { - print_debug("bad device\r\n"); + print_debug("bad device\n"); break; } byte = status & 0xff; print_debug_hex8(byte); print_debug_char(' '); } - print_debug("\r\n"); + print_debug("\n"); } } } Modified: trunk/src/lib/generic_sdram.c ============================================================================== --- trunk/src/lib/generic_sdram.c Wed Mar 31 16:34:40 2010 (r5341) +++ trunk/src/lib/generic_sdram.c Wed Mar 31 16:47:43 2010 (r5342) @@ -9,7 +9,7 @@ #if CONFIG_USE_PRINTK_IN_CAR printk(BIOS_DEBUG, "%s%02x\n", strval, val); #else - print_debug(strval); print_debug_hex8(val); print_debug("\r\n"); + print_debug(strval); print_debug_hex8(val); print_debug("\n"); #endif } @@ -48,7 +48,7 @@ * Some chipsets do the work for us while on others * we need to it by hand. */ - print_debug("Ram3\r\n"); + print_debug("Ram3\n"); #if RAMINIT_SYSINFO == 1 sdram_enable(controllers, ctrl, sysinfo); @@ -56,5 +56,5 @@ sdram_enable(controllers, ctrl); #endif - print_debug("Ram4\r\n"); + print_debug("Ram4\n"); } Modified: trunk/src/lib/ramtest.c ============================================================================== --- trunk/src/lib/ramtest.c Wed Mar 31 16:34:40 2010 (r5341) +++ trunk/src/lib/ramtest.c Wed Mar 31 16:47:43 2010 (r5342) @@ -52,13 +52,13 @@ * Fill. */ #if CONFIG_USE_PRINTK_IN_CAR - printk(BIOS_DEBUG, "DRAM fill: 0x%08lx-0x%08lx\r\n", start, stop); + printk(BIOS_DEBUG, "DRAM fill: 0x%08lx-0x%08lx\n", start, stop); #else print_debug("DRAM fill: "); print_debug_hex32(start); print_debug("-"); print_debug_hex32(stop); - print_debug("\r\n"); + print_debug("\n"); #endif for(addr = start; addr < stop ; addr += 4) { /* Display address being filled */ @@ -74,10 +74,10 @@ }; /* Display final address */ #if CONFIG_USE_PRINTK_IN_CAR - printk(BIOS_DEBUG, "%08lx\r\nDRAM filled\r\n", addr); + printk(BIOS_DEBUG, "%08lx\nDRAM filled\n", addr); #else print_debug_hex32(addr); - print_debug("\r\nDRAM filled\r\n"); + print_debug("\nDRAM filled\n"); #endif } @@ -89,13 +89,13 @@ * Verify. */ #if CONFIG_USE_PRINTK_IN_CAR - printk(BIOS_DEBUG, "DRAM verify: 0x%08lx-0x%08lx\r\n", start, stop); + printk(BIOS_DEBUG, "DRAM verify: 0x%08lx-0x%08lx\n", start, stop); #else print_debug("DRAM verify: "); print_debug_hex32(start); print_debug_char('-'); print_debug_hex32(stop); - print_debug("\r\n"); + print_debug("\n"); #endif for(addr = start; addr < stop ; addr += 4) { unsigned long value; @@ -112,20 +112,20 @@ if (value != addr) { /* Display address with error */ #if CONFIG_USE_PRINTK_IN_CAR - printk(BIOS_ERR, "Fail: @0x%08lx Read value=0x%08lx\r\n", addr, value); + printk(BIOS_ERR, "Fail: @0x%08lx Read value=0x%08lx\n", addr, value); #else print_err("Fail: @0x"); print_err_hex32(addr); print_err(" Read value=0x"); print_err_hex32(value); - print_err("\r\n"); + print_err("\n"); #endif i++; if(i>256) { #if CONFIG_USE_PRINTK_IN_CAR - printk(BIOS_DEBUG, "Aborting.\n\r"); + printk(BIOS_DEBUG, "Aborting.\n"); #else - print_debug("Aborting.\n\r"); + print_debug("Aborting.\n"); #endif break; } @@ -140,17 +140,17 @@ if (i) { #if CONFIG_USE_PRINTK_IN_CAR - printk(BIOS_DEBUG, "\r\nDRAM did _NOT_ verify!\r\n"); + printk(BIOS_DEBUG, "\nDRAM did _NOT_ verify!\n"); #else - print_debug("\r\nDRAM did _NOT_ verify!\r\n"); + print_debug("\nDRAM did _NOT_ verify!\n"); #endif die("DRAM ERROR"); } else { #if CONFIG_USE_PRINTK_IN_CAR - printk(BIOS_DEBUG, "\r\nDRAM range verified.\r\n"); + printk(BIOS_DEBUG, "\nDRAM range verified.\n"); #else - print_debug("\r\nDRAM range verified.\r\n"); + print_debug("\nDRAM range verified.\n"); #endif } } @@ -164,22 +164,22 @@ * are tested. -Tyson */ #if CONFIG_USE_PRINTK_IN_CAR - printk(BIOS_DEBUG, "Testing DRAM : %08lx - %08lx\r\n", start, stop); + printk(BIOS_DEBUG, "Testing DRAM : %08lx - %08lx\n", start, stop); #else print_debug("Testing DRAM : "); print_debug_hex32(start); print_debug("-"); print_debug_hex32(stop); - print_debug("\r\n"); + print_debug("\n"); #endif ram_fill(start, stop); /* Make sure we don't read before we wrote */ phys_memory_barrier(); ram_verify(start, stop); #if CONFIG_USE_PRINTK_IN_CAR - printk(BIOS_DEBUG, "Done.\r\n"); + printk(BIOS_DEBUG, "Done.\n"); #else - print_debug("Done.\r\n"); + print_debug("Done.\n"); #endif } Modified: trunk/src/mainboard/amd/dbm690t/romstage.c ============================================================================== --- trunk/src/mainboard/amd/dbm690t/romstage.c Wed Mar 31 16:34:40 2010 (r5341) +++ trunk/src/mainboard/amd/dbm690t/romstage.c Wed Mar 31 16:47:43 2010 (r5342) @@ -177,7 +177,7 @@ printk(BIOS_DEBUG, "needs_reset=0x%x\n", needs_reset); if (needs_reset) { - print_info("ht reset -\r\n"); + print_info("ht reset -\n"); soft_reset(); } Modified: trunk/src/mainboard/amd/mahogany/romstage.c ============================================================================== --- trunk/src/mainboard/amd/mahogany/romstage.c Wed Mar 31 16:34:40 2010 (r5341) +++ trunk/src/mainboard/amd/mahogany/romstage.c Wed Mar 31 16:47:43 2010 (r5342) @@ -176,7 +176,7 @@ printk(BIOS_DEBUG, "needs_reset=0x%x\n", needs_reset); if (needs_reset) { - print_info("ht reset -\r\n"); + print_info("ht reset -\n"); soft_reset(); } Modified: trunk/src/mainboard/amd/pistachio/romstage.c ============================================================================== --- trunk/src/mainboard/amd/pistachio/romstage.c Wed Mar 31 16:34:40 2010 (r5341) +++ trunk/src/mainboard/amd/pistachio/romstage.c Wed Mar 31 16:47:43 2010 (r5342) @@ -183,7 +183,7 @@ post_code(0x06); if (needs_reset) { - print_info("ht reset -\r\n"); + print_info("ht reset -\n"); soft_reset(); } Modified: trunk/src/mainboard/amd/rumba/romstage.c ============================================================================== --- trunk/src/mainboard/amd/rumba/romstage.c Wed Mar 31 16:34:40 2010 (r5341) +++ trunk/src/mainboard/amd/rumba/romstage.c Wed Mar 31 16:47:43 2010 (r5342) @@ -50,7 +50,7 @@ /* get module banks (sides) per dimm, SPD byte 5 */ module_banks = spd_read_byte(0xA0, 5); if (module_banks < 1 || module_banks > 2) - print_err("Module banks per dimm\r\n"); + print_err("Module banks per dimm\n"); module_banks >>= 1; msr.hi &= ~(1 << CF07_UPPER_D0_MB_SHIFT); msr.hi |= (module_banks << CF07_UPPER_D0_MB_SHIFT); @@ -58,7 +58,7 @@ /* get component banks per module bank, SPD byte 17 */ val = spd_read_byte(0xA0, 17); if (val < 2 || val > 4) - print_err("Component banks per module bank\r\n"); + print_err("Component banks per module bank\n"); val >>= 2; msr.hi &= ~(0x1 << CF07_UPPER_D0_CB_SHIFT); msr.hi |= (val << CF07_UPPER_D0_CB_SHIFT); @@ -78,7 +78,7 @@ print_debug("computed msr.hi "); print_debug_hex32(msr.hi); - print_debug("\r\n"); + print_debug("\n"); msr.lo = 0x00003000; wrmsr(MC_CF07_DATA, msr); Modified: trunk/src/mainboard/amd/serengeti_cheetah/ap_romstage.c ============================================================================== --- trunk/src/mainboard/amd/serengeti_cheetah/ap_romstage.c Wed Mar 31 16:34:40 2010 (r5341) +++ trunk/src/mainboard/amd/serengeti_cheetah/ap_romstage.c Wed Mar 31 16:47:43 2010 (r5342) @@ -69,7 +69,7 @@ #if CONFIG_USE_PRINTK_IN_CAR printk(BIOS_DEBUG, "CODE IN CACHE ON NODE: %02x\n"); #else - print_debug("CODE IN CACHE ON NODE:"); print_debug_hex8(id.nodeid); print_debug("\r\n"); + print_debug("CODE IN CACHE ON NODE:"); print_debug_hex8(id.nodeid); print_debug("\n"); #endif train_ram(id.nodeid, sysinfo, sysinfox); Modified: trunk/src/mainboard/amd/serengeti_cheetah/romstage.c ============================================================================== --- trunk/src/mainboard/amd/serengeti_cheetah/romstage.c Wed Mar 31 16:34:40 2010 (r5341) +++ trunk/src/mainboard/amd/serengeti_cheetah/romstage.c Wed Mar 31 16:47:43 2010 (r5342) @@ -92,14 +92,14 @@ { #define SMBUS_HUB 0x18 int ret, i; - print_debug("change_i2c_mux i="); print_debug_hex8(device); print_debug("\r\n"); + print_debug("change_i2c_mux i="); print_debug_hex8(device); print_debug("\n"); i=2; do { ret = smbus_write_byte(SMBUS_HUB, 0x01, device); - print_debug("change_i2c_mux 1 ret="); print_debug_hex32(ret); print_debug("\r\n"); + print_debug("change_i2c_mux 1 ret="); print_debug_hex32(ret); print_debug("\n"); } while ((ret!=0) && (i-->0)); ret = smbus_write_byte(SMBUS_HUB, 0x03, 0); - print_debug("change_i2c_mux 2 ret="); print_debug_hex32(ret); print_debug("\r\n"); + print_debug("change_i2c_mux 2 ret="); print_debug_hex32(ret); print_debug("\n"); } #endif @@ -209,7 +209,7 @@ dump_pci_device(PCI_DEV(0, 0x19, 0)); #endif - print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\r\n"); + print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\n"); #if CONFIG_MEM_TRAIN_SEQ == 1 set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram @@ -246,7 +246,7 @@ /* Read FIDVID_STATUS */ msr_t msr; msr=rdmsr(0xc0010042); - print_debug("begin msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\r\n"); + print_debug("begin msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n"); } @@ -260,7 +260,7 @@ { msr_t msr; msr=rdmsr(0xc0010042); - print_debug("end msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\r\n"); + print_debug("end msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n"); } @@ -276,7 +276,7 @@ // fidvid change will issue one LDTSTOP and the HT change will be effective too if (needs_reset) { - print_info("ht reset -\r\n"); + print_info("ht reset -\n"); soft_reset_x(sysinfo->sbbusn, sysinfo->sbdn); } #endif Modified: trunk/src/mainboard/arima/hdama/debug.c ============================================================================== --- trunk/src/mainboard/arima/hdama/debug.c Wed Mar 31 16:34:40 2010 (r5341) +++ trunk/src/mainboard/arima/hdama/debug.c Wed Mar 31 16:47:43 2010 (r5342) @@ -23,7 +23,7 @@ continue; } print_debug_pci_dev(dev); - print_debug("\r\n"); + print_debug("\n"); } } @@ -31,7 +31,7 @@ { int i; print_debug_pci_dev(dev); - print_debug("\r\n"); + print_debug("\n"); for(i = 0; i <= 255; i++) { unsigned char val; @@ -43,7 +43,7 @@ print_debug_char(' '); print_debug_hex8(val); if ((i & 0x0f) == 0x0f) { - print_debug("\r\n"); + print_debug("\n"); } } } @@ -70,7 +70,7 @@ int n; for(n = 0; n < controllers; n++) { int i; - print_debug("\r\n"); + print_debug("\n"); activate_spd_rom(&ctrl[n]); for(i = 0; i < 4; i++) { unsigned device; @@ -87,13 +87,13 @@ int status; unsigned char byte; if ((j & 0xf) == 0) { - print_debug("\r\n"); + print_debug("\n"); print_debug_hex8(j); print_debug(": "); } status = spd_read_byte(device, j); if (status < 0) { - print_debug("bad device\r\n"); + print_debug("bad device\n"); break; } #if 0 @@ -104,7 +104,7 @@ #endif print_debug_char(' '); } - print_debug("\r\n"); + print_debug("\n"); } device = ctrl[n].channel1[i]; if (device) { @@ -119,13 +119,13 @@ int status; unsigned char byte; if ((j & 0xf) == 0) { - print_debug("\r\n"); + print_debug("\n"); print_debug_hex8(j); print_debug(": "); } status = spd_read_byte(device, j); if (status < 0) { - print_debug("bad device\r\n"); + print_debug("bad device\n"); break; } #if 0 @@ -136,7 +136,7 @@ #endif print_debug_char(' '); } - print_debug("\r\n"); + print_debug("\n"); } } } Modified: trunk/src/mainboard/arima/hdama/romstage.c ============================================================================== --- trunk/src/mainboard/arima/hdama/romstage.c Wed Mar 31 16:34:40 2010 (r5341) +++ trunk/src/mainboard/arima/hdama/romstage.c Wed Mar 31 16:47:43 2010 (r5342) @@ -148,7 +148,7 @@ needs_reset |= ht_setup_chains_x(); if (needs_reset) { - print_info("ht reset -\r\n"); + print_info("ht reset -\n"); soft_reset(); } Modified: trunk/src/mainboard/asus/a8n_e/romstage.c ============================================================================== --- trunk/src/mainboard/asus/a8n_e/romstage.c Wed Mar 31 16:34:40 2010 (r5341) +++ trunk/src/mainboard/asus/a8n_e/romstage.c Wed Mar 31 16:47:43 2010 (r5342) @@ -165,7 +165,7 @@ needs_reset |= ck804_early_setup_x(); if (needs_reset) { - print_info("ht reset -\r\n"); + print_info("ht reset -\n"); soft_reset(); } Modified: trunk/src/mainboard/asus/a8v-e_se/romstage.c ============================================================================== --- trunk/src/mainboard/asus/a8v-e_se/romstage.c Wed Mar 31 16:34:40 2010 (r5341) +++ trunk/src/mainboard/asus/a8v-e_se/romstage.c Wed Mar 31 16:47:43 2010 (r5342) @@ -89,7 +89,7 @@ uint8_t tmp; set_bios_reset(); - print_debug("soft reset \r\n"); + print_debug("soft reset \n"); /* PCI reset */ tmp = pci_read_config8(PCI_DEV(0, 0x11, 0), 0x4f); @@ -195,7 +195,7 @@ console_init(); enable_rom_decode(); - print_info("now booting... fallback\r\n"); + print_info("now booting... fallback\n"); /* Is this a CPU only reset? Or is this a secondary CPU? */ if (!cpu_init_detectedx && boot_cpu()) { @@ -210,7 +210,7 @@ console_init(); enable_rom_decode(); - print_info("now booting... real_main\r\n"); + print_info("now booting... real_main\n"); if (bist == 0) bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); @@ -222,7 +222,7 @@ setup_coherent_ht_domain(); wait_all_core0_started(); - print_info("now booting... Core0 started\r\n"); + print_info("now booting... Core0 started\n"); #if CONFIG_LOGICAL_CPUS==1 /* It is said that we should start core1 after all core0 launched. */ @@ -237,7 +237,7 @@ needs_reset |= k8t890_early_setup_ht(); if (needs_reset) { - print_debug("ht reset -\r\n"); + print_debug("ht reset -\n"); soft_reset(); } Modified: trunk/src/mainboard/asus/m2v-mx_se/romstage.c ============================================================================== --- trunk/src/mainboard/asus/m2v-mx_se/romstage.c Wed Mar 31 16:34:40 2010 (r5341) +++ trunk/src/mainboard/asus/m2v-mx_se/romstage.c Wed Mar 31 16:47:43 2010 (r5342) @@ -105,12 +105,12 @@ /* this function might fail on some K8 CPUs with errata #181 */ static void ldtstop_sb(void) { - print_debug("toggle LDTSTP#\r\n"); + print_debug("toggle LDTSTP#\n"); u8 reg = inb (VT8237R_ACPI_IO_BASE + 0x5c); reg = reg ^ (1 << 0); outb(reg, VT8237R_ACPI_IO_BASE + 0x5c); reg = inb(VT8237R_ACPI_IO_BASE + 0x15); - print_debug("done\r\n"); + print_debug("done\n"); } #include "cpu/amd/model_fxx/fidvid.c" @@ -127,7 +127,7 @@ uint8_t tmp; set_bios_reset(); - print_debug("soft reset \r\n"); + print_debug("soft reset \n"); /* PCI reset */ tmp = pci_read_config8(PCI_DEV(0, 0x11, 0), 0x4f); @@ -188,7 +188,7 @@ console_init(); enable_rom_decode(); - print_info("now booting... real_main\r\n"); + print_info("now booting... real_main\n"); if (bist == 0) bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); @@ -199,7 +199,7 @@ setup_coherent_ht_domain(); wait_all_core0_started(); - print_info("now booting... Core0 started\r\n"); + print_info("now booting... Core0 started\n"); #if CONFIG_LOGICAL_CPUS==1 /* It is said that we should start core1 after all core0 launched. */ @@ -222,9 +222,9 @@ if (needs_reset) { print_debug_hex8(needs_reset); - print_debug("Xht reset -\r\n"); + print_debug("Xht reset -\n"); soft_reset(); - print_debug("NO reset\r\n"); + print_debug("NO reset\n"); } @@ -233,7 +233,7 @@ vt8237_sb_enable_fid_vid(); enable_fid_change(); - print_debug("after enable_fid_change\r\n"); + print_debug("after enable_fid_change\n"); init_fidvid_bsp(bsp_apicid); Modified: trunk/src/mainboard/bcom/winnetp680/romstage.c ============================================================================== --- trunk/src/mainboard/bcom/winnetp680/romstage.c Wed Mar 31 16:34:40 2010 (r5341) +++ trunk/src/mainboard/bcom/winnetp680/romstage.c Wed Mar 31 16:47:43 2010 (r5342) @@ -101,26 +101,26 @@ uart_init(); console_init(); - print_spew("In romstage.c:main()\r\n"); + print_spew("In romstage.c:main()\n"); enable_smbus(); smbus_fixup(&ctrl); if (bist == 0) { - print_debug("doing early_mtrr\r\n"); + print_debug("doing early_mtrr\n"); early_mtrr_init(); } /* Halt if there was a built-in self test failure. */ report_bist_failure(bist); - print_debug("Enabling mainboard devices\r\n"); + print_debug("Enabling mainboard devices\n"); enable_mainboard_devices(); ddr_ram_setup(&ctrl); /* ram_check(0, 640 * 1024); */ - print_spew("Leaving romstage.c:main()\r\n"); + print_spew("Leaving romstage.c:main()\n"); } Modified: trunk/src/mainboard/broadcom/blast/romstage.c ============================================================================== --- trunk/src/mainboard/broadcom/blast/romstage.c Wed Mar 31 16:34:40 2010 (r5341) +++ trunk/src/mainboard/broadcom/blast/romstage.c Wed Mar 31 16:47:43 2010 (r5342) @@ -70,9 +70,9 @@ { #define SMBUS_HUB 0x71 int ret; - print_debug("change_i2c_mux i="); print_debug_hex8(device); print_debug("\r\n"); + print_debug("change_i2c_mux i="); print_debug_hex8(device); print_debug("\n"); ret = smbus_send_byte(SMBUS_HUB, device); - print_debug("change_i2c_mux ret="); print_debug_hex32(ret); print_debug("\r\n"); + print_debug("change_i2c_mux ret="); print_debug_hex32(ret); print_debug("\n"); } #endif @@ -152,7 +152,7 @@ /* Halt if there was a built in self test failure */ report_bist_failure(bist); - print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\r\n"); + print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\n"); setup_blast_resource_map(); @@ -175,7 +175,7 @@ bcm5785_early_setup(); if (needs_reset) { - print_info("ht reset -\r\n"); + print_info("ht reset -\n"); soft_reset(); } Modified: trunk/src/mainboard/dell/s1850/debug.c ============================================================================== --- trunk/src/mainboard/dell/s1850/debug.c Wed Mar 31 16:34:40 2010 (r5341) +++ trunk/src/mainboard/dell/s1850/debug.c Wed Mar 31 16:47:43 2010 (r5342) @@ -12,7 +12,7 @@ print_debug_hex8(index); print_debug(": 0x"); print_debug_hex8(data); - print_debug("\r\n"); + print_debug("\n"); return; } @@ -49,52 +49,52 @@ int i; unsigned char data; - print_debug("\r\n*** SERVER I/O REGISTERS ***\r\n"); + print_debug("\n*** SERVER I/O REGISTERS ***\n"); for (i=0x10; i<=0x2d; i++) { print_reg((unsigned char)i); } #if 0 - print_debug("\r\n*** XBUS REGISTERS ***\r\n"); + print_debug("\n*** XBUS REGISTERS ***\n"); setup_func(0x0f); for (i=0xf0; i<=0xff; i++) { print_reg((unsigned char)i); } - print_debug("\r\n*** SERIAL 1 CONFIG REGISTERS ***\r\n"); + print_debug("\n*** SERIAL 1 CONFIG REGISTERS ***\n"); setup_func(0x03); print_reg(0xf0); - print_debug("\r\n*** SERIAL 2 CONFIG REGISTERS ***\r\n"); + print_debug("\n*** SERIAL 2 CONFIG REGISTERS ***\n"); setup_func(0x02); print_reg(0xf0); #endif - print_debug("\r\n*** GPIO REGISTERS ***\r\n"); + print_debug("\n*** GPIO REGISTERS ***\n"); setup_func(0x07); for (i=0xf0; i<=0xf8; i++) { print_reg((unsigned char)i); } - print_debug("\r\n*** GPIO VALUES ***\r\n"); + print_debug("\n*** GPIO VALUES ***\n"); data = inb(0x68a); - print_debug("\r\nGPDO 4: 0x"); + print_debug("\nGPDO 4: 0x"); print_debug_hex8(data); data = inb(0x68b); - print_debug("\r\nGPDI 4: 0x"); + print_debug("\nGPDI 4: 0x"); print_debug_hex8(data); - print_debug("\r\n"); + print_debug("\n"); #if 0 - print_debug("\r\n*** WATCHDOG TIMER REGISTERS ***\r\n"); + print_debug("\n*** WATCHDOG TIMER REGISTERS ***\n"); setup_func(0x0a); print_reg(0xf0); - print_debug("\r\n*** FAN CONTROL REGISTERS ***\r\n"); + print_debug("\n*** FAN CONTROL REGISTERS ***\n"); setup_func(0x09); print_reg(0xf0); print_reg(0xf1); - print_debug("\r\n*** RTC REGISTERS ***\r\n"); + print_debug("\n*** RTC REGISTERS ***\n"); setup_func(0x10); print_reg(0xf0); print_reg(0xf1); @@ -104,7 +104,7 @@ print_reg(0xfe); print_reg(0xff); - print_debug("\r\n*** HEALTH MONITORING & CONTROL REGISTERS ***\r\n"); + print_debug("\n*** HEALTH MONITORING & CONTROL REGISTERS ***\n"); setup_func(0x14); print_reg(0xf0); #endif @@ -135,7 +135,7 @@ continue; } print_debug_pci_dev(dev); - print_debug("\r\n"); + print_debug("\n"); } } @@ -143,7 +143,7 @@ { int i; print_debug_pci_dev(dev); - print_debug("\r\n"); + print_debug("\n"); for(i = 0; i <= 255; i++) { unsigned char val; @@ -155,7 +155,7 @@ print_debug_char(' '); print_debug_hex8(val); if ((i & 0x0f) == 0x0f) { - print_debug("\r\n"); + print_debug("\n"); } } } @@ -165,7 +165,7 @@ int i; unsigned long bar; - print_debug("BAR 14 Dump\r\n"); + print_debug("BAR 14 Dump\n"); bar = pci_read_config32(dev, 0x14); for(i = 0; i <= 0x300; i+=4) { @@ -178,14 +178,14 @@ val = pci_read_config8(dev, i); #endif if((i%4)==0) { - print_debug("\r\n"); + print_debug("\n"); print_debug_hex16(i); print_debug_char(' '); } print_debug_hex32(read32(bar + i)); print_debug_char(' '); } - print_debug("\r\n"); + print_debug("\n"); } static void dump_pci_devices(void) @@ -212,14 +212,14 @@ while(device <= SMBUS_MEM_DEVICE_END) { int status = 0; int i; - print_debug("\r\n"); + print_debug("\n"); print_debug("dimm "); print_debug_hex8(device); for(i = 0; (i < 256) ; i++) { unsigned char byte; if ((i % 16) == 0) { - print_debug("\r\n"); + print_debug("\n"); print_debug_hex8(i); print_debug(": "); } @@ -227,7 +227,7 @@ if (status < 0) { print_debug("bad device: "); print_debug_hex8(-status); - print_debug("\r\n"); + print_debug("\n"); break; } print_debug_hex8(status); @@ -245,7 +245,7 @@ while(device <= SMBUS_MEM_DEVICE_END) { int status = 0; int i; - print_debug("\r\n"); + print_debug("\n"); print_debug("dimm "); print_debug_hex8(device); @@ -256,7 +256,7 @@ print_debug("present: "); } print_debug_hex8(status); - print_debug("\r\n"); + print_debug("\n"); device += SMBUS_MEM_DEVICE_INC; print_debug("\n"); } @@ -269,7 +269,7 @@ while(device <= 0x42) { int status = 0; int i; - print_debug("\r\n"); + print_debug("\n"); print_debug("ipmi "); print_debug_hex8(device); @@ -279,7 +279,7 @@ if (status < 0) { print_debug("bad device: "); print_debug_hex8(-status); - print_debug("\r\n"); + print_debug("\n"); break; } print_debug_hex8(status); Modified: trunk/src/mainboard/dell/s1850/watchdog.c ============================================================================== --- trunk/src/mainboard/dell/s1850/watchdog.c Wed Mar 31 16:34:40 2010 (r5341) +++ trunk/src/mainboard/dell/s1850/watchdog.c Wed Mar 31 16:47:43 2010 (r5342) @@ -52,6 +52,6 @@ { // disable_sio_watchdog(NSC_WD_DEV); disable_ich5_watchdog(); - print_debug("Watchdogs disabled\r\n"); + print_debug("Watchdogs disabled\n"); } Modified: trunk/src/mainboard/digitallogic/msm586seg/romstage.c ============================================================================== --- trunk/src/mainboard/digitallogic/msm586seg/romstage.c Wed Mar 31 16:34:40 2010 (r5341) +++ trunk/src/mainboard/digitallogic/msm586seg/romstage.c Wed Mar 31 16:47:43 2010 (r5342) @@ -80,7 +80,7 @@ print_err_hex8(c); print_err(" "); } - print_err("\r\n"); + print_err("\n"); } } @@ -190,16 +190,16 @@ uart_init(); console_init(); for(i = 0; i < 100; i++) - print_err("fill usart\r\n"); + print_err("fill usart\n"); // while(1) - print_err("HI THERE!\r\n"); + print_err("HI THERE!\n"); // sizemem(); staticmem(); print_err("c60 is "); print_err_hex16(*(unsigned short *)0xfffefc60); print_err("\n"); // while(1) - print_err("STATIC MEM DONE\r\n"); + print_err("STATIC MEM DONE\n"); outb(0xee, 0x80); print_err("loop forever ...\n"); @@ -227,12 +227,12 @@ #endif #if 0 - print_err("RAM CHECK!\r\n"); + print_err("RAM CHECK!\n"); // Check 16MB of memory @ 0 ram_check(0x00000000, 0x01000000); #endif #if 0 - print_err("RAM CHECK for 32 MB!\r\n"); + print_err("RAM CHECK for 32 MB!\n"); // Check 32MB of memory @ 0 ram_check(0x00000000, 0x02000000); #endif @@ -243,17 +243,17 @@ for(i = 0; i < 0x20000; i++) { /* print_err("Set dst "); print_err_hex32((unsigned long) dst); - print_err(" to "); print_err_hex32(*src); print_err("\r\n"); + print_err(" to "); print_err_hex32(*src); print_err("\n"); */ *dst = *src; - //print_err(" dst is now "); print_err_hex32(*dst); print_err("\r\n"); + //print_err(" dst is now "); print_err_hex32(*dst); print_err("\n"); dst++, src++; outb((unsigned char)i, 0x80); } } dumpmem(); outb(0, 0x80); - print_err("loop forever\r\n"); + print_err("loop forever\n"); outb(0xdd, 0x80); __asm__ volatile( "movl %0, %%edi\n\t" @@ -262,7 +262,7 @@ : "a" (0x4000) ); - print_err("Oh dear, I'm afraid it didn't work...\r\n"); + print_err("Oh dear, I'm afraid it didn't work...\n"); while(1); #endif Modified: trunk/src/mainboard/gigabyte/ga_2761gxdk/ap_romstage.c ============================================================================== --- trunk/src/mainboard/gigabyte/ga_2761gxdk/ap_romstage.c Wed Mar 31 16:34:40 2010 (r5341) +++ trunk/src/mainboard/gigabyte/ga_2761gxdk/ap_romstage.c Wed Mar 31 16:47:43 2010 (r5342) @@ -84,7 +84,7 @@ id = get_node_core_id_x(); //FIXME: for USBDEBUG_DIRECT you need to make sure dbg_info get assigned in AP - print_debug("CODE IN CACHE ON NODE:"); print_debug_hex8(id.nodeid); print_debug("\r\n"); + print_debug("CODE IN CACHE ON NODE:"); print_debug_hex8(id.nodeid); print_debug("\n"); train_ram(id.nodeid, sysinfo, sysinfox); Modified: trunk/src/mainboard/gigabyte/ga_2761gxdk/romstage.c ============================================================================== --- trunk/src/mainboard/gigabyte/ga_2761gxdk/romstage.c Wed Mar 31 16:34:40 2010 (r5341) +++ trunk/src/mainboard/gigabyte/ga_2761gxdk/romstage.c Wed Mar 31 16:47:43 2010 (r5342) @@ -215,7 +215,7 @@ console_init(); printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1); - print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\r\n"); + print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\n"); #if CONFIG_MEM_TRAIN_SEQ == 1 set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram @@ -241,7 +241,7 @@ { msr_t msr; msr=rdmsr(0xc0010042); - print_debug("begin msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\r\n"); + print_debug("begin msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n"); } @@ -255,7 +255,7 @@ { msr_t msr; msr=rdmsr(0xc0010042); - print_debug("end msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\r\n"); + print_debug("end msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n"); } #endif @@ -265,7 +265,7 @@ // fidvid change will issue one LDTSTOP and the HT change will be effective too if (needs_reset) { - print_info("ht reset -\r\n"); + print_info("ht reset -\n"); soft_reset(); } allow_all_aps_stop(bsp_apicid); Modified: trunk/src/mainboard/gigabyte/m57sli/ap_romstage.c ============================================================================== --- trunk/src/mainboard/gigabyte/m57sli/ap_romstage.c Wed Mar 31 16:34:40 2010 (r5341) +++ trunk/src/mainboard/gigabyte/m57sli/ap_romstage.c Wed Mar 31 16:47:43 2010 (r5342) @@ -82,7 +82,7 @@ id = get_node_core_id_x(); //FIXME: for USBDEBUG_DIRECT you need to make sure dbg_info get assigned in AP - print_debug("CODE IN CACHE ON NODE:"); print_debug_hex8(id.nodeid); print_debug("\r\n"); + print_debug("CODE IN CACHE ON NODE:"); print_debug_hex8(id.nodeid); print_debug("\n"); train_ram(id.nodeid, sysinfo, sysinfox); Modified: trunk/src/mainboard/gigabyte/m57sli/romstage.c ============================================================================== --- trunk/src/mainboard/gigabyte/m57sli/romstage.c Wed Mar 31 16:34:40 2010 (r5341) +++ trunk/src/mainboard/gigabyte/m57sli/romstage.c Wed Mar 31 16:47:43 2010 (r5342) @@ -228,7 +228,7 @@ console_init(); printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1); - print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\r\n"); + print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\n"); #if CONFIG_MEM_TRAIN_SEQ == 1 set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram @@ -254,7 +254,7 @@ { msr_t msr; msr=rdmsr(0xc0010042); - print_debug("begin msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\r\n"); + print_debug("begin msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n"); } @@ -268,7 +268,7 @@ { msr_t msr; msr=rdmsr(0xc0010042); - print_debug("end msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\r\n"); + print_debug("end msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n"); } #endif @@ -279,7 +279,7 @@ // fidvid change will issue one LDTSTOP and the HT change will be effective too if (needs_reset) { - print_info("ht reset -\r\n"); + print_info("ht reset -\n"); soft_reset(); } allow_all_aps_stop(bsp_apicid); Modified: trunk/src/mainboard/hp/dl145_g3/romstage.c ============================================================================== --- trunk/src/mainboard/hp/dl145_g3/romstage.c Wed Mar 31 16:34:40 2010 (r5341) +++ trunk/src/mainboard/hp/dl145_g3/romstage.c Wed Mar 31 16:47:43 2010 (r5342) @@ -230,7 +230,7 @@ pilot_early_init(SERIAL_DEV); //config port is being taken from SERIAL_DEV printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1); - print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\r\n"); + print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\n"); #if CONFIG_MEM_TRAIN_SEQ == 1 set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram @@ -256,7 +256,7 @@ { msr_t msr; msr=rdmsr(0xc0010042); - print_debug("begin msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\r\n"); + print_debug("begin msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n"); } enable_fid_change(); enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn); @@ -265,7 +265,7 @@ { msr_t msr; msr=rdmsr(0xc0010042); - print_debug("end msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\r\n"); + print_debug("end msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n"); } #endif @@ -274,7 +274,7 @@ // fidvid change will issue one LDTSTOP and the HT change will be effective too if (needs_reset) { - print_info("ht reset -\r\n"); + print_info("ht reset -\n"); soft_reset(); } Modified: trunk/src/mainboard/ibm/e325/romstage.c ============================================================================== --- trunk/src/mainboard/ibm/e325/romstage.c Wed Mar 31 16:34:40 2010 (r5341) +++ trunk/src/mainboard/ibm/e325/romstage.c Wed Mar 31 16:47:43 2010 (r5342) @@ -151,7 +151,7 @@ needs_reset |= ht_setup_chains_x(); if (needs_reset) { - print_info("ht reset -\r\n"); + print_info("ht reset -\n"); soft_reset(); } Modified: trunk/src/mainboard/ibm/e326/romstage.c ============================================================================== --- trunk/src/mainboard/ibm/e326/romstage.c Wed Mar 31 16:34:40 2010 (r5341) +++ trunk/src/mainboard/ibm/e326/romstage.c Wed Mar 31 16:47:43 2010 (r5342) @@ -151,7 +151,7 @@ needs_reset |= ht_setup_chains_x(); if (needs_reset) { - print_info("ht reset -\r\n"); + print_info("ht reset -\n"); soft_reset(); } Modified: trunk/src/mainboard/intel/eagleheights/debug.c ============================================================================== --- trunk/src/mainboard/intel/eagleheights/debug.c Wed Mar 31 16:34:40 2010 (r5341) +++ trunk/src/mainboard/intel/eagleheights/debug.c Wed Mar 31 16:47:43 2010 (r5342) @@ -34,7 +34,7 @@ print_debug_hex8(index); print_debug(": 0x"); print_debug_hex8(data); - print_debug("\r\n"); + print_debug("\n"); return; } @@ -71,52 +71,52 @@ int i; unsigned char data; - print_debug("\r\n*** SERVER I/O REGISTERS ***\r\n"); + print_debug("\n*** SERVER I/O REGISTERS ***\n"); for (i=0x10; i<=0x2d; i++) { print_reg((unsigned char)i); } #if 0 - print_debug("\r\n*** XBUS REGISTERS ***\r\n"); + print_debug("\n*** XBUS REGISTERS ***\n"); setup_func(0x0f); for (i=0xf0; i<=0xff; i++) { print_reg((unsigned char)i); } - print_debug("\r\n*** SERIAL 1 CONFIG REGISTERS ***\r\n"); + print_debug("\n*** SERIAL 1 CONFIG REGISTERS ***\n"); setup_func(0x03); print_reg(0xf0); - print_debug("\r\n*** SERIAL 2 CONFIG REGISTERS ***\r\n"); + print_debug("\n*** SERIAL 2 CONFIG REGISTERS ***\n"); setup_func(0x02); print_reg(0xf0); #endif - print_debug("\r\n*** GPIO REGISTERS ***\r\n"); + print_debug("\n*** GPIO REGISTERS ***\n"); setup_func(0x07); for (i=0xf0; i<=0xf8; i++) { print_reg((unsigned char)i); } - print_debug("\r\n*** GPIO VALUES ***\r\n"); + print_debug("\n*** GPIO VALUES ***\n"); data = inb(0x68a); - print_debug("\r\nGPDO 4: 0x"); + print_debug("\nGPDO 4: 0x"); print_debug_hex8(data); data = inb(0x68b); - print_debug("\r\nGPDI 4: 0x"); + print_debug("\nGPDI 4: 0x"); print_debug_hex8(data); - print_debug("\r\n"); + print_debug("\n"); #if 0 - print_debug("\r\n*** WATCHDOG TIMER REGISTERS ***\r\n"); + print_debug("\n*** WATCHDOG TIMER REGISTERS ***\n"); setup_func(0x0a); print_reg(0xf0); - print_debug("\r\n*** FAN CONTROL REGISTERS ***\r\n"); + print_debug("\n*** FAN CONTROL REGISTERS ***\n"); setup_func(0x09); print_reg(0xf0); print_reg(0xf1); - print_debug("\r\n*** RTC REGISTERS ***\r\n"); + print_debug("\n*** RTC REGISTERS ***\n"); setup_func(0x10); print_reg(0xf0); print_reg(0xf1); @@ -126,7 +126,7 @@ print_reg(0xfe); print_reg(0xff); - print_debug("\r\n*** HEALTH MONITORING & CONTROL REGISTERS ***\r\n"); + print_debug("\n*** HEALTH MONITORING & CONTROL REGISTERS ***\n"); setup_func(0x14); print_reg(0xf0); #endif @@ -157,7 +157,7 @@ continue; } print_debug_pci_dev(dev); - print_debug("\r\n"); + print_debug("\n"); } } @@ -165,7 +165,7 @@ { int i; print_debug_pci_dev(dev); - print_debug("\r\n"); + print_debug("\n"); for(i = 0; i <= 255; i++) { unsigned char val; @@ -177,7 +177,7 @@ print_debug_char(' '); print_debug_hex8(val); if ((i & 0x0f) == 0x0f) { - print_debug("\r\n"); + print_debug("\n"); } } } @@ -187,7 +187,7 @@ int i; unsigned long bar; - print_debug("BAR 14 Dump\r\n"); + print_debug("BAR 14 Dump\n"); bar = pci_read_config32(dev, 0x14); for(i = 0; i <= 0x300; i+=4) { @@ -200,14 +200,14 @@ val = pci_read_config8(dev, i); #endif if((i%4)==0) { - print_debug("\r\n"); + print_debug("\n"); print_debug_hex16(i); print_debug_char(' '); } print_debug_hex32(read32(bar + i)); print_debug_char(' '); } - print_debug("\r\n"); + print_debug("\n"); } static void dump_pci_devices(void) @@ -231,7 +231,7 @@ static void dump_spd_registers(const struct mem_controller *ctrl) { int i; - print_debug("\r\n"); + print_debug("\n"); for(i = 0; i < 4; i++) { unsigned device; device = ctrl->channel0[i]; @@ -245,20 +245,20 @@ int status; unsigned char byte; if ((j & 0xf) == 0) { - print_debug("\r\n"); + print_debug("\n"); print_debug_hex8(j); print_debug(": "); } status = smbus_read_byte(device, j); if (status < 0) { - print_debug("bad device\r\n"); + print_debug("bad device\n"); break; } byte = status & 0xff; print_debug_hex8(byte); print_debug_char(' '); } - print_debug("\r\n"); + print_debug("\n"); } device = ctrl->channel1[i]; if (device) { @@ -271,20 +271,20 @@ int status; unsigned char byte; if ((j & 0xf) == 0) { - print_debug("\r\n"); + print_debug("\n"); print_debug_hex8(j); print_debug(": "); } status = smbus_read_byte(device, j); if (status < 0) { - print_debug("bad device\r\n"); + print_debug("bad device\n"); break; } byte = status & 0xff; print_debug_hex8(byte); print_debug_char(' '); } - print_debug("\r\n"); + print_debug("\n"); } } } @@ -297,13 +297,13 @@ while(device <= SMBUS_MEM_DEVICE_END) { int status = 0; int i; - print_debug("\r\n"); + print_debug("\n"); print_debug("dimm "); print_debug_hex8(device); for(i = 0; (i < 256) ; i++) { if ((i % 16) == 0) { - print_debug("\r\n"); + print_debug("\n"); print_debug_hex8(i); print_debug(": "); } @@ -311,7 +311,7 @@ if (status < 0) { print_debug("bad device: "); print_debug_hex8(-status); - print_debug("\r\n"); + print_debug("\n"); break; } print_debug_hex8(status); @@ -329,7 +329,7 @@ while(device <= 0x42) { int status = 0; int i; - print_debug("\r\n"); + print_debug("\n"); print_debug("ipmi "); print_debug_hex8(device); @@ -338,7 +338,7 @@ if (status < 0) { print_debug("bad device: "); print_debug_hex8(-status); - print_debug("\r\n"); + print_debug("\n"); break; } print_debug_hex8(status); Modified: trunk/src/mainboard/intel/jarrell/debug.c ============================================================================== --- trunk/src/mainboard/intel/jarrell/debug.c Wed Mar 31 16:34:40 2010 (r5341) +++ trunk/src/mainboard/intel/jarrell/debug.c Wed Mar 31 16:47:43 2010 (r5342) @@ -12,7 +12,7 @@ print_debug_hex8(index); print_debug(": 0x"); print_debug_hex8(data); - print_debug("\r\n"); + print_debug("\n"); return; } @@ -49,52 +49,52 @@ int i; unsigned char data; - print_debug("\r\n*** SERVER I/O REGISTERS ***\r\n"); + print_debug("\n*** SERVER I/O REGISTERS ***\n"); for (i=0x10; i<=0x2d; i++) { print_reg((unsigned char)i); } #if 0 - print_debug("\r\n*** XBUS REGISTERS ***\r\n"); + print_debug("\n*** XBUS REGISTERS ***\n"); setup_func(0x0f); for (i=0xf0; i<=0xff; i++) { print_reg((unsigned char)i); } - print_debug("\r\n*** SERIAL 1 CONFIG REGISTERS ***\r\n"); + print_debug("\n*** SERIAL 1 CONFIG REGISTERS ***\n"); setup_func(0x03); print_reg(0xf0); - print_debug("\r\n*** SERIAL 2 CONFIG REGISTERS ***\r\n"); + print_debug("\n*** SERIAL 2 CONFIG REGISTERS ***\n"); setup_func(0x02); print_reg(0xf0); #endif - print_debug("\r\n*** GPIO REGISTERS ***\r\n"); + print_debug("\n*** GPIO REGISTERS ***\n"); setup_func(0x07); for (i=0xf0; i<=0xf8; i++) { print_reg((unsigned char)i); } - print_debug("\r\n*** GPIO VALUES ***\r\n"); + print_debug("\n*** GPIO VALUES ***\n"); data = inb(0x68a); - print_debug("\r\nGPDO 4: 0x"); + print_debug("\nGPDO 4: 0x"); print_debug_hex8(data); data = inb(0x68b); - print_debug("\r\nGPDI 4: 0x"); + print_debug("\nGPDI 4: 0x"); print_debug_hex8(data); - print_debug("\r\n"); + print_debug("\n"); #if 0 - print_debug("\r\n*** WATCHDOG TIMER REGISTERS ***\r\n"); + print_debug("\n*** WATCHDOG TIMER REGISTERS ***\n"); setup_func(0x0a); print_reg(0xf0); - print_debug("\r\n*** FAN CONTROL REGISTERS ***\r\n"); + print_debug("\n*** FAN CONTROL REGISTERS ***\n"); setup_func(0x09); print_reg(0xf0); print_reg(0xf1); - print_debug("\r\n*** RTC REGISTERS ***\r\n"); + print_debug("\n*** RTC REGISTERS ***\n"); setup_func(0x10); print_reg(0xf0); print_reg(0xf1); @@ -104,7 +104,7 @@ print_reg(0xfe); print_reg(0xff); - print_debug("\r\n*** HEALTH MONITORING & CONTROL REGISTERS ***\r\n"); + print_debug("\n*** HEALTH MONITORING & CONTROL REGISTERS ***\n"); setup_func(0x14); print_reg(0xf0); #endif @@ -135,7 +135,7 @@ continue; } print_debug_pci_dev(dev); - print_debug("\r\n"); + print_debug("\n"); } } @@ -143,7 +143,7 @@ { int i; print_debug_pci_dev(dev); - print_debug("\r\n"); + print_debug("\n"); for(i = 0; i <= 255; i++) { unsigned char val; @@ -155,7 +155,7 @@ print_debug_char(' '); print_debug_hex8(val); if ((i & 0x0f) == 0x0f) { - print_debug("\r\n"); + print_debug("\n"); } } } @@ -165,7 +165,7 @@ int i; unsigned long bar; - print_debug("BAR 14 Dump\r\n"); + print_debug("BAR 14 Dump\n"); bar = pci_read_config32(dev, 0x14); for(i = 0; i <= 0x300; i+=4) { @@ -178,14 +178,14 @@ val = pci_read_config8(dev, i); #endif if((i%4)==0) { - print_debug("\r\n"); + print_debug("\n"); print_debug_hex16(i); print_debug_char(' '); } print_debug_hex32(read32(bar + i)); print_debug_char(' '); } - print_debug("\r\n"); + print_debug("\n"); } static void dump_pci_devices(void) @@ -209,7 +209,7 @@ static void dump_spd_registers(const struct mem_controller *ctrl) { int i; - print_debug("\r\n"); + print_debug("\n"); for(i = 0; i < 4; i++) { unsigned device; device = ctrl->channel0[i]; @@ -223,20 +223,20 @@ int status; unsigned char byte; if ((j & 0xf) == 0) { - print_debug("\r\n"); + print_debug("\n"); print_debug_hex8(j); print_debug(": "); } status = smbus_read_byte(device, j); if (status < 0) { - print_debug("bad device\r\n"); + print_debug("bad device\n"); break; } byte = status & 0xff; print_debug_hex8(byte); print_debug_char(' '); } - print_debug("\r\n"); + print_debug("\n"); } device = ctrl->channel1[i]; if (device) { @@ -249,20 +249,20 @@ int status; unsigned char byte; if ((j & 0xf) == 0) { - print_debug("\r\n"); + print_debug("\n"); print_debug_hex8(j); print_debug(": "); } status = smbus_read_byte(device, j); if (status < 0) { - print_debug("bad device\r\n"); + print_debug("bad device\n"); break; } byte = status & 0xff; print_debug_hex8(byte); print_debug_char(' '); } - print_debug("\r\n"); + print_debug("\n"); } } } @@ -275,14 +275,14 @@ while(device <= SMBUS_MEM_DEVICE_END) { int status = 0; int i; - print_debug("\r\n"); + print_debug("\n"); print_debug("dimm "); print_debug_hex8(device); for(i = 0; (i < 256) ; i++) { unsigned char byte; if ((i % 16) == 0) { - print_debug("\r\n"); + print_debug("\n"); print_debug_hex8(i); print_debug(": "); } @@ -290,7 +290,7 @@ if (status < 0) { print_debug("bad device: "); print_debug_hex8(-status); - print_debug("\r\n"); + print_debug("\n"); break; } print_debug_hex8(status); @@ -308,7 +308,7 @@ while(device <= 0x42) { int status = 0; int i; - print_debug("\r\n"); + print_debug("\n"); print_debug("ipmi "); print_debug_hex8(device); @@ -318,7 +318,7 @@ if (status < 0) { print_debug("bad device: "); print_debug_hex8(-status); - print_debug("\r\n"); + print_debug("\n"); break; } print_debug_hex8(status); Modified: trunk/src/mainboard/intel/jarrell/jarrell_fixups.c ============================================================================== --- trunk/src/mainboard/intel/jarrell/jarrell_fixups.c Wed Mar 31 16:34:40 2010 (r5341) +++ trunk/src/mainboard/intel/jarrell/jarrell_fixups.c Wed Mar 31 16:47:43 2010 (r5342) @@ -58,12 +58,12 @@ /* set gpio 42,44 signal levels */ data = inb(gpio_index + PC87427_GPDO_4); if ((data & 0x14) == (0xff & (((bits&2)?0:1)<<4 | ((bits&1)?0:1)<<2))) { - print_debug("set_pllsel: correct settings detected!\r\n"); + print_debug("set_pllsel: correct settings detected!\n"); return; /* settings already configured */ } else { outb((data & 0xeb) | ((bits&2)?0:1)<<4 | ((bits&1)?0:1)<<2, gpio_index + PC87427_GPDO_4); /* reset */ - print_debug("set_pllsel: settings adjusted, now resetting...\r\n"); + print_debug("set_pllsel: settings adjusted, now resetting...\n"); // hard_reset(); /* should activate a PCI_RST, which should reset MCH, but it doesn't seem to work ???? */ // mch_reset(); full_reset(); Modified: trunk/src/mainboard/intel/jarrell/power_reset_check.c ============================================================================== --- trunk/src/mainboard/intel/jarrell/power_reset_check.c Wed Mar 31 16:34:40 2010 (r5341) +++ trunk/src/mainboard/intel/jarrell/power_reset_check.c Wed Mar 31 16:47:43 2010 (r5342) @@ -6,7 +6,7 @@ cmos=cmos_read(RTC_BOOT_BYTE)>>4 ; print_debug("Boot byte = "); print_debug_hex8(cmos); - print_debug("\r\n"); + print_debug("\n"); if((cmos>2)&&(cmos&1)) full_reset(); } Modified: trunk/src/mainboard/intel/jarrell/watchdog.c ============================================================================== --- trunk/src/mainboard/intel/jarrell/watchdog.c Wed Mar 31 16:34:40 2010 (r5341) +++ trunk/src/mainboard/intel/jarrell/watchdog.c Wed Mar 31 16:47:43 2010 (r5342) @@ -91,7 +91,7 @@ disable_sio_watchdog(NSC_WD_DEV); disable_ich5_watchdog(); disable_jarell_frb3(); - print_debug("Watchdogs disabled\r\n"); + print_debug("Watchdogs disabled\n"); } static void ich5_watchdog_on(void) @@ -134,5 +134,5 @@ value &= ~(1 << 11); outw(value, base + 0x08); - print_debug("Watchdog ICH5 enabled\r\n"); + print_debug("Watchdog ICH5 enabled\n"); } Modified: trunk/src/mainboard/intel/xe7501devkit/romstage.c ============================================================================== --- trunk/src/mainboard/intel/xe7501devkit/romstage.c Wed Mar 31 16:34:40 2010 (r5341) +++ trunk/src/mainboard/intel/xe7501devkit/romstage.c Wed Mar 31 16:47:43 2010 (r5342) @@ -86,6 +86,6 @@ // NOTE: ROMCC dies with an internal compiler error // if the following line is removed. - print_debug("SDRAM is up.\r\n"); + print_debug("SDRAM is up.\n"); } Modified: trunk/src/mainboard/iwill/dk8_htx/romstage.c ============================================================================== --- trunk/src/mainboard/iwill/dk8_htx/romstage.c Wed Mar 31 16:34:40 2010 (r5341) +++ trunk/src/mainboard/iwill/dk8_htx/romstage.c Wed Mar 31 16:47:43 2010 (r5342) @@ -167,7 +167,7 @@ setup_mb_resource_map(); - print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\r\n"); + print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\n"); #if CONFIG_MEM_TRAIN_SEQ == 1 set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram @@ -193,7 +193,7 @@ { msr_t msr; msr=rdmsr(0xc0010042); - print_debug("begin msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\r\n"); + print_debug("begin msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n"); } @@ -207,7 +207,7 @@ { msr_t msr; msr=rdmsr(0xc0010042); - print_debug("end msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\r\n"); + print_debug("end msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n"); } #endif @@ -217,7 +217,7 @@ // fidvid change will issue one LDTSTOP and the HT change will be effective too if (needs_reset) { - print_info("ht reset -\r\n"); + print_info("ht reset -\n"); soft_reset_x(sysinfo->sbbusn, sysinfo->sbdn); } Modified: trunk/src/mainboard/iwill/dk8s2/romstage.c ============================================================================== --- trunk/src/mainboard/iwill/dk8s2/romstage.c Wed Mar 31 16:34:40 2010 (r5341) +++ trunk/src/mainboard/iwill/dk8s2/romstage.c Wed Mar 31 16:47:43 2010 (r5342) @@ -167,7 +167,7 @@ setup_default_resource_map(); - print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\r\n"); + print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\n"); #if CONFIG_MEM_TRAIN_SEQ == 1 set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram @@ -193,7 +193,7 @@ { msr_t msr; msr=rdmsr(0xc0010042); - print_debug("begin msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\r\n"); + print_debug("begin msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n"); } @@ -207,7 +207,7 @@ { msr_t msr; msr=rdmsr(0xc0010042); - print_debug("end msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\r\n"); + print_debug("end msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n"); } #endif @@ -217,7 +217,7 @@ // fidvid change will issue one LDTSTOP and the HT change will be effective too if (needs_reset) { - print_info("ht reset -\r\n"); + print_info("ht reset -\n"); soft_reset_x(sysinfo->sbbusn, sysinfo->sbdn); } Modified: trunk/src/mainboard/iwill/dk8x/romstage.c ============================================================================== --- trunk/src/mainboard/iwill/dk8x/romstage.c Wed Mar 31 16:34:40 2010 (r5341) +++ trunk/src/mainboard/iwill/dk8x/romstage.c Wed Mar 31 16:47:43 2010 (r5342) @@ -167,7 +167,7 @@ setup_default_resource_map(); - print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\r\n"); + print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\n"); #if CONFIG_MEM_TRAIN_SEQ == 1 set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram @@ -193,7 +193,7 @@ { msr_t msr; msr=rdmsr(0xc0010042); - print_debug("begin msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\r\n"); + print_debug("begin msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n"); } @@ -207,7 +207,7 @@ { msr_t msr; msr=rdmsr(0xc0010042); - print_debug("end msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\r\n"); + print_debug("end msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n"); } #endif @@ -217,7 +217,7 @@ // fidvid change will issue one LDTSTOP and the HT change will be effective too if (needs_reset) { - print_info("ht reset -\r\n"); + print_info("ht reset -\n"); soft_reset_x(sysinfo->sbbusn, sysinfo->sbdn); } Modified: trunk/src/mainboard/jetway/j7f24/romstage.c ============================================================================== --- trunk/src/mainboard/jetway/j7f24/romstage.c Wed Mar 31 16:34:40 2010 (r5341) +++ trunk/src/mainboard/jetway/j7f24/romstage.c Wed Mar 31 16:47:43 2010 (r5342) @@ -103,26 +103,26 @@ uart_init(); console_init(); - print_spew("In romstage.c:main()\r\n"); + print_spew("In romstage.c:main()\n"); enable_smbus(); smbus_fixup(&ctrl); if (bist == 0) { - print_debug("doing early_mtrr\r\n"); + print_debug("doing early_mtrr\n"); early_mtrr_init(); } /* Halt if there was a built-in self test failure. */ report_bist_failure(bist); - print_debug("Enabling mainboard devices\r\n"); + print_debug("Enabling mainboard devices\n"); enable_mainboard_devices(); ddr_ram_setup(&ctrl); /* ram_check(0, 640 * 1024); */ - print_spew("Leaving romstage.c:main()\r\n"); + print_spew("Leaving romstage.c:main()\n"); } Modified: trunk/src/mainboard/kontron/kt690/romstage.c ============================================================================== --- trunk/src/mainboard/kontron/kt690/romstage.c Wed Mar 31 16:34:40 2010 (r5341) +++ trunk/src/mainboard/kontron/kt690/romstage.c Wed Mar 31 16:47:43 2010 (r5342) @@ -180,7 +180,7 @@ printk(BIOS_DEBUG, "needs_reset=0x%x\n", needs_reset); if (needs_reset) { - print_info("ht reset -\r\n"); + print_info("ht reset -\n"); soft_reset(); } Modified: trunk/src/mainboard/lippert/frontrunner/romstage.c ============================================================================== --- trunk/src/mainboard/lippert/frontrunner/romstage.c Wed Mar 31 16:34:40 2010 (r5341) +++ trunk/src/mainboard/lippert/frontrunner/romstage.c Wed Mar 31 16:47:43 2010 (r5342) @@ -24,7 +24,7 @@ msr_t msr; /* 1. Initialize GLMC registers base on SPD values, * Hard coded as XpressROM for now */ - //print_debug("sdram_enable step 1\r\n"); + //print_debug("sdram_enable step 1\n"); msr = rdmsr(0x20000018); msr.hi = 0x10076013; msr.lo = 0x3400; Modified: trunk/src/mainboard/lippert/spacerunner-lx/romstage.c ============================================================================== --- trunk/src/mainboard/lippert/spacerunner-lx/romstage.c Wed Mar 31 16:34:40 2010 (r5341) +++ trunk/src/mainboard/lippert/spacerunner-lx/romstage.c Wed Mar 31 16:47:43 2010 (r5342) @@ -91,7 +91,7 @@ if (address >= sizeof(spdbytes) || spdbytes[address] == 0xFF) { print_err("ERROR: spd_read_byte(DIMM0, 0x"); print_err_hex8(address); - print_err(") returns 0xff\r\n"); + print_err(") returns 0xff\n"); } #endif @@ -222,7 +222,7 @@ if ((err = smc_send_config(SMC_CONFIG))) { print_err("ERROR "); print_err_char('0'+err); - print_err(" sending config data to SMC\r\n"); + print_err(" sending config data to SMC\n"); } sdram_initialize(1, memctrl); Modified: trunk/src/mainboard/msi/ms7135/romstage.c ============================================================================== --- trunk/src/mainboard/msi/ms7135/romstage.c Wed Mar 31 16:34:40 2010 (r5341) +++ trunk/src/mainboard/msi/ms7135/romstage.c Wed Mar 31 16:47:43 2010 (r5342) @@ -169,7 +169,7 @@ needs_reset |= ck804_early_setup_x(); if (needs_reset) { - print_info("ht reset -\r\n"); + print_info("ht reset -\n"); soft_reset(); } Modified: trunk/src/mainboard/msi/ms7260/ap_romstage.c ============================================================================== --- trunk/src/mainboard/msi/ms7260/ap_romstage.c Wed Mar 31 16:34:40 2010 (r5341) +++ trunk/src/mainboard/msi/ms7260/ap_romstage.c Wed Mar 31 16:47:43 2010 (r5342) @@ -72,7 +72,7 @@ */ print_debug("CODE IN CACHE ON NODE:"); print_debug_hex8(id.nodeid); - print_debug("\r\n"); + print_debug("\n"); train_ram(id.nodeid, sysinfo, sysinfox); Modified: trunk/src/mainboard/msi/ms7260/romstage.c ============================================================================== --- trunk/src/mainboard/msi/ms7260/romstage.c Wed Mar 31 16:34:40 2010 (r5341) +++ trunk/src/mainboard/msi/ms7260/romstage.c Wed Mar 31 16:47:43 2010 (r5342) @@ -190,7 +190,7 @@ printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1); print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); - print_debug("\r\n"); + print_debug("\n"); #if CONFIG_MEM_TRAIN_SEQ == 1 /* In BSP so could hold all AP until sysinfo is in RAM. */ @@ -220,7 +220,7 @@ print_debug("begin msr fid, vid "); print_debug_hex32(msr.hi); print_debug_hex32(msr.lo); - print_debug("\r\n"); + print_debug("\n"); } enable_fid_change(); @@ -232,7 +232,7 @@ print_debug("end msr fid, vid "); print_debug_hex32(msr.hi); print_debug_hex32(msr.lo); - print_debug("\r\n"); + print_debug("\n"); } #endif @@ -242,7 +242,7 @@ /* fidvid change will issue one LDTSTOP and the HT change will be effective too. */ if (needs_reset) { - print_info("ht reset -\r\n"); + print_info("ht reset -\n"); soft_reset(); } allow_all_aps_stop(bsp_apicid); Modified: trunk/src/mainboard/msi/ms9185/romstage.c ============================================================================== --- trunk/src/mainboard/msi/ms9185/romstage.c Wed Mar 31 16:34:40 2010 (r5341) +++ trunk/src/mainboard/msi/ms9185/romstage.c Wed Mar 31 16:47:43 2010 (r5342) @@ -204,7 +204,7 @@ dump_pci_device(PCI_DEV(0, 0x19, 0)); #endif - print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\r\n"); + print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\n"); setup_coherent_ht_domain(); @@ -235,7 +235,7 @@ { msr_t msr; msr=rdmsr(0xc0010042); - print_debug("begin msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\r\n"); + print_debug("begin msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n"); } @@ -249,7 +249,7 @@ { msr_t msr; msr=rdmsr(0xc0010042); - print_debug("end msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\r\n"); + print_debug("end msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n"); } #endif @@ -260,7 +260,7 @@ // fidvid change will issue one LDTSTOP and the HT change will be effective too if (needs_reset) { - print_info("ht reset -\r\n"); + print_info("ht reset -\n"); soft_reset(); } #endif Modified: trunk/src/mainboard/msi/ms9282/romstage.c ============================================================================== --- trunk/src/mainboard/msi/ms9282/romstage.c Wed Mar 31 16:34:40 2010 (r5341) +++ trunk/src/mainboard/msi/ms9282/romstage.c Wed Mar 31 16:47:43 2010 (r5342) @@ -214,7 +214,7 @@ needs_reset |= mcp55_early_setup_x(); if (needs_reset) { - print_info("ht reset -\r\n"); + print_info("ht reset -\n"); soft_reset(); } Modified: trunk/src/mainboard/newisys/khepri/romstage.c ============================================================================== --- trunk/src/mainboard/newisys/khepri/romstage.c Wed Mar 31 16:34:40 2010 (r5341) +++ trunk/src/mainboard/newisys/khepri/romstage.c Wed Mar 31 16:47:43 2010 (r5342) @@ -168,7 +168,7 @@ needs_reset |= ht_setup_chains_x(); if (needs_reset) { - print_info("ht reset -\r\n"); + print_info("ht reset -\n"); soft_reset(); } Modified: trunk/src/mainboard/nvidia/l1_2pvv/ap_romstage.c ============================================================================== --- trunk/src/mainboard/nvidia/l1_2pvv/ap_romstage.c Wed Mar 31 16:34:40 2010 (r5341) +++ trunk/src/mainboard/nvidia/l1_2pvv/ap_romstage.c Wed Mar 31 16:47:43 2010 (r5342) @@ -82,7 +82,7 @@ id = get_node_core_id_x(); //FIXME: for USBDEBUG_DIRECT you need to make sure dbg_info get assigned in AP - print_debug("CODE IN CACHE ON NODE:"); print_debug_hex8(id.nodeid); print_debug("\r\n"); + print_debug("CODE IN CACHE ON NODE:"); print_debug_hex8(id.nodeid); print_debug("\n"); train_ram(id.nodeid, sysinfo, sysinfox); Modified: trunk/src/mainboard/nvidia/l1_2pvv/romstage.c ============================================================================== --- trunk/src/mainboard/nvidia/l1_2pvv/romstage.c Wed Mar 31 16:34:40 2010 (r5341) +++ trunk/src/mainboard/nvidia/l1_2pvv/romstage.c Wed Mar 31 16:47:43 2010 (r5342) @@ -215,7 +215,7 @@ console_init(); printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1); - print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\r\n"); + print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\n"); #if CONFIG_MEM_TRAIN_SEQ == 1 set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram @@ -241,7 +241,7 @@ { msr_t msr; msr=rdmsr(0xc0010042); - print_debug("begin msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\r\n"); + print_debug("begin msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n"); } @@ -255,7 +255,7 @@ { msr_t msr; msr=rdmsr(0xc0010042); - print_debug("end msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\r\n"); + print_debug("end msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n"); } #endif @@ -266,7 +266,7 @@ // fidvid change will issue one LDTSTOP and the HT change will be effective too if (needs_reset) { - print_info("ht reset -\r\n"); + print_info("ht reset -\n"); soft_reset(); } allow_all_aps_stop(bsp_apicid); Modified: trunk/src/mainboard/olpc/btest/romstage.c ============================================================================== --- trunk/src/mainboard/olpc/btest/romstage.c Wed Mar 31 16:34:40 2010 (r5341) +++ trunk/src/mainboard/olpc/btest/romstage.c Wed Mar 31 16:47:43 2010 (r5342) @@ -90,7 +90,7 @@ print_debug("computed msr.hi "); print_debug_hex32(msr.hi); - print_debug("\r\n"); + print_debug("\n"); /* this is a standard value, DOES NOT PROBABLY MATCH FROM ABOVE */ /* well, it may be close. It's about 200,000 ticks */ Modified: trunk/src/mainboard/olpc/rev_a/romstage.c ============================================================================== --- trunk/src/mainboard/olpc/rev_a/romstage.c Wed Mar 31 16:34:40 2010 (r5341) +++ trunk/src/mainboard/olpc/rev_a/romstage.c Wed Mar 31 16:47:43 2010 (r5342) @@ -90,7 +90,7 @@ print_debug("computed msr.hi "); print_debug_hex32(msr.hi); - print_debug("\r\n"); + print_debug("\n"); /* this is a standard value, DOES NOT PROBABLY MATCH FROM ABOVE */ /* well, it may be close. It's about 200,000 ticks */ Modified: trunk/src/mainboard/pcengines/alix1c/romstage.c ============================================================================== --- trunk/src/mainboard/pcengines/alix1c/romstage.c Wed Mar 31 16:34:40 2010 (r5341) +++ trunk/src/mainboard/pcengines/alix1c/romstage.c Wed Mar 31 16:47:43 2010 (r5342) @@ -98,7 +98,7 @@ print_debug_hex8(address); print_debug(" returns "); print_debug_hex8(spdbytes[address]); - print_debug("\r\n"); + print_debug("\n"); return spdbytes[address]; } Modified: trunk/src/mainboard/sunw/ultra40/romstage.c ============================================================================== --- trunk/src/mainboard/sunw/ultra40/romstage.c Wed Mar 31 16:34:40 2010 (r5341) +++ trunk/src/mainboard/sunw/ultra40/romstage.c Wed Mar 31 16:47:43 2010 (r5342) @@ -193,7 +193,7 @@ needs_reset |= ck804_early_setup_x(); if (needs_reset) { - print_info("ht reset -\r\n"); + print_info("ht reset -\n"); soft_reset(); } Modified: trunk/src/mainboard/supermicro/h8dme/ap_romstage.c ============================================================================== --- trunk/src/mainboard/supermicro/h8dme/ap_romstage.c Wed Mar 31 16:34:40 2010 (r5341) +++ trunk/src/mainboard/supermicro/h8dme/ap_romstage.c Wed Mar 31 16:47:43 2010 (r5342) @@ -86,7 +86,7 @@ id = get_node_core_id_x(); - print_debug("CODE IN CACHE ON NODE:"); print_debug_hex8(id.nodeid); print_debug("\r\n"); + print_debug("CODE IN CACHE ON NODE:"); print_debug_hex8(id.nodeid); print_debug("\n"); train_ram(id.nodeid, sysinfo, sysinfox); Modified: trunk/src/mainboard/supermicro/h8dme/romstage.c ============================================================================== --- trunk/src/mainboard/supermicro/h8dme/romstage.c Wed Mar 31 16:34:40 2010 (r5341) +++ trunk/src/mainboard/supermicro/h8dme/romstage.c Wed Mar 31 16:47:43 2010 (r5342) @@ -94,7 +94,7 @@ { u32 device; - print_debug("\r\n"); + print_debug("\n"); for (device = 1; device < 0x80; device++) { int j; if (smbus_read_byte(device, 0) < 0) @@ -108,12 +108,12 @@ break; } if ((j & 0xf) == 0) { - printk(BIOS_DEBUG, "\r\n%02x: ", j); + printk(BIOS_DEBUG, "\n%02x: ", j); } byte = status & 0xff; printk(BIOS_DEBUG, "%02x ", byte); } - print_debug("\r\n"); + print_debug("\n"); } } @@ -137,13 +137,13 @@ smbus_send_byte(SMBUS_SWITCH1, device & 0x0f); smbus_send_byte_one(SMBUS_SWITCH2, (device >> 4) & 0x0f); int ret; - print_debug("change_i2c_mux i="); print_debug_hex8(device); print_debug("\r\n"); + print_debug("change_i2c_mux i="); print_debug_hex8(device); print_debug("\n"); dump_smbus_registers(); ret = smbus_send_byte(SMBUS_SWITCH1, device); - print_debug("change_i2c_mux ret="); print_debug_hex32(ret); print_debug("\r\n"); + print_debug("change_i2c_mux ret="); print_debug_hex32(ret); print_debug("\n"); dump_smbus_registers(); ret = smbus_send_byte_one(SMBUS_SWITCH2, device); - print_debug("change_i2c_mux ret="); print_debug_hex32(ret); print_debug("\r\n"); + print_debug("change_i2c_mux ret="); print_debug_hex32(ret); print_debug("\n"); dump_smbus_registers(); } */ @@ -273,7 +273,7 @@ print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); - print_debug("\r\n"); + print_debug("\n"); #if CONFIG_MEM_TRAIN_SEQ == 1 set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram @@ -303,7 +303,7 @@ print_debug("begin msr fid, vid "); print_debug_hex32(msr.hi); print_debug_hex32(msr.lo); - print_debug("\r\n"); + print_debug("\n"); } @@ -320,7 +320,7 @@ print_debug("end msr fid, vid "); print_debug_hex32(msr.hi); print_debug_hex32(msr.lo); - print_debug("\r\n"); + print_debug("\n"); } #endif @@ -332,7 +332,7 @@ // fidvid change will issue one LDTSTOP and the HT change will be effective too if (needs_reset) { - print_info("ht reset -\r\n"); + print_info("ht reset -\n"); soft_reset(); } #endif Modified: trunk/src/mainboard/supermicro/h8dmr/ap_romstage.c ============================================================================== --- trunk/src/mainboard/supermicro/h8dmr/ap_romstage.c Wed Mar 31 16:34:40 2010 (r5341) +++ trunk/src/mainboard/supermicro/h8dmr/ap_romstage.c Wed Mar 31 16:47:43 2010 (r5342) @@ -86,7 +86,7 @@ id = get_node_core_id_x(); - print_debug("CODE IN CACHE ON NODE:"); print_debug_hex8(id.nodeid); print_debug("\r\n"); + print_debug("CODE IN CACHE ON NODE:"); print_debug_hex8(id.nodeid); print_debug("\n"); train_ram(id.nodeid, sysinfo, sysinfox); Modified: trunk/src/mainboard/supermicro/h8dmr/romstage.c ============================================================================== --- trunk/src/mainboard/supermicro/h8dmr/romstage.c Wed Mar 31 16:34:40 2010 (r5341) +++ trunk/src/mainboard/supermicro/h8dmr/romstage.c Wed Mar 31 16:47:43 2010 (r5342) @@ -202,7 +202,7 @@ setup_mb_resource_map(); - print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\r\n"); + print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\n"); #if CONFIG_MEM_TRAIN_SEQ == 1 set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram @@ -228,7 +228,7 @@ { msr_t msr; msr=rdmsr(0xc0010042); - print_debug("begin msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\r\n"); + print_debug("begin msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n"); } @@ -242,7 +242,7 @@ { msr_t msr; msr=rdmsr(0xc0010042); - print_debug("end msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\r\n"); + print_debug("end msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n"); } #endif @@ -254,7 +254,7 @@ // fidvid change will issue one LDTSTOP and the HT change will be effective too if (needs_reset) { - print_info("ht reset -\r\n"); + print_info("ht reset -\n"); soft_reset(); } #endif Modified: trunk/src/mainboard/supermicro/x6dai_g/debug.c ============================================================================== --- trunk/src/mainboard/supermicro/x6dai_g/debug.c Wed Mar 31 16:34:40 2010 (r5341) +++ trunk/src/mainboard/supermicro/x6dai_g/debug.c Wed Mar 31 16:47:43 2010 (r5342) @@ -12,7 +12,7 @@ print_debug_hex8(index); print_debug(": 0x"); print_debug_hex8(data); - print_debug("\r\n"); + print_debug("\n"); return; } @@ -49,52 +49,52 @@ int i; unsigned char data; - print_debug("\r\n*** SERVER I/O REGISTERS ***\r\n"); + print_debug("\n*** SERVER I/O REGISTERS ***\n"); for (i=0x10; i<=0x2d; i++) { print_reg((unsigned char)i); } #if 0 - print_debug("\r\n*** XBUS REGISTERS ***\r\n"); + print_debug("\n*** XBUS REGISTERS ***\n"); setup_func(0x0f); for (i=0xf0; i<=0xff; i++) { print_reg((unsigned char)i); } - print_debug("\r\n*** SERIAL 1 CONFIG REGISTERS ***\r\n"); + print_debug("\n*** SERIAL 1 CONFIG REGISTERS ***\n"); setup_func(0x03); print_reg(0xf0); - print_debug("\r\n*** SERIAL 2 CONFIG REGISTERS ***\r\n"); + print_debug("\n*** SERIAL 2 CONFIG REGISTERS ***\n"); setup_func(0x02); print_reg(0xf0); #endif - print_debug("\r\n*** GPIO REGISTERS ***\r\n"); + print_debug("\n*** GPIO REGISTERS ***\n"); setup_func(0x07); for (i=0xf0; i<=0xf8; i++) { print_reg((unsigned char)i); } - print_debug("\r\n*** GPIO VALUES ***\r\n"); + print_debug("\n*** GPIO VALUES ***\n"); data = inb(0x68a); - print_debug("\r\nGPDO 4: 0x"); + print_debug("\nGPDO 4: 0x"); print_debug_hex8(data); data = inb(0x68b); - print_debug("\r\nGPDI 4: 0x"); + print_debug("\nGPDI 4: 0x"); print_debug_hex8(data); - print_debug("\r\n"); + print_debug("\n"); #if 0 - print_debug("\r\n*** WATCHDOG TIMER REGISTERS ***\r\n"); + print_debug("\n*** WATCHDOG TIMER REGISTERS ***\n"); setup_func(0x0a); print_reg(0xf0); - print_debug("\r\n*** FAN CONTROL REGISTERS ***\r\n"); + print_debug("\n*** FAN CONTROL REGISTERS ***\n"); setup_func(0x09); print_reg(0xf0); print_reg(0xf1); - print_debug("\r\n*** RTC REGISTERS ***\r\n"); + print_debug("\n*** RTC REGISTERS ***\n"); setup_func(0x10); print_reg(0xf0); print_reg(0xf1); @@ -104,7 +104,7 @@ print_reg(0xfe); print_reg(0xff); - print_debug("\r\n*** HEALTH MONITORING & CONTROL REGISTERS ***\r\n"); + print_debug("\n*** HEALTH MONITORING & CONTROL REGISTERS ***\n"); setup_func(0x14); print_reg(0xf0); #endif @@ -135,7 +135,7 @@ continue; } print_debug_pci_dev(dev); - print_debug("\r\n"); + print_debug("\n"); } } @@ -143,7 +143,7 @@ { int i; print_debug_pci_dev(dev); - print_debug("\r\n"); + print_debug("\n"); for(i = 0; i <= 255; i++) { unsigned char val; @@ -155,7 +155,7 @@ print_debug_char(' '); print_debug_hex8(val); if ((i & 0x0f) == 0x0f) { - print_debug("\r\n"); + print_debug("\n"); } } } @@ -165,7 +165,7 @@ int i; unsigned long bar; - print_debug("BAR 14 Dump\r\n"); + print_debug("BAR 14 Dump\n"); bar = pci_read_config32(dev, 0x14); for(i = 0; i <= 0x300; i+=4) { @@ -178,14 +178,14 @@ val = pci_read_config8(dev, i); #endif if((i%4)==0) { - print_debug("\r\n"); + print_debug("\n"); print_debug_hex16(i); print_debug_char(' '); } print_debug_hex32(read32(bar + i)); print_debug_char(' '); } - print_debug("\r\n"); + print_debug("\n"); } static void dump_pci_devices(void) @@ -209,7 +209,7 @@ static void dump_spd_registers(const struct mem_controller *ctrl) { int i; - print_debug("\r\n"); + print_debug("\n"); for(i = 0; i < 4; i++) { unsigned device; device = ctrl->channel0[i]; @@ -223,20 +223,20 @@ int status; unsigned char byte; if ((j & 0xf) == 0) { - print_debug("\r\n"); + print_debug("\n"); print_debug_hex8(j); print_debug(": "); } status = smbus_read_byte(device, j); if (status < 0) { - print_debug("bad device\r\n"); + print_debug("bad device\n"); break; } byte = status & 0xff; print_debug_hex8(byte); print_debug_char(' '); } - print_debug("\r\n"); + print_debug("\n"); } device = ctrl->channel1[i]; if (device) { @@ -249,20 +249,20 @@ int status; unsigned char byte; if ((j & 0xf) == 0) { - print_debug("\r\n"); + print_debug("\n"); print_debug_hex8(j); print_debug(": "); } status = smbus_read_byte(device, j); if (status < 0) { - print_debug("bad device\r\n"); + print_debug("bad device\n"); break; } byte = status & 0xff; print_debug_hex8(byte); print_debug_char(' '); } - print_debug("\r\n"); + print_debug("\n"); } } } @@ -275,14 +275,14 @@ while(device <= SMBUS_MEM_DEVICE_END) { int status = 0; int i; - print_debug("\r\n"); + print_debug("\n"); print_debug("dimm "); print_debug_hex8(device); for(i = 0; (i < 256) ; i++) { unsigned char byte; if ((i % 16) == 0) { - print_debug("\r\n"); + print_debug("\n"); print_debug_hex8(i); print_debug(": "); } @@ -290,7 +290,7 @@ if (status < 0) { print_debug("bad device: "); print_debug_hex8(-status); - print_debug("\r\n"); + print_debug("\n"); break; } print_debug_hex8(status); @@ -308,7 +308,7 @@ while(device <= 0x42) { int status = 0; int i; - print_debug("\r\n"); + print_debug("\n"); print_debug("ipmi "); print_debug_hex8(device); @@ -318,7 +318,7 @@ if (status < 0) { print_debug("bad device: "); print_debug_hex8(-status); - print_debug("\r\n"); + print_debug("\n"); break; } print_debug_hex8(status); Modified: trunk/src/mainboard/supermicro/x6dai_g/watchdog.c ============================================================================== --- trunk/src/mainboard/supermicro/x6dai_g/watchdog.c Wed Mar 31 16:34:40 2010 (r5341) +++ trunk/src/mainboard/supermicro/x6dai_g/watchdog.c Wed Mar 31 16:47:43 2010 (r5342) @@ -37,6 +37,6 @@ static void disable_watchdogs(void) { disable_esb6300_watchdog(); - print_debug("Watchdogs disabled\r\n"); + print_debug("Watchdogs disabled\n"); } Modified: trunk/src/mainboard/supermicro/x6dhe_g/debug.c ============================================================================== --- trunk/src/mainboard/supermicro/x6dhe_g/debug.c Wed Mar 31 16:34:40 2010 (r5341) +++ trunk/src/mainboard/supermicro/x6dhe_g/debug.c Wed Mar 31 16:47:43 2010 (r5342) @@ -12,7 +12,7 @@ print_debug_hex8(index); print_debug(": 0x"); print_debug_hex8(data); - print_debug("\r\n"); + print_debug("\n"); return; } @@ -49,52 +49,52 @@ int i; unsigned char data; - print_debug("\r\n*** SERVER I/O REGISTERS ***\r\n"); + print_debug("\n*** SERVER I/O REGISTERS ***\n"); for (i=0x10; i<=0x2d; i++) { print_reg((unsigned char)i); } #if 0 - print_debug("\r\n*** XBUS REGISTERS ***\r\n"); + print_debug("\n*** XBUS REGISTERS ***\n"); setup_func(0x0f); for (i=0xf0; i<=0xff; i++) { print_reg((unsigned char)i); } - print_debug("\r\n*** SERIAL 1 CONFIG REGISTERS ***\r\n"); + print_debug("\n*** SERIAL 1 CONFIG REGISTERS ***\n"); setup_func(0x03); print_reg(0xf0); - print_debug("\r\n*** SERIAL 2 CONFIG REGISTERS ***\r\n"); + print_debug("\n*** SERIAL 2 CONFIG REGISTERS ***\n"); setup_func(0x02); print_reg(0xf0); #endif - print_debug("\r\n*** GPIO REGISTERS ***\r\n"); + print_debug("\n*** GPIO REGISTERS ***\n"); setup_func(0x07); for (i=0xf0; i<=0xf8; i++) { print_reg((unsigned char)i); } - print_debug("\r\n*** GPIO VALUES ***\r\n"); + print_debug("\n*** GPIO VALUES ***\n"); data = inb(0x68a); - print_debug("\r\nGPDO 4: 0x"); + print_debug("\nGPDO 4: 0x"); print_debug_hex8(data); data = inb(0x68b); - print_debug("\r\nGPDI 4: 0x"); + print_debug("\nGPDI 4: 0x"); print_debug_hex8(data); - print_debug("\r\n"); + print_debug("\n"); #if 0 - print_debug("\r\n*** WATCHDOG TIMER REGISTERS ***\r\n"); + print_debug("\n*** WATCHDOG TIMER REGISTERS ***\n"); setup_func(0x0a); print_reg(0xf0); - print_debug("\r\n*** FAN CONTROL REGISTERS ***\r\n"); + print_debug("\n*** FAN CONTROL REGISTERS ***\n"); setup_func(0x09); print_reg(0xf0); print_reg(0xf1); - print_debug("\r\n*** RTC REGISTERS ***\r\n"); + print_debug("\n*** RTC REGISTERS ***\n"); setup_func(0x10); print_reg(0xf0); print_reg(0xf1); @@ -104,7 +104,7 @@ print_reg(0xfe); print_reg(0xff); - print_debug("\r\n*** HEALTH MONITORING & CONTROL REGISTERS ***\r\n"); + print_debug("\n*** HEALTH MONITORING & CONTROL REGISTERS ***\n"); setup_func(0x14); print_reg(0xf0); #endif @@ -135,7 +135,7 @@ continue; } print_debug_pci_dev(dev); - print_debug("\r\n"); + print_debug("\n"); } } @@ -143,7 +143,7 @@ { int i; print_debug_pci_dev(dev); - print_debug("\r\n"); + print_debug("\n"); for(i = 0; i <= 255; i++) { unsigned char val; @@ -155,7 +155,7 @@ print_debug_char(' '); print_debug_hex8(val); if ((i & 0x0f) == 0x0f) { - print_debug("\r\n"); + print_debug("\n"); } } } @@ -165,7 +165,7 @@ int i; unsigned long bar; - print_debug("BAR 14 Dump\r\n"); + print_debug("BAR 14 Dump\n"); bar = pci_read_config32(dev, 0x14); for(i = 0; i <= 0x300; i+=4) { @@ -178,14 +178,14 @@ val = pci_read_config8(dev, i); #endif if((i%4)==0) { - print_debug("\r\n"); + print_debug("\n"); print_debug_hex16(i); print_debug_char(' '); } print_debug_hex32(read32(bar + i)); print_debug_char(' '); } - print_debug("\r\n"); + print_debug("\n"); } static void dump_pci_devices(void) @@ -209,7 +209,7 @@ static void dump_spd_registers(const struct mem_controller *ctrl) { int i; - print_debug("\r\n"); + print_debug("\n"); for(i = 0; i < 4; i++) { unsigned device; device = ctrl->channel0[i]; @@ -223,20 +223,20 @@ int status; unsigned char byte; if ((j & 0xf) == 0) { - print_debug("\r\n"); + print_debug("\n"); print_debug_hex8(j); print_debug(": "); } status = smbus_read_byte(device, j); if (status < 0) { - print_debug("bad device\r\n"); + print_debug("bad device\n"); break; } byte = status & 0xff; print_debug_hex8(byte); print_debug_char(' '); } - print_debug("\r\n"); + print_debug("\n"); } device = ctrl->channel1[i]; if (device) { @@ -249,20 +249,20 @@ int status; unsigned char byte; if ((j & 0xf) == 0) { - print_debug("\r\n"); + print_debug("\n"); print_debug_hex8(j); print_debug(": "); } status = smbus_read_byte(device, j); if (status < 0) { - print_debug("bad device\r\n"); + print_debug("bad device\n"); break; } byte = status & 0xff; print_debug_hex8(byte); print_debug_char(' '); } - print_debug("\r\n"); + print_debug("\n"); } } } @@ -275,14 +275,14 @@ while(device <= SMBUS_MEM_DEVICE_END) { int status = 0; int i; - print_debug("\r\n"); + print_debug("\n"); print_debug("dimm "); print_debug_hex8(device); for(i = 0; (i < 256) ; i++) { unsigned char byte; if ((i % 16) == 0) { - print_debug("\r\n"); + print_debug("\n"); print_debug_hex8(i); print_debug(": "); } @@ -290,7 +290,7 @@ if (status < 0) { print_debug("bad device: "); print_debug_hex8(-status); - print_debug("\r\n"); + print_debug("\n"); break; } print_debug_hex8(status); @@ -308,7 +308,7 @@ while(device <= 0x42) { int status = 0; int i; - print_debug("\r\n"); + print_debug("\n"); print_debug("ipmi "); print_debug_hex8(device); @@ -318,7 +318,7 @@ if (status < 0) { print_debug("bad device: "); print_debug_hex8(-status); - print_debug("\r\n"); + print_debug("\n"); break; } print_debug_hex8(status); Modified: trunk/src/mainboard/supermicro/x6dhe_g/watchdog.c ============================================================================== --- trunk/src/mainboard/supermicro/x6dhe_g/watchdog.c Wed Mar 31 16:34:40 2010 (r5341) +++ trunk/src/mainboard/supermicro/x6dhe_g/watchdog.c Wed Mar 31 16:47:43 2010 (r5342) @@ -94,6 +94,6 @@ // disable_sio_watchdog(NSC_WD_DEV); disable_esb6300_watchdog(); // disable_jarell_frb3(); - print_debug("Watchdogs disabled\r\n"); + print_debug("Watchdogs disabled\n"); } Modified: trunk/src/mainboard/supermicro/x6dhe_g2/debug.c ============================================================================== --- trunk/src/mainboard/supermicro/x6dhe_g2/debug.c Wed Mar 31 16:34:40 2010 (r5341) +++ trunk/src/mainboard/supermicro/x6dhe_g2/debug.c Wed Mar 31 16:47:43 2010 (r5342) @@ -12,7 +12,7 @@ print_debug_hex8(index); print_debug(": 0x"); print_debug_hex8(data); - print_debug("\r\n"); + print_debug("\n"); return; } @@ -49,52 +49,52 @@ int i; unsigned char data; - print_debug("\r\n*** SERVER I/O REGISTERS ***\r\n"); + print_debug("\n*** SERVER I/O REGISTERS ***\n"); for (i=0x10; i<=0x2d; i++) { print_reg((unsigned char)i); } #if 0 - print_debug("\r\n*** XBUS REGISTERS ***\r\n"); + print_debug("\n*** XBUS REGISTERS ***\n"); setup_func(0x0f); for (i=0xf0; i<=0xff; i++) { print_reg((unsigned char)i); } - print_debug("\r\n*** SERIAL 1 CONFIG REGISTERS ***\r\n"); + print_debug("\n*** SERIAL 1 CONFIG REGISTERS ***\n"); setup_func(0x03); print_reg(0xf0); - print_debug("\r\n*** SERIAL 2 CONFIG REGISTERS ***\r\n"); + print_debug("\n*** SERIAL 2 CONFIG REGISTERS ***\n"); setup_func(0x02); print_reg(0xf0); #endif - print_debug("\r\n*** GPIO REGISTERS ***\r\n"); + print_debug("\n*** GPIO REGISTERS ***\n"); setup_func(0x07); for (i=0xf0; i<=0xf8; i++) { print_reg((unsigned char)i); } - print_debug("\r\n*** GPIO VALUES ***\r\n"); + print_debug("\n*** GPIO VALUES ***\n"); data = inb(0x68a); - print_debug("\r\nGPDO 4: 0x"); + print_debug("\nGPDO 4: 0x"); print_debug_hex8(data); data = inb(0x68b); - print_debug("\r\nGPDI 4: 0x"); + print_debug("\nGPDI 4: 0x"); print_debug_hex8(data); - print_debug("\r\n"); + print_debug("\n"); #if 0 - print_debug("\r\n*** WATCHDOG TIMER REGISTERS ***\r\n"); + print_debug("\n*** WATCHDOG TIMER REGISTERS ***\n"); setup_func(0x0a); print_reg(0xf0); - print_debug("\r\n*** FAN CONTROL REGISTERS ***\r\n"); + print_debug("\n*** FAN CONTROL REGISTERS ***\n"); setup_func(0x09); print_reg(0xf0); print_reg(0xf1); - print_debug("\r\n*** RTC REGISTERS ***\r\n"); + print_debug("\n*** RTC REGISTERS ***\n"); setup_func(0x10); print_reg(0xf0); print_reg(0xf1); @@ -104,7 +104,7 @@ print_reg(0xfe); print_reg(0xff); - print_debug("\r\n*** HEALTH MONITORING & CONTROL REGISTERS ***\r\n"); + print_debug("\n*** HEALTH MONITORING & CONTROL REGISTERS ***\n"); setup_func(0x14); print_reg(0xf0); #endif @@ -135,7 +135,7 @@ continue; } print_debug_pci_dev(dev); - print_debug("\r\n"); + print_debug("\n"); } } @@ -143,7 +143,7 @@ { int i; print_debug_pci_dev(dev); - print_debug("\r\n"); + print_debug("\n"); for(i = 0; i <= 255; i++) { unsigned char val; @@ -155,7 +155,7 @@ print_debug_char(' '); print_debug_hex8(val); if ((i & 0x0f) == 0x0f) { - print_debug("\r\n"); + print_debug("\n"); } } } @@ -165,7 +165,7 @@ int i; unsigned long bar; - print_debug("BAR 14 Dump\r\n"); + print_debug("BAR 14 Dump\n"); bar = pci_read_config32(dev, 0x14); for(i = 0; i <= 0x300; i+=4) { @@ -178,14 +178,14 @@ val = pci_read_config8(dev, i); #endif if((i%4)==0) { - print_debug("\r\n"); + print_debug("\n"); print_debug_hex16(i); print_debug_char(' '); } print_debug_hex32(read32(bar + i)); print_debug_char(' '); } - print_debug("\r\n"); + print_debug("\n"); } static void dump_pci_devices(void) @@ -209,7 +209,7 @@ static void dump_spd_registers(const struct mem_controller *ctrl) { int i; - print_debug("\r\n"); + print_debug("\n"); for(i = 0; i < 4; i++) { unsigned device; device = ctrl->channel0[i]; @@ -223,20 +223,20 @@ int status; unsigned char byte; if ((j & 0xf) == 0) { - print_debug("\r\n"); + print_debug("\n"); print_debug_hex8(j); print_debug(": "); } status = smbus_read_byte(device, j); if (status < 0) { - print_debug("bad device\r\n"); + print_debug("bad device\n"); break; } byte = status & 0xff; print_debug_hex8(byte); print_debug_char(' '); } - print_debug("\r\n"); + print_debug("\n"); } device = ctrl->channel1[i]; if (device) { @@ -249,20 +249,20 @@ int status; unsigned char byte; if ((j & 0xf) == 0) { - print_debug("\r\n"); + print_debug("\n"); print_debug_hex8(j); print_debug(": "); } status = smbus_read_byte(device, j); if (status < 0) { - print_debug("bad device\r\n"); + print_debug("bad device\n"); break; } byte = status & 0xff; print_debug_hex8(byte); print_debug_char(' '); } - print_debug("\r\n"); + print_debug("\n"); } } } @@ -275,14 +275,14 @@ while(device <= SMBUS_MEM_DEVICE_END) { int status = 0; int i; - print_debug("\r\n"); + print_debug("\n"); print_debug("dimm "); print_debug_hex8(device); for(i = 0; (i < 256) ; i++) { unsigned char byte; if ((i % 16) == 0) { - print_debug("\r\n"); + print_debug("\n"); print_debug_hex8(i); print_debug(": "); } @@ -290,7 +290,7 @@ if (status < 0) { print_debug("bad device: "); print_debug_hex8(-status); - print_debug("\r\n"); + print_debug("\n"); break; } print_debug_hex8(status); @@ -308,7 +308,7 @@ while(device <= 0x42) { int status = 0; int i; - print_debug("\r\n"); + print_debug("\n"); print_debug("ipmi "); print_debug_hex8(device); @@ -318,7 +318,7 @@ if (status < 0) { print_debug("bad device: "); print_debug_hex8(-status); - print_debug("\r\n"); + print_debug("\n"); break; } print_debug_hex8(status); Modified: trunk/src/mainboard/supermicro/x6dhe_g2/watchdog.c ============================================================================== --- trunk/src/mainboard/supermicro/x6dhe_g2/watchdog.c Wed Mar 31 16:34:40 2010 (r5341) +++ trunk/src/mainboard/supermicro/x6dhe_g2/watchdog.c Wed Mar 31 16:47:43 2010 (r5342) @@ -94,6 +94,6 @@ // disable_sio_watchdog(NSC_WD_DEV); disable_esb6300_watchdog(); // disable_jarell_frb3(); - print_debug("Watchdogs disabled\r\n"); + print_debug("Watchdogs disabled\n"); } Modified: trunk/src/mainboard/supermicro/x6dhr_ig/debug.c ============================================================================== --- trunk/src/mainboard/supermicro/x6dhr_ig/debug.c Wed Mar 31 16:34:40 2010 (r5341) +++ trunk/src/mainboard/supermicro/x6dhr_ig/debug.c Wed Mar 31 16:47:43 2010 (r5342) @@ -12,7 +12,7 @@ print_debug_hex8(index); print_debug(": 0x"); print_debug_hex8(data); - print_debug("\r\n"); + print_debug("\n"); return; } @@ -49,52 +49,52 @@ int i; unsigned char data; - print_debug("\r\n*** SERVER I/O REGISTERS ***\r\n"); + print_debug("\n*** SERVER I/O REGISTERS ***\n"); for (i=0x10; i<=0x2d; i++) { print_reg((unsigned char)i); } #if 0 - print_debug("\r\n*** XBUS REGISTERS ***\r\n"); + print_debug("\n*** XBUS REGISTERS ***\n"); setup_func(0x0f); for (i=0xf0; i<=0xff; i++) { print_reg((unsigned char)i); } - print_debug("\r\n*** SERIAL 1 CONFIG REGISTERS ***\r\n"); + print_debug("\n*** SERIAL 1 CONFIG REGISTERS ***\n"); setup_func(0x03); print_reg(0xf0); - print_debug("\r\n*** SERIAL 2 CONFIG REGISTERS ***\r\n"); + print_debug("\n*** SERIAL 2 CONFIG REGISTERS ***\n"); setup_func(0x02); print_reg(0xf0); #endif - print_debug("\r\n*** GPIO REGISTERS ***\r\n"); + print_debug("\n*** GPIO REGISTERS ***\n"); setup_func(0x07); for (i=0xf0; i<=0xf8; i++) { print_reg((unsigned char)i); } - print_debug("\r\n*** GPIO VALUES ***\r\n"); + print_debug("\n*** GPIO VALUES ***\n"); data = inb(0x68a); - print_debug("\r\nGPDO 4: 0x"); + print_debug("\nGPDO 4: 0x"); print_debug_hex8(data); data = inb(0x68b); - print_debug("\r\nGPDI 4: 0x"); + print_debug("\nGPDI 4: 0x"); print_debug_hex8(data); - print_debug("\r\n"); + print_debug("\n"); #if 0 - print_debug("\r\n*** WATCHDOG TIMER REGISTERS ***\r\n"); + print_debug("\n*** WATCHDOG TIMER REGISTERS ***\n"); setup_func(0x0a); print_reg(0xf0); - print_debug("\r\n*** FAN CONTROL REGISTERS ***\r\n"); + print_debug("\n*** FAN CONTROL REGISTERS ***\n"); setup_func(0x09); print_reg(0xf0); print_reg(0xf1); - print_debug("\r\n*** RTC REGISTERS ***\r\n"); + print_debug("\n*** RTC REGISTERS ***\n"); setup_func(0x10); print_reg(0xf0); print_reg(0xf1); @@ -104,7 +104,7 @@ print_reg(0xfe); print_reg(0xff); - print_debug("\r\n*** HEALTH MONITORING & CONTROL REGISTERS ***\r\n"); + print_debug("\n*** HEALTH MONITORING & CONTROL REGISTERS ***\n"); setup_func(0x14); print_reg(0xf0); #endif @@ -135,7 +135,7 @@ continue; } print_debug_pci_dev(dev); - print_debug("\r\n"); + print_debug("\n"); } } @@ -143,7 +143,7 @@ { int i; print_debug_pci_dev(dev); - print_debug("\r\n"); + print_debug("\n"); for(i = 0; i <= 255; i++) { unsigned char val; @@ -155,7 +155,7 @@ print_debug_char(' '); print_debug_hex8(val); if ((i & 0x0f) == 0x0f) { - print_debug("\r\n"); + print_debug("\n"); } } } @@ -165,7 +165,7 @@ int i; unsigned long bar; - print_debug("BAR 14 Dump\r\n"); + print_debug("BAR 14 Dump\n"); bar = pci_read_config32(dev, 0x14); for(i = 0; i <= 0x300; i+=4) { @@ -178,14 +178,14 @@ val = pci_read_config8(dev, i); #endif if((i%4)==0) { - print_debug("\r\n"); + print_debug("\n"); print_debug_hex16(i); print_debug_char(' '); } print_debug_hex32(read32(bar + i)); print_debug_char(' '); } - print_debug("\r\n"); + print_debug("\n"); } static void dump_pci_devices(void) @@ -209,7 +209,7 @@ static void dump_spd_registers(const struct mem_controller *ctrl) { int i; - print_debug("\r\n"); + print_debug("\n"); for(i = 0; i < 4; i++) { unsigned device; device = ctrl->channel0[i]; @@ -223,20 +223,20 @@ int status; unsigned char byte; if ((j & 0xf) == 0) { - print_debug("\r\n"); + print_debug("\n"); print_debug_hex8(j); print_debug(": "); } status = smbus_read_byte(device, j); if (status < 0) { - print_debug("bad device\r\n"); + print_debug("bad device\n"); break; } byte = status & 0xff; print_debug_hex8(byte); print_debug_char(' '); } - print_debug("\r\n"); + print_debug("\n"); } device = ctrl->channel1[i]; if (device) { @@ -249,20 +249,20 @@ int status; unsigned char byte; if ((j & 0xf) == 0) { - print_debug("\r\n"); + print_debug("\n"); print_debug_hex8(j); print_debug(": "); } status = smbus_read_byte(device, j); if (status < 0) { - print_debug("bad device\r\n"); + print_debug("bad device\n"); break; } byte = status & 0xff; print_debug_hex8(byte); print_debug_char(' '); } - print_debug("\r\n"); + print_debug("\n"); } } } @@ -275,14 +275,14 @@ while(device <= SMBUS_MEM_DEVICE_END) { int status = 0; int i; - print_debug("\r\n"); + print_debug("\n"); print_debug("dimm "); print_debug_hex8(device); for(i = 0; (i < 256) ; i++) { unsigned char byte; if ((i % 16) == 0) { - print_debug("\r\n"); + print_debug("\n"); print_debug_hex8(i); print_debug(": "); } @@ -290,7 +290,7 @@ if (status < 0) { print_debug("bad device: "); print_debug_hex8(-status); - print_debug("\r\n"); + print_debug("\n"); break; } print_debug_hex8(status); @@ -308,7 +308,7 @@ while(device <= 0x42) { int status = 0; int i; - print_debug("\r\n"); + print_debug("\n"); print_debug("ipmi "); print_debug_hex8(device); @@ -318,7 +318,7 @@ if (status < 0) { print_debug("bad device: "); print_debug_hex8(-status); - print_debug("\r\n"); + print_debug("\n"); break; } print_debug_hex8(status); Modified: trunk/src/mainboard/supermicro/x6dhr_ig/watchdog.c ============================================================================== --- trunk/src/mainboard/supermicro/x6dhr_ig/watchdog.c Wed Mar 31 16:34:40 2010 (r5341) +++ trunk/src/mainboard/supermicro/x6dhr_ig/watchdog.c Wed Mar 31 16:47:43 2010 (r5342) @@ -94,6 +94,6 @@ // disable_sio_watchdog(NSC_WD_DEV); disable_ich5_watchdog(); // disable_jarell_frb3(); - print_debug("Watchdogs disabled\r\n"); + print_debug("Watchdogs disabled\n"); } Modified: trunk/src/mainboard/supermicro/x6dhr_ig2/debug.c ============================================================================== --- trunk/src/mainboard/supermicro/x6dhr_ig2/debug.c Wed Mar 31 16:34:40 2010 (r5341) +++ trunk/src/mainboard/supermicro/x6dhr_ig2/debug.c Wed Mar 31 16:47:43 2010 (r5342) @@ -12,7 +12,7 @@ print_debug_hex8(index); print_debug(": 0x"); print_debug_hex8(data); - print_debug("\r\n"); + print_debug("\n"); return; } @@ -49,52 +49,52 @@ int i; unsigned char data; - print_debug("\r\n*** SERVER I/O REGISTERS ***\r\n"); + print_debug("\n*** SERVER I/O REGISTERS ***\n"); for (i=0x10; i<=0x2d; i++) { print_reg((unsigned char)i); } #if 0 - print_debug("\r\n*** XBUS REGISTERS ***\r\n"); + print_debug("\n*** XBUS REGISTERS ***\n"); setup_func(0x0f); for (i=0xf0; i<=0xff; i++) { print_reg((unsigned char)i); } - print_debug("\r\n*** SERIAL 1 CONFIG REGISTERS ***\r\n"); + print_debug("\n*** SERIAL 1 CONFIG REGISTERS ***\n"); setup_func(0x03); print_reg(0xf0); - print_debug("\r\n*** SERIAL 2 CONFIG REGISTERS ***\r\n"); + print_debug("\n*** SERIAL 2 CONFIG REGISTERS ***\n"); setup_func(0x02); print_reg(0xf0); #endif - print_debug("\r\n*** GPIO REGISTERS ***\r\n"); + print_debug("\n*** GPIO REGISTERS ***\n"); setup_func(0x07); for (i=0xf0; i<=0xf8; i++) { print_reg((unsigned char)i); } - print_debug("\r\n*** GPIO VALUES ***\r\n"); + print_debug("\n*** GPIO VALUES ***\n"); data = inb(0x68a); - print_debug("\r\nGPDO 4: 0x"); + print_debug("\nGPDO 4: 0x"); print_debug_hex8(data); data = inb(0x68b); - print_debug("\r\nGPDI 4: 0x"); + print_debug("\nGPDI 4: 0x"); print_debug_hex8(data); - print_debug("\r\n"); + print_debug("\n"); #if 0 - print_debug("\r\n*** WATCHDOG TIMER REGISTERS ***\r\n"); + print_debug("\n*** WATCHDOG TIMER REGISTERS ***\n"); setup_func(0x0a); print_reg(0xf0); - print_debug("\r\n*** FAN CONTROL REGISTERS ***\r\n"); + print_debug("\n*** FAN CONTROL REGISTERS ***\n"); setup_func(0x09); print_reg(0xf0); print_reg(0xf1); - print_debug("\r\n*** RTC REGISTERS ***\r\n"); + print_debug("\n*** RTC REGISTERS ***\n"); setup_func(0x10); print_reg(0xf0); print_reg(0xf1); @@ -104,7 +104,7 @@ print_reg(0xfe); print_reg(0xff); - print_debug("\r\n*** HEALTH MONITORING & CONTROL REGISTERS ***\r\n"); + print_debug("\n*** HEALTH MONITORING & CONTROL REGISTERS ***\n"); setup_func(0x14); print_reg(0xf0); #endif @@ -135,7 +135,7 @@ continue; } print_debug_pci_dev(dev); - print_debug("\r\n"); + print_debug("\n"); } } @@ -143,7 +143,7 @@ { int i; print_debug_pci_dev(dev); - print_debug("\r\n"); + print_debug("\n"); for(i = 0; i <= 255; i++) { unsigned char val; @@ -155,7 +155,7 @@ print_debug_char(' '); print_debug_hex8(val); if ((i & 0x0f) == 0x0f) { - print_debug("\r\n"); + print_debug("\n"); } } } @@ -165,7 +165,7 @@ int i; unsigned long bar; - print_debug("BAR 14 Dump\r\n"); + print_debug("BAR 14 Dump\n"); bar = pci_read_config32(dev, 0x14); for(i = 0; i <= 0x300; i+=4) { @@ -178,14 +178,14 @@ val = pci_read_config8(dev, i); #endif if((i%4)==0) { - print_debug("\r\n"); + print_debug("\n"); print_debug_hex16(i); print_debug_char(' '); } print_debug_hex32(read32(bar + i)); print_debug_char(' '); } - print_debug("\r\n"); + print_debug("\n"); } static void dump_pci_devices(void) @@ -209,7 +209,7 @@ static void dump_spd_registers(const struct mem_controller *ctrl) { int i; - print_debug("\r\n"); + print_debug("\n"); for(i = 0; i < 4; i++) { unsigned device; device = ctrl->channel0[i]; @@ -223,20 +223,20 @@ int status; unsigned char byte; if ((j & 0xf) == 0) { - print_debug("\r\n"); + print_debug("\n"); print_debug_hex8(j); print_debug(": "); } status = smbus_read_byte(device, j); if (status < 0) { - print_debug("bad device\r\n"); + print_debug("bad device\n"); break; } byte = status & 0xff; print_debug_hex8(byte); print_debug_char(' '); } - print_debug("\r\n"); + print_debug("\n"); } device = ctrl->channel1[i]; if (device) { @@ -249,20 +249,20 @@ int status; unsigned char byte; if ((j & 0xf) == 0) { - print_debug("\r\n"); + print_debug("\n"); print_debug_hex8(j); print_debug(": "); } status = smbus_read_byte(device, j); if (status < 0) { - print_debug("bad device\r\n"); + print_debug("bad device\n"); break; } byte = status & 0xff; print_debug_hex8(byte); print_debug_char(' '); } - print_debug("\r\n"); + print_debug("\n"); } } } @@ -275,14 +275,14 @@ while(device <= SMBUS_MEM_DEVICE_END) { int status = 0; int i; - print_debug("\r\n"); + print_debug("\n"); print_debug("dimm "); print_debug_hex8(device); for(i = 0; (i < 256) ; i++) { unsigned char byte; if ((i % 16) == 0) { - print_debug("\r\n"); + print_debug("\n"); print_debug_hex8(i); print_debug(": "); } @@ -290,7 +290,7 @@ if (status < 0) { print_debug("bad device: "); print_debug_hex8(-status); - print_debug("\r\n"); + print_debug("\n"); break; } print_debug_hex8(status); @@ -308,7 +308,7 @@ while(device <= 0x42) { int status = 0; int i; - print_debug("\r\n"); + print_debug("\n"); print_debug("ipmi "); print_debug_hex8(device); @@ -318,7 +318,7 @@ if (status < 0) { print_debug("bad device: "); print_debug_hex8(-status); - print_debug("\r\n"); + print_debug("\n"); break; } print_debug_hex8(status); Modified: trunk/src/mainboard/supermicro/x6dhr_ig2/watchdog.c ============================================================================== --- trunk/src/mainboard/supermicro/x6dhr_ig2/watchdog.c Wed Mar 31 16:34:40 2010 (r5341) +++ trunk/src/mainboard/supermicro/x6dhr_ig2/watchdog.c Wed Mar 31 16:47:43 2010 (r5342) @@ -94,6 +94,6 @@ // disable_sio_watchdog(NSC_WD_DEV); disable_ich5_watchdog(); // disable_jarell_frb3(); - print_debug("Watchdogs disabled\r\n"); + print_debug("Watchdogs disabled\n"); } Modified: trunk/src/mainboard/technexion/tim5690/romstage.c ============================================================================== --- trunk/src/mainboard/technexion/tim5690/romstage.c Wed Mar 31 16:34:40 2010 (r5341) +++ trunk/src/mainboard/technexion/tim5690/romstage.c Wed Mar 31 16:47:43 2010 (r5342) @@ -184,7 +184,7 @@ printk(BIOS_DEBUG, "needs_reset=0x%x\n", needs_reset); if (needs_reset) { - print_info("ht reset -\r\n"); + print_info("ht reset -\n"); soft_reset(); } Modified: trunk/src/mainboard/technexion/tim8690/romstage.c ============================================================================== --- trunk/src/mainboard/technexion/tim8690/romstage.c Wed Mar 31 16:34:40 2010 (r5341) +++ trunk/src/mainboard/technexion/tim8690/romstage.c Wed Mar 31 16:47:43 2010 (r5342) @@ -178,7 +178,7 @@ printk(BIOS_DEBUG, "needs_reset=0x%x\n", needs_reset); if (needs_reset) { - print_info("ht reset -\r\n"); + print_info("ht reset -\n"); soft_reset(); } Modified: trunk/src/mainboard/technologic/ts5300/romstage.c ============================================================================== --- trunk/src/mainboard/technologic/ts5300/romstage.c Wed Mar 31 16:34:40 2010 (r5341) +++ trunk/src/mainboard/technologic/ts5300/romstage.c Wed Mar 31 16:47:43 2010 (r5342) @@ -56,18 +56,18 @@ TS9500_LED_ON; - print_err("TS-9500 add-on found:\r\n"); + print_err("TS-9500 add-on found:\n"); val=inb(0x19b); for (i=0; i<8; i++) { print_err(" DIP"); print_err_char(i+0x31); print_err(": "); if((val&(1<<i))!=0) - print_err("on\r\n"); + print_err("on\n"); else - print_err("off\r\n"); + print_err("off\n"); } - print_err("\r\n"); + print_err("\n"); val=inb(0x19a); @@ -76,11 +76,11 @@ print_err_char(i+0x30-5); print_err(": "); if((val&(1<<i))!=0) - print_err("on\r\n"); + print_err("on\n"); else - print_err("off\r\n"); + print_err("off\n"); } - print_err("\r\n"); + print_err("\n"); TS9500_LED_OFF; } @@ -92,29 +92,29 @@ print_err("Mainboard: "); val=inb(0x74); switch(val) { - case 0x50: print_err("TS-5300\r\n"); break; - case 0x40: print_err("TS-5400\r\n"); break; - case 0x60: print_err("TS-5500\r\n"); break; - case 0x20: print_err("TS-5600\r\n"); break; - case 0x70: print_err("TS-5700\r\n"); break; - default: print_err("unknown\r\n"); break; + case 0x50: print_err("TS-5300\n"); break; + case 0x40: print_err("TS-5400\n"); break; + case 0x60: print_err("TS-5500\n"); break; + case 0x20: print_err("TS-5600\n"); break; + case 0x70: print_err("TS-5700\n"); break; + default: print_err("unknown\n"); break; } val=inb(0x75); print_err(" SRAM option: "); if((val&1)==0) print_err("not "); - print_err("installed\r\n"); + print_err("installed\n"); print_err(" RS-485 option: "); if((val&2)==0) print_err("not "); - print_err("installed\r\n"); + print_err("installed\n"); val=inb(0x76); print_err(" Temp. range: "); - if((val&2)==0) print_err("commercial\r\n"); - else print_err("industrial\r\n"); + if((val&2)==0) print_err("commercial\n"); + else print_err("industrial\n"); - print_err("\r\n"); + print_err("\n"); val=inb(0x77); for (i=1; i<8; i++) { @@ -122,11 +122,11 @@ print_err_char(i+0x30); print_err(": "); if((val&(1<<i))!=0) - print_err("on\r\n"); + print_err("on\n"); else - print_err("off\r\n"); + print_err("off\n"); } - print_err("\r\n"); + print_err("\n"); /* Detect TS-9500 */ val=inb(0x19d); @@ -157,9 +157,9 @@ console_init(); - print_err("Technologic Systems TS5300 - http://www.embeddedx86.com/\r\n"); + print_err("Technologic Systems TS5300 - http://www.embeddedx86.com/\n"); staticmem(); - print_err("Memory initialized: 32MB\r\n"); + print_err("Memory initialized: 32MB\n"); #if 1 identify_system(); @@ -167,7 +167,7 @@ #if 0 // Check 32MB of memory @ 0 (very slow!) - print_err("Checking memory:\r\n"); + print_err("Checking memory:\n"); ram_check(0x00000000, 0x000a0000); ram_check(0x000b0000, 0x02000000); #endif Modified: trunk/src/mainboard/tyan/s2735/romstage.c ============================================================================== --- trunk/src/mainboard/tyan/s2735/romstage.c Wed Mar 31 16:34:40 2010 (r5341) +++ trunk/src/mainboard/tyan/s2735/romstage.c Wed Mar 31 16:47:43 2010 (r5342) @@ -129,9 +129,9 @@ : "=a" (v_esp) ); #if CONFIG_USE_PRINTK_IN_CAR - printk(BIOS_DEBUG, "v_esp=%08x\r\n", v_esp); + printk(BIOS_DEBUG, "v_esp=%08x\n", v_esp); #else - print_debug("v_esp="); print_debug_hex32(v_esp); print_debug("\r\n"); + print_debug("v_esp="); print_debug_hex32(v_esp); print_debug("\n"); #endif } @@ -141,9 +141,9 @@ cpu_reset_x: #if CONFIG_USE_PRINTK_IN_CAR - printk(BIOS_DEBUG, "cpu_reset = %08x\r\n",cpu_reset); + printk(BIOS_DEBUG, "cpu_reset = %08x\n",cpu_reset); #else - print_debug("cpu_reset = "); print_debug_hex32(cpu_reset); print_debug("\r\n"); + print_debug("cpu_reset = "); print_debug_hex32(cpu_reset); print_debug("\n"); #endif if(cpu_reset == 0) { @@ -184,21 +184,21 @@ /* We can not go back any more, we lost old stack data in cache as ram*/ if(new_cpu_reset==0) { - print_debug("Use Ram as Stack now - done\r\n"); + print_debug("Use Ram as Stack now - done\n"); } else { - print_debug("Use Ram as Stack now - \r\n"); + print_debug("Use Ram as Stack now - \n"); } #if CONFIG_USE_PRINTK_IN_CAR - printk(BIOS_DEBUG, "new_cpu_reset = %08x\r\n", new_cpu_reset); + printk(BIOS_DEBUG, "new_cpu_reset = %08x\n", new_cpu_reset); #else - print_debug("new_cpu_reset = "); print_debug_hex32(new_cpu_reset); print_debug("\r\n"); + print_debug("new_cpu_reset = "); print_debug_hex32(new_cpu_reset); print_debug("\n"); #endif #ifdef DEACTIVATE_CAR print_debug("Deactivating CAR"); #include DEACTIVATE_CAR_FILE - print_debug(" - Done.\r\n"); + print_debug(" - Done.\n"); #endif /*copy and execute coreboot_ram */ copy_and_run(new_cpu_reset); @@ -206,7 +206,7 @@ } #endif - print_debug("should not be here -\r\n"); + print_debug("should not be here -\n"); } Modified: trunk/src/mainboard/tyan/s2850/romstage.c ============================================================================== --- trunk/src/mainboard/tyan/s2850/romstage.c Wed Mar 31 16:34:40 2010 (r5341) +++ trunk/src/mainboard/tyan/s2850/romstage.c Wed Mar 31 16:47:43 2010 (r5342) @@ -144,7 +144,7 @@ needs_reset |= ht_setup_chains_x(); if (needs_reset) { - print_info("ht reset -\r\n"); + print_info("ht reset -\n"); soft_reset(); } Modified: trunk/src/mainboard/tyan/s2875/romstage.c ============================================================================== --- trunk/src/mainboard/tyan/s2875/romstage.c Wed Mar 31 16:34:40 2010 (r5341) +++ trunk/src/mainboard/tyan/s2875/romstage.c Wed Mar 31 16:47:43 2010 (r5342) @@ -143,7 +143,7 @@ needs_reset |= ht_setup_chains_x(); if (needs_reset) { - print_info("ht reset -\r\n"); + print_info("ht reset -\n"); soft_reset(); } Modified: trunk/src/mainboard/tyan/s2880/romstage.c ============================================================================== --- trunk/src/mainboard/tyan/s2880/romstage.c Wed Mar 31 16:34:40 2010 (r5341) +++ trunk/src/mainboard/tyan/s2880/romstage.c Wed Mar 31 16:47:43 2010 (r5342) @@ -145,7 +145,7 @@ needs_reset |= ht_setup_chains_x(); if (needs_reset) { - print_info("ht reset -\r\n"); + print_info("ht reset -\n"); soft_reset(); } Modified: trunk/src/mainboard/tyan/s2881/romstage.c ============================================================================== --- trunk/src/mainboard/tyan/s2881/romstage.c Wed Mar 31 16:34:40 2010 (r5341) +++ trunk/src/mainboard/tyan/s2881/romstage.c Wed Mar 31 16:47:43 2010 (r5342) @@ -154,7 +154,7 @@ needs_reset |= ht_setup_chains_x(); if (needs_reset) { - print_info("ht reset -\r\n"); + print_info("ht reset -\n"); soft_reset(); } Modified: trunk/src/mainboard/tyan/s2882/romstage.c ============================================================================== --- trunk/src/mainboard/tyan/s2882/romstage.c Wed Mar 31 16:34:40 2010 (r5341) +++ trunk/src/mainboard/tyan/s2882/romstage.c Wed Mar 31 16:47:43 2010 (r5342) @@ -149,7 +149,7 @@ needs_reset |= ht_setup_chains_x(); if (needs_reset) { - print_info("ht reset -\r\n"); + print_info("ht reset -\n"); soft_reset(); } Modified: trunk/src/mainboard/tyan/s2885/romstage.c ============================================================================== --- trunk/src/mainboard/tyan/s2885/romstage.c Wed Mar 31 16:34:40 2010 (r5341) +++ trunk/src/mainboard/tyan/s2885/romstage.c Wed Mar 31 16:47:43 2010 (r5342) @@ -158,7 +158,7 @@ needs_reset |= ht_setup_chains_x(); if (needs_reset) { - print_info("ht reset -\r\n"); + print_info("ht reset -\n"); soft_reset(); } Modified: trunk/src/mainboard/tyan/s2891/romstage.c ============================================================================== --- trunk/src/mainboard/tyan/s2891/romstage.c Wed Mar 31 16:34:40 2010 (r5341) +++ trunk/src/mainboard/tyan/s2891/romstage.c Wed Mar 31 16:47:43 2010 (r5342) @@ -169,7 +169,7 @@ needs_reset |= ck804_early_setup_x(); if (needs_reset) { - printk(BIOS_INFO, "ht reset -\r\n"); + printk(BIOS_INFO, "ht reset -\n"); soft_reset(); } Modified: trunk/src/mainboard/tyan/s2912/ap_romstage.c ============================================================================== --- trunk/src/mainboard/tyan/s2912/ap_romstage.c Wed Mar 31 16:34:40 2010 (r5341) +++ trunk/src/mainboard/tyan/s2912/ap_romstage.c Wed Mar 31 16:47:43 2010 (r5342) @@ -79,7 +79,7 @@ id = get_node_core_id_x(); //FIXME: for USBDEBUG_DIRECT you need to make sure dbg_info get assigned in AP - print_debug("CODE IN CACHE ON NODE:"); print_debug_hex8(id.nodeid); print_debug("\r\n"); + print_debug("CODE IN CACHE ON NODE:"); print_debug_hex8(id.nodeid); print_debug("\n"); train_ram(id.nodeid, sysinfo, sysinfox); Modified: trunk/src/mainboard/tyan/s2912/romstage.c ============================================================================== --- trunk/src/mainboard/tyan/s2912/romstage.c Wed Mar 31 16:34:40 2010 (r5341) +++ trunk/src/mainboard/tyan/s2912/romstage.c Wed Mar 31 16:47:43 2010 (r5342) @@ -211,7 +211,7 @@ console_init(); printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1); - print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\r\n"); + print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\n"); #if CONFIG_MEM_TRAIN_SEQ == 1 set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram @@ -237,7 +237,7 @@ { msr_t msr; msr=rdmsr(0xc0010042); - print_debug("begin msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\r\n"); + print_debug("begin msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n"); } @@ -251,7 +251,7 @@ { msr_t msr; msr=rdmsr(0xc0010042); - print_debug("end msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\r\n"); + print_debug("end msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n"); } #endif @@ -262,7 +262,7 @@ // fidvid change will issue one LDTSTOP and the HT change will be effective too if (needs_reset) { - print_info("ht reset -\r\n"); + print_info("ht reset -\n"); soft_reset(); } Modified: trunk/src/mainboard/tyan/s4880/romstage.c ============================================================================== --- trunk/src/mainboard/tyan/s4880/romstage.c Wed Mar 31 16:34:40 2010 (r5341) +++ trunk/src/mainboard/tyan/s4880/romstage.c Wed Mar 31 16:47:43 2010 (r5342) @@ -66,11 +66,11 @@ { #define SMBUS_HUB 0x18 int ret; - print_debug("change_i2c_mux i="); print_debug_hex8(device); print_debug("\r\n"); + print_debug("change_i2c_mux i="); print_debug_hex8(device); print_debug("\n"); ret = smbus_write_byte(SMBUS_HUB, 0x01, device); - print_debug("change_i2c_mux 1 ret="); print_debug_hex32(ret); print_debug("\r\n"); + print_debug("change_i2c_mux 1 ret="); print_debug_hex32(ret); print_debug("\n"); ret = smbus_write_byte(SMBUS_HUB, 0x03, 0); - print_debug("change_i2c_mux 2 ret="); print_debug_hex32(ret); print_debug("\r\n"); + print_debug("change_i2c_mux 2 ret="); print_debug_hex32(ret); print_debug("\n"); } #endif @@ -195,7 +195,7 @@ needs_reset |= ht_setup_chains_x(); if (needs_reset) { - print_info("ht reset -\r\n"); + print_info("ht reset -\n"); soft_reset(); } Modified: trunk/src/mainboard/tyan/s4882/romstage.c ============================================================================== --- trunk/src/mainboard/tyan/s4882/romstage.c Wed Mar 31 16:34:40 2010 (r5341) +++ trunk/src/mainboard/tyan/s4882/romstage.c Wed Mar 31 16:47:43 2010 (r5342) @@ -70,14 +70,14 @@ { #define SMBUS_HUB 0x18 int ret, i; - print_debug("change_i2c_mux i="); print_debug_hex8(device); print_debug("\r\n"); + print_debug("change_i2c_mux i="); print_debug_hex8(device); print_debug("\n"); i=2; do { ret = smbus_write_byte(SMBUS_HUB, 0x01, device); - print_debug("change_i2c_mux 1 ret="); print_debug_hex32(ret); print_debug("\r\n"); + print_debug("change_i2c_mux 1 ret="); print_debug_hex32(ret); print_debug("\n"); } while ((ret!=0) && (i-->0)); ret = smbus_write_byte(SMBUS_HUB, 0x03, 0); - print_debug("change_i2c_mux 2 ret="); print_debug_hex32(ret); print_debug("\r\n"); + print_debug("change_i2c_mux 2 ret="); print_debug_hex32(ret); print_debug("\n"); } #endif @@ -178,7 +178,7 @@ needs_reset |= ht_setup_chains_x(); if (needs_reset) { - print_info("ht reset -\r\n"); + print_info("ht reset -\n"); soft_reset(); } Modified: trunk/src/mainboard/via/epia-cn/romstage.c ============================================================================== --- trunk/src/mainboard/via/epia-cn/romstage.c Wed Mar 31 16:34:40 2010 (r5341) +++ trunk/src/mainboard/via/epia-cn/romstage.c Wed Mar 31 16:47:43 2010 (r5342) @@ -98,26 +98,26 @@ uart_init(); console_init(); - print_spew("In romstage.c:main()\r\n"); + print_spew("In romstage.c:main()\n"); enable_smbus(); smbus_fixup(&ctrl); if (bist == 0) { - print_debug("doing early_mtrr\r\n"); + print_debug("doing early_mtrr\n"); early_mtrr_init(); } /* Halt if there was a built-in self test failure. */ report_bist_failure(bist); - print_debug("Enabling mainboard devices\r\n"); + print_debug("Enabling mainboard devices\n"); enable_mainboard_devices(); ddr_ram_setup(&ctrl); /* ram_check(0, 640 * 1024); */ - print_spew("Leaving romstage.c:main()\r\n"); + print_spew("Leaving romstage.c:main()\n"); } Modified: trunk/src/mainboard/via/epia-m/romstage.c ============================================================================== --- trunk/src/mainboard/via/epia-m/romstage.c Wed Mar 31 16:34:40 2010 (r5341) +++ trunk/src/mainboard/via/epia-m/romstage.c Wed Mar 31 16:47:43 2010 (r5342) @@ -102,7 +102,7 @@ enable_smbus(); - print_spew("In romstage.c:main()\r\n"); + print_spew("In romstage.c:main()\n"); /* Halt if there was a built in self test failure */ report_bist_failure(bist); @@ -111,10 +111,10 @@ outb(5, 0x80); - print_debug(" Enabling mainboard devices\r\n"); + print_debug(" Enabling mainboard devices\n"); enable_mainboard_devices(); - print_debug(" Enabling shadow ram\r\n"); + print_debug(" Enabling shadow ram\n"); enable_shadow_ram(); ddr_ram_setup((const struct mem_controller *)0); @@ -141,12 +141,12 @@ #endif if (bist == 0) { - print_debug(" Doing MTRR init.\r\n"); + print_debug(" Doing MTRR init.\n"); early_mtrr_init(); } //dump_pci_devices(); - print_spew("Leaving romstage.c:main()\r\n"); + print_spew("Leaving romstage.c:main()\n"); } Modified: trunk/src/mainboard/via/epia-m700/romstage.c ============================================================================== --- trunk/src/mainboard/via/epia-m700/romstage.c Wed Mar 31 16:34:40 2010 (r5341) +++ trunk/src/mainboard/via/epia-m700/romstage.c Wed Mar 31 16:47:43 2010 (r5342) @@ -76,13 +76,13 @@ device_t dev; u16 tmp, result; - print_debug("In acpi_is_wakeup_early_via_vx800\r\n"); + print_debug("In acpi_is_wakeup_early_via_vx800\n"); /* Power management controller */ dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VX855_LPC), 0); if (dev == PCI_DEV_INVALID) - die("Power management controller not found\r\n"); + die("Power management controller not found\n"); /* Set ACPI base address to I/O VX800_ACPI_IO_BASE. */ pci_write_config16(dev, 0x88, VX800_ACPI_IO_BASE | 0x1); @@ -94,7 +94,7 @@ result = ((tmp & (7 << 10)) >> 10) == 1 ? 3 : 0; print_debug(" boot_mode="); print_debug_hex16(result); - print_debug("\r\n"); + print_debug("\n"); return result; } @@ -142,7 +142,7 @@ pci_write_config8(dev, 0x5b, 0x01); #endif - print_debug("In enable_mainboard_devices \r\n"); + print_debug("In enable_mainboard_devices \n"); /* Enable P2P Bridge Header for external PCI bus. */ dev = pci_locate_device(PCI_ID(0x1106, 0xa353), 0); @@ -482,7 +482,7 @@ * early_mtrr_init() call. */ #if 0 - print_debug("doing early_mtrr\r\n"); + print_debug("doing early_mtrr\n"); early_mtrr_init(); #endif } @@ -490,7 +490,7 @@ /* Halt if there was a built-in self test failure. */ report_bist_failure(bist); - print_debug("Enabling mainboard devices\r\n"); + print_debug("Enabling mainboard devices\n"); enable_mainboard_devices(); /* @@ -501,7 +501,7 @@ Data = pci_read_config8(device, 0xf6); print_debug("NB chip revision ="); print_debug_hex8(Data); - print_debug("\r\n"); + print_debug("\n"); /* Make NB ready before DRAM init. */ via_pci_inittable(Data, mNbStage1InitTbl); @@ -518,7 +518,7 @@ u8 ramregs[] = { 0x43, 0x42, 0x41, 0x40 }; DRAM_SYS_ATTR DramAttr; - print_debug("This is an S3 wakeup\r\n"); + print_debug("This is an S3 wakeup\n"); memset(&DramAttr, 0, sizeof(DRAM_SYS_ATTR)); /* @@ -553,7 +553,7 @@ /* Just copy this function from draminit to here! */ SetUMARam(); - print_debug("Resume from S3, RAM init was ignored\r\n"); + print_debug("Resume from S3, RAM init was ignored\n"); } else { ddr2_ram_setup(); ram_check(0, 640 * 1024); @@ -675,7 +675,7 @@ ); #endif /* This can have function call, because no variable used before this. */ - print_debug("Copy memory to high memory to protect s3 wakeup vector code \r\n"); + print_debug("Copy memory to high memory to protect s3 wakeup vector code \n"); memcpy((unsigned char *)((*(u32 *) WAKE_MEM_INFO) - 64 * 1024 - 0x100000), (unsigned char *)0, 0xa0000); memcpy((unsigned char *)((*(u32 *) WAKE_MEM_INFO) - 64 * 1024 - @@ -725,11 +725,11 @@ unsigned v_esp; __asm__ volatile ("movl %%esp, %0\n\t":"=a" (v_esp)); #if CONFIG_USE_PRINTK_IN_CAR - printk(BIOS_DEBUG, "v_esp=%08x\r\n", v_esp); + printk(BIOS_DEBUG, "v_esp=%08x\n", v_esp); #else print_debug("v_esp="); print_debug_hex32(v_esp); - print_debug("\r\n"); + print_debug("\n"); #endif } #endif @@ -744,11 +744,11 @@ cpu_reset = 0; #if CONFIG_USE_PRINTK_IN_CAR - printk(BIOS_DEBUG, "cpu_reset = %08x\r\n", cpu_reset); + printk(BIOS_DEBUG, "cpu_reset = %08x\n", cpu_reset); #else print_debug("cpu_reset = "); print_debug_hex32(cpu_reset); - print_debug("\r\n"); + print_debug("\n"); #endif if (cpu_reset == 0) @@ -789,16 +789,16 @@ /* We can't go back anymore, we lost old stack data in CAR. */ if (new_cpu_reset == 0) - print_debug("Use Ram as Stack now - done\r\n"); + print_debug("Use Ram as Stack now - done\n"); else - print_debug("Use Ram as Stack now - \r\n"); + print_debug("Use Ram as Stack now - \n"); #if CONFIG_USE_PRINTK_IN_CAR - printk(BIOS_DEBUG, "new_cpu_reset = %08x\r\n", new_cpu_reset); + printk(BIOS_DEBUG, "new_cpu_reset = %08x\n", new_cpu_reset); #else print_debug("new_cpu_reset = "); print_debug_hex32(new_cpu_reset); - print_debug("\r\n"); + print_debug("\n"); #endif jason_tsc_count_car(); @@ -808,6 +808,6 @@ } #endif - print_debug("should not be here -\r\n"); + print_debug("should not be here -\n"); } Modified: trunk/src/mainboard/via/epia-n/romstage.c ============================================================================== --- trunk/src/mainboard/via/epia-n/romstage.c Wed Mar 31 16:34:40 2010 (r5341) +++ trunk/src/mainboard/via/epia-n/romstage.c Wed Mar 31 16:47:43 2010 (r5342) @@ -124,7 +124,7 @@ uart_init(); console_init(); - print_spew("In romstage.c:main()\r\n"); + print_spew("In romstage.c:main()\n"); enable_smbus(); smbus_fixup(&ctrl); @@ -132,25 +132,25 @@ /* Halt if there was a built-in self test failure. */ report_bist_failure(bist); - print_debug("Enabling mainboard devices\r\n"); + print_debug("Enabling mainboard devices\n"); enable_mainboard_devices(); - print_debug("Enable F-ROM Shadow RAM\r\n"); + print_debug("Enable F-ROM Shadow RAM\n"); enable_shadow_ram(); /* setup cpu */ - print_debug("Setup CPU Interface\r\n"); + print_debug("Setup CPU Interface\n"); c3_cpu_setup(ctrl.d0f2); ddr_ram_setup(); if (bist == 0) { - print_debug("doing early_mtrr\r\n"); + print_debug("doing early_mtrr\n"); early_mtrr_init(); } //ram_check(0, 640 * 1024); - print_spew("Leaving romstage.c:main()\r\n"); + print_spew("Leaving romstage.c:main()\n"); } Modified: trunk/src/mainboard/via/vt8454c/debug.c ============================================================================== --- trunk/src/mainboard/via/vt8454c/debug.c Wed Mar 31 16:34:40 2010 (r5341) +++ trunk/src/mainboard/via/vt8454c/debug.c Wed Mar 31 16:47:43 2010 (r5342) @@ -42,7 +42,7 @@ continue; } print_debug_pci_dev(dev); - print_debug("\r\n"); + print_debug("\n"); } } @@ -50,7 +50,7 @@ { int i; print_debug_pci_dev(dev); - print_debug("\r\n"); + print_debug("\n"); for (i = 0; i <= 255; i++) { unsigned char val; @@ -62,7 +62,7 @@ print_debug_char(' '); print_debug_hex8(val); if ((i & 0x0f) == 0x0f) { - print_debug("\r\n"); + print_debug("\n"); } } } @@ -90,7 +90,7 @@ int i; udelay(2000); print_debug_hex16(port); - print_debug(":\r\n"); + print_debug(":\n"); for (i = 0; i < 256; i++) { u8 val; if ((i & 0x0f) == 0) { @@ -101,7 +101,7 @@ print_debug_char(' '); print_debug_hex8(val); if ((i & 0x0f) == 0x0f) { - print_debug("\r\n"); + print_debug("\n"); } port++; } Modified: trunk/src/mainboard/via/vt8454c/romstage.c ============================================================================== --- trunk/src/mainboard/via/vt8454c/romstage.c Wed Mar 31 16:34:40 2010 (r5341) +++ trunk/src/mainboard/via/vt8454c/romstage.c Wed Mar 31 16:47:43 2010 (r5342) @@ -121,7 +121,7 @@ #ifdef DEACTIVATE_CAR print_debug("Deactivating CAR"); #include DEACTIVATE_CAR_FILE - print_debug(" - Done.\r\n"); + print_debug(" - Done.\n"); #endif copy_and_run(0); } Modified: trunk/src/northbridge/amd/amdk8/amdk8_f.h ============================================================================== --- trunk/src/northbridge/amd/amdk8/amdk8_f.h Wed Mar 31 16:34:40 2010 (r5341) +++ trunk/src/northbridge/amd/amdk8/amdk8_f.h Wed Mar 31 16:47:43 2010 (r5342) @@ -559,7 +559,7 @@ for(i=0; i<sysinfo->nodes; i++) { #ifdef __PRE_RAM__ - print_debug("mem_trained["); print_debug_hex8(i); print_debug("]="); print_debug_hex8(sysinfo->mem_trained[i]); print_debug("\r\n"); + print_debug("mem_trained["); print_debug_hex8(i); print_debug("]="); print_debug_hex8(sysinfo->mem_trained[i]); print_debug("\n"); #else printk(BIOS_DEBUG, "mem_trained[%02x]=%02x\n", i, sysinfo->mem_trained[i]); #endif @@ -576,7 +576,7 @@ } if(needs_reset) { #ifdef __PRE_RAM__ - print_debug("mem trained failed\r\n"); + print_debug("mem trained failed\n"); soft_reset(); #else printk(BIOS_DEBUG, "mem trained failed\n"); Modified: trunk/src/northbridge/amd/amdk8/coherent_ht.c ============================================================================== --- trunk/src/northbridge/amd/amdk8/coherent_ht.c Wed Mar 31 16:34:40 2010 (r5341) +++ trunk/src/northbridge/amd/amdk8/coherent_ht.c Wed Mar 31 16:47:43 2010 (r5342) @@ -111,7 +111,7 @@ static inline void print_linkn (const char *strval, uint8_t byteval) { - printk(BIOS_DEBUG, "%s%02x\r\n", strval, byteval); + printk(BIOS_DEBUG, "%s%02x\n", strval, byteval); } static void disable_probes(void) @@ -149,7 +149,7 @@ HTTC_DIS_RD_DW_P | HTTC_DIS_RD_B_P; pci_write_config32(NODE_HT(0), HT_TRANSACTION_CONTROL, val); - print_spew("done.\r\n"); + print_spew("done.\n"); } @@ -200,7 +200,7 @@ val &= ~((1<<1)|(1<<0)); pci_write_config32(NODE_HT(node), 0x6c, val); - print_spew(" done.\r\n"); + print_spew(" done.\n"); } static void fill_row(u8 node, u8 row, u32 value) @@ -250,7 +250,7 @@ val |= node; /* new node */ pci_write_config32(NODE_HT(7), 0x60, val); - print_spew(" done.\r\n"); + print_spew(" done.\n"); } static int verify_connection(u8 dest) @@ -513,7 +513,7 @@ pci_write_config32(NODE_MP(7), reg, value); } - print_spew("done\r\n"); + print_spew("done\n"); } #endif /* CONFIG_MAX_PHYSICAL_CPUS > 1*/ @@ -652,7 +652,7 @@ static void setup_uniprocessor(void) { - print_spew("Enabling UP settings\r\n"); + print_spew("Enabling UP settings\n"); #if CONFIG_LOGICAL_CPUS==1 unsigned tmp = (pci_read_config32(NODE_MC(0), 0xe8) >> 12) & 3; if (tmp>0) return; @@ -1478,7 +1478,7 @@ { unsigned nodes; - print_spew("Enabling SMP settings\r\n"); + print_spew("Enabling SMP settings\n"); nodes = setup_smp2(); #if CONFIG_MAX_PHYSICAL_CPUS > 2 @@ -1496,7 +1496,7 @@ nodes = setup_smp8(); #endif - printk(BIOS_DEBUG, "%02x nodes initialized.\r\n", nodes); + printk(BIOS_DEBUG, "%02x nodes initialized.\n", nodes); return nodes; } @@ -1515,14 +1515,14 @@ #if CONFIG_MAX_PHYSICAL_CPUS > 2 case 0x02: /* MPCap */ if(nodes > 2) { - print_err("Going back to DP\r\n"); + print_err("Going back to DP\n"); return 2; } break; #endif case 0x00: /* Non SMP */ if(nodes >1 ) { - print_err("Going back to UP\r\n"); + print_err("Going back to UP\n"); return 1; } break; @@ -1601,7 +1601,7 @@ * registers on Hammer A0 revision. */ - print_spew("coherent_ht_finalize\r\n"); + print_spew("coherent_ht_finalize\n"); #if CONFIG_K8_REV_F_SUPPORT == 0 rev_a0 = is_cpu_rev_a0(); #endif @@ -1642,7 +1642,7 @@ #endif } - print_spew("done\r\n"); + print_spew("done\n"); } static int apply_cpu_errata_fixes(unsigned nodes) Modified: trunk/src/northbridge/amd/amdk8/incoherent_ht.c ============================================================================== --- trunk/src/northbridge/amd/amdk8/incoherent_ht.c Wed Mar 31 16:34:40 2010 (r5341) +++ trunk/src/northbridge/amd/amdk8/incoherent_ht.c Wed Mar 31 16:47:43 2010 (r5342) @@ -26,7 +26,7 @@ static inline void print_linkn_in (const char *strval, uint8_t byteval) { - printk(BIOS_DEBUG, "%s%02x\r\n", strval, byteval); + printk(BIOS_DEBUG, "%s%02x\n", strval, byteval); } static uint8_t ht_lookup_capability(device_t dev, uint16_t val) @@ -127,7 +127,7 @@ uint32_t id; freq_cap = pci_read_config16(dev, pos); - printk(BIOS_SPEW, "pos=0x%x, unfiltered freq_cap=0x%x\r\n", pos, freq_cap); + printk(BIOS_SPEW, "pos=0x%x, unfiltered freq_cap=0x%x\n", pos, freq_cap); freq_cap &= ~(1 << HT_FREQ_VENDOR); /* Ignore Vendor HT frequencies */ id = pci_read_config32(dev, 0); @@ -157,8 +157,8 @@ #endif } - printk(BIOS_SPEW, "pos=0x%x, filtered freq_cap=0x%x\r\n", pos, freq_cap); - //printk(BIOS_SPEW, "capping to 800/600/400/200 MHz\r\n"); + printk(BIOS_SPEW, "pos=0x%x, filtered freq_cap=0x%x\n", pos, freq_cap); + //printk(BIOS_SPEW, "capping to 800/600/400/200 MHz\n"); //freq_cap &= 0x3f; return freq_cap; } @@ -220,14 +220,14 @@ int needs_reset; /* Set link width and frequency */ - printk(BIOS_SPEW, "entering ht_optimize_link\r\n"); + printk(BIOS_SPEW, "entering ht_optimize_link\n"); /* Initially assume everything is already optimized and I don't need a reset */ needs_reset = 0; /* Get the frequency capabilities */ freq_cap1 = ht_read_freq_cap(dev1, pos1 + LINK_FREQ_CAP(offs1)); freq_cap2 = ht_read_freq_cap(dev2, pos2 + LINK_FREQ_CAP(offs2)); - printk(BIOS_SPEW, "freq_cap1=0x%x, freq_cap2=0x%x\r\n", freq_cap1, freq_cap2); + printk(BIOS_SPEW, "freq_cap1=0x%x, freq_cap2=0x%x\n", freq_cap1, freq_cap2); /* Calculate the highest possible frequency */ freq = log2(freq_cap1 & freq_cap2); @@ -236,11 +236,11 @@ old_freq = pci_read_config8(dev1, pos1 + LINK_FREQ(offs1)); old_freq &= 0x0f; needs_reset |= old_freq != freq; - printk(BIOS_SPEW, "dev1 old_freq=0x%x, freq=0x%x, needs_reset=0x%0x\r\n", old_freq, freq, needs_reset); + printk(BIOS_SPEW, "dev1 old_freq=0x%x, freq=0x%x, needs_reset=0x%0x\n", old_freq, freq, needs_reset); old_freq = pci_read_config8(dev2, pos2 + LINK_FREQ(offs2)); old_freq &= 0x0f; needs_reset |= old_freq != freq; - printk(BIOS_SPEW, "dev2 old_freq=0x%x, freq=0x%x, needs_reset=0x%0x\r\n", old_freq, freq, needs_reset); + printk(BIOS_SPEW, "dev2 old_freq=0x%x, freq=0x%x, needs_reset=0x%0x\n", old_freq, freq, needs_reset); /* Set the Calculated link frequency */ pci_write_config8(dev1, pos1 + LINK_FREQ(offs1), freq); @@ -249,45 +249,45 @@ /* Get the width capabilities */ width_cap1 = ht_read_width_cap(dev1, pos1 + LINK_WIDTH(offs1)); width_cap2 = ht_read_width_cap(dev2, pos2 + LINK_WIDTH(offs2)); - printk(BIOS_SPEW, "width_cap1=0x%x, width_cap2=0x%x\r\n", width_cap1, width_cap2); + printk(BIOS_SPEW, "width_cap1=0x%x, width_cap2=0x%x\n", width_cap1, width_cap2); /* Calculate dev1's input width */ ln_width1 = link_width_to_pow2[width_cap1 & 7]; ln_width2 = link_width_to_pow2[(width_cap2 >> 4) & 7]; - printk(BIOS_SPEW, "dev1 input ln_width1=0x%x, ln_width2=0x%x\r\n", ln_width1, ln_width2); + printk(BIOS_SPEW, "dev1 input ln_width1=0x%x, ln_width2=0x%x\n", ln_width1, ln_width2); if (ln_width1 > ln_width2) { ln_width1 = ln_width2; } width = pow2_to_link_width[ln_width1]; - printk(BIOS_SPEW, "dev1 input width=0x%x\r\n", width); + printk(BIOS_SPEW, "dev1 input width=0x%x\n", width); /* Calculate dev1's output width */ ln_width1 = link_width_to_pow2[(width_cap1 >> 4) & 7]; ln_width2 = link_width_to_pow2[width_cap2 & 7]; - printk(BIOS_SPEW, "dev1 output ln_width1=0x%x, ln_width2=0x%x\r\n", ln_width1, ln_width2); + printk(BIOS_SPEW, "dev1 output ln_width1=0x%x, ln_width2=0x%x\n", ln_width1, ln_width2); if (ln_width1 > ln_width2) { ln_width1 = ln_width2; } width |= pow2_to_link_width[ln_width1] << 4; - printk(BIOS_SPEW, "dev1 input|output width=0x%x\r\n", width); + printk(BIOS_SPEW, "dev1 input|output width=0x%x\n", width); /* See if I am changing dev1's width */ old_width = pci_read_config8(dev1, pos1 + LINK_WIDTH(offs1) + 1); old_width &= 0x77; needs_reset |= old_width != width; - printk(BIOS_SPEW, "old dev1 input|output width=0x%x\r\n", width); + printk(BIOS_SPEW, "old dev1 input|output width=0x%x\n", width); /* Set dev1's widths */ pci_write_config8(dev1, pos1 + LINK_WIDTH(offs1) + 1, width); /* Calculate dev2's width */ width = ((width & 0x70) >> 4) | ((width & 0x7) << 4); - printk(BIOS_SPEW, "dev2 input|output width=0x%x\r\n", width); + printk(BIOS_SPEW, "dev2 input|output width=0x%x\n", width); /* See if I am changing dev2's width */ old_width = pci_read_config8(dev2, pos2 + LINK_WIDTH(offs2) + 1); old_width &= 0x77; needs_reset |= old_width != width; - printk(BIOS_SPEW, "old dev2 input|output width=0x%x\r\n", width); + printk(BIOS_SPEW, "old dev2 input|output width=0x%x\n", width); /* Set dev2's widths */ pci_write_config8(dev2, pos2 + LINK_WIDTH(offs2) + 1, width); @@ -371,7 +371,7 @@ print_err("udev="); print_err_hex32(udev); print_err("\tupos="); print_err_hex32(upos); print_err("\tuoffs="); print_err_hex32(uoffs); - print_err("\tHT link capability not found\r\n"); + print_err("\tHT link capability not found\n"); break; } @@ -852,16 +852,16 @@ unsigned link_pair_num = sysinfo->link_pair_num; - printk(BIOS_SPEW, "entering optimize_link_incoherent_ht\r\n"); - printk(BIOS_SPEW, "sysinfo->link_pair_num=0x%x\r\n", link_pair_num); + printk(BIOS_SPEW, "entering optimize_link_incoherent_ht\n"); + printk(BIOS_SPEW, "sysinfo->link_pair_num=0x%x\n", link_pair_num); for(i=0; i< link_pair_num; i++) { struct link_pair_st *link_pair= &sysinfo->link_pair[i]; reset_needed |= ht_optimize_link(link_pair->udev, link_pair->upos, link_pair->uoffs, link_pair->dev, link_pair->pos, link_pair->offs); - printk(BIOS_SPEW, "after ht_optimize_link for link pair %d, reset_needed=0x%x\r\n", i, reset_needed); + printk(BIOS_SPEW, "after ht_optimize_link for link pair %d, reset_needed=0x%x\n", i, reset_needed); } reset_needed |= optimize_link_read_pointers_chain(sysinfo->ht_c_num); - printk(BIOS_SPEW, "after optimize_link_read_pointers_chain, reset_needed=0x%x\r\n", reset_needed); + printk(BIOS_SPEW, "after optimize_link_read_pointers_chain, reset_needed=0x%x\n", reset_needed); return reset_needed; Modified: trunk/src/northbridge/amd/amdk8/northbridge.c ============================================================================== --- trunk/src/northbridge/amd/amdk8/northbridge.c Wed Mar 31 16:34:40 2010 (r5341) +++ trunk/src/northbridge/amd/amdk8/northbridge.c Wed Mar 31 16:47:43 2010 (r5342) @@ -1224,7 +1224,7 @@ e0_later_single_core = 0; } if(e0_later_single_core) { - printk(BIOS_DEBUG, "\tFound Rev E or Rev F later single core\r\n"); + printk(BIOS_DEBUG, "\tFound Rev E or Rev F later single core\n"); j=1; } Modified: trunk/src/northbridge/amd/amdk8/raminit_f_dqs.c ============================================================================== --- trunk/src/northbridge/amd/amdk8/raminit_f_dqs.c Wed Mar 31 16:34:40 2010 (r5341) +++ trunk/src/northbridge/amd/amdk8/raminit_f_dqs.c Wed Mar 31 16:47:43 2010 (r5342) @@ -25,7 +25,7 @@ { #if DQS_TRAIN_DEBUG > 0 if(DQS_TRAIN_DEBUG > level) { - printk(BIOS_DEBUG, "%s%x\r\n", str, val); + printk(BIOS_DEBUG, "%s%x\n", str, val); } #endif } @@ -34,7 +34,7 @@ { #if DQS_TRAIN_DEBUG > 0 if(DQS_TRAIN_DEBUG > level) { - printk(BIOS_DEBUG, "%s%08x%s%08x\r\n", str, val, str2, val2); + printk(BIOS_DEBUG, "%s%08x%s%08x\n", str, val, str2, val2); } #endif } @@ -43,14 +43,14 @@ { #if DQS_TRAIN_DEBUG > 0 if(DQS_TRAIN_DEBUG > level) { - printk(BIOS_DEBUG, "%s[%02x]=%08x%08x\r\n", str, i, val, val2); + printk(BIOS_DEBUG, "%s[%02x]=%08x%08x\n", str, i, val, val2); } #endif } static inline void print_debug_dqs_tsc_x(const char *str, unsigned i, unsigned val, unsigned val2) { - printk(BIOS_DEBUG, "%s[%02x]=%08x%08x\r\n", str, i, val, val2); + printk(BIOS_DEBUG, "%s[%02x]=%08x%08x\n", str, i, val, val2); } @@ -583,7 +583,7 @@ } } - print_debug_dqs("\r\nTrainRcvEn: 0 ctrl", ctrl->node_id, 0); + print_debug_dqs("\nTrainRcvEn: 0 ctrl", ctrl->node_id, 0); print_debug_addr("TrainRcvEn: buf_a:", buf_a); @@ -1401,7 +1401,7 @@ } - print_debug_dqs("\r\nTrainDQSRdWrPos: 0 ctrl ", ctrl->node_id, 0); + print_debug_dqs("\nTrainDQSRdWrPos: 0 ctrl ", ctrl->node_id, 0); printk(BIOS_DEBUG, "TrainDQSRdWrPos: buf_a:%p\n", buf_a); @@ -1525,25 +1525,25 @@ static unsigned train_DqsRcvrEn(const struct mem_controller *ctrl, unsigned Pass, struct sys_info *sysinfo) { - print_debug_dqs("\r\ntrain_DqsRcvrEn: begin ctrl ", ctrl->node_id, 0); + print_debug_dqs("\ntrain_DqsRcvrEn: begin ctrl ", ctrl->node_id, 0); if(TrainRcvrEn(ctrl, Pass, sysinfo)) { return 1; } - print_debug_dqs("\r\ntrain_DqsRcvrEn: end ctrl ", ctrl->node_id, 0); + print_debug_dqs("\ntrain_DqsRcvrEn: end ctrl ", ctrl->node_id, 0); return 0; } static unsigned train_DqsPos(const struct mem_controller *ctrl, struct sys_info *sysinfo) { - print_debug_dqs("\r\ntrain_DqsPos: begin ctrl ", ctrl->node_id, 0); + print_debug_dqs("\ntrain_DqsPos: begin ctrl ", ctrl->node_id, 0); if(TrainDQSRdWrPos(ctrl, sysinfo) != 0) { - printk(BIOS_ERR, "\r\nDQS Training Rd Wr failed ctrl%02x\r\n", ctrl->node_id); + printk(BIOS_ERR, "\nDQS Training Rd Wr failed ctrl%02x\n", ctrl->node_id); return 1; } else { SetEccDQSRdWrPos(ctrl, sysinfo); } - print_debug_dqs("\r\ntrain_DqsPos: end ctrl ", ctrl->node_id, 0); + print_debug_dqs("\ntrain_DqsPos: end ctrl ", ctrl->node_id, 0); return 0; } @@ -1700,7 +1700,7 @@ } sizek = 1 << align; #if CONFIG_MEM_TRAIN_SEQ != 1 - printk(BIOS_DEBUG, "Setting variable MTRR %d, base: %4ldMB, range: %4ldMB, type %s\r\n", + printk(BIOS_DEBUG, "Setting variable MTRR %d, base: %4ldMB, range: %4ldMB, type %s\n", reg, range_startk >>10, sizek >> 10, (type==MTRR_TYPE_UNCACHEABLE)?"UC": ((type==MTRR_TYPE_WRBACK)?"WB":"Other") @@ -1952,7 +1952,7 @@ printk(BIOS_DEBUG, "DQS Training:RcvrEn:Pass1: %02x\n", i); if(train_DqsRcvrEn(ctrl+i, 1, sysinfo)) goto out; - printk(BIOS_DEBUG, " done\r\n"); + printk(BIOS_DEBUG, " done\n"); } tsc[1] = rdtsc(); @@ -1970,7 +1970,7 @@ printk(BIOS_DEBUG, "DQS Training:DQSPos: %02x\n", i); if(train_DqsPos(ctrl+i, sysinfo)) goto out; - printk(BIOS_DEBUG, " done\r\n"); + printk(BIOS_DEBUG, " done\n"); } tsc[3] = rdtsc(); @@ -1983,7 +1983,7 @@ printk(BIOS_DEBUG, "DQS Training:RcvrEn:Pass2: %02x\n", i); if(train_DqsRcvrEn(ctrl+i, 2, sysinfo)) goto out; - printk(BIOS_DEBUG, " done\r\n"); + printk(BIOS_DEBUG, " done\n"); sysinfo->mem_trained[i]=1; dqs_save_MC_NVRAM((ctrl+i)->f2); } @@ -2033,7 +2033,7 @@ } if(v) { - printk(BIOS_DEBUG, " done\r\n"); + printk(BIOS_DEBUG, " done\n"); tsc[1] = rdtsc(); printk(BIOS_DEBUG, "set DQS timing:DQSPos: %02x\n", i); } @@ -2044,7 +2044,7 @@ } if(v) { - printk(BIOS_DEBUG, " done\r\n"); + printk(BIOS_DEBUG, " done\n"); tsc[2] = rdtsc(); printk(BIOS_DEBUG, "set DQS timing:RcvrEn:Pass2: %02x\n", i); @@ -2055,7 +2055,7 @@ } if(v) { - printk(BIOS_DEBUG, " done\r\n"); + printk(BIOS_DEBUG, " done\n"); tsc[3] = rdtsc(); } Modified: trunk/src/northbridge/amd/amdk8/raminit_test.c ============================================================================== --- trunk/src/northbridge/amd/amdk8/raminit_test.c Wed Mar 31 16:34:40 2010 (r5341) +++ trunk/src/northbridge/amd/amdk8/raminit_test.c Wed Mar 31 16:47:43 2010 (r5342) @@ -394,7 +394,7 @@ #if 0 print_debug("spd_count: "); print_debug_hex32(spd_count); - print_debug("\r\n"); + print_debug("\n"); #endif } @@ -410,9 +410,9 @@ reset_tests(); spd_fail_count = i; - print_debug("\r\nSPD will fail after: "); + print_debug("\nSPD will fail after: "); print_debug_hex32(spd_fail_count); - print_debug(" accesses.\r\n"); + print_debug(" accesses.\n"); memcpy(&spd_data[0*256], spd_micron_512MB_DDR333, 256); memcpy(&spd_data[1*256], spd_micron_512MB_DDR333, 256); Modified: trunk/src/northbridge/amd/amdk8/setup_resource_map.c ============================================================================== --- trunk/src/northbridge/amd/amdk8/setup_resource_map.c Wed Mar 31 16:34:40 2010 (r5341) +++ trunk/src/northbridge/amd/amdk8/setup_resource_map.c Wed Mar 31 16:47:43 2010 (r5342) @@ -5,14 +5,14 @@ int i; // print_debug("setting up resource map offset...."); #if 0 - print_debug("\r\n"); + print_debug("\n"); #endif for(i = 0; i < max; i += 3) { device_t dev; unsigned where; unsigned long reg; #if 0 - prink_debug("%08x <- %08x\r\n", register_values[i] + offset_pci_dev, register_values[i+2]); + prink_debug("%08x <- %08x\n", register_values[i] + offset_pci_dev, register_values[i+2]); #endif dev = (register_values[i] & ~0xfff) + offset_pci_dev; where = register_values[i] & 0xfff; @@ -27,7 +27,7 @@ pci_write_config32(register_values[i], reg); #endif } -// print_debug("done.\r\n"); +// print_debug("done.\n"); } #define RES_PCI_IO 0x10 @@ -45,11 +45,11 @@ #endif #if RES_DEBUG - print_debug("\r\n"); + print_debug("\n"); #endif for(i = 0; i < max; i += 4) { #if RES_DEBUG - printk(BIOS_DEBUG, "%04x: %02x %08x <- & %08x | %08x\r\n", + printk(BIOS_DEBUG, "%04x: %02x %08x <- & %08x | %08x\n", i>>2, register_values[i], register_values[i+1] + ( (register_values[i]==RES_PCI_IO) ? offset_pci_dev : 0), register_values[i+2], @@ -112,7 +112,7 @@ } #if RES_DEBUG - print_debug("done.\r\n"); + print_debug("done.\n"); #endif } static void setup_resource_map_x(const unsigned int *register_values, int max) @@ -125,11 +125,11 @@ #endif #if RES_DEBUG - print_debug("\r\n"); + print_debug("\n"); #endif for(i = 0; i < max; i += 4) { #if RES_DEBUG - printk(BIOS_DEBUG, "%04x: %02x %08x <- & %08x | %08x\r\n", + printk(BIOS_DEBUG, "%04x: %02x %08x <- & %08x | %08x\n", i/4, register_values[i],register_values[i+1], register_values[i+2], register_values[i+3]); #endif switch (register_values[i]) { @@ -188,7 +188,7 @@ } #if RES_DEBUG - print_debug("done.\r\n"); + print_debug("done.\n"); #endif } @@ -223,7 +223,7 @@ print_debug(" -> "); reg = inb(where); print_debug_hex8(reg); - print_debug("\r\n"); + print_debug("\n"); #endif } } @@ -262,7 +262,7 @@ print_debug(" -> "); reg = inl(where); print_debug_hex32(reg); - print_debug("\r\n"); + print_debug("\n"); #endif } } @@ -289,7 +289,7 @@ print_debug(" RB "); reg = read32(where); print_debug_hex32(reg); - print_debug("\r\n"); + print_debug("\n"); #endif } } Modified: trunk/src/northbridge/amd/gx1/raminit.c ============================================================================== --- trunk/src/northbridge/amd/gx1/raminit.c Wed Mar 31 16:34:40 2010 (r5341) +++ trunk/src/northbridge/amd/gx1/raminit.c Wed Mar 31 16:47:43 2010 (r5342) @@ -143,7 +143,7 @@ #if 0 print_debug("MC_BANK_CFG = "); print_debug_hex32(getGX1Mem(GX_BASE + MC_BANK_CFG)); - print_debug("\r\n"); + print_debug("\n"); #endif /* retrieve the page size from the MC register */ @@ -152,7 +152,7 @@ #if 0 print_debug(" page_size = "); print_debug_hex32(page_size); - print_debug("\r\n"); + print_debug("\n"); #endif comp_banks = (((getGX1Mem(GX_BASE + MC_BANK_CFG) & (DIMM_COMP_BNK << dimm_shift)) >> dimm_shift) >> 12); @@ -169,7 +169,7 @@ #if 0 print_debug("MC_BANK_CFG = "); print_debug_hex32(getGX1Mem(GX_BASE + MC_BANK_CFG)); - print_debug("\r\n"); + print_debug("\n"); #endif return(getGX1Mem(GX_BASE + MC_BANK_CFG) & (DIMM_MOD_BNK << dimm_shift)); } @@ -181,7 +181,7 @@ #if 0 print_debug("MC_BANK_CFG = "); print_debug_hex32(getGX1Mem(GX_BASE + MC_BANK_CFG)); - print_debug("\r\n"); + print_debug("\n"); #endif page_size = page_size << (((getGX1Mem(GX_BASE + MC_BANK_CFG) & (DIMM_PG_SZ << dimm_shift)) >> dimm_shift) >> 4); @@ -189,7 +189,7 @@ #if 0 print_debug(" page_size = "); print_debug_hex32(page_size); - print_debug("\r\n"); + print_debug("\n"); #endif setGX1Mem(0, TEST_DATA1); @@ -203,7 +203,7 @@ #if 0 print_debug("MC_BANK_CFG = "); print_debug_hex32(getGX1Mem(GX_BASE + MC_BANK_CFG)); - print_debug("\r\n"); + print_debug("\n"); #endif return(getGX1Mem(GX_BASE + MC_BANK_CFG) & (DIMM_COMP_BNK << dimm_shift)); } @@ -225,7 +225,7 @@ #if 0 print_debug(" Page size Config = "); print_debug_hex32(page_size_config << dimm_shift); - print_debug("\r\n"); + print_debug("\n"); #endif return(page_size_config << dimm_shift); } @@ -257,7 +257,7 @@ print_debug("Probing for DIMM"); print_debug_char((dimm_shift >> 4) + 0x30); - print_debug("\r\n"); + print_debug("\n"); setGX1Mem(0, TEST_DATA1); setGX1Mem(0x100, 0); @@ -269,7 +269,7 @@ print_debug(" Found DIMM"); print_debug_char((dimm_shift >> 4) + 0x30); - print_debug("\r\n"); + print_debug("\n"); return 1; } @@ -285,7 +285,7 @@ print_debug(" Page Size: "); print_debug_hex32(0x400 << ((mem_config & (DIMM_PG_SZ << dimm_shift)) >> (dimm_shift + 4))); - print_debug("\r\n"); + print_debug("\n"); /* Now do component banks detection */ @@ -294,7 +294,7 @@ print_debug(" Component Banks: "); print_debug_char((((mem_config & (DIMM_COMP_BNK << dimm_shift)) >> (dimm_shift + 12)) ? 4 : 2) + 0x30); - print_debug("\r\n"); + print_debug("\n"); /* Now do module banks */ @@ -303,7 +303,7 @@ print_debug(" Module Banks: "); print_debug_char((((mem_config & (DIMM_MOD_BNK << dimm_shift)) >> (dimm_shift + 14)) ? 2 : 1) + 0x30); - print_debug("\r\n"); + print_debug("\n"); mem_config &= (~(DIMM_SZ << dimm_shift)); mem_config |= (size_dimm(dimm_shift)); @@ -311,7 +311,7 @@ print_debug(" DIMM size: "); print_debug_hex32(1 << ((mem_config & (DIMM_SZ << dimm_shift)) >> (dimm_shift + 8)) + 22); - print_debug("\r\n"); + print_debug("\n"); return (mem_config); } @@ -320,7 +320,7 @@ { unsigned int mem_config = 0x00700070; - print_debug("Setting up default parameters for memory\r\n"); + print_debug("Setting up default parameters for memory\n"); outb(0x70, 0x80); setGX1Mem(GX_BASE + MC_MEM_CNTRL2, 0x000007d8); /* Disable all CLKS, Shift = 3 */ @@ -335,7 +335,7 @@ enable_dimm(); - print_debug("Sizing memory\r\n"); + print_debug("Sizing memory\n"); setGX1Mem(GX_BASE + MC_BANK_CFG, 0x00705740); do_refresh(); @@ -346,7 +346,7 @@ print_debug("MC_BANK_CFG = "); print_debug_hex32(mem_config); - print_debug("\r\n"); + print_debug("\n"); setGX1Mem(GX_BASE + MC_BANK_CFG, mem_config); enable_dimm(); Modified: trunk/src/northbridge/amd/gx2/pll_reset.c ============================================================================== --- trunk/src/northbridge/amd/gx2/pll_reset.c Wed Mar 31 16:34:40 2010 (r5341) +++ trunk/src/northbridge/amd/gx2/pll_reset.c Wed Mar 31 16:47:43 2010 (r5342) @@ -276,11 +276,11 @@ msr.lo |= PLLMSRlo1; wrmsr(GLCP_SYS_RSTPLL, msr); - print_debug("Reset PLL\n\r"); + print_debug("Reset PLL\n"); msr.lo |= PLLMSRlo2; wrmsr(GLCP_SYS_RSTPLL,msr); - print_debug("should not be here\n\r"); + print_debug("should not be here\n"); #endif print_err("shit"); while (1) @@ -289,7 +289,7 @@ if (msr.lo & GLCP_SYS_RSTPLL_SWFLAGS_MASK) { /* PLL is already set and we are reboot from PLL reset */ - print_debug("reboot from BIOS reset\n\r"); + print_debug("reboot from BIOS reset\n"); return; } @@ -310,11 +310,11 @@ msr.lo |= ((0xde << 16) | (1 << 26) | (1 << 24)); wrmsr(0x4c000014, msr); - print_debug("Reset PLL\n\r"); + print_debug("Reset PLL\n"); msr.lo |= ((1<<14) |(1<<13) | (1<<0)); wrmsr(0x4c000014,msr); - print_debug("should not be here\n\r"); + print_debug("should not be here\n"); } #endif // #if USE_GOODRICH_VERSION Modified: trunk/src/northbridge/amd/gx2/raminit.c ============================================================================== --- trunk/src/northbridge/amd/gx2/raminit.c Wed Mar 31 16:34:40 2010 (r5341) +++ trunk/src/northbridge/amd/gx2/raminit.c Wed Mar 31 16:47:43 2010 (r5342) @@ -21,13 +21,13 @@ msr = rdmsr(0x2000001a); msr.lo = 0x0101; wrmsr(0x2000001a, msr); - //print_debug("sdram_enable step 2\r\n"); + //print_debug("sdram_enable step 2\n"); /* 3. release CKE mask to enable CKE */ msr = rdmsr(0x2000001d); msr.lo &= ~(0x03 << 8); wrmsr(0x2000201d, msr); - //print_debug("sdram_enable step 3\r\n"); + //print_debug("sdram_enable step 3\n"); /* 4. set and clear REF_TST 16 times, more shouldn't hurt * why this is before EMRS and MRS ? */ @@ -38,7 +38,7 @@ msr.lo &= ~(0x01 << 3); wrmsr(0x20000018, msr); } - //print_debug("sdram_enable step 4\r\n"); + //print_debug("sdram_enable step 4\n"); /* 5. set refresh interval */ msr = rdmsr(0x20000018); @@ -50,7 +50,7 @@ msr.lo &= ~(0x03 << 6); msr.lo |= (0x00 << 6); wrmsr(0x20000018, msr); - //print_debug("sdram_enable step 5\r\n"); + //print_debug("sdram_enable step 5\n"); /* 6. enable DLL, load Extended Mode Register by set and clear PROG_DRAM */ msr = rdmsr(0x20000018); @@ -58,7 +58,7 @@ wrmsr(0x20000018, msr); msr.lo &= ~((0x01 << 28) | 0x01); wrmsr(0x20000018, msr); - //print_debug("sdram_enable step 6\r\n"); + //print_debug("sdram_enable step 6\n"); /* 7. Reset DLL, Bit 27 is undocumented in GX datasheet, * it is documented in LX datasheet */ @@ -68,7 +68,7 @@ wrmsr(0x20000018, msr); msr.lo &= ~((0x01 << 27) | 0x01); wrmsr(0x20000018, msr); - //print_debug("sdram_enable step 7\r\n"); + //print_debug("sdram_enable step 7\n"); /* 8. load Mode Register by set and clear PROG_DRAM */ msr = rdmsr(0x20000018); @@ -76,7 +76,7 @@ wrmsr(0x20000018, msr); msr.lo &= ~0x01; wrmsr(0x20000018, msr); - //print_debug("sdram_enable step 8\r\n"); + //print_debug("sdram_enable step 8\n"); /* wait 200 SDCLKs */ for (i = 0; i < 200; i++) @@ -107,7 +107,7 @@ /* make sure there is nothing stale in the cache */ __asm__("wbinvd\n"); - print_debug("RAM DLL lock\r\n"); + print_debug("RAM DLL lock\n"); /* The RAM dll needs a write to lock on so generate a few dummy writes */ volatile unsigned long *ptr; for (i=0;i<5;i++) { Modified: trunk/src/northbridge/amd/lx/pll_reset.c ============================================================================== --- trunk/src/northbridge/amd/lx/pll_reset.c Wed Mar 31 16:34:40 2010 (r5341) +++ trunk/src/northbridge/amd/lx/pll_reset.c Wed Mar 31 16:47:43 2010 (r5342) @@ -68,7 +68,7 @@ __asm__ __volatile__("hlt\n"); } - print_debug("Done pll_reset\r\n"); + print_debug("Done pll_reset\n"); return; } Modified: trunk/src/northbridge/amd/lx/raminit.c ============================================================================== --- trunk/src/northbridge/amd/lx/raminit.c Wed Mar 31 16:34:40 2010 (r5341) +++ trunk/src/northbridge/amd/lx/raminit.c Wed Mar 31 16:47:43 2010 (r5342) @@ -32,12 +32,12 @@ /* This is so ugly. */ print_debug("==========================="); print_debug(s); - print_debug("======================================\r\n"); + print_debug("======================================\n"); } void hcf(void) { - print_emerg("DIE\r\n"); + print_emerg("DIE\n"); /* this guarantees we flush the UART fifos (if any) and also * ensures that things, in general, keep going so no debug output * is lost @@ -200,7 +200,7 @@ /* current speed > max speed? */ if (GeodeLinkSpeed() > speed) { - print_emerg("DIMM overclocked. Check GeodeLink Speed\r\n"); + print_emerg("DIMM overclocked. Check GeodeLink Speed\n"); POST_CODE(POST_PLL_MEM_FAIL); hcf(); } @@ -340,7 +340,7 @@ } else if ((casmap0 &= casmap1)) { spd_byte = CASDDR[__builtin_ctz((uint32_t) casmap0)]; } else { - print_emerg("DIMM CAS Latencies not compatible\r\n"); + print_emerg("DIMM CAS Latencies not compatible\n"); POST_CODE(ERROR_DIFF_DIMMS); hcf(); } @@ -532,7 +532,7 @@ msr.lo |= CFCLK_LOWER_TRISTATE_DIS_SET; wrmsr(MC_CFCLK_DBUG, msr); - print_info("Enabled MTest for TLA debug\r\n"); + print_info("Enabled MTest for TLA debug\n"); } static void sdram_set_registers(const struct mem_controller *ctrl) @@ -576,7 +576,7 @@ banner("Check DIMM 0"); /* Check DIMM is not Register and not Buffered DIMMs. */ if ((spd_byte != 0xFF) && (spd_byte & 3)) { - print_emerg("DIMM0 NOT COMPATIBLE\r\n"); + print_emerg("DIMM0 NOT COMPATIBLE\n"); POST_CODE(ERROR_UNSUPPORTED_DIMM); hcf(); } @@ -649,7 +649,7 @@ msr = rdmsr(MC_CF07_DATA); if ((msr.hi & ((7 << CF07_UPPER_D1_PSZ_SHIFT) | (7 << CF07_UPPER_D0_PSZ_SHIFT))) == ((7 << CF07_UPPER_D1_PSZ_SHIFT) | (7 << CF07_UPPER_D0_PSZ_SHIFT))) { - print_emerg("No memory in the system\r\n"); + print_emerg("No memory in the system\n"); POST_CODE(ERROR_NO_DIMMS); hcf(); } Modified: trunk/src/northbridge/intel/e7501/debug.c ============================================================================== --- trunk/src/northbridge/intel/e7501/debug.c Wed Mar 31 16:34:40 2010 (r5341) +++ trunk/src/northbridge/intel/e7501/debug.c Wed Mar 31 16:47:43 2010 (r5342) @@ -27,7 +27,7 @@ continue; } print_debug_pci_dev(dev); - print_debug("\r\n"); + print_debug("\n"); } } @@ -40,9 +40,9 @@ unsigned char val; if ((i & 0x0f) == 0) { #if CONFIG_USE_PRINTK_IN_CAR - printk(BIOS_DEBUG, "\r\n%02x:",i); + printk(BIOS_DEBUG, "\n%02x:",i); #else - print_debug("\r\n"); + print_debug("\n"); print_debug_hex8(i); print_debug_char(':'); #endif @@ -55,7 +55,7 @@ print_debug_hex8(val); #endif } - print_debug("\r\n"); + print_debug("\n"); } static void dump_pci_devices(void) @@ -95,7 +95,7 @@ static void dump_spd_registers(const struct mem_controller *ctrl) { int i; - print_debug("\r\n"); + print_debug("\n"); for(i = 0; i < 4; i++) { unsigned device; device = ctrl->channel0[i]; @@ -114,9 +114,9 @@ unsigned char byte; if ((j & 0xf) == 0) { #if CONFIG_USE_PRINTK_IN_CAR - printk(BIOS_DEBUG, "\r\n%02x: ", j); + printk(BIOS_DEBUG, "\n%02x: ", j); #else - print_debug("\r\n"); + print_debug("\n"); print_debug_hex8(j); print_debug(": "); #endif @@ -133,7 +133,7 @@ print_debug_char(' '); #endif } - print_debug("\r\n"); + print_debug("\n"); } device = ctrl->channel1[i]; if (device) { @@ -151,9 +151,9 @@ unsigned char byte; if ((j & 0xf) == 0) { #if CONFIG_USE_PRINTK_IN_CAR - printk(BIOS_DEBUG, "\r\n%02x: ", j); + printk(BIOS_DEBUG, "\n%02x: ", j); #else - print_debug("\r\n"); + print_debug("\n"); print_debug_hex8(j); print_debug(": "); #endif @@ -170,14 +170,14 @@ print_debug_char(' '); #endif } - print_debug("\r\n"); + print_debug("\n"); } } } static void dump_smbus_registers(void) { unsigned device; - print_debug("\r\n"); + print_debug("\n"); for(device = 1; device < 0x80; device++) { int j; if( smbus_read_byte(device, 0) < 0 ) continue; @@ -196,9 +196,9 @@ } if ((j & 0xf) == 0) { #if CONFIG_USE_PRINTK_IN_CAR - printk(BIOS_DEBUG, "\r\n%02x: ",j); + printk(BIOS_DEBUG, "\n%02x: ",j); #else - print_debug("\r\n"); + print_debug("\n"); print_debug_hex8(j); print_debug(": "); #endif @@ -211,7 +211,7 @@ print_debug_char(' '); #endif } - print_debug("\r\n"); + print_debug("\n"); } } @@ -220,10 +220,10 @@ int i; #if CONFIG_USE_PRINTK_IN_CAR - printk(BIOS_DEBUG, "%04x:\r\n", port); + printk(BIOS_DEBUG, "%04x:\n", port); #else print_debug_hex16(port); - print_debug(":\r\n"); + print_debug(":\n"); #endif for(i=0;i<256;i++) { uint8_t val; @@ -243,7 +243,7 @@ print_debug_hex8(val); #endif if ((i & 0x0f) == 0x0f) { - print_debug("\r\n"); + print_debug("\n"); } port++; } @@ -256,9 +256,9 @@ for(i=start;i<end;i++) { if((i & 0xf)==0) { #if CONFIG_USE_PRINTK_IN_CAR - printk(BIOS_DEBUG, "\r\n%08x:", i); + printk(BIOS_DEBUG, "\n%08x:", i); #else - print_debug("\r\n"); + print_debug("\n"); print_debug_hex32(i); print_debug(":"); #endif @@ -270,6 +270,6 @@ print_debug_hex8((unsigned char)*((unsigned char *)i)); #endif } - print_debug("\r\n"); + print_debug("\n"); } #endif Modified: trunk/src/northbridge/intel/e7501/raminit.c ============================================================================== --- trunk/src/northbridge/intel/e7501/raminit.c Wed Mar 31 16:34:40 2010 (r5341) +++ trunk/src/northbridge/intel/e7501/raminit.c Wed Mar 31 16:47:43 2010 (r5342) @@ -35,7 +35,7 @@ #endif #define E7501_SDRAM_MODE (SDRAM_BURST_INTERLEAVED | SDRAM_BURST_4) -#define SPD_ERROR "Error reading SPD info\r\n" +#define SPD_ERROR "Error reading SPD info\n" // NOTE: This used to be 0x100000. // That doesn't work on systems where A20M# is asserted, because @@ -481,7 +481,7 @@ static void die_on_spd_error(int spd_return_value) { if (spd_return_value < 0) - die("Error reading SPD info\r\n"); + die("Error reading SPD info\n"); } //---------------------------------------------------------------------------------- @@ -522,7 +522,7 @@ value = spd_read_byte(dimm_socket_address, SPD_NUM_DIMM_BANKS); if (value < 0) goto hw_err; if (value > 2) - die("Bad SPD value\r\n"); + die("Bad SPD value\n"); if (value == 2) { pgsz.side2 = pgsz.side1; // Assume symmetric banks until we know differently @@ -755,7 +755,7 @@ spd_value = spd_read_byte(channel1_dimm, SPD_MODULE_ATTRIBUTES); if (!(spd_value & MODULE_REGISTERED) || (spd_value < 0)) { - print_debug("Skipping un-matched DIMMs - only dual-channel operation supported\r\n"); + print_debug("Skipping un-matched DIMMs - only dual-channel operation supported\n"); continue; } @@ -780,11 +780,11 @@ dimm_mask |= ((1<<i) | (1<<(MAX_DIMM_SOCKETS_PER_CHANNEL + i))); } else - print_debug("Skipping un-matched DIMMs - only dual-channel operation supported\r\n"); + print_debug("Skipping un-matched DIMMs - only dual-channel operation supported\n"); #else switch (bDualChannel) { case 0: - print_debug("Skipping un-matched DIMMs - only dual-channel operation supported\r\n"); + print_debug("Skipping un-matched DIMMs - only dual-channel operation supported\n"); break; default: @@ -873,7 +873,7 @@ RAM_DEBUG_MESSAGE(" Sending RAM command to 0x"); RAM_DEBUG_HEX32(dimm_start_address + e7501_mode_bits); - RAM_DEBUG_MESSAGE("\r\n"); + RAM_DEBUG_MESSAGE("\n"); read32(dimm_start_address + e7501_mode_bits); // Set the start of the next DIMM @@ -1017,10 +1017,10 @@ RAM_DEBUG_HEX32(sz.side1); RAM_DEBUG_MESSAGE(" "); RAM_DEBUG_HEX32(sz.side2); - RAM_DEBUG_MESSAGE("\r\n"); + RAM_DEBUG_MESSAGE("\n"); if (sz.side1 == 0) - die("Bad SPD value\r\n"); + die("Bad SPD value\n"); total_dram_64M_multiple = configure_dimm_row_boundaries(sz, total_dram_64M_multiple, i); } @@ -1105,7 +1105,7 @@ uint8_t byte; - RAM_DEBUG_MESSAGE("Initializing ECC state...\r\n"); + RAM_DEBUG_MESSAGE("Initializing ECC state...\n"); /* Initialize ECC bits , use ECC zero mode (new to 7501)*/ pci_write_config8(PCI_DEV(0, 0, 0), MCHCFGNS, 0x06); pci_write_config8(PCI_DEV(0, 0, 0), MCHCFGNS, 0x07); @@ -1117,7 +1117,7 @@ } while ( (byte & 0x08 ) == 0); pci_write_config8(PCI_DEV(0, 0, 0), MCHCFGNS, byte & 0xfc); - RAM_DEBUG_MESSAGE("ECC state initialized.\r\n"); + RAM_DEBUG_MESSAGE("ECC state initialized.\n"); /* Clear the ECC error bits */ pci_write_config8(PCI_DEV(0, 0, 1), DRAM_FERR, 0x03); @@ -1373,7 +1373,7 @@ } } else - die("No CAS# latencies compatible with all DIMMs!!\r\n"); + die("No CAS# latencies compatible with all DIMMs!!\n"); pci_write_config32(PCI_DEV(0, 0, 0), DRT, dram_timing); @@ -1462,14 +1462,14 @@ die_on_spd_error(value); value &= 0x7f; // Mask off self-refresh bit if(value > MAX_SPD_REFRESH_RATE) { - print_err("unsupported refresh rate\r\n"); + print_err("unsupported refresh rate\n"); continue; } // Get the appropriate E7501 refresh mode for this DIMM dimm_refresh_mode = refresh_rate_map[value]; if (dimm_refresh_mode > 7) { - print_err("unsupported refresh rate\r\n"); + print_err("unsupported refresh rate\n"); continue; } @@ -1680,7 +1680,7 @@ uint32_t dword; uint8_t maybe_strength_control; - RAM_DEBUG_MESSAGE("Setting RCOMP registers.\r\n"); + RAM_DEBUG_MESSAGE("Setting RCOMP registers.\n"); /*enable access to the rcomp bar*/ dword = pci_read_config32(PCI_DEV(0, 0, 0), MAYBE_MCHTST); @@ -1805,8 +1805,8 @@ return; /* 1 & 2 Power up and start clocks */ - RAM_DEBUG_MESSAGE("Ram Enable 1\r\n"); - RAM_DEBUG_MESSAGE("Ram Enable 2\r\n"); + RAM_DEBUG_MESSAGE("Ram Enable 1\n"); + RAM_DEBUG_MESSAGE("Ram Enable 2\n"); /* A 200us delay is needed */ @@ -1814,23 +1814,23 @@ EXTRA_DELAY /* 3. Apply NOP */ - RAM_DEBUG_MESSAGE("Ram Enable 3\r\n"); + RAM_DEBUG_MESSAGE("Ram Enable 3\n"); do_ram_command(RAM_COMMAND_NOP, 0); EXTRA_DELAY /* 4 Precharge all */ - RAM_DEBUG_MESSAGE("Ram Enable 4\r\n"); + RAM_DEBUG_MESSAGE("Ram Enable 4\n"); do_ram_command(RAM_COMMAND_PRECHARGE, 0); EXTRA_DELAY /* wait until the all banks idle state... */ /* 5. Issue EMRS to enable DLL */ - RAM_DEBUG_MESSAGE("Ram Enable 5\r\n"); + RAM_DEBUG_MESSAGE("Ram Enable 5\n"); do_ram_command(RAM_COMMAND_EMRS, SDRAM_EXTMODE_DLL_ENABLE | SDRAM_EXTMODE_DRIVE_NORMAL); EXTRA_DELAY /* 6. Reset DLL */ - RAM_DEBUG_MESSAGE("Ram Enable 6\r\n"); + RAM_DEBUG_MESSAGE("Ram Enable 6\n"); set_ram_mode(E7501_SDRAM_MODE | SDRAM_MODE_DLL_RESET); EXTRA_DELAY @@ -1842,12 +1842,12 @@ EXTRA_DELAY /* 7 Precharge all */ - RAM_DEBUG_MESSAGE("Ram Enable 7\r\n"); + RAM_DEBUG_MESSAGE("Ram Enable 7\n"); do_ram_command(RAM_COMMAND_PRECHARGE, 0); EXTRA_DELAY /* 8 Now we need 2 AUTO REFRESH / CBR cycles to be performed */ - RAM_DEBUG_MESSAGE("Ram Enable 8\r\n"); + RAM_DEBUG_MESSAGE("Ram Enable 8\n"); do_ram_command(RAM_COMMAND_CBR, 0); EXTRA_DELAY do_ram_command(RAM_COMMAND_CBR, 0); @@ -1867,17 +1867,17 @@ EXTRA_DELAY /* 9 mode register set */ - RAM_DEBUG_MESSAGE("Ram Enable 9\r\n"); + RAM_DEBUG_MESSAGE("Ram Enable 9\n"); set_ram_mode(E7501_SDRAM_MODE | SDRAM_MODE_NORMAL); EXTRA_DELAY /* 10 DDR Receive FIFO RE-Sync */ - RAM_DEBUG_MESSAGE("Ram Enable 10\r\n"); + RAM_DEBUG_MESSAGE("Ram Enable 10\n"); RAM_RESET_DDR_PTR(); EXTRA_DELAY /* 11 normal operation */ - RAM_DEBUG_MESSAGE("Ram Enable 11\r\n"); + RAM_DEBUG_MESSAGE("Ram Enable 11\n"); do_ram_command(RAM_COMMAND_NORMAL, 0); EXTRA_DELAY @@ -1897,7 +1897,7 @@ dram_controller_mode |= (1<<17); // NOTE: undocumented reserved bit pci_write_config32(PCI_DEV(0, 0, 0), DRC, dram_controller_mode); - RAM_DEBUG_MESSAGE("Northbridge following SDRAM init:\r\n"); + RAM_DEBUG_MESSAGE("Northbridge following SDRAM init:\n"); DUMPNORTH(); // verify_ram(); @@ -1917,19 +1917,19 @@ { uint8_t dimm_mask; - RAM_DEBUG_MESSAGE("Reading SPD data...\r\n"); + RAM_DEBUG_MESSAGE("Reading SPD data...\n"); //activate_spd_rom(ctrl); Not necessary for this chipset dimm_mask = spd_get_supported_dimms(ctrl); if (dimm_mask == 0) { - print_debug("No usable memory for this controller\r\n"); + print_debug("No usable memory for this controller\n"); } else { enable_e7501_clocks(dimm_mask); - RAM_DEBUG_MESSAGE("setting based on SPD data...\r\n"); + RAM_DEBUG_MESSAGE("setting based on SPD data...\n"); configure_e7501_row_attributes(ctrl, dimm_mask); configure_e7501_dram_controller_mode(ctrl, dimm_mask); @@ -1938,7 +1938,7 @@ configure_e7501_dram_timing(ctrl, dimm_mask); DO_DELAY - RAM_DEBUG_MESSAGE("done\r\n"); + RAM_DEBUG_MESSAGE("done\n"); } // NOTE: configure_e7501_ram_addresses() is NOT called here. @@ -1963,7 +1963,7 @@ // static void sdram_set_registers(const struct mem_controller *ctrl) { - RAM_DEBUG_MESSAGE("Northbridge prior to SDRAM init:\r\n"); + RAM_DEBUG_MESSAGE("Northbridge prior to SDRAM init:\n"); DUMPNORTH(); ram_set_rcomp_regs(); Modified: trunk/src/northbridge/intel/e7520/memory_initialized.c ============================================================================== --- trunk/src/northbridge/intel/e7520/memory_initialized.c Wed Mar 31 16:34:40 2010 (r5341) +++ trunk/src/northbridge/intel/e7520/memory_initialized.c Wed Mar 31 16:47:43 2010 (r5342) @@ -7,7 +7,7 @@ drc = pci_read_config32(NB_DEV, DRC); //print_debug("memory_initialized: DRC: "); //print_debug_hex32(drc); - //print_debug("\r\n"); + //print_debug("\n"); return (drc & (1<<29)); } Modified: trunk/src/northbridge/intel/e7520/raminit.c ============================================================================== --- trunk/src/northbridge/intel/e7520/raminit.c Wed Mar 31 16:34:40 2010 (r5341) +++ trunk/src/northbridge/intel/e7520/raminit.c Wed Mar 31 16:47:43 2010 (r5342) @@ -74,7 +74,7 @@ reg |= register_values[i+2]; pci_write_config32(dev, where, reg); } - print_spew("done.\r\n"); + print_spew("done.\n"); } @@ -155,7 +155,7 @@ goto out; val_err: - die("Bad SPD value\r\n"); + die("Bad SPD value\n"); /* If an hw_error occurs report that I have no memory */ hw_err: sz.side1 = 0; @@ -283,7 +283,7 @@ goto out; val_err: - die("Bad SPD value\r\n"); + die("Bad SPD value\n"); /* If an hw_error occurs report that I have no memory */ hw_err: dra = 0; @@ -538,7 +538,7 @@ } else { - die("Invalid SPD 9 bus speed.\r\n"); + die("Invalid SPD 9 bus speed.\n"); } /* 0x78 DRT */ @@ -576,7 +576,7 @@ ecc = 2; } else if (ecc == 1) { - die("ERROR - Mixed DDR & DDR2 RAM\r\n"); + die("ERROR - Mixed DDR & DDR2 RAM\n"); } } else if ( reg == 7 ) { @@ -584,15 +584,15 @@ ecc = 1; } else if ( ecc > 1 ) { - die("ERROR - Mixed DDR & DDR2 RAM\r\n"); + die("ERROR - Mixed DDR & DDR2 RAM\n"); } } else { - die("ERROR - RAM not DDR\r\n"); + die("ERROR - RAM not DDR\n"); } } else { - die("ERROR - Non ECC memory dimm\r\n"); + die("ERROR - Non ECC memory dimm\n"); } value = spd_read_byte(ctrl->channel0[cnt], 12); /*refresh rate*/ @@ -621,10 +621,10 @@ ecc = 2; if (read_option(CMOS_VSTART_ECC_memory,CMOS_VLEN_ECC_memory,1) == 0) { ecc = 0; /* ECC off in CMOS so disable it */ - print_debug("ECC off\r\n"); + print_debug("ECC off\n"); } else { - print_debug("ECC on\r\n"); + print_debug("ECC on\n"); } drc &= ~(3 << 20); /* clear the ecc bits */ drc |= (ecc << 20); /* or in the calculated ecc bits */ @@ -654,7 +654,7 @@ goto out; val_err: - die("Bad SPD value\r\n"); + die("Bad SPD value\n"); /* If an hw_error occurs report that I have no memory */ hw_err: drc = 0; @@ -669,7 +669,7 @@ /* Test if we can read the spd and if ram is ddr or ddr2 */ dimm_mask = spd_detect_dimms(ctrl); if (!(dimm_mask & ((1 << DIMM_SOCKETS) - 1))) { - print_err("No memory for this cpu\r\n"); + print_err("No memory for this cpu\n"); return; } return; @@ -771,12 +771,12 @@ data32 = 0x777becdc; /* ESSD */ break; } - die("Error - First dimm slot empty\r\n"); + die("Error - First dimm slot empty\n"); } print_debug("ODT Value = "); print_debug_hex32(data32); - print_debug("\r\n"); + print_debug("\n"); pci_write_config32(PCI_DEV(0, 0x00, 0), 0xb0, data32); @@ -1009,7 +1009,7 @@ print_debug_hex32(recena); print_debug(", Receive enable B = "); print_debug_hex32(recenb); - print_debug("\r\n"); + print_debug("\n"); /* clear out the calibration area */ write32(BAR+DCALDATA+(16*4), 0x00000000); @@ -1075,7 +1075,7 @@ 0xffffffff, 0xffffffff, 0x000000ff}; mask = spd_detect_dimms(ctrl); - print_debug("Starting SDRAM Enable\r\n"); + print_debug("Starting SDRAM Enable\n"); /* 0x80 */ #ifdef DIMM_MAP_LOGICAL @@ -1087,7 +1087,7 @@ /* set dram type and Front Side Bus freq. */ drc = spd_set_dram_controller_mode(ctrl, mask); if( drc == 0) { - die("Error calculating DRC\r\n"); + die("Error calculating DRC\n"); } pll_setup(drc); data32 = drc & ~(3 << 20); /* clear ECC mode */ @@ -1124,7 +1124,7 @@ for(i=0;i<8;i++) { /* loop throught each dimm to test for row */ print_debug("DIMM "); print_debug_hex8(i); - print_debug("\r\n"); + print_debug("\n"); /* Apply NOP */ do_delay(); @@ -1307,7 +1307,7 @@ write32(BAR+DCALCSR, 0x0008000f); /* clear memory and init ECC */ - print_debug("Clearing memory\r\n"); + print_debug("Clearing memory\n"); for(i=0;i<64;i+=4) { write32(BAR+DCALDATA+i, 0x00000000); } @@ -1324,13 +1324,13 @@ data32 |= (1 << 31); pci_write_config32(PCI_DEV(0, 0x00, 0), 0x98, data32); /* wait for completion */ - print_debug("Waiting for mem complete\r\n"); + print_debug("Waiting for mem complete\n"); while(1) { data32 = pci_read_config32(PCI_DEV(0, 0x00, 0), 0x98); if( (data32 & (1<<31)) == 0) break; } - print_debug("Done\r\n"); + print_debug("Done\n"); /* Set initialization complete */ /* 0x7c DRC */ Modified: trunk/src/northbridge/intel/e7525/raminit.c ============================================================================== --- trunk/src/northbridge/intel/e7525/raminit.c Wed Mar 31 16:34:40 2010 (r5341) +++ trunk/src/northbridge/intel/e7525/raminit.c Wed Mar 31 16:47:43 2010 (r5342) @@ -74,7 +74,7 @@ reg |= register_values[i+2]; pci_write_config32(dev, where, reg); } - print_spew("done.\r\n"); + print_spew("done.\n"); } @@ -155,7 +155,7 @@ goto out; val_err: - die("Bad SPD value\r\n"); + die("Bad SPD value\n"); /* If an hw_error occurs report that I have no memory */ hw_err: sz.side1 = 0; @@ -283,7 +283,7 @@ goto out; val_err: - die("Bad SPD value\r\n"); + die("Bad SPD value\n"); /* If an hw_error occurs report that I have no memory */ hw_err: dra = 0; @@ -538,7 +538,7 @@ } else { - die("Invalid SPD 9 bus speed.\r\n"); + die("Invalid SPD 9 bus speed.\n"); } /* 0x78 DRT */ @@ -576,7 +576,7 @@ ecc = 2; } else if (ecc == 1) { - die("ERROR - Mixed DDR & DDR2 RAM\r\n"); + die("ERROR - Mixed DDR & DDR2 RAM\n"); } } else if ( reg == 7 ) { @@ -584,15 +584,15 @@ ecc = 1; } else if ( ecc > 1 ) { - die("ERROR - Mixed DDR & DDR2 RAM\r\n"); + die("ERROR - Mixed DDR & DDR2 RAM\n"); } } else { - die("ERROR - RAM not DDR\r\n"); + die("ERROR - RAM not DDR\n"); } } else { - die("ERROR - Non ECC memory dimm\r\n"); + die("ERROR - Non ECC memory dimm\n"); } value = spd_read_byte(ctrl->channel0[cnt], 12); /*refresh rate*/ @@ -621,10 +621,10 @@ ecc = 2; if (read_option(CMOS_VSTART_ECC_memory,CMOS_VLEN_ECC_memory,1) == 0) { ecc = 0; /* ECC off in CMOS so disable it */ - print_debug("ECC off\r\n"); + print_debug("ECC off\n"); } else { - print_debug("ECC on\r\n"); + print_debug("ECC on\n"); } drc &= ~(3 << 20); /* clear the ecc bits */ drc |= (ecc << 20); /* or in the calculated ecc bits */ @@ -654,7 +654,7 @@ goto out; val_err: - die("Bad SPD value\r\n"); + die("Bad SPD value\n"); /* If an hw_error occurs report that I have no memory */ hw_err: drc = 0; @@ -669,7 +669,7 @@ /* Test if we can read the spd and if ram is ddr or ddr2 */ dimm_mask = spd_detect_dimms(ctrl); if (!(dimm_mask & ((1 << DIMM_SOCKETS) - 1))) { - print_err("No memory for this cpu\r\n"); + print_err("No memory for this cpu\n"); return; } return; @@ -742,12 +742,12 @@ data32 = 0x777becdc; /* ESSD */ break; } - die("Error - First dimm slot empty\r\n"); + die("Error - First dimm slot empty\n"); } print_debug("ODT Value = "); print_debug_hex32(data32); - print_debug("\r\n"); + print_debug("\n"); pci_write_config32(ctrl->f0, 0xb0, data32); @@ -980,7 +980,7 @@ print_debug_hex32(recena); print_debug(", Receive enable B = "); print_debug_hex32(recenb); - print_debug("\r\n"); + print_debug("\n"); /* clear out the calibration area */ write32(BAR+DCALDATA+(16*4), 0x00000000); @@ -1046,7 +1046,7 @@ 0xffffffff, 0xffffffff, 0x000000ff}; mask = spd_detect_dimms(ctrl); - print_debug("Starting SDRAM Enable\r\n"); + print_debug("Starting SDRAM Enable\n"); /* 0x80 */ #ifdef DIMM_MAP_LOGICAL @@ -1058,7 +1058,7 @@ /* set dram type and Front Side Bus freq. */ drc = spd_set_dram_controller_mode(ctrl, mask); if( drc == 0) { - die("Error calculating DRC\r\n"); + die("Error calculating DRC\n"); } data32 = drc & ~(3 << 20); /* clear ECC mode */ data32 = data32 & ~(7 << 8); /* clear refresh rates */ @@ -1094,7 +1094,7 @@ for(i=0;i<8;i++) { /* loop throught each dimm to test for row */ print_debug("DIMM "); print_debug_hex8(i); - print_debug("\r\n"); + print_debug("\n"); /* Apply NOP */ do_delay(); @@ -1274,7 +1274,7 @@ write32(BAR+DCALCSR, 0x0008000f); /* clear memory and init ECC */ - print_debug("Clearing memory\r\n"); + print_debug("Clearing memory\n"); for(i=0;i<64;i+=4) { write32(BAR+DCALDATA+i, 0x00000000); } @@ -1291,13 +1291,13 @@ data32 |= (1 << 31); pci_write_config32(ctrl->f0, 0x98, data32); /* wait for completion */ - print_debug("Waiting for mem complete\r\n"); + print_debug("Waiting for mem complete\n"); while(1) { data32 = pci_read_config32(ctrl->f0, 0x98); if( (data32 & (1<<31)) == 0) break; } - print_debug("Done\r\n"); + print_debug("Done\n"); /* Set initialization complete */ /* 0x7c DRC */ Modified: trunk/src/northbridge/intel/i3100/raminit.c ============================================================================== --- trunk/src/northbridge/intel/i3100/raminit.c Wed Mar 31 16:34:40 2010 (r5341) +++ trunk/src/northbridge/intel/i3100/raminit.c Wed Mar 31 16:47:43 2010 (r5342) @@ -76,7 +76,7 @@ reg |= register_values[i+2]; pci_write_config32(dev, where, reg); } - print_spew("done.\r\n"); + print_spew("done.\n"); } struct dimm_size { @@ -149,7 +149,7 @@ goto out; val_err: - die("Bad SPD value\r\n"); + die("Bad SPD value\n"); /* If an hw_error occurs report that I have no memory */ hw_err: sz.side1 = 0; @@ -277,7 +277,7 @@ goto out; val_err: - die("Bad SPD value\r\n"); + die("Bad SPD value\n"); /* If an hw_error occurs report that I have no memory */ hw_err: dra = 0; @@ -528,7 +528,7 @@ } else { - die("Invalid SPD 9 bus speed.\r\n"); + die("Invalid SPD 9 bus speed.\n"); } /* 0x78 DRT */ @@ -556,7 +556,7 @@ continue; } value = spd_read_byte(ctrl->channel0[cnt], 11); /* ECC */ - if (value != 2) die("ERROR - Non ECC memory dimm\r\n"); + if (value != 2) die("ERROR - Non ECC memory dimm\n"); value = spd_read_byte(ctrl->channel0[cnt], 12); /*refresh rate*/ value &= 0x0f; /* clip self refresh bit */ @@ -595,7 +595,7 @@ goto out; val_err: - die("Bad SPD value\r\n"); + die("Bad SPD value\n"); /* If an hw_error occurs report that I have no memory */ hw_err: drc = 0; @@ -610,7 +610,7 @@ /* Test if we can read the spd and if ram is ddr or ddr2 */ dimm_mask = spd_detect_dimms(ctrl); if (!(dimm_mask & ((1 << DIMM_SOCKETS) - 1))) { - print_err("No memory for this cpu\r\n"); + print_err("No memory for this cpu\n"); return; } return; @@ -683,12 +683,12 @@ data32 = 0x777becdc; /* ESSD */ break; } - die("Error - First dimm slot empty\r\n"); + die("Error - First dimm slot empty\n"); } print_debug("ODT Value = "); print_debug_hex32(data32); - print_debug("\r\n"); + print_debug("\n"); pci_write_config32(ctrl->f0, DDR2ODTC, data32); @@ -921,7 +921,7 @@ print_debug_hex32(recena); print_debug(", Receive enable B = "); print_debug_hex32(recenb); - print_debug("\r\n"); + print_debug("\n"); /* clear out the calibration area */ write32(MCBAR+DCALDATA+(16*4), 0x00000000); @@ -977,7 +977,7 @@ 0xffffffff, 0xffffffff, 0x000000ff}; mask = spd_detect_dimms(ctrl); - print_debug("Starting SDRAM Enable\r\n"); + print_debug("Starting SDRAM Enable\n"); /* 0x80 */ #ifdef DIMM_MAP_LOGICAL @@ -989,7 +989,7 @@ /* set dram type and Front Side Bus freq. */ drc = spd_set_dram_controller_mode(ctrl, mask); if( drc == 0) { - die("Error calculating DRC\r\n"); + die("Error calculating DRC\n"); } data32 = drc & ~(3 << 20); /* clear ECC mode */ data32 = data32 & ~(7 << 8); /* clear refresh rates */ @@ -1024,7 +1024,7 @@ for(i=0;i<8;i+=2) { /* loop through each dimm to test */ print_debug("DIMM "); print_debug_hex8(i); - print_debug("\r\n"); + print_debug("\n"); /* Apply NOP */ do_delay(); @@ -1177,7 +1177,7 @@ write32(MCBAR+DCALCSR, 0x0008000f); /* clear memory and init ECC */ - print_debug("Clearing memory\r\n"); + print_debug("Clearing memory\n"); for(i=0;i<64;i+=4) { write32(MCBAR+DCALDATA+i, 0x00000000); } @@ -1194,13 +1194,13 @@ data32 |= (1 << 31); pci_write_config32(ctrl->f0, 0x98, data32); /* wait for completion */ - print_debug("Waiting for mem complete\r\n"); + print_debug("Waiting for mem complete\n"); while(1) { data32 = pci_read_config32(ctrl->f0, 0x98); if( (data32 & (1<<31)) == 0) break; } - print_debug("Done\r\n"); + print_debug("Done\n"); /* Set initialization complete */ /* 0x7c DRC */ Modified: trunk/src/northbridge/intel/i3100/raminit_ep80579.c ============================================================================== --- trunk/src/northbridge/intel/i3100/raminit_ep80579.c Wed Mar 31 16:34:40 2010 (r5341) +++ trunk/src/northbridge/intel/i3100/raminit_ep80579.c Wed Mar 31 16:47:43 2010 (r5342) @@ -122,7 +122,7 @@ goto out; val_err: - die("Bad SPD value\r\n"); + die("Bad SPD value\n"); /* If an hw_error occurs report that I have no memory */ hw_err: sz.side1 = 0; @@ -134,7 +134,7 @@ print_debug_hex8(sz.side1); print_debug("."); print_debug_hex8(sz.side2); - print_debug("\r\n"); + print_debug("\n"); return sz; } @@ -167,14 +167,14 @@ } print_debug("DRB = "); print_debug_hex32(pci_read_config32(ctrl->f0, DRB)); - print_debug("\r\n"); + print_debug("\n"); cum >>= 1; /* set TOM top of memory */ pci_write_config16(ctrl->f0, TOM, cum); print_debug("TOM = "); print_debug_hex16(cum); - print_debug("\r\n"); + print_debug("\n"); /* set TOLM top of low memory */ if (cum > 0x18) { cum = 0x18; @@ -183,7 +183,7 @@ pci_write_config16(ctrl->f0, TOLM, cum); print_debug("TOLM = "); print_debug_hex16(cum); - print_debug("\r\n"); + print_debug("\n"); return 0; } @@ -202,7 +202,7 @@ print_debug_hex8(device); print_debug(" = "); print_debug_hex8(byte); - print_debug("\r\n"); + print_debug("\n"); if (byte == 8) { dimm_mask |= (1 << i); } @@ -227,29 +227,29 @@ } value = spd_read_byte(ctrl->channel0[i], SPD_NUM_ROWS); - if (value < 0) die("Bad SPD data\r\n"); - if ((value & 0xf) == 0) die("Invalid # of rows\r\n"); + if (value < 0) die("Bad SPD data\n"); + if ((value & 0xf) == 0) die("Invalid # of rows\n"); dra |= (((value-13) & 0x7) << 23); dra |= (((value-13) & 0x7) << 29); reg += value & 0xf; value = spd_read_byte(ctrl->channel0[i], SPD_NUM_COLUMNS); - if (value < 0) die("Bad SPD data\r\n"); - if ((value & 0xf) == 0) die("Invalid # of columns\r\n"); + if (value < 0) die("Bad SPD data\n"); + if ((value & 0xf) == 0) die("Invalid # of columns\n"); dra |= (((value-10) & 0x7) << 20); dra |= (((value-10) & 0x7) << 26); reg += value & 0xf; value = spd_read_byte(ctrl->channel0[i], SPD_NUM_BANKS_PER_SDRAM); - if (value < 0) die("Bad SPD data\r\n"); - if ((value & 0xff) == 0) die("Invalid # of banks\r\n"); + if (value < 0) die("Bad SPD data\n"); + if ((value & 0xff) == 0) die("Invalid # of banks\n"); reg += log2(value & 0xff); print_debug("dimm "); print_debug_hex8(i); print_debug(" reg = "); print_debug_hex8(reg); - print_debug("\r\n"); + print_debug("\n"); /* set device density */ dra |= ((31-reg)); @@ -270,7 +270,7 @@ print_debug_hex8(i); print_debug(" = "); print_debug_hex32(dra); - print_debug("\r\n"); + print_debug("\n"); pci_write_config32(ctrl->f0, DRA + (i*4), dra); } @@ -320,10 +320,10 @@ else if (val & 0x40) cl = 6; else - die("CAS latency mismatch\r\n"); + die("CAS latency mismatch\n"); print_debug("cl = "); print_debug_hex8(cl); - print_debug("\r\n"); + print_debug("\n"); ci = cycle[index]; @@ -349,10 +349,10 @@ } print_debug("trc = "); print_debug_hex8(trc); - print_debug("\r\n"); + print_debug("\n"); print_debug("trfc = "); print_debug_hex8(trfc); - print_debug("\r\n"); + print_debug("\n"); /* Tras, Trtp, Twtr in cycles */ for (i = 0; i < DIMM_SOCKETS; i++) { @@ -374,38 +374,38 @@ } print_debug("tras = "); print_debug_hex8(tras); - print_debug("\r\n"); + print_debug("\n"); print_debug("trtp = "); print_debug_hex8(trtp); - print_debug("\r\n"); + print_debug("\n"); print_debug("twtr = "); print_debug_hex8(twtr); - print_debug("\r\n"); + print_debug("\n"); val = (drt0[index] | ((trc - 11) << 12) | ((cl - 3) << 9) | ((cl - 3) << 6) | ((cl - 3) << 3)); print_debug("drt0 = "); print_debug_hex32(val); - print_debug("\r\n"); + print_debug("\n"); pci_write_config32(ctrl->f0, DRT0, val); val = (drt1[index] | ((tras - 8) << 28) | ((trtp - 2) << 25) | (twtr << 15)); print_debug("drt1 = "); print_debug_hex32(val); - print_debug("\r\n"); + print_debug("\n"); pci_write_config32(ctrl->f0, DRT1, val); val = (magic[index]); print_debug("magic = "); print_debug_hex32(val); - print_debug("\r\n"); + print_debug("\n"); pci_write_config32(PCI_DEV(0, 0x08, 0), 0xcc, val); val = (mrs[index] | (cl << 20)); print_debug("mrs = "); print_debug_hex32(val); - print_debug("\r\n"); + print_debug("\n"); return val; } @@ -422,11 +422,11 @@ if (!(dimm_mask & (1 << i))) continue; if ((spd_read_byte(ctrl->channel0[i], SPD_MODULE_DATA_WIDTH_LSB) & 0xf0) != 0x40) - die("ERROR: Only 64-bit DIMMs supported\r\n"); + die("ERROR: Only 64-bit DIMMs supported\n"); if (!(spd_read_byte(ctrl->channel0[i], SPD_DIMM_CONFIG_TYPE) & 0x02)) - die("ERROR: Only ECC DIMMs supported\r\n"); + die("ERROR: Only ECC DIMMs supported\n"); if (spd_read_byte(ctrl->channel0[i], SPD_PRIMARY_SDRAM_WIDTH) != 0x08) - die("ERROR: Only x8 DIMMs supported\r\n"); + die("ERROR: Only x8 DIMMs supported\n"); value = spd_read_byte(ctrl->channel0[i], SPD_MIN_CYCLE_TIME_AT_CAS_MAX); if (value > cycle) @@ -434,7 +434,7 @@ } print_debug("cycle = "); print_debug_hex8(cycle); - print_debug("\r\n"); + print_debug("\n"); drc |= (1 << 20); /* enable ECC */ drc |= (3 << 30); /* enable CKE on each DIMM */ @@ -446,42 +446,42 @@ print_debug("msr 0xcd = "); print_debug_hex32(msr.hi); print_debug_hex32(msr.lo); - print_debug("\r\n"); + print_debug("\n"); /* TODO check that this msr really indicates fsb speed! */ if (msr.lo & 0x07) { - print_info("533 MHz FSB\r\n"); + print_info("533 MHz FSB\n"); if (cycle <= 0x25) { drc |= 0x5; - print_info("400 MHz DDR\r\n"); + print_info("400 MHz DDR\n"); } else if (cycle <= 0x30) { drc |= 0x7; - print_info("333 MHz DDR\r\n"); + print_info("333 MHz DDR\n"); } else if (cycle <= 0x3d) { drc |= 0x4; - print_info("266 MHz DDR\r\n"); + print_info("266 MHz DDR\n"); } else { drc |= 0x2; - print_info("200 MHz DDR\r\n"); + print_info("200 MHz DDR\n"); } } else { - print_info("400 MHz FSB\r\n"); + print_info("400 MHz FSB\n"); if (cycle <= 0x30) { drc |= 0x7; - print_info("333 MHz DDR\r\n"); + print_info("333 MHz DDR\n"); } else if (cycle <= 0x3d) { drc |= 0x0; - print_info("266 MHz DDR\r\n"); + print_info("266 MHz DDR\n"); } else { drc |= 0x2; - print_info("200 MHz DDR\r\n"); + print_info("200 MHz DDR\n"); } } print_debug("DRC = "); print_debug_hex32(drc); - print_debug("\r\n"); + print_debug("\n"); return drc; } @@ -494,7 +494,7 @@ /* Test if we can read the SPD */ dimm_mask = spd_detect_dimms(ctrl); if (!(dimm_mask & ((1 << DIMM_SOCKETS) - 1))) { - print_err("No memory for this cpu\r\n"); + print_err("No memory for this cpu\n"); return; } return; @@ -524,14 +524,14 @@ print_debug("ODT Value = "); print_debug_hex32(data32); - print_debug("\r\n"); + print_debug("\n"); pci_write_config32(ctrl->f0, DDR2ODTC, data32); for (i = 0; i < 2; i++) { print_debug("ODT CS"); print_debug_hex8(i); - print_debug("\r\n"); + print_debug("\n"); write32(BAR+DCALADDR, 0x0b840001); write32(BAR+DCALCSR, 0x80000003 | ((i+1)<<21)); @@ -547,14 +547,14 @@ int i; for (i = 0x0; i < 0x2a0; i += 4) { if ((i % 16) == 0) { - print_debug("\r\n"); + print_debug("\n"); print_debug_hex16(i); print_debug(": "); } print_debug_hex32(read32(BAR+i)); print_debug(" "); } - print_debug("\r\n"); + print_debug("\n"); } @@ -570,12 +570,12 @@ u16 data16; mask = spd_detect_dimms(ctrl); - print_debug("Starting SDRAM Enable\r\n"); + print_debug("Starting SDRAM Enable\n"); /* Set DRAM type and Front Side Bus frequency */ drc = spd_set_dram_controller_mode(ctrl, mask); if (drc == 0) { - die("Error calculating DRC\r\n"); + die("Error calculating DRC\n"); } data32 = drc & ~(3 << 20); /* clear ECC mode */ data32 = data32 | (3 << 5); /* temp turn off ODT */ @@ -600,7 +600,7 @@ for (cs = 0; cs < 2; cs++) { print_debug("NOP CS"); print_debug_hex8(cs); - print_debug("\r\n"); + print_debug("\n"); udelay(16); write32(BAR+DCALCSR, (0x00000000 | ((cs+1)<<21))); write32(BAR+DCALCSR, (0x80000000 | ((cs+1)<<21))); @@ -614,7 +614,7 @@ for (cs = 0; cs < 2; cs++) { print_debug("NOP CS"); print_debug_hex8(cs); - print_debug("\r\n"); + print_debug("\n"); write32(BAR + DCALCSR, (0x80000000 | ((cs+1)<<21))); data32 = read32(BAR+DCALCSR); while (data32 & 0x80000000) @@ -626,7 +626,7 @@ for (cs = 0; cs < 2; cs++) { print_debug("Precharge CS"); print_debug_hex8(cs); - print_debug("\r\n"); + print_debug("\n"); write32(BAR+DCALADDR, 0x04000000); write32(BAR+DCALCSR, (0x80000002 | ((cs+1)<<21))); data32 = read32(BAR+DCALCSR); @@ -639,7 +639,7 @@ for (cs = 0; cs < 2; cs++) { print_debug("EMRS CS"); print_debug_hex8(cs); - print_debug("\r\n"); + print_debug("\n"); write32(BAR+DCALADDR, 0x0b840001); write32(BAR+DCALCSR, (0x80000003 | ((cs+1)<<21))); data32 = read32(BAR+DCALCSR); @@ -651,7 +651,7 @@ for (cs = 0; cs < 2; cs++) { print_debug("MRS CS"); print_debug_hex8(cs); - print_debug("\r\n"); + print_debug("\n"); write32(BAR+DCALADDR, mode_reg); write32(BAR+DCALCSR, (0x80000003 | ((cs+1)<<21))); data32 = read32(BAR+DCALCSR); @@ -664,7 +664,7 @@ for (cs = 0; cs < 2; cs++) { print_debug("Precharge CS"); print_debug_hex8(cs); - print_debug("\r\n"); + print_debug("\n"); write32(BAR+DCALADDR, 0x04000000); write32(BAR+DCALCSR, (0x80000002 | ((cs+1)<<21))); data32 = read32(BAR+DCALCSR); @@ -678,7 +678,7 @@ for (cs = 0; cs < 2; cs++) { print_debug("Refresh CS"); print_debug_hex8(cs); - print_debug("\r\n"); + print_debug("\n"); write32(BAR+DCALCSR, (0x80000001 | ((cs+1)<<21))); data32 = read32(BAR+DCALCSR); while (data32 & 0x80000000) @@ -691,7 +691,7 @@ for (cs = 0; cs < 2; cs++) { print_debug("MRS CS"); print_debug_hex8(cs); - print_debug("\r\n"); + print_debug("\n"); write32(BAR+DCALADDR, (mode_reg & ~(1<<24))); write32(BAR+DCALCSR, (0x80000003 | ((cs+1)<<21))); data32 = read32(BAR+DCALCSR); @@ -704,7 +704,7 @@ for (cs = 0; cs < 2; cs++) { print_debug("EMRS CS"); print_debug_hex8(cs); - print_debug("\r\n"); + print_debug("\n"); write32(BAR+DCALADDR, 0x0b840001); write32(BAR+DCALCSR, (0x80000003 | ((cs+1)<<21))); data32 = read32(BAR+DCALCSR); @@ -728,7 +728,7 @@ for (cs = 0; cs < 1; cs++) { print_debug("receive enable calibration CS"); print_debug_hex8(cs); - print_debug("\r\n"); + print_debug("\n"); write32(BAR+DCALCSR, (0x8000000c | ((cs+1)<<21))); data32 = read32(BAR+DCALCSR); while (data32 & 0x80000000) @@ -755,17 +755,17 @@ continue; print_debug("clear memory CS"); print_debug_hex8(cs); - print_debug("\r\n"); + print_debug("\n"); write32(BAR+MBCSR, 0xa00000f0 | ((cs+1)<<20) | (0<<16)); data32 = read32(BAR+MBCSR); while (data32 & 0x80000000) data32 = read32(BAR+MBCSR); if (data32 & 0x40000000) - print_debug("failed!\r\n"); + print_debug("failed!\n"); } /* Clear read/write FIFO pointers */ - print_debug("clear read/write fifo pointers\r\n"); + print_debug("clear read/write fifo pointers\n"); write32(BAR+DDRIOMC2, read32(BAR+DDRIOMC2) | (1<<15)); udelay(16); write32(BAR+DDRIOMC2, read32(BAR+DDRIOMC2) & ~(1<<15)); @@ -773,7 +773,7 @@ dump_dcal_regs(); - print_debug("Done\r\n"); + print_debug("Done\n"); /* Set initialization complete */ drc |= (1 << 29); Modified: trunk/src/northbridge/intel/i440bx/debug.c ============================================================================== --- trunk/src/northbridge/intel/i440bx/debug.c Wed Mar 31 16:34:40 2010 (r5341) +++ trunk/src/northbridge/intel/i440bx/debug.c Wed Mar 31 16:47:43 2010 (r5342) @@ -2,7 +2,7 @@ static void dump_spd_registers(void) { int i; - print_debug("\r\n"); + print_debug("\n"); for(i = 0; i < DIMM_SOCKETS; i++) { unsigned device; device = DIMM_SPD_BASE + i; @@ -16,20 +16,20 @@ int status; unsigned char byte; if ((j & 0xf) == 0) { - print_debug("\r\n"); + print_debug("\n"); print_debug_hex8(j); print_debug(": "); } status = spd_read_byte(device, j); if (status < 0) { - print_debug("bad device\r\n"); + print_debug("bad device\n"); break; } byte = status & 0xff; print_debug_hex8(byte); print_debug_char(' '); } - print_debug("\r\n"); + print_debug("\n"); } } } Modified: trunk/src/northbridge/intel/i440bx/raminit.c ============================================================================== --- trunk/src/northbridge/intel/i440bx/raminit.c Wed Mar 31 16:34:40 2010 (r5341) +++ trunk/src/northbridge/intel/i440bx/raminit.c Wed Mar 31 16:47:43 2010 (r5342) @@ -420,7 +420,7 @@ PRINT_DEBUG_HEX16(reg16); PRINT_DEBUG(" to 0x"); PRINT_DEBUG_HEX32(addr); - PRINT_DEBUG("\r\n"); + PRINT_DEBUG("\n"); #endif read32(addr); @@ -606,7 +606,7 @@ PRINT_DEBUG_HEX8(reg); PRINT_DEBUG(") for DIMM "); PRINT_DEBUG_HEX8(i); - PRINT_DEBUG("\r\n"); + PRINT_DEBUG("\n"); } pci_write_config8(NB, DRAMC, reg); @@ -621,7 +621,7 @@ int i, max; uint8_t reg; - PRINT_DEBUG("Northbridge prior to SDRAM init:\r\n"); + PRINT_DEBUG("Northbridge prior to SDRAM init:\n"); DUMPNORTH(); max = ARRAY_SIZE(register_values); @@ -637,7 +637,7 @@ PRINT_DEBUG_HEX8(register_values[i]); PRINT_DEBUG(" to 0x"); PRINT_DEBUG_HEX8(reg); - PRINT_DEBUG("\r\n"); + PRINT_DEBUG("\n"); #endif } } @@ -731,11 +731,11 @@ } PRINT_DEBUG("DIMM in slot "); PRINT_DEBUG_HEX8(i); - PRINT_DEBUG("\r\n"); + PRINT_DEBUG("\n"); if (edosd == 0x06) { - print_err("Mixing EDO/SDRAM unsupported!\r\n"); - die("HALT\r\n"); + print_err("Mixing EDO/SDRAM unsupported!\n"); + die("HALT\n"); } /* "DRA" is our RPS for the two rows on this DIMM. */ @@ -816,12 +816,12 @@ if (col == 4) bpr |= 0xc0; } else { - print_err("# of banks of DIMM unsupported!\r\n"); - die("HALT\r\n"); + print_err("# of banks of DIMM unsupported!\n"); + die("HALT\n"); } if (dra == -1) { - print_err("Page size not supported\r\n"); - die("HALT\r\n"); + print_err("Page size not supported\n"); + die("HALT\n"); } /* @@ -831,14 +831,14 @@ */ struct dimm_size sz = spd_get_dimm_size(device); if ((sz.side1 < 8)) { - print_err("DIMMs smaller than 8MB per side\r\n" - "are not supported on this NB.\r\n"); - die("HALT\r\n"); + print_err("DIMMs smaller than 8MB per side\n" + "are not supported on this NB.\n"); + die("HALT\n"); } if ((sz.side1 > 128)) { - print_err("DIMMs > 128MB per side\r\n" - "are not supported on this NB\r\n"); - die("HALT\r\n"); + print_err("DIMMs > 128MB per side\n" + "are not supported on this NB\n"); + die("HALT\n"); } /* Divide size by 8 to set up the DRB registers. */ @@ -855,7 +855,7 @@ #if 0 PRINT_DEBUG("No DIMM found in slot "); PRINT_DEBUG_HEX8(i); - PRINT_DEBUG("\r\n"); + PRINT_DEBUG("\n"); #endif /* If there's no DIMM in the slot, set dra to 0x00. */ @@ -870,7 +870,7 @@ #if 0 PRINT_DEBUG("DRB has been set to 0x"); PRINT_DEBUG_HEX16(drb); - PRINT_DEBUG("\r\n"); + PRINT_DEBUG("\n"); #endif /* Brings the upper DRB back down to be base for @@ -886,19 +886,19 @@ pci_write_config8(NB, PGPOL + 1, bpr); PRINT_DEBUG("PGPOL[BPR] has been set to 0x"); PRINT_DEBUG_HEX8(bpr); - PRINT_DEBUG("\r\n"); + PRINT_DEBUG("\n"); /* Set DRAM row page size register. */ pci_write_config16(NB, RPS, rps); PRINT_DEBUG("RPS has been set to 0x"); PRINT_DEBUG_HEX16(rps); - PRINT_DEBUG("\r\n"); + PRINT_DEBUG("\n"); /* ### ECC */ pci_write_config8(NB, NBXCFG + 3, nbxecc); PRINT_DEBUG("NBXECC[31:24] has been set to 0x"); PRINT_DEBUG_HEX8(nbxecc); - PRINT_DEBUG("\r\n"); + PRINT_DEBUG("\n"); /* Set DRAMC[4:3] to proper memory type (EDO/SDRAM). * TODO: Registered SDRAM support. @@ -917,7 +917,7 @@ pci_write_config8(NB, DRAMC, value); PRINT_DEBUG("DRAMC has been set to 0x"); PRINT_DEBUG_HEX8(value); - PRINT_DEBUG("\r\n"); + PRINT_DEBUG("\n"); } static void sdram_set_spd_registers(void) @@ -947,38 +947,38 @@ udelay(200); /* 1. Apply NOP. Wait 200 clock cycles (200us should do). */ - PRINT_DEBUG("RAM Enable 1: Apply NOP\r\n"); + PRINT_DEBUG("RAM Enable 1: Apply NOP\n"); do_ram_command(RAM_COMMAND_NOP); udelay(200); /* 2. Precharge all. Wait tRP. */ - PRINT_DEBUG("RAM Enable 2: Precharge all\r\n"); + PRINT_DEBUG("RAM Enable 2: Precharge all\n"); do_ram_command(RAM_COMMAND_PRECHARGE); udelay(1); /* 3. Perform 8 refresh cycles. Wait tRC each time. */ - PRINT_DEBUG("RAM Enable 3: CBR\r\n"); + PRINT_DEBUG("RAM Enable 3: CBR\n"); for (i = 0; i < 8; i++) { do_ram_command(RAM_COMMAND_CBR); udelay(1); } /* 4. Mode register set. Wait two memory cycles. */ - PRINT_DEBUG("RAM Enable 4: Mode register set\r\n"); + PRINT_DEBUG("RAM Enable 4: Mode register set\n"); do_ram_command(RAM_COMMAND_MRS); udelay(2); /* 5. Normal operation. */ - PRINT_DEBUG("RAM Enable 5: Normal operation\r\n"); + PRINT_DEBUG("RAM Enable 5: Normal operation\n"); do_ram_command(RAM_COMMAND_NORMAL); udelay(1); /* 6. Finally enable refresh. */ - PRINT_DEBUG("RAM Enable 6: Enable refresh\r\n"); + PRINT_DEBUG("RAM Enable 6: Enable refresh\n"); // pci_write_config8(NB, PMCR, 0x10); spd_enable_refresh(); udelay(1); - PRINT_DEBUG("Northbridge following SDRAM init:\r\n"); + PRINT_DEBUG("Northbridge following SDRAM init:\n"); DUMPNORTH(); } Modified: trunk/src/northbridge/intel/i440lx/raminit.c ============================================================================== --- trunk/src/northbridge/intel/i440lx/raminit.c Wed Mar 31 16:34:40 2010 (r5341) +++ trunk/src/northbridge/intel/i440lx/raminit.c Wed Mar 31 16:47:43 2010 (r5342) @@ -171,7 +171,7 @@ PRINT_DEBUG_HEX16(reg16); PRINT_DEBUG(" to 0x"); PRINT_DEBUG_HEX32(addr); - PRINT_DEBUG("\r\n"); + PRINT_DEBUG("\n"); #endif read32(addr); @@ -201,7 +201,7 @@ PRINT_DEBUG("spd_enable_refresh: dramc = 0x"); PRINT_DEBUG_HEX8(reg); - PRINT_DEBUG("\r\n"); + PRINT_DEBUG("\n"); } /*----------------------------------------------------------------------------- @@ -225,7 +225,7 @@ reg32 = pci_read_config32(NB, APBASE); PRINT_DEBUG("APBASE "); PRINT_DEBUG_HEX32(reg32); - PRINT_DEBUG("\r\n"); + PRINT_DEBUG("\n"); #endif } @@ -244,10 +244,10 @@ #if 0 uint16_t reg16; reg16 = pci_read_config16(NB, PACCFG); - printk(BIOS_DEBUG, "i82443LX Host Freq: 6%C MHz\r\n", (reg16 & 0x4000) ? '0' : '6'); + printk(BIOS_DEBUG, "i82443LX Host Freq: 6%C MHz\n", (reg16 & 0x4000) ? '0' : '6'); #endif - PRINT_DEBUG("Northbridge prior to SDRAM init:\r\n"); + PRINT_DEBUG("Northbridge prior to SDRAM init:\n"); DUMPNORTH(); northbridge_init(); @@ -279,11 +279,11 @@ } else { PRINT_DEBUG(" FAIL "); } - PRINT_DEBUG("\r\n"); + PRINT_DEBUG("\n"); #endif } - PRINT_DEBUG("Northbridge atexit sdram set registers\r\n"); + PRINT_DEBUG("Northbridge atexit sdram set registers\n"); DUMPNORTH(); } @@ -342,7 +342,7 @@ */ PRINT_DEBUG_HEX16(ds); - PRINT_DEBUG("\r\n"); + PRINT_DEBUG("\n"); memsize += ds; @@ -363,7 +363,7 @@ PRINT_DEBUG(" "); PRINT_DEBUG_HEX16(ds); - PRINT_DEBUG("\r\n"); + PRINT_DEBUG("\n"); /* * modify DRT register if current row isn't empty @@ -384,7 +384,7 @@ #if 0 PRINT_DEBUG("Mem: 0x"); PRINT_DEBUG_HEX16(memsize * 8); - PRINT_DEBUG(" MB\r\n"); + PRINT_DEBUG(" MB\n"); if (memsize == 0) { /* maybe we should use some nice die/hlt sequence with printing on console @@ -392,8 +392,8 @@ * maybe such event_handler can be commonly defined routine to decrease * code duplication? */ - PRINT_DEBUG("No memory detected via SPD\r\n"); - PRINT_DEBUG("Reverting to hardcoded 64M single side dimm in first bank\r\n"); + PRINT_DEBUG("No memory detected via SPD\n"); + PRINT_DEBUG("Reverting to hardcoded 64M single side dimm in first bank\n"); } #endif @@ -418,38 +418,38 @@ udelay(200); /* 1. Apply NOP. Wait 200 clock cycles (clock might be 60 or 66 Mhz). */ - PRINT_DEBUG("RAM Enable 1: Apply NOP\r\n"); + PRINT_DEBUG("RAM Enable 1: Apply NOP\n"); do_ram_command(RAM_COMMAND_NOP); udelay(200); /* 2. Precharge all. Wait tRP. */ - PRINT_DEBUG("RAM Enable 2: Precharge all\r\n"); + PRINT_DEBUG("RAM Enable 2: Precharge all\n"); do_ram_command(RAM_COMMAND_PRECHARGE); udelay(1); /* 3. Perform 8 refresh cycles. Wait tRC each time. */ - PRINT_DEBUG("RAM Enable 3: CBR\r\n"); + PRINT_DEBUG("RAM Enable 3: CBR\n"); for (i = 0; i < 8; i++) { do_ram_command(RAM_COMMAND_CBR); udelay(1); } /* 4. Mode register set. Wait two memory cycles. */ - PRINT_DEBUG("RAM Enable 4: Mode register set\r\n"); + PRINT_DEBUG("RAM Enable 4: Mode register set\n"); do_ram_command(RAM_COMMAND_MRS); udelay(2); /* 5. Normal operation. */ - PRINT_DEBUG("RAM Enable 5: Normal operation\r\n"); + PRINT_DEBUG("RAM Enable 5: Normal operation\n"); do_ram_command(RAM_COMMAND_NORMAL); udelay(1); /* 6. Finally enable refresh. */ - PRINT_DEBUG("RAM Enable 6: Enable refresh\r\n"); + PRINT_DEBUG("RAM Enable 6: Enable refresh\n"); pci_write_config8(NB, DRAMC, 0x01); spd_enable_refresh(); udelay(1); - PRINT_DEBUG("Northbridge following SDRAM init:\r\n"); + PRINT_DEBUG("Northbridge following SDRAM init:\n"); } Modified: trunk/src/northbridge/intel/i82810/debug.c ============================================================================== --- trunk/src/northbridge/intel/i82810/debug.c Wed Mar 31 16:34:40 2010 (r5341) +++ trunk/src/northbridge/intel/i82810/debug.c Wed Mar 31 16:47:43 2010 (r5342) @@ -2,7 +2,7 @@ static void dump_spd_registers(void) { int i; - print_debug("\r\n"); + print_debug("\n"); for(i = 0; i < DIMM_SOCKETS; i++) { unsigned device; device = DIMM_SPD_BASE + i; @@ -16,20 +16,20 @@ int status; unsigned char byte; if ((j & 0xf) == 0) { - print_debug("\r\n"); + print_debug("\n"); print_debug_hex8(j); print_debug(": "); } status = smbus_read_byte(device, j); if (status < 0) { - print_debug("bad device\r\n"); + print_debug("bad device\n"); break; } byte = status & 0xff; print_debug_hex8(byte); print_debug_char(' '); } - print_debug("\r\n"); + print_debug("\n"); } } } Modified: trunk/src/northbridge/intel/i82810/raminit.c ============================================================================== --- trunk/src/northbridge/intel/i82810/raminit.c Wed Mar 31 16:34:40 2010 (r5341) +++ trunk/src/northbridge/intel/i82810/raminit.c Wed Mar 31 16:47:43 2010 (r5342) @@ -150,7 +150,7 @@ PRINT_DEBUG_HEX8(reg8); PRINT_DEBUG(" to 0x"); PRINT_DEBUG_HEX32(addr); - PRINT_DEBUG("\r\n"); + PRINT_DEBUG("\n"); #endif read32(addr); @@ -164,7 +164,7 @@ PRINT_DEBUG_HEX8(reg8); PRINT_DEBUG(" to 0x"); PRINT_DEBUG_HEX32(addr); - PRINT_DEBUG("\r\n"); + PRINT_DEBUG("\n"); #endif read32(addr); } @@ -194,14 +194,14 @@ if (smbus_read_byte(DIMM_SPD_BASE + i, 2) == 4) { print_debug("Found DIMM in slot "); print_debug_hex8(i); - print_debug("\r\n"); + print_debug("\n"); dimm_size = smbus_read_byte(DIMM_SPD_BASE + i, 31); /* WISHLIST: would be nice to display it as decimal? */ print_debug("DIMM is 0x"); print_debug_hex8(dimm_size * 4); - print_debug("MB\r\n"); + print_debug("MB\n"); /* The i810 can't handle DIMMs larger than 128MB per * side. This will fail if the DIMM uses a @@ -211,9 +211,9 @@ */ if (dimm_size > 32) { print_err("DIMM row sizes larger than 128MB not" - "supported on i810\r\n"); + "supported on i810\n"); print_err - ("Attempting to treat as 128MB DIMM\r\n"); + ("Attempting to treat as 128MB DIMM\n"); dimm_size = 32; } @@ -225,19 +225,19 @@ print_debug("After translation, dimm_size is 0x"); print_debug_hex8(dimm_size); - print_debug("\r\n"); + print_debug("\n"); /* If the DIMM is dual-sided, the DRP value is +2 */ /* TODO: Figure out asymetrical configurations. */ if ((smbus_read_byte(DIMM_SPD_BASE + i, 127) | 0xf) == 0xff) { - print_debug("DIMM is dual-sided\r\n"); + print_debug("DIMM is dual-sided\n"); dimm_size += 2; } } else { print_debug("No DIMM found in slot "); print_debug_hex8(i); - print_debug("\r\n"); + print_debug("\n"); /* If there's no DIMM in the slot, set value to 0. */ dimm_size = 0x00; @@ -249,7 +249,7 @@ print_debug("DRP calculated to 0x"); print_debug_hex8(drp); - print_debug("\r\n"); + print_debug("\n"); pci_write_config8(PCI_DEV(0, 0, 0), DRP, drp); } @@ -354,7 +354,7 @@ print_debug("BUFF_SC calculated to 0x"); print_debug_hex16(buff_sc); - print_debug("\r\n"); + print_debug("\n"); pci_write_config16(PCI_DEV(0, 0, 0), BUFF_SC, buff_sc); } @@ -411,32 +411,32 @@ int i; /* 1. Apply NOP. */ - PRINT_DEBUG("RAM Enable 1: Apply NOP\r\n"); + PRINT_DEBUG("RAM Enable 1: Apply NOP\n"); do_ram_command(RAM_COMMAND_NOP); udelay(200); /* 2. Precharge all. Wait tRP. */ - PRINT_DEBUG("RAM Enable 2: Precharge all\r\n"); + PRINT_DEBUG("RAM Enable 2: Precharge all\n"); do_ram_command(RAM_COMMAND_PRECHARGE); udelay(1); /* 3. Perform 8 refresh cycles. Wait tRC each time. */ - PRINT_DEBUG("RAM Enable 3: CBR\r\n"); + PRINT_DEBUG("RAM Enable 3: CBR\n"); for (i = 0; i < 8; i++) { do_ram_command(RAM_COMMAND_CBR); udelay(1); } /* 4. Mode register set. Wait two memory cycles. */ - PRINT_DEBUG("RAM Enable 4: Mode register set\r\n"); + PRINT_DEBUG("RAM Enable 4: Mode register set\n"); do_ram_command(RAM_COMMAND_MRS); udelay(2); /* 5. Normal operation (enables refresh at 15.6usec). */ - PRINT_DEBUG("RAM Enable 5: Normal operation\r\n"); + PRINT_DEBUG("RAM Enable 5: Normal operation\n"); do_ram_command(RAM_COMMAND_NORMAL); udelay(1); - PRINT_DEBUG("Northbridge following SDRAM init:\r\n"); + PRINT_DEBUG("Northbridge following SDRAM init:\n"); DUMPNORTH(); } Modified: trunk/src/northbridge/intel/i82830/raminit.c ============================================================================== --- trunk/src/northbridge/intel/i82830/raminit.c Wed Mar 31 16:34:40 2010 (r5341) +++ trunk/src/northbridge/intel/i82830/raminit.c Wed Mar 31 16:47:43 2010 (r5342) @@ -79,7 +79,7 @@ pci_write_config32(NORTHBRIDGE, DRC, reg32); PRINT_DEBUG("RAM command 0x"); PRINT_DEBUG_HEX32(reg32); - PRINT_DEBUG("\r\n"); + PRINT_DEBUG("\n"); } static void ram_read32(u8 dimm_start, u32 offset) @@ -89,24 +89,24 @@ PRINT_DEBUG_HEX32(dimm_start * 32 * 1024 * 1024); PRINT_DEBUG(" => 0x"); PRINT_DEBUG_HEX32(read32(dimm_start * 32 * 1024 * 1024)); - PRINT_DEBUG("\r\n"); + PRINT_DEBUG("\n"); PRINT_DEBUG(" Writing RAM at 0x"); PRINT_DEBUG_HEX32(dimm_start * 32 * 1024 * 1024); PRINT_DEBUG(" <= 0x"); PRINT_DEBUG_HEX32(offset); - PRINT_DEBUG("\r\n"); + PRINT_DEBUG("\n"); write32(dimm_start * 32 * 1024 * 1024, offset); PRINT_DEBUG(" Reading RAM at 0x"); PRINT_DEBUG_HEX32(dimm_start * 32 * 1024 * 1024); PRINT_DEBUG(" => 0x"); PRINT_DEBUG_HEX32(read32(dimm_start * 32 * 1024 * 1024)); - PRINT_DEBUG("\r\n"); + PRINT_DEBUG("\n"); } else { PRINT_DEBUG(" Sending RAM command to 0x"); PRINT_DEBUG_HEX32((dimm_start * 32 * 1024 * 1024) + offset); - PRINT_DEBUG("\r\n"); + PRINT_DEBUG("\n"); read32((dimm_start * 32 * 1024 * 1024) + offset); } } @@ -141,7 +141,7 @@ if (dimm_end > dimm_start) { print_debug("Initializing SDRAM Row "); print_debug_hex8(row); - print_debug("\r\n"); + print_debug("\n"); /* NOP command */ PRINT_DEBUG(" NOP "); @@ -177,7 +177,7 @@ udelay(1); /* Perform a dummy memory read/write cycle */ - PRINT_DEBUG(" Performing dummy read/write\r\n"); + PRINT_DEBUG(" Performing dummy read/write\n"); ram_read32(dimm_start, 0x55aa55aa); udelay(1); } @@ -256,29 +256,29 @@ if (spd_read_byte(device, SPD_MEMORY_TYPE) == 0x4) { print_debug("Found DIMM in slot "); print_debug_hex8(i); - print_debug("\r\n"); + print_debug("\n"); sz = spd_get_dimm_size(device); /* WISHLIST: would be nice to display it as decimal? */ print_debug("DIMM is 0x"); print_debug_hex16(sz.side1); - print_debug(" on side 1\r\n"); + print_debug(" on side 1\n"); print_debug("DIMM is 0x"); print_debug_hex16(sz.side2); - print_debug(" on side 2\r\n"); + print_debug(" on side 2\n"); /* - Memory compatibility checks - */ /* Test for PC133 (i82830 only supports PC133) */ /* PC133 SPD9 - cycle time is always 75 */ if (spd_read_byte(device, SPD_MIN_CYCLE_TIME_AT_CAS_MAX) != 0x75) { - print_err("SPD9 DIMM Is Not PC133 Compatable\r\n"); - die("HALT\r\n"); + print_err("SPD9 DIMM Is Not PC133 Compatable\n"); + die("HALT\n"); } /* PC133 SPD10 - access time is always 54 */ if (spd_read_byte(device, SPD_ACCESS_TIME_FROM_CLOCK) != 0x54) { - print_err("SPD10 DIMM Is Not PC133 Compatable\r\n"); - die("HALT\r\n"); + print_err("SPD10 DIMM Is Not PC133 Compatable\n"); + die("HALT\n"); } /* The i82830 only supports a symmetrical dual-sided dimms @@ -286,23 +286,23 @@ * side or larger than 256MB per side. */ if ((sz.side2 != 0) && (sz.side1 != sz.side2)) { - print_err("This northbridge only supports\r\n"); - print_err("symmetrical dual-sided DIMMs\r\n"); - print_err("booting as a single-sided DIMM\r\n"); + print_err("This northbridge only supports\n"); + print_err("symmetrical dual-sided DIMMs\n"); + print_err("booting as a single-sided DIMM\n"); sz.side2 = 0; } if ((sz.side1 < 32)) { - print_err("DIMMs smaller than 32MB per side\r\n"); - print_err("are not supported on this northbridge\r\n"); - die("HALT\r\n"); + print_err("DIMMs smaller than 32MB per side\n"); + print_err("are not supported on this northbridge\n"); + die("HALT\n"); } if ((sz.side1 > 256)) { print_err - ("DIMMs larger than 256MB per side\r\n"); + ("DIMMs larger than 256MB per side\n"); print_err - ("are not supported on this northbridge\r\n"); - die("HALT\r\n"); + ("are not supported on this northbridge\n"); + die("HALT\n"); } /* - End Memory compatibility checks - */ @@ -316,7 +316,7 @@ } else { PRINT_DEBUG("No DIMM found in slot "); PRINT_DEBUG_HEX8(i); - PRINT_DEBUG("\r\n"); + PRINT_DEBUG("\n"); /* If there's no DIMM in the slot, set value to 0. */ drb1 = 0; @@ -330,12 +330,12 @@ PRINT_DEBUG_HEX8(DRB); PRINT_DEBUG(" has been set to 0x"); PRINT_DEBUG_HEX8(drb1); - PRINT_DEBUG("\r\n"); + PRINT_DEBUG("\n"); PRINT_DEBUG("DRB1 0x"); PRINT_DEBUG_HEX8(DRB + 1); PRINT_DEBUG(" has been set to 0x"); PRINT_DEBUG_HEX8(drb1 + drb2); - PRINT_DEBUG("\r\n"); + PRINT_DEBUG("\n"); } else if (i == 1) { value = pci_read_config8(NORTHBRIDGE, DRB + 1); pci_write_config8(NORTHBRIDGE, DRB + 2, value + drb1); @@ -344,12 +344,12 @@ PRINT_DEBUG_HEX8(DRB + 2); PRINT_DEBUG(" has been set to 0x"); PRINT_DEBUG_HEX8(value + drb1); - PRINT_DEBUG("\r\n"); + PRINT_DEBUG("\n"); PRINT_DEBUG("DRB3 0x"); PRINT_DEBUG_HEX8(DRB + 3); PRINT_DEBUG(" has been set to 0x"); PRINT_DEBUG_HEX8(value + drb1 + drb2); - PRINT_DEBUG("\r\n"); + PRINT_DEBUG("\n"); /* We need to set the highest DRB value to 0x64 and 0x65. * These are supposed to be "Reserved" but memory will @@ -374,7 +374,7 @@ if (spd_read_byte(device, SPD_MEMORY_TYPE) == 0x4) { print_debug("Found DIMM in slot "); print_debug_hex8(i); - print_debug(", setting DRA...\r\n"); + print_debug(", setting DRA...\n"); dra = 0x00; @@ -403,8 +403,8 @@ } else if (dra == 16) { dra = 0xF3; /* 16KB */ } else { - print_err("Page size not supported\r\n"); - die("HALT\r\n"); + print_err("Page size not supported\n"); + die("HALT\n"); } } else if (value == 2) { if (dra == 2) { @@ -416,18 +416,18 @@ } else if (dra == 16) { dra = 0x33; /* 16KB */ } else { - print_err("Page size not supported\r\n"); - die("HALT\r\n"); + print_err("Page size not supported\n"); + die("HALT\n"); } } else { - print_err("# of banks of DIMM not supported\r\n"); - die("HALT\r\n"); + print_err("# of banks of DIMM not supported\n"); + die("HALT\n"); } } else { PRINT_DEBUG("No DIMM found in slot "); PRINT_DEBUG_HEX8(i); - PRINT_DEBUG(", setting DRA to 0xFF\r\n"); + PRINT_DEBUG(", setting DRA to 0xFF\n"); /* If there's no DIMM in the slot, set dra value to 0xFF. */ dra = 0xFF; @@ -439,7 +439,7 @@ PRINT_DEBUG_HEX8(DRA + i); PRINT_DEBUG(" has been set to 0x"); PRINT_DEBUG_HEX8(dra); - PRINT_DEBUG("\r\n"); + PRINT_DEBUG("\n"); } } @@ -468,7 +468,7 @@ static void sdram_set_registers(void) { - PRINT_DEBUG("Setting initial sdram registers....\r\n"); + PRINT_DEBUG("Setting initial sdram registers....\n"); /* Calculate the value for DRT DRAM Timing Register */ set_dram_timing(); @@ -482,7 +482,7 @@ /* Setup DRAM Row Attribute Registers */ set_dram_row_attributes(); - PRINT_DEBUG("Initial sdram registers have been set.\r\n"); + PRINT_DEBUG("Initial sdram registers have been set.\n"); } static void northbridge_set_registers(void) @@ -490,7 +490,7 @@ u16 value; int igd_memory = 0; - PRINT_DEBUG("Setting initial nothbridge registers....\r\n"); + PRINT_DEBUG("Setting initial nothbridge registers....\n"); /* Set the value for Fixed DRAM Hole Control Register */ pci_write_config8(NORTHBRIDGE, FDHC, 0x00); @@ -536,7 +536,7 @@ value |= 1; // 64MB aperture pci_write_config16(NORTHBRIDGE, GCC1, value); - PRINT_DEBUG("Initial northbridge registers have been set.\r\n"); + PRINT_DEBUG("Initial northbridge registers have been set.\n"); } static void sdram_initialize(void) @@ -554,13 +554,13 @@ initialize_dimm_rows(); /* Enable Refresh */ - PRINT_DEBUG("Enabling Refresh\r\n"); + PRINT_DEBUG("Enabling Refresh\n"); reg32 = pci_read_config32(NORTHBRIDGE, DRC); reg32 |= (RAM_COMMAND_REFRESH << 8); pci_write_config32(NORTHBRIDGE, DRC, reg32); /* Set initialization complete */ - PRINT_DEBUG("Setting initialization complete\r\n"); + PRINT_DEBUG("Setting initialization complete\n"); reg32 = pci_read_config32(NORTHBRIDGE, DRC); reg32 |= (RAM_COMMAND_IC << 29); pci_write_config32(NORTHBRIDGE, DRC, reg32); @@ -568,6 +568,6 @@ /* Setup Initial Northbridge Registers */ northbridge_set_registers(); - PRINT_DEBUG("Northbridge following SDRAM init:\r\n"); + PRINT_DEBUG("Northbridge following SDRAM init:\n"); DUMPNORTH(); } Modified: trunk/src/northbridge/intel/i855/debug.c ============================================================================== --- trunk/src/northbridge/intel/i855/debug.c Wed Mar 31 16:34:40 2010 (r5341) +++ trunk/src/northbridge/intel/i855/debug.c Wed Mar 31 16:47:43 2010 (r5342) @@ -60,7 +60,7 @@ continue; } print_debug_pci_dev(dev); - print_debug("\r\n"); + print_debug("\n"); } } @@ -68,7 +68,7 @@ { int i; print_debug_pci_dev(dev); - print_debug("\r\n"); + print_debug("\n"); for(i = 0; i <= 255; i++) { unsigned char val; @@ -80,7 +80,7 @@ print_debug_char(' '); print_debug_hex8(val); if ((i & 0x0f) == 0x0f) { - print_debug("\r\n"); + print_debug("\n"); } } } @@ -105,7 +105,7 @@ static void dump_spd_registers(const struct mem_controller *ctrl) { int i; - print_debug("\r\n"); + print_debug("\n"); for(i = 0; i < 2; i++) { unsigned device; device = ctrl->channel0[i]; @@ -119,20 +119,20 @@ int status; unsigned char byte; if ((j & 0xf) == 0) { - print_debug("\r\n"); + print_debug("\n"); print_debug_hex8(j); print_debug(": "); } status = smbus_read_byte(device, j); if (status < 0) { - print_debug("bad device\r\n"); + print_debug("bad device\n"); break; } byte = status & 0xff; print_debug_hex8(byte); print_debug_char(' '); } - print_debug("\r\n"); + print_debug("\n"); } #if 0 device = ctrl->channel1[i]; @@ -146,20 +146,20 @@ int status; unsigned char byte; if ((j & 0xf) == 0) { - print_debug("\r\n"); + print_debug("\n"); print_debug_hex8(j); print_debug(": "); } status = smbus_read_byte(device, j); if (status < 0) { - print_debug("bad device\r\n"); + print_debug("bad device\n"); break; } byte = status & 0xff; print_debug_hex8(byte); print_debug_char(' '); } - print_debug("\r\n"); + print_debug("\n"); } #endif } @@ -167,7 +167,7 @@ static void dump_smbus_registers(void) { int i; - print_debug("\r\n"); + print_debug("\n"); for(i = 1; i < 0x80; i++) { unsigned device; device = i; @@ -178,20 +178,20 @@ int status; unsigned char byte; if ((j & 0xf) == 0) { - print_debug("\r\n"); + print_debug("\n"); print_debug_hex8(j); print_debug(": "); } status = smbus_read_byte(device, j); if (status < 0) { - print_debug("bad device\r\n"); + print_debug("bad device\n"); break; } byte = status & 0xff; print_debug_hex8(byte); print_debug_char(' '); } - print_debug("\r\n"); + print_debug("\n"); } } #endif Modified: trunk/src/northbridge/intel/i855/raminit.c ============================================================================== --- trunk/src/northbridge/intel/i855/raminit.c Wed Mar 31 16:34:40 2010 (r5341) +++ trunk/src/northbridge/intel/i855/raminit.c Wed Mar 31 16:47:43 2010 (r5342) @@ -31,7 +31,7 @@ static void sdram_set_registers(const struct mem_controller *ctrl) { /* - print_debug("Before configuration:\r\n"); + print_debug("Before configuration:\n"); dump_pci_devices(); */ } @@ -212,7 +212,7 @@ adjusted_mode = ((mode & 0x800) << (13 - 11)) | ((mode & 0x3ff) << (12 - 9)); print_debug("Setting mode: "); print_debug_hex32(adjusted_mode + addr); - print_debug("\r\n"); + print_debug("\n"); read32(adjusted_mode + addr); } @@ -229,39 +229,39 @@ { int i; uint32_t rank1 = (1 << 30) / 2; - print_debug("Ram enable 1\r\n"); + print_debug("Ram enable 1\n"); delay(); delay(); - print_debug("Ram enable 2\r\n"); + print_debug("Ram enable 2\n"); ram_command(ctrl, 1, 0); ram_command(ctrl, 1, rank1); delay(); delay(); - print_debug("Ram enable 3\r\n"); + print_debug("Ram enable 3\n"); ram_command(ctrl, 2, 0); ram_command(ctrl, 2, rank1); delay(); delay(); - print_debug("Ram enable 4\r\n"); + print_debug("Ram enable 4\n"); ram_command_mrs(ctrl, 4, SDRAM_EXTMODE_DLL_ENABLE, 0); ram_command_mrs(ctrl, 4, SDRAM_EXTMODE_DLL_ENABLE, rank1); delay(); delay(); - print_debug("Ram enable 5\r\n"); + print_debug("Ram enable 5\n"); ram_command_mrs(ctrl, 3, VG85X_MODE | SDRAM_MODE_DLL_RESET, 0); ram_command_mrs(ctrl, 3, VG85X_MODE | SDRAM_MODE_DLL_RESET, rank1); - print_debug("Ram enable 6\r\n"); + print_debug("Ram enable 6\n"); ram_command(ctrl, 2, 0); ram_command(ctrl, 2, rank1); delay(); delay(); - print_debug("Ram enable 7\r\n"); + print_debug("Ram enable 7\n"); for(i = 0; i < 8; i++) { ram_command(ctrl, 6, 0); ram_command(ctrl, 6, rank1); @@ -269,28 +269,28 @@ delay(); } - print_debug("Ram enable 8\r\n"); + print_debug("Ram enable 8\n"); ram_command_mrs(ctrl, 3, VG85X_MODE | SDRAM_MODE_NORMAL, 0); ram_command_mrs(ctrl, 3, VG85X_MODE | SDRAM_MODE_NORMAL, rank1); - print_debug("Ram enable 9\r\n"); + print_debug("Ram enable 9\n"); ram_command(ctrl, 7, 0); ram_command(ctrl, 7, rank1); delay(); delay(); - print_debug("Ram enable 9\r\n"); + print_debug("Ram enable 9\n"); set_initialize_complete(ctrl); delay(); delay(); delay(); - print_debug("After configuration:\r\n"); + print_debug("After configuration:\n"); /* dump_pci_devices(); */ /* - print_debug("\n\n***** RAM TEST *****\r\n"); + print_debug("\n\n***** RAM TEST *****\n"); ram_check(0, 0xa0000); ram_check(0x100000, 0x40000000); */ Modified: trunk/src/northbridge/via/cn400/raminit.c ============================================================================== --- trunk/src/northbridge/via/cn400/raminit.c Wed Mar 31 16:34:40 2010 (r5341) +++ trunk/src/northbridge/via/cn400/raminit.c Wed Mar 31 16:47:43 2010 (r5342) @@ -151,7 +151,7 @@ unsigned long bank_address; - print_debug("CN400 RAM init starting\r\n"); + print_debug("CN400 RAM init starting\n"); pci_write_config8(ctrl.d0f7, 0x75, 0x08); @@ -176,7 +176,7 @@ */ c = 0; b = smbus_read_byte(0x50, SPD_NUM_BANKS_PER_SDRAM); - //print_val("Detecting Memory\r\nNumber of Banks ",b); + //print_val("Detecting Memory\nNumber of Banks ",b); // Only supporting 4 bank chips just now if( b == 4 ){ @@ -186,7 +186,7 @@ c = 0x01; bank = 0x40; b = smbus_read_byte(0x50, SPD_NUM_ROWS); - //print_val("\r\nNumber of Rows ", b); + //print_val("\nNumber of Rows ", b); if( b >= 0x0d ){ // 256/512Mb @@ -199,7 +199,7 @@ Read SPD byte 13, Primary DRAM width. */ b = smbus_read_byte(0x50, SPD_PRIMARY_SDRAM_WIDTH); - //print_val("\r\nPrimary DRAM width", b); + //print_val("\nPrimary DRAM width", b); if( b != 4 ) // not 64/128Mb (x4) c = 0x81; // 256Mb } @@ -208,12 +208,12 @@ Read SPD byte 4, Number of column addresses. */ b = smbus_read_byte(0x50, SPD_NUM_COLUMNS); - //print_val("\r\nNo Columns ",b); + //print_val("\nNo Columns ",b); if( b == 10 || b == 11 || b == 12) c |= 0x60; // 10/11 bit col addr if( b == 9 ) c |= 0x40; // 9 bit col addr if( b == 8 ) c |= 0x20; // 8 bit col addr - //print_val("\r\nMA type ", c); + //print_val("\nMA type ", c); pci_write_config8(ctrl.d0f3, 0x50, c); } @@ -223,7 +223,7 @@ /* else { - die("DRAM module size is not supported by CN400\r\n"); + die("DRAM module size is not supported by CN400\n"); } */ @@ -281,7 +281,7 @@ // SPD byte 5 # of physical banks b = smbus_read_byte(0x50, SPD_NUM_DIMM_BANKS); - //print_val("\r\nNo Physical Banks ",b); + //print_val("\nNo Physical Banks ",b); if( b == 2) { c <<=1; @@ -289,7 +289,7 @@ } /* else { - die("Only a single DIMM is supported by EPIA-N(L)\r\n"); + die("Only a single DIMM is supported by EPIA-N(L)\n"); } */ // set banks 1,2,3... @@ -309,7 +309,7 @@ /* Read SPD byte 18 CAS Latency */ b = smbus_read_byte(0x50, SPD_ACCEPTABLE_CAS_LATENCIES); -/* print_debug("\r\nCAS Supported "); +/* print_debug("\nCAS Supported "); if(b & 0x04) print_debug("2 "); if(b & 0x08) @@ -318,11 +318,11 @@ print_debug("3"); c = smbus_read_byte(0x50, SPD_MIN_CYCLE_TIME_AT_CAS_MAX); - print_val("\r\nCycle time at CL X (nS)", c); + print_val("\nCycle time at CL X (nS)", c); c = smbus_read_byte(0x50, SPD_SDRAM_CYCLE_TIME_2ND); - print_val("\r\nCycle time at CL X-0.5 (nS)", c); + print_val("\nCycle time at CL X-0.5 (nS)", c); c = smbus_read_byte(0x50, SPD_SDRAM_CYCLE_TIME_3RD); - print_val("\r\nCycle time at CL X-1 (nS)", c); + print_val("\nCycle time at CL X-1 (nS)", c); */ /* Scaling of Cycle Time SPD data */ /* 7 4 3 0 */ @@ -330,27 +330,27 @@ bank = smbus_read_byte(0x50, SPD_MIN_CYCLE_TIME_AT_CAS_MAX); if( b & 0x10 ){ // DDR offering optional CAS 3 - //print_debug("\r\nStarting at CAS 3"); + //print_debug("\nStarting at CAS 3"); c = 0x30; /* see if we can better it */ if( b & 0x08 ){ // DDR mandatory CAS 2.5 if( smbus_read_byte(0x50, SPD_SDRAM_CYCLE_TIME_2ND) <= bank ){ // we can manage max MHz at CAS 2.5 - //print_debug("\r\nWe can do CAS 2.5"); + //print_debug("\nWe can do CAS 2.5"); c = 0x20; } } if( b & 0x04 ){ // DDR mandatory CAS 2 if( smbus_read_byte(0x50, SPD_SDRAM_CYCLE_TIME_3RD) <= bank ){ // we can manage max Mhz at CAS 2 - //print_debug("\r\nWe can do CAS 2"); + //print_debug("\nWe can do CAS 2"); c = 0x10; } } }else{ // no optional CAS values just 2 & 2.5 - //print_debug("\r\nStarting at CAS 2.5"); + //print_debug("\nStarting at CAS 2.5"); c = 0x20; // assume CAS 2.5 if( b & 0x04){ // Should always happen if( smbus_read_byte(0x50, SPD_SDRAM_CYCLE_TIME_2ND) <= bank){ // we can manage max Mhz at CAS 2 - //print_debug("\r\nWe can do CAS 2"); + //print_debug("\nWe can do CAS 2"); c = 0x10; } } @@ -386,7 +386,7 @@ b = smbus_read_byte(0x50, SPD_MIN_ROW_PRECHARGE_TIME); - //print_val("\r\ntRP ",b); + //print_val("\ntRP ",b); if ( b >= (5 * bank)) { c |= 0x03; // set tRP = 5T } @@ -404,7 +404,7 @@ */ b = smbus_read_byte(0x50, SPD_MIN_RAS_TO_CAS_DELAY); - //print_val("\r\ntRCD ",b); + //print_val("\ntRCD ",b); if ( b >= (5 * bank)) c |= 0x0C; // set tRCD = 5T else if ( b >= (4 * bank)) c |= 0x08; // set tRCD = 4T @@ -421,8 +421,8 @@ bank = bank >> 2; b = smbus_read_byte(0x50, SPD_MIN_ACTIVE_TO_PRECHARGE_DELAY); - //print_val("\r\ntRAS ",b); - //print_val("\r\nBank ", bank); + //print_val("\ntRAS ",b); + //print_val("\nBank ", bank); if ( b >= (9 * bank)) c |= 0xC0; // set tRAS = 9T else if ( b >= (8 * bank)) c |= 0x80; // set tRAS = 8T else if ( b >= (7 * bank)) c |= 0x40; // set tRAS = 7T @@ -537,7 +537,7 @@ c &= 0x08; if ( c == 0x08 ) { - print_debug("Setting Burst Length 8\r\n"); + print_debug("Setting Burst Length 8\n"); /* CPU Frequency Device 0 Function 2 Offset 54 @@ -723,7 +723,7 @@ break; } - print_val("\r\nLow Bond ",i); + print_val("\nLow Bond ",i); if( i < 0xff ){ c = i++; for( ; i <0xff ; i++){ @@ -767,7 +767,7 @@ print_val(" High Bond ",i); c = ((i - c)<<1)/3 + c; print_val(" Setting DQS delay",c); - print_debug("\r\n"); + print_debug("\n"); pci_write_config8(ctrl.d0f3,0x70,c); }else{ pci_write_config8(ctrl.d0f3,0x70,0x67); @@ -822,5 +822,5 @@ /* VGA device. */ pci_write_config16(ctrl.d0f3, 0xa0, (1 << 15)); pci_write_config16(ctrl.d0f3, 0xa4, 0x0010); - print_debug("CN400 raminit.c done\r\n"); + print_debug("CN400 raminit.c done\n"); } Modified: trunk/src/northbridge/via/cn700/raminit.c ============================================================================== --- trunk/src/northbridge/via/cn700/raminit.c Wed Mar 31 16:34:40 2010 (r5341) +++ trunk/src/northbridge/via/cn700/raminit.c Wed Mar 31 16:47:43 2010 (r5342) @@ -183,7 +183,7 @@ } if (result == 0xff) - die("DRAM module size too big, not supported by CN700\r\n"); + die("DRAM module size too big, not supported by CN700\n"); pci_write_config8(ctrl->d0f3, 0x40, result); pci_write_config8(ctrl->d0f3, 0x48, 0x00); @@ -389,30 +389,30 @@ u8 i; /* 1. Apply NOP. */ - PRINT_DEBUG_MEM("RAM Enable 1: Apply NOP\r\n"); + PRINT_DEBUG_MEM("RAM Enable 1: Apply NOP\n"); do_ram_command(dev, RAM_COMMAND_NOP); udelay(100); read32(rank_address + 0x10); /* 2. Precharge all. */ udelay(400); - PRINT_DEBUG_MEM("RAM Enable 2: Precharge all\r\n"); + PRINT_DEBUG_MEM("RAM Enable 2: Precharge all\n"); do_ram_command(dev, RAM_COMMAND_PRECHARGE); read32(rank_address + 0x10); /* 3. Mode register set. */ - PRINT_DEBUG_MEM("RAM Enable 4: Mode register set\r\n"); + PRINT_DEBUG_MEM("RAM Enable 4: Mode register set\n"); do_ram_command(dev, RAM_COMMAND_MRS); read32(rank_address + 0x120000); /* EMRS DLL Enable */ read32(rank_address + 0x800); /* MRS DLL Reset */ /* 4. Precharge all again. */ - PRINT_DEBUG_MEM("RAM Enable 2: Precharge all\r\n"); + PRINT_DEBUG_MEM("RAM Enable 2: Precharge all\n"); do_ram_command(dev, RAM_COMMAND_PRECHARGE); read32(rank_address + 0x0); /* 5. Perform 8 refresh cycles. Wait tRC each time. */ - PRINT_DEBUG_MEM("RAM Enable 3: CBR\r\n"); + PRINT_DEBUG_MEM("RAM Enable 3: CBR\n"); do_ram_command(dev, RAM_COMMAND_CBR); for (i = 0; i < 8; i++) { read32(rank_address + 0x20); @@ -420,7 +420,7 @@ } /* 6. Mode register set. */ - PRINT_DEBUG_MEM("RAM Enable 4: Mode register set\r\n"); + PRINT_DEBUG_MEM("RAM Enable 4: Mode register set\n"); /* Safe value for now, BL=8, WR=5, CAS=4 */ /* * (E)MRS values are from the BPG. No direct explanation is given, but @@ -433,7 +433,7 @@ read32(rank_address + 0x120020); /* EMRS OCD Calibration Mode Exit */ /* 8. Normal operation */ - PRINT_DEBUG_MEM("RAM Enable 5: Normal operation\r\n"); + PRINT_DEBUG_MEM("RAM Enable 5: Normal operation\n"); do_ram_command(dev, RAM_COMMAND_NORMAL); read32(rank_address + 0x30); } Modified: trunk/src/northbridge/via/cx700/cx700_early_smbus.c ============================================================================== --- trunk/src/northbridge/via/cx700/cx700_early_smbus.c Wed Mar 31 16:34:40 2010 (r5341) +++ trunk/src/northbridge/via/cx700/cx700_early_smbus.c Wed Mar 31 16:47:43 2010 (r5342) @@ -66,25 +66,25 @@ print_err("SMBus Error: "); print_err_hex8(host_status_register); - print_err("\r\n"); + print_err("\n"); if (loops >= SMBUS_TIMEOUT) { - print_err("SMBus Timout\r\n"); + print_err("SMBus Timout\n"); } if (host_status_register & (1 << 4)) { - print_err("Interrup/SMI# was Failed Bus Transaction\r\n"); + print_err("Interrup/SMI# was Failed Bus Transaction\n"); } if (host_status_register & (1 << 3)) { - print_err("Bus Error\r\n"); + print_err("Bus Error\n"); } if (host_status_register & (1 << 2)) { - print_err("Device Error\r\n"); + print_err("Device Error\n"); } if (host_status_register & (1 << 1)) { /* This isn't a real error... */ - print_debug("Interrupt/SMI# was Successful Completion\r\n"); + print_debug("Interrupt/SMI# was Successful Completion\n"); } if (host_status_register & (1 << 0)) { - print_err("Host Busy\r\n"); + print_err("Host Busy\n"); } } @@ -240,7 +240,7 @@ for (dimm = 0; dimm < DIMM_SOCKETS; dimm++) { print_debug("SPD Data for DIMM "); print_debug_hex8(dimm); - print_debug("\r\n"); + print_debug("\n"); val = get_spd_data(ctrl, dimm, 0); if (val == 0xff) { @@ -248,7 +248,7 @@ } else if (val == 0x80) { regs = 128; } else { - print_debug("No DIMM present\r\n"); + print_debug("No DIMM present\n"); regs = 0; } for (offset = 0; offset < regs; offset++) { @@ -256,7 +256,7 @@ print_debug_hex8(offset); print_debug(" = 0x"); print_debug_hex8(get_spd_data(ctrl, dimm, offset)); - print_debug("\r\n"); + print_debug("\n"); } } } Modified: trunk/src/northbridge/via/vt8601/raminit.c ============================================================================== --- trunk/src/northbridge/via/vt8601/raminit.c Wed Mar 31 16:34:40 2010 (r5341) +++ trunk/src/northbridge/via/vt8601/raminit.c Wed Mar 31 16:47:43 2010 (r5342) @@ -79,7 +79,7 @@ print_debug_hex8(pci_read_config8(north, r + c)); print_debug(" "); } - print_debug("\r\n"); + print_debug("\n"); if (r >= 240) break; } @@ -90,13 +90,13 @@ device_t north = (device_t) PCI_DEV(0, 0, 0); uint8_t c, r; - print_err("vt8601 init starting\r\n"); + print_err("vt8601 init starting\n"); print_debug_hex32(north); print_debug(" is the north\n"); print_debug_hex16(pci_read_config16(north, 0)); print_debug(" "); print_debug_hex16(pci_read_config16(north, 2)); - print_debug("\r\n"); + print_debug("\n"); /* All we are doing now is setting initial known-good values that will * be revised later as we read SPD @@ -186,7 +186,7 @@ print_info("Slot "); print_info_hex8(slot); if (smbus_read_byte(module, 2) != 4) { - print_info(" is empty\r\n"); + print_info(" is empty\n"); return 0; } print_info(" is SDRAM "); @@ -211,7 +211,7 @@ print_info("x2"); value = (value << 16) | value; } - print_info("\r\n"); + print_info("\n"); return value; } @@ -288,19 +288,19 @@ /* set NOP */ pci_write_config8(north, 0x6C, 0x01); - print_debug("NOP\r\n"); + print_debug("NOP\n"); /* wait 200us */ // You need to do the memory reference. That causes the nop cycle. dimms_read(0); udelay(400); - print_debug("PRECHARGE\r\n"); + print_debug("PRECHARGE\n"); /* set precharge */ pci_write_config8(north, 0x6C, 0x02); - print_debug("DUMMY READS\r\n"); + print_debug("DUMMY READS\n"); /* dummy reads */ dimms_read(0); udelay(200); - print_debug("CBR\r\n"); + print_debug("CBR\n"); /* set CBR */ pci_write_config8(north, 0x6C, 0x04); @@ -321,7 +321,7 @@ udelay(200); dimms_read(0); udelay(200); - print_debug("MRS\r\n"); + print_debug("MRS\n"); /* set MRS */ pci_write_config8(north, 0x6c, 0x03); #if DIMM_CL2 @@ -330,21 +330,21 @@ dimms_read(0x1d0); #endif udelay(200); - print_debug("NORMAL\r\n"); + print_debug("NORMAL\n"); /* set to normal mode */ pci_write_config8(north, 0x6C, 0x08); dimms_write(0x55aa55aa); dimms_read(0); udelay(200); - print_debug("set ref. rate\r\n"); + print_debug("set ref. rate\n"); // Set the refresh rate. #if DIMM_PC133 pci_write_config8(north, 0x6A, 0x86); #else pci_write_config8(north, 0x6A, 0x65); #endif - print_debug("enable multi-page open\r\n"); + print_debug("enable multi-page open\n"); // enable multi-page open pci_write_config8(north, 0x6B, 0x0d); @@ -381,8 +381,8 @@ else /* 256MB or more per side */ ma = 0xe; print_debug_hex16(ma); - print_debug(" is the MA type\r\n"); + print_debug(" is the MA type\n"); set_ma_mapping(north, slot, ma); } - print_err("vt8601 done\r\n"); + print_err("vt8601 done\n"); } Modified: trunk/src/northbridge/via/vt8623/raminit.c ============================================================================== --- trunk/src/northbridge/via/vt8623/raminit.c Wed Mar 31 16:34:40 2010 (r5341) +++ trunk/src/northbridge/via/vt8623/raminit.c Wed Mar 31 16:47:43 2010 (r5342) @@ -56,7 +56,7 @@ print_debug_hex8(pci_read_config8(north, r+c)); print_debug(" "); } - print_debug("\r\n"); + print_debug("\n"); } } void print_val(char *str, int val) @@ -72,7 +72,7 @@ uint16_t i,j; unsigned long bank_address; - print_debug("vt8623 init starting\r\n"); + print_debug("vt8623 init starting\n"); north = pci_locate_device(PCI_ID(0x1106, 0x3123), 0); north = 0; @@ -102,7 +102,7 @@ */ c = 0; b = smbus_read_byte(0xa0,17); - print_val("Detecting Memory\r\nNumber of Banks ",b); + print_val("Detecting Memory\nNumber of Banks ",b); if( b != 2 ){ // not 16 Mb type @@ -110,14 +110,14 @@ Read SPD byte 3, Number of row addresses. */ b = smbus_read_byte(0xa0,3); - print_val("\r\nNumber of Rows ",b); + print_val("\nNumber of Rows ",b); if( b >= 0x0d ){ // not 64/128Mb (rows <=12) /* Read SPD byte 13, Primary DRAM width. */ b = smbus_read_byte(0xa0,13); - print_val("\r\nPriamry DRAM width",b); + print_val("\nPriamry DRAM width",b); if( b != 4 ) // mot 64/128Mb (x4) c = 0x80; // 256Mb } @@ -128,13 +128,13 @@ Read SPD byte 4, Number of column addresses. */ b = smbus_read_byte(0xa0,4); - print_val("\r\nNo Columns ",b); + print_val("\nNo Columns ",b); if( b == 10 || b == 11 ) c |= 0x60; // 10/11 bit col addr if( b == 9 ) c |= 0x40; // 9 bit col addr if( b == 8 ) c |= 0x20; // 8 bit col addr } - print_val("\r\nMA type ",c); + print_val("\nMA type ",c); pci_write_config8(north,0x58,c); /* @@ -161,18 +161,18 @@ else c = 0x01; // Error, use default - print_val("\r\nBank 0 (*16 Mb) ",c); + print_val("\nBank 0 (*16 Mb) ",c); // set bank zero size pci_write_config8(north,0x5a,c); // SPD byte 5 # of physical banks b = smbus_read_byte(0xa0,5); - print_val("\r\nNo Physical Banks ",b); + print_val("\nNo Physical Banks ",b); if( b == 2) c <<=1; - print_val("\r\nTotal Memory (*16 Mb) ",c); + print_val("\nTotal Memory (*16 Mb) ",c); // set banks 1,2,3 pci_write_config8(north,0x5b,c); pci_write_config8(north,0x5c,c); @@ -181,40 +181,40 @@ /* Read SPD byte 18 CAS Latency */ b = smbus_read_byte(0xa0,18); - print_debug("\r\nCAS Supported "); + print_debug("\nCAS Supported "); if(b & 0x04) print_debug("2 "); if(b & 0x08) print_debug("2.5 "); if(b & 0x10) print_debug("3"); - print_val("\r\nCycle time at CL X (nS)",smbus_read_byte(0xa0,9)); - print_val("\r\nCycle time at CL X-0.5 (nS)",smbus_read_byte(0xa0,23)); - print_val("\r\nCycle time at CL X-1 (nS)",smbus_read_byte(0xa0,25)); + print_val("\nCycle time at CL X (nS)",smbus_read_byte(0xa0,9)); + print_val("\nCycle time at CL X-0.5 (nS)",smbus_read_byte(0xa0,23)); + print_val("\nCycle time at CL X-1 (nS)",smbus_read_byte(0xa0,25)); if( b & 0x10 ){ // DDR offering optional CAS 3 - print_debug("\r\nStarting at CAS 3"); + print_debug("\nStarting at CAS 3"); c = 0x30; /* see if we can better it */ if( b & 0x08 ){ // DDR mandatory CAS 2.5 if( smbus_read_byte(0xa0,23) <= 0x75 ){ // we can manage 133Mhz at CAS 2.5 - print_debug("\r\nWe can do CAS 2.5"); + print_debug("\nWe can do CAS 2.5"); c = 0x20; } } if( b & 0x04 ){ // DDR mandatory CAS 2 if( smbus_read_byte(0xa0,25) <= 0x75 ){ // we can manage 133Mhz at CAS 2 - print_debug("\r\nWe can do CAS 2"); + print_debug("\nWe can do CAS 2"); c = 0x10; } } }else{ // no optional CAS values just 2 & 2.5 - print_debug("\r\nStarting at CAS 2.5"); + print_debug("\nStarting at CAS 2.5"); c = 0x20; // assume CAS 2.5 if( b & 0x04){ // Should always happen if( smbus_read_byte(0xa0,23) <= 0x75){ // we can manage 133Mhz at CAS 2 - print_debug("\r\nWe can do CAS 2"); + print_debug("\nWe can do CAS 2"); c = 0x10; } } @@ -254,7 +254,7 @@ */ b = smbus_read_byte(0xa0,27); - print_val("\r\ntRP ",b); + print_val("\ntRP ",b); if( b > 0x3c ) // set tRP = 3T c |= 0x80; @@ -266,7 +266,7 @@ */ b = smbus_read_byte(0xa0,29); - print_val("\r\ntRCD ",b); + print_val("\ntRCD ",b); if( b > 0x3c ) // set tRCD = 3T c |= 0x04; @@ -278,7 +278,7 @@ */ b = smbus_read_byte(0xa0,30); - print_val("\r\ntRAS ",b); + print_val("\ntRAS ",b); if( b > 0x25 ) // set tRAS = 6T c |= 0x40; @@ -500,7 +500,7 @@ break; } - print_val("\r\nLow Bond ",i); + print_val("\nLow Bond ",i); if( i < 0xff ){ c = i++; for( ; i <0xff ; i++){ @@ -549,7 +549,7 @@ pci_write_config8(north,0x68,c); pci_write_config8(north,0x68,0x42); }else{ - print_debug("Unable to determine low bond - Setting default\r\n"); + print_debug("Unable to determine low bond - Setting default\n"); pci_write_config8(north,0x68,0x59); } @@ -608,10 +608,10 @@ pci_write_config8(north,0xac,0x2f); pci_write_config8(north,0xae,0x04); - print_debug("vt8623 done\r\n"); + print_debug("vt8623 done\n"); dumpnorth(north); - print_debug("AGP\r\n"); + print_debug("AGP\n"); north = pci_locate_device(PCI_ID(0x1106, 0xb091), 0); pci_write_config32(north,0x20,0xddf0dc00); pci_write_config32(north,0x24,0xdbf0d800); Modified: trunk/src/northbridge/via/vx800/examples/romstage.c ============================================================================== --- trunk/src/northbridge/via/vx800/examples/romstage.c Wed Mar 31 16:34:40 2010 (r5341) +++ trunk/src/northbridge/via/vx800/examples/romstage.c Wed Mar 31 16:47:43 2010 (r5342) @@ -52,13 +52,13 @@ device_t dev; u16 tmp, result; - print_debug("In acpi_is_wakeup_early_via_vx800\r\n"); + print_debug("In acpi_is_wakeup_early_via_vx800\n"); /* Power management controller */ dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VX855_LPC), 0); if (dev == PCI_DEV_INVALID) - die("Power management controller not found\r\n"); + die("Power management controller not found\n"); /* Set ACPI base address to I/O VX800_ACPI_IO_BASE. */ pci_write_config16(dev, 0x88, VX800_ACPI_IO_BASE | 0x1); @@ -70,7 +70,7 @@ result = ((tmp & (7 << 10)) >> 10) == 1 ? 3 : 0; print_debug(" boot_mode="); print_debug_hex16(result); - print_debug("\r\n"); + print_debug("\n"); return result; } @@ -85,7 +85,7 @@ device_t dev; uint16_t values; - print_debug("In enable_mainboard_devices \r\n"); + print_debug("In enable_mainboard_devices \n"); /* Enable P2P Bridge Header for External PCI BUS. @@ -375,14 +375,14 @@ if (bist == 0) { // CAR need mtrr untill mem is ok, so i disable this early_mtrr_init(); - //print_debug("doing early_mtrr\r\n"); + //print_debug("doing early_mtrr\n"); //early_mtrr_init(); } /* Halt if there was a built-in self test failure. */ report_bist_failure(bist); - print_debug("Enabling mainboard devices\r\n"); + print_debug("Enabling mainboard devices\n"); enable_mainboard_devices(); u8 Data; @@ -392,7 +392,7 @@ Data = pci_read_config8(device, 0xf6); print_debug("NB chip revision ="); print_debug_hex8(Data); - print_debug("\r\n"); + print_debug("\n"); /* make NB ready before draminit */ via_pci_inittable(Data, mNbStage1InitTbl); @@ -405,7 +405,7 @@ u8 ramregs[] = { 0x43, 0x42, 0x41, 0x40 }; DRAM_SYS_ATTR DramAttr; - print_debug("This is a S3 wakeup\r\n"); + print_debug("This is a S3 wakeup\n"); memset(&DramAttr, 0, sizeof(DRAM_SYS_ATTR)); /*Step1 DRAM Detection; DDR1 or DDR2; Get SPD Data; Rank Presence;64 or 128bit; Unbuffered or registered; 1T or 2T */ @@ -429,7 +429,7 @@ DRAMRegFinalValue(&DramAttr); // I just copy this function from draminit to here! SetUMARam(); // I just copy this function from draminit to here! - print_debug("Resume from S3, RAM init was ignored\r\n"); + print_debug("Resume from S3, RAM init was ignored\n"); } else { ddr2_ram_setup(); ram_check(0, 640 * 1024); @@ -528,7 +528,7 @@ "rep movsd\n\t" ::"g"(memtop4) );*/ - print_debug("copy memory to high memory to protect s3 wakeup vector code \r\n"); //this can have function call, because no variable used before this + print_debug("copy memory to high memory to protect s3 wakeup vector code \n"); //this can have function call, because no variable used before this memcpy((unsigned char *) ((*(u32 *) WAKE_MEM_INFO) - 64 * 1024 - 0x100000), (unsigned char *) 0, 0xa0000); @@ -572,11 +572,11 @@ __asm__ volatile ("movl %%esp, %0\n\t":"=a" (v_esp) ); #if CONFIG_USE_PRINTK_IN_CAR - printk(BIOS_DEBUG, "v_esp=%08x\r\n", v_esp); + printk(BIOS_DEBUG, "v_esp=%08x\n", v_esp); #else print_debug("v_esp="); print_debug_hex32(v_esp); - print_debug("\r\n"); + print_debug("\n"); #endif } @@ -588,11 +588,11 @@ //stack cpu_reset = 0; #if CONFIG_USE_PRINTK_IN_CAR - printk(BIOS_DEBUG, "cpu_reset = %08x\r\n", cpu_reset); + printk(BIOS_DEBUG, "cpu_reset = %08x\n", cpu_reset); #else print_debug("cpu_reset = "); print_debug_hex32(cpu_reset); - print_debug("\r\n"); + print_debug("\n"); #endif if (cpu_reset == 0) { @@ -635,16 +635,16 @@ /* We can not go back any more, we lost old stack data in cache as ram */ if (new_cpu_reset == 0) { - print_debug("Use Ram as Stack now - done\r\n"); + print_debug("Use Ram as Stack now - done\n"); } else { - print_debug("Use Ram as Stack now - \r\n"); + print_debug("Use Ram as Stack now - \n"); } #if CONFIG_USE_PRINTK_IN_CAR - printk(BIOS_DEBUG, "new_cpu_reset = %08x\r\n", new_cpu_reset); + printk(BIOS_DEBUG, "new_cpu_reset = %08x\n", new_cpu_reset); #else print_debug("new_cpu_reset = "); print_debug_hex32(new_cpu_reset); - print_debug("\r\n"); + print_debug("\n"); #endif /*copy and execute coreboot_ram */ copy_and_run(new_cpu_reset); @@ -653,6 +653,6 @@ #endif - print_debug("should not be here -\r\n"); + print_debug("should not be here -\n"); } Modified: trunk/src/northbridge/via/vx800/vga.c ============================================================================== --- trunk/src/northbridge/via/vx800/vga.c Wed Mar 31 16:34:40 2010 (r5341) +++ trunk/src/northbridge/via/vx800/vga.c Wed Mar 31 16:47:43 2010 (r5342) @@ -102,7 +102,7 @@ } #else /* Attempt to manually force the rom to load */ - printk(BIOS_DEBUG, "Forcing rom load\r\n"); + printk(BIOS_DEBUG, "Forcing rom load\n"); pci_rom_load(dev, 0xfff80000); run_bios(dev, 0xc0000); #endif Modified: trunk/src/northbridge/via/vx800/vx800_early_smbus.c ============================================================================== --- trunk/src/northbridge/via/vx800/vx800_early_smbus.c Wed Mar 31 16:34:40 2010 (r5341) +++ trunk/src/northbridge/via/vx800/vx800_early_smbus.c Wed Mar 31 16:47:43 2010 (r5342) @@ -60,32 +60,32 @@ /* Internal functions */ static void smbus_print_error(unsigned char host_status_register, int loops) { -// print_err("some i2c error\r\n"); +// print_err("some i2c error\n"); /* Check if there actually was an error */ if (host_status_register == 0x00 || host_status_register == 0x40 || host_status_register == 0x42) return; print_err("smbus_error: "); print_err_hex8(host_status_register); - print_err("\r\n"); + print_err("\n"); if (loops >= SMBUS_TIMEOUT) { - print_err("SMBus Timout\r\n"); + print_err("SMBus Timout\n"); } if (host_status_register & (1 << 4)) { - print_err("Interrup/SMI# was Failed Bus Transaction\r\n"); + print_err("Interrup/SMI# was Failed Bus Transaction\n"); } if (host_status_register & (1 << 3)) { - print_err("Bus Error\r\n"); + print_err("Bus Error\n"); } if (host_status_register & (1 << 2)) { - print_err("Device Error\r\n"); + print_err("Device Error\n"); } if (host_status_register & (1 << 1)) { /* This isn't a real error... */ - print_debug("Interrupt/SMI# was Successful Completion\r\n"); + print_debug("Interrupt/SMI# was Successful Completion\n"); } if (host_status_register & (1 << 0)) { - print_err("Host Busy\r\n"); + print_err("Host Busy\n"); } } @@ -204,7 +204,7 @@ if (dev == PCI_DEV_INVALID) { /* This won't display text if enable_smbus() is before serial init */ - die("Power Managment Controller not found\r\n"); + die("Power Managment Controller not found\n"); } /* Set clock source */ @@ -253,7 +253,7 @@ ram_slots = ARRAY_SIZE(ctrl->channel0); if (!ram_slots) { - print_err("smbus_fixup() thinks there are no RAM slots!\r\n"); + print_err("smbus_fixup() thinks there are no RAM slots!\n"); return; } @@ -279,9 +279,9 @@ } if (i >= SMBUS_TIMEOUT) - print_err("SMBus timed out while warming up\r\n"); + print_err("SMBus timed out while warming up\n"); else - PRINT_DEBUG("Done\r\n"); + PRINT_DEBUG("Done\n"); } /* Debugging Function */ @@ -294,7 +294,7 @@ for (dimm = 0; dimm < 8; dimm++) { print_debug("SPD Data for DIMM "); print_debug_hex8(dimm); - print_debug("\r\n"); + print_debug("\n"); val = get_spd_data(dimm, 0); if (val == 0xff) { @@ -302,7 +302,7 @@ } else if (val == 0x80) { regs = 128; } else { - print_debug("No DIMM present\r\n"); + print_debug("No DIMM present\n"); regs = 0; } for (offset = 0; offset < regs; offset++) { @@ -310,7 +310,7 @@ print_debug_hex8(offset); print_debug(" = 0x"); print_debug_hex8(get_spd_data(dimm, offset)); - print_debug("\r\n"); + print_debug("\n"); } } } Modified: trunk/src/southbridge/amd/amd8111/amd8111_early_smbus.c ============================================================================== --- trunk/src/southbridge/amd/amd8111/amd8111_early_smbus.c Wed Mar 31 16:34:40 2010 (r5341) +++ trunk/src/southbridge/amd/amd8111/amd8111_early_smbus.c Wed Mar 31 16:47:43 2010 (r5342) @@ -9,7 +9,7 @@ dev = pci_locate_device(PCI_ID(0x1022, 0x746b), 0); if (dev == PCI_DEV_INVALID) { - die("SMBUS controller not found\r\n"); + die("SMBUS controller not found\n"); } pci_write_config32(dev, 0x58, SMBUS_IO_BASE | 1); @@ -23,7 +23,7 @@ /* clear any lingering errors, so the transaction will run */ outw(inw(SMBUS_IO_BASE + SMBGSTATUS), SMBUS_IO_BASE + SMBGSTATUS); - print_spew("SMBus controller enabled\r\n"); + print_spew("SMBus controller enabled\n"); } static int smbus_recv_byte(unsigned device) Modified: trunk/src/southbridge/amd/cs5535/cs5535_early_setup.c ============================================================================== --- trunk/src/southbridge/amd/cs5535/cs5535_early_setup.c Wed Mar 31 16:34:40 2010 (r5341) +++ trunk/src/southbridge/amd/cs5535/cs5535_early_setup.c Wed Mar 31 16:47:43 2010 (r5342) @@ -164,19 +164,19 @@ msr = rdmsr(GLCP_SYS_RSTPLL); if (msr.lo & (0x3f << 26)) { /* PLL is already set and we are reboot from PLL reset */ - print_debug("reboot from BIOS reset\n\r"); + print_debug("reboot from BIOS reset\n"); return; } - print_debug("Setup idsel\r\n"); + print_debug("Setup idsel\n"); cs5535_setup_idsel(); - print_debug("Setup iobase\r\n"); + print_debug("Setup iobase\n"); cs5535_usb_swapsif(); cs5535_setup_iobase(); - print_debug("Setup gpio\r\n"); + print_debug("Setup gpio\n"); cs5535_setup_gpio(); - print_debug("Setup cis_mode\r\n"); + print_debug("Setup cis_mode\n"); cs5535_setup_cis_mode(); - print_debug("Setup smbus\r\n"); + print_debug("Setup smbus\n"); cs5535_enable_smbus(); dummy(); } Modified: trunk/src/southbridge/amd/cs5536/cs5536_early_setup.c ============================================================================== --- trunk/src/southbridge/amd/cs5536/cs5536_early_setup.c Wed Mar 31 16:34:40 2010 (r5341) +++ trunk/src/southbridge/amd/cs5536/cs5536_early_setup.c Wed Mar 31 16:47:43 2010 (r5342) @@ -257,18 +257,18 @@ msr = rdmsr(GLCP_SYS_RSTPLL); if (msr.lo & (0x3f << 26)) { /* PLL is already set and we are reboot from PLL reset */ - //print_debug("reboot from BIOS reset\n\r"); + //print_debug("reboot from BIOS reset\n"); return; } - //print_debug("Setup idsel\r\n"); + //print_debug("Setup idsel\n"); cs5536_setup_idsel(); - //print_debug("Setup iobase\r\n"); + //print_debug("Setup iobase\n"); cs5536_usb_swapsif(); cs5536_setup_iobase(); - //print_debug("Setup gpio\r\n"); + //print_debug("Setup gpio\n"); cs5536_setup_gpio(); - //print_debug("Setup smbus\r\n"); + //print_debug("Setup smbus\n"); cs5536_enable_smbus(); - //print_debug("Setup power button\r\n"); + //print_debug("Setup power button\n"); cs5536_setup_power_button(); } Modified: trunk/src/southbridge/amd/cs5536/cs5536_early_smbus.c ============================================================================== --- trunk/src/southbridge/amd/cs5536/cs5536_early_smbus.c Wed Mar 31 16:34:40 2010 (r5341) +++ trunk/src/southbridge/amd/cs5536/cs5536_early_smbus.c Wed Mar 31 16:47:43 2010 (r5342) @@ -199,7 +199,7 @@ print_debug_hex8(error); print_debug(" device:"); print_debug_hex8(device); - print_debug("\r\n"); + print_debug("\n"); /* stop, clean up the error, and leave */ smbus_stop_condition(smbus_io_base); outb(inb(smbus_io_base + SMB_STS), smbus_io_base + SMB_STS); Modified: trunk/src/southbridge/amd/sb600/sb600_early_setup.c ============================================================================== --- trunk/src/southbridge/amd/sb600/sb600_early_setup.c Wed Mar 31 16:34:40 2010 (r5341) +++ trunk/src/southbridge/amd/sb600/sb600_early_setup.c Wed Mar 31 16:47:43 2010 (r5342) @@ -44,7 +44,7 @@ dev = pci_locate_device(PCI_ID(0x1002, 0x4385), 0); if (dev == PCI_DEV_INVALID) { - die("SMBUS controller not found\r\n"); + die("SMBUS controller not found\n"); /* NOT REACHED */ } return pci_read_config8(dev, 0x08); @@ -290,10 +290,10 @@ dev = pci_locate_device(PCI_ID(0x1002, 0x4385), 0); if (dev == PCI_DEV_INVALID) { - die("SMBUS controller not found\r\n"); + die("SMBUS controller not found\n"); /* NOT REACHED */ } - printk(BIOS_INFO, "SMBus controller enabled, sb revision is 0x%x\r\n", + printk(BIOS_INFO, "SMBus controller enabled, sb revision is 0x%x\n", get_sb600_revision()); /* sbPorAtStartOfTblCfg */ Modified: trunk/src/southbridge/amd/sb700/sb700_early_setup.c ============================================================================== --- trunk/src/southbridge/amd/sb700/sb700_early_setup.c Wed Mar 31 16:34:40 2010 (r5341) +++ trunk/src/southbridge/amd/sb700/sb700_early_setup.c Wed Mar 31 16:47:43 2010 (r5342) @@ -51,7 +51,7 @@ dev = pci_locate_device(PCI_ID(0x1002, 0x4385), 0); if (dev == PCI_DEV_INVALID) { - die("SMBUS controller not found\r\n"); + die("SMBUS controller not found\n"); /* NOT REACHED */ } rev_id = pci_read_config8(dev, 0x08); @@ -81,7 +81,7 @@ } else if (rev_id == 0x3D) { rev = 0x15; } else - die("It is not SB700 or SB710\r\n"); + die("It is not SB700 or SB710\n"); return rev; } @@ -306,10 +306,10 @@ dev = pci_locate_device(PCI_ID(0x1002, 0x4385), 0); if (dev == PCI_DEV_INVALID) { - die("SMBUS controller not found\r\n"); + die("SMBUS controller not found\n"); /* NOT REACHED */ } - printk(BIOS_INFO, "SMBus controller enabled, sb revision is A%x\r\n", + printk(BIOS_INFO, "SMBus controller enabled, sb revision is A%x\n", set_sb700_revision()); /* sbPorAtStartOfTblCfg */ Modified: trunk/src/southbridge/broadcom/bcm5785/bcm5785_early_smbus.c ============================================================================== --- trunk/src/southbridge/broadcom/bcm5785/bcm5785_early_smbus.c Wed Mar 31 16:34:40 2010 (r5341) +++ trunk/src/southbridge/broadcom/bcm5785/bcm5785_early_smbus.c Wed Mar 31 16:47:43 2010 (r5342) @@ -13,10 +13,10 @@ dev = pci_locate_device(PCI_ID(0x1166, 0x0205), 0); // 0x0201? if (dev == PCI_DEV_INVALID) { - die("SMBUS controller not found\r\n"); + die("SMBUS controller not found\n"); } - print_debug("SMBus controller enabled\r\n"); + print_debug("SMBus controller enabled\n"); /* set smbus iobase */ pci_write_config32(dev, 0x90, SMBUS_IO_BASE | 1); /* Set smbus iospace enable */ Modified: trunk/src/southbridge/broadcom/bcm5785/bcm5785_lpc.c ============================================================================== --- trunk/src/southbridge/broadcom/bcm5785/bcm5785_lpc.c Wed Mar 31 16:34:40 2010 (r5341) +++ trunk/src/southbridge/broadcom/bcm5785/bcm5785_lpc.c Wed Mar 31 16:47:43 2010 (r5342) @@ -86,7 +86,7 @@ if(!(res->flags & IORESOURCE_IO)) continue; base = res->base; end = resource_end(res); - printk(BIOS_DEBUG, "bcm5785lpc decode:%s, base=0x%08lx, end=0x%08lx\r\n",dev_path(child),base, end); + printk(BIOS_DEBUG, "bcm5785lpc decode:%s, base=0x%08lx, end=0x%08lx\n",dev_path(child),base, end); switch(base) { case 0x60: //KBC case 0x64: Modified: trunk/src/southbridge/broadcom/bcm5785/bcm5785_sata.c ============================================================================== --- trunk/src/southbridge/broadcom/bcm5785/bcm5785_sata.c Wed Mar 31 16:34:40 2010 (r5341) +++ trunk/src/southbridge/broadcom/bcm5785/bcm5785_sata.c Wed Mar 31 16:47:43 2010 (r5342) @@ -53,13 +53,13 @@ for(i=0; i<4; i++) { mmio = base + 0x100 * i; byte = read8(mmio + 0x40); - printk(BIOS_DEBUG, "port %d PHY status = %02x\r\n", i, byte); + printk(BIOS_DEBUG, "port %d PHY status = %02x\n", i, byte); if(byte & 0x4) {// bit 2 is set byte = read8(mmio+0x48); write8(mmio + 0x48, byte | 1); write8(mmio + 0x48, byte & (~1)); byte = read8(mmio + 0x40); - printk(BIOS_DEBUG, "after reset port %d PHY status = %02x\r\n", i, byte); + printk(BIOS_DEBUG, "after reset port %d PHY status = %02x\n", i, byte); } } Modified: trunk/src/southbridge/intel/esb6300/esb6300_early_smbus.c ============================================================================== --- trunk/src/southbridge/intel/esb6300/esb6300_early_smbus.c Wed Mar 31 16:34:40 2010 (r5341) +++ trunk/src/southbridge/intel/esb6300/esb6300_early_smbus.c Wed Mar 31 16:47:43 2010 (r5342) @@ -6,7 +6,7 @@ { device_t dev = PCI_DEV(0x0, 0x1f, 0x3); - print_spew("SMBus controller enabled\r\n"); + print_spew("SMBus controller enabled\n"); pci_write_config32(dev, 0x20, SMBUS_IO_BASE | 1); pci_write_config8(dev, 0x40, 1); pci_write_config8(dev, 0x4, 1); @@ -92,7 +92,7 @@ SMBUS_IO_BASE + SMBHSTSTAT); } - print_debug("SMBUS Block complete\r\n"); + print_debug("SMBUS Block complete\n"); return 0; } Modified: trunk/src/southbridge/intel/i3100/i3100_early_smbus.c ============================================================================== --- trunk/src/southbridge/intel/i3100/i3100_early_smbus.c Wed Mar 31 16:34:40 2010 (r5341) +++ trunk/src/southbridge/intel/i3100/i3100_early_smbus.c Wed Mar 31 16:47:43 2010 (r5342) @@ -26,7 +26,7 @@ { device_t dev = PCI_DEV(0x0, 0x1f, 0x3); - print_spew("SMBus controller enabled\r\n"); + print_spew("SMBus controller enabled\n"); pci_write_config32(dev, 0x20, SMBUS_IO_BASE | 1); pci_write_config8(dev, 0x40, 1); pci_write_config8(dev, 0x4, 1); Modified: trunk/src/southbridge/intel/i82371eb/i82371eb_early_smbus.c ============================================================================== --- trunk/src/southbridge/intel/i82371eb/i82371eb_early_smbus.c Wed Mar 31 16:34:40 2010 (r5341) +++ trunk/src/southbridge/intel/i82371eb/i82371eb_early_smbus.c Wed Mar 31 16:47:43 2010 (r5342) @@ -38,9 +38,9 @@ PCI_DEVICE_ID_INTEL_82371AB_SMB_ACPI), 0); if (dev == PCI_DEV_INVALID) - die("SMBus controller not found\r\n"); + die("SMBus controller not found\n"); - print_spew("SMBus controller enabled\r\n"); + print_spew("SMBus controller enabled\n"); /* Set the SMBus I/O base. */ pci_write_config32(dev, SMBBA, SMBUS_IO_BASE | 1); Modified: trunk/src/southbridge/intel/i82371eb/i82371eb_smbus.h ============================================================================== --- trunk/src/southbridge/intel/i82371eb/i82371eb_smbus.h Wed Mar 31 16:34:40 2010 (r5341) +++ trunk/src/southbridge/intel/i82371eb/i82371eb_smbus.h Wed Mar 31 16:47:43 2010 (r5342) @@ -192,7 +192,7 @@ #if 0 print_debug("Read fail "); print_debug_hex16(status_register); - print_debug("\r\n"); + print_debug("\n"); #endif return SMBUS_ERROR; } Modified: trunk/src/southbridge/intel/i82801ax/i82801ax_early_smbus.c ============================================================================== --- trunk/src/southbridge/intel/i82801ax/i82801ax_early_smbus.c Wed Mar 31 16:34:40 2010 (r5341) +++ trunk/src/southbridge/intel/i82801ax/i82801ax_early_smbus.c Wed Mar 31 16:47:43 2010 (r5342) @@ -58,7 +58,7 @@ /* Clear any lingering errors, so transactions can run. */ outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT); - print_debug("SMBus controller enabled\r\n"); + print_debug("SMBus controller enabled\n"); } static inline int smbus_read_byte(unsigned device, unsigned address) @@ -69,7 +69,7 @@ static void smbus_write_byte(unsigned device, unsigned address, unsigned char val) { - print_err("Unimplemented smbus_write_byte() called\r\n"); + print_err("Unimplemented smbus_write_byte() called\n"); return; } Modified: trunk/src/southbridge/intel/i82801ax/i82801ax_smbus.h ============================================================================== --- trunk/src/southbridge/intel/i82801ax/i82801ax_smbus.h Wed Mar 31 16:34:40 2010 (r5341) +++ trunk/src/southbridge/intel/i82801ax/i82801ax_smbus.h Wed Mar 31 16:47:43 2010 (r5342) @@ -116,7 +116,7 @@ unsigned data1, unsigned data2) { #warning "do_smbus_write_block is commented out" - print_err("Untested smbus_write_block called\r\n"); + print_err("Untested smbus_write_block called\n"); #if 0 unsigned char global_control_register; unsigned char global_status_register; @@ -177,7 +177,7 @@ SMBUS_IO_BASE + SMBHSTSTAT); } - print_debug("SMBUS Block complete\r\n"); + print_debug("SMBUS Block complete\n"); return 0; #endif } Modified: trunk/src/southbridge/intel/i82801ax/i82801ax_watchdog.c ============================================================================== --- trunk/src/southbridge/intel/i82801ax/i82801ax_watchdog.c Wed Mar 31 16:34:40 2010 (r5341) +++ trunk/src/southbridge/intel/i82801ax/i82801ax_watchdog.c Wed Mar 31 16:47:43 2010 (r5342) @@ -51,5 +51,5 @@ outw(0x0008, base + 0x04); outw(0x0002, base + 0x06); - printk(BIOS_DEBUG, "ICH Watchdog disabled\r\n"); + printk(BIOS_DEBUG, "ICH Watchdog disabled\n"); } Modified: trunk/src/southbridge/intel/i82801bx/i82801bx_early_smbus.c ============================================================================== --- trunk/src/southbridge/intel/i82801bx/i82801bx_early_smbus.c Wed Mar 31 16:34:40 2010 (r5341) +++ trunk/src/southbridge/intel/i82801bx/i82801bx_early_smbus.c Wed Mar 31 16:47:43 2010 (r5342) @@ -58,7 +58,7 @@ /* Clear any lingering errors, so transactions can run. */ outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT); - print_debug("SMBus controller enabled\r\n"); + print_debug("SMBus controller enabled\n"); } static inline int smbus_read_byte(unsigned device, unsigned address) @@ -69,7 +69,7 @@ static void smbus_write_byte(unsigned device, unsigned address, unsigned char val) { - print_err("Unimplemented smbus_write_byte() called\r\n"); + print_err("Unimplemented smbus_write_byte() called\n"); return; } Modified: trunk/src/southbridge/intel/i82801bx/i82801bx_smbus.h ============================================================================== --- trunk/src/southbridge/intel/i82801bx/i82801bx_smbus.h Wed Mar 31 16:34:40 2010 (r5341) +++ trunk/src/southbridge/intel/i82801bx/i82801bx_smbus.h Wed Mar 31 16:47:43 2010 (r5342) @@ -116,7 +116,7 @@ unsigned data1, unsigned data2) { #warning "do_smbus_write_block is commented out" - print_err("Untested smbus_write_block called\r\n"); + print_err("Untested smbus_write_block called\n"); #if 0 unsigned char global_control_register; unsigned char global_status_register; @@ -177,7 +177,7 @@ SMBUS_IO_BASE + SMBHSTSTAT); } - print_debug("SMBUS Block complete\r\n"); + print_debug("SMBUS Block complete\n"); return 0; #endif } Modified: trunk/src/southbridge/intel/i82801bx/i82801bx_watchdog.c ============================================================================== --- trunk/src/southbridge/intel/i82801bx/i82801bx_watchdog.c Wed Mar 31 16:34:40 2010 (r5341) +++ trunk/src/southbridge/intel/i82801bx/i82801bx_watchdog.c Wed Mar 31 16:47:43 2010 (r5342) @@ -50,5 +50,5 @@ outw(0x0008, base + 0x04); outw(0x0002, base + 0x06); - printk(BIOS_DEBUG, "ICH Watchdog disabled\r\n"); + printk(BIOS_DEBUG, "ICH Watchdog disabled\n"); } Modified: trunk/src/southbridge/intel/i82801cx/i82801cx_early_smbus.c ============================================================================== --- trunk/src/southbridge/intel/i82801cx/i82801cx_early_smbus.c Wed Mar 31 16:34:40 2010 (r5341) +++ trunk/src/southbridge/intel/i82801cx/i82801cx_early_smbus.c Wed Mar 31 16:47:43 2010 (r5342) @@ -5,7 +5,7 @@ { device_t dev = PCI_DEV(0x0, 0x1f, 0x3); - print_debug("SMBus controller enabled\r\n"); + print_debug("SMBus controller enabled\n"); /* set smbus iobase */ pci_write_config32(dev, SMB_BASE, SMBUS_IO_BASE | PCI_BASE_ADDRESS_SPACE_IO); /* Set smbus enable */ Modified: trunk/src/southbridge/intel/i82801dx/i82801dx_early_smbus.c ============================================================================== --- trunk/src/southbridge/intel/i82801dx/i82801dx_early_smbus.c Wed Mar 31 16:34:40 2010 (r5341) +++ trunk/src/southbridge/intel/i82801dx/i82801dx_early_smbus.c Wed Mar 31 16:47:43 2010 (r5342) @@ -42,7 +42,7 @@ { device_t dev = PCI_DEV(0x0, 0x1f, 0x3); - print_debug("SMBus controller enabled\r\n"); + print_debug("SMBus controller enabled\n"); /* set smbus iobase */ pci_write_config32(dev, 0x20, SMBUS_IO_BASE | 1); /* Set smbus enable */ @@ -119,7 +119,7 @@ unsigned char global_status_register; unsigned char byte; - /*print_err("smbus_read_byte\r\n"); */ + /*print_err("smbus_read_byte\n"); */ if (smbus_wait_until_ready() < 0) { print_err_hex8(-2); return -2; @@ -169,7 +169,7 @@ /* print_err("smbus_read_byte: "); print_err_hex32(device); print_err(" ad "); print_err_hex32(address); - print_err("value "); print_err_hex8(byte); print_err("\r\n"); + print_err("value "); print_err_hex8(byte); print_err("\n"); */ return byte; } Modified: trunk/src/southbridge/intel/i82801ex/i82801ex_early_smbus.c ============================================================================== --- trunk/src/southbridge/intel/i82801ex/i82801ex_early_smbus.c Wed Mar 31 16:34:40 2010 (r5341) +++ trunk/src/southbridge/intel/i82801ex/i82801ex_early_smbus.c Wed Mar 31 16:47:43 2010 (r5342) @@ -6,7 +6,7 @@ { device_t dev = PCI_DEV(0x0, 0x1f, 0x3); - print_spew("SMBus controller enabled\r\n"); + print_spew("SMBus controller enabled\n"); pci_write_config32(dev, 0x20, SMBUS_IO_BASE | 1); print_debug_hex32(pci_read_config32(dev, 0x20)); @@ -35,7 +35,7 @@ return; } - print_debug("Unimplemented smbus_write_byte() called.\r\n"); + print_debug("Unimplemented smbus_write_byte() called.\n"); #if 0 /* setup transaction */ @@ -125,7 +125,7 @@ SMBUS_IO_BASE + SMBHSTSTAT); } - print_debug("SMBUS Block complete\r\n"); + print_debug("SMBUS Block complete\n"); return 0; } Modified: trunk/src/southbridge/intel/i82801ex/i82801ex_watchdog.c ============================================================================== --- trunk/src/southbridge/intel/i82801ex/i82801ex_watchdog.c Wed Mar 31 16:34:40 2010 (r5341) +++ trunk/src/southbridge/intel/i82801ex/i82801ex_watchdog.c Wed Mar 31 16:47:43 2010 (r5342) @@ -24,6 +24,6 @@ /* Clear TCO timeout status */ outw(0x0008, base + 0x04); outw(0x0002, base + 0x06); - printk(BIOS_DEBUG, "Watchdog ICH5 disabled\r\n"); + printk(BIOS_DEBUG, "Watchdog ICH5 disabled\n"); } Modified: trunk/src/southbridge/intel/i82801gx/i82801gx_early_smbus.c ============================================================================== --- trunk/src/southbridge/intel/i82801gx/i82801gx_early_smbus.c Wed Mar 31 16:34:40 2010 (r5341) +++ trunk/src/southbridge/intel/i82801gx/i82801gx_early_smbus.c Wed Mar 31 16:47:43 2010 (r5342) @@ -49,7 +49,7 @@ /* Clear any lingering errors, so transactions can run. */ outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT); - print_debug("SMBus controller enabled.\r\n"); + print_debug("SMBus controller enabled.\n"); } static inline int smbus_read_byte(unsigned device, unsigned address) Modified: trunk/src/southbridge/intel/i82801gx/i82801gx_watchdog.c ============================================================================== --- trunk/src/southbridge/intel/i82801gx/i82801gx_watchdog.c Wed Mar 31 16:34:40 2010 (r5341) +++ trunk/src/southbridge/intel/i82801gx/i82801gx_watchdog.c Wed Mar 31 16:47:43 2010 (r5342) @@ -49,5 +49,5 @@ outw(0x0008, base + 0x04); outw(0x0002, base + 0x06); - printk(BIOS_DEBUG, "ICH7 watchdog disabled\r\n"); + printk(BIOS_DEBUG, "ICH7 watchdog disabled\n"); } Modified: trunk/src/southbridge/nvidia/ck804/ck804_early_smbus.c ============================================================================== --- trunk/src/southbridge/nvidia/ck804/ck804_early_smbus.c Wed Mar 31 16:34:40 2010 (r5341) +++ trunk/src/southbridge/nvidia/ck804/ck804_early_smbus.c Wed Mar 31 16:47:43 2010 (r5342) @@ -12,9 +12,9 @@ device_t dev; dev = pci_locate_device(PCI_ID(0x10de, 0x0052), 0); if (dev == PCI_DEV_INVALID) - die("SMBus controller not found\r\n"); + die("SMBus controller not found\n"); - print_debug("SMBus controller enabled\r\n"); + print_debug("SMBus controller enabled\n"); /* Set SMBus I/O base. */ pci_write_config32(dev, 0x20, SMBUS_IO_BASE | 1); Modified: trunk/src/southbridge/nvidia/ck804/ck804_lpc.c ============================================================================== --- trunk/src/southbridge/nvidia/ck804/ck804_lpc.c Wed Mar 31 16:34:40 2010 (r5341) +++ trunk/src/southbridge/nvidia/ck804/ck804_lpc.c Wed Mar 31 16:47:43 2010 (r5342) @@ -250,7 +250,7 @@ continue; base = res->base; end = resource_end(res); - printk(BIOS_DEBUG, "ck804 lpc decode:%s, base=0x%08lx, end=0x%08lx\r\n", dev_path(child), base, end); + printk(BIOS_DEBUG, "ck804 lpc decode:%s, base=0x%08lx, end=0x%08lx\n", dev_path(child), base, end); switch (base) { case 0x3f8: // COM1 reg |= (1 << 0); Modified: trunk/src/southbridge/nvidia/ck804/ck804_sata.c ============================================================================== --- trunk/src/southbridge/nvidia/ck804/ck804_sata.c Wed Mar 31 16:34:40 2010 (r5341) +++ trunk/src/southbridge/nvidia/ck804/ck804_sata.c Wed Mar 31 16:47:43 2010 (r5342) @@ -51,7 +51,7 @@ return; dword = *(base + 0); - printk(BIOS_DEBUG, "*(base+0)=%08x\r\n", dword); + printk(BIOS_DEBUG, "*(base+0)=%08x\n", dword); if (dword == 0x113) { loop = 200000; // 2 do { @@ -60,11 +60,11 @@ break; udelay(10); } while (--loop > 0); - printk(BIOS_DEBUG, "loop=%d, *(base+4)=%08x\r\n", loop, dword); + printk(BIOS_DEBUG, "loop=%d, *(base+4)=%08x\n", loop, dword); } dword = *(base + 0x40); - printk(BIOS_DEBUG, "*(base+0x40)=%08x\r\n", dword); + printk(BIOS_DEBUG, "*(base+0x40)=%08x\n", dword); if (dword == 0x113) { loop = 200000; //2 do { @@ -73,7 +73,7 @@ break; udelay(10); } while (--loop > 0); - printk(BIOS_DEBUG, "loop=%d, *(base+0x44)=%08x\r\n", loop, dword); + printk(BIOS_DEBUG, "loop=%d, *(base+0x44)=%08x\n", loop, dword); } } #endif Modified: trunk/src/southbridge/nvidia/mcp55/mcp55_early_setup_car.c ============================================================================== --- trunk/src/southbridge/nvidia/mcp55/mcp55_early_setup_car.c Wed Mar 31 16:34:40 2010 (r5341) +++ trunk/src/southbridge/nvidia/mcp55/mcp55_early_setup_car.c Wed Mar 31 16:47:43 2010 (r5342) @@ -412,7 +412,7 @@ } out: - print_debug("mcp55_num:"); print_debug_hex8(mcp55_num); print_debug("\r\n"); + print_debug("mcp55_num:"); print_debug_hex8(mcp55_num); print_debug("\n"); mcp55_early_set_port(mcp55_num, busn, devn, io_base); mcp55_early_setup(mcp55_num, busn, devn, io_base, pci_e_x); Modified: trunk/src/southbridge/nvidia/mcp55/mcp55_early_smbus.c ============================================================================== --- trunk/src/southbridge/nvidia/mcp55/mcp55_early_smbus.c Wed Mar 31 16:34:40 2010 (r5341) +++ trunk/src/southbridge/nvidia/mcp55/mcp55_early_smbus.c Wed Mar 31 16:47:43 2010 (r5342) @@ -33,10 +33,10 @@ dev = pci_locate_device(PCI_ID(0x10de, 0x0368), 0); #if 0 if (dev == PCI_DEV_INVALID) { - die("SMBUS controller not found\r\n"); + die("SMBUS controller not found\n"); } - print_debug("SMBus controller enabled\r\n"); + print_debug("SMBus controller enabled\n"); #endif /* set smbus iobase */ pci_write_config32(dev, 0x20, SMBUS0_IO_BASE | 1); Modified: trunk/src/southbridge/sis/sis966/sis966_aza.c ============================================================================== --- trunk/src/southbridge/sis/sis966/sis966_aza.c Wed Mar 31 16:34:40 2010 (r5341) +++ trunk/src/southbridge/sis/sis966/sis966_aza.c Wed Mar 31 16:47:43 2010 (r5342) @@ -277,14 +277,14 @@ for(i=0;i<0xff;i+=4){ if((i%16)==0){ - print_debug("\r\n"); + print_debug("\n"); print_debug_hex8(i); print_debug(": "); } print_debug_hex32(pci_read_config32(dev,i)); print_debug(" "); } - print_debug("\r\n"); + print_debug("\n"); } #endif Modified: trunk/src/southbridge/sis/sis966/sis966_ide.c ============================================================================== --- trunk/src/southbridge/sis/sis966/sis966_ide.c Wed Mar 31 16:34:40 2010 (r5341) +++ trunk/src/southbridge/sis/sis966/sis966_ide.c Wed Mar 31 16:47:43 2010 (r5342) @@ -156,14 +156,14 @@ for(i=0;i<0xff;i+=4){ if((i%16)==0){ - print_debug("\r\n"); + print_debug("\n"); print_debug_hex8(i); print_debug(": "); } print_debug_hex32(pci_read_config32(dev,i)); print_debug(" "); } - print_debug("\r\n"); + print_debug("\n"); } #endif print_debug("IDE_INIT:<----------\n"); Modified: trunk/src/southbridge/sis/sis966/sis966_nic.c ============================================================================== --- trunk/src/southbridge/sis/sis966/sis966_nic.c Wed Mar 31 16:34:40 2010 (r5341) +++ trunk/src/southbridge/sis/sis966/sis966_nic.c Wed Mar 31 16:47:43 2010 (r5342) @@ -270,7 +270,7 @@ if(!res) { - printk(BIOS_DEBUG, "NIC Cannot find resource..\r\n"); + printk(BIOS_DEBUG, "NIC Cannot find resource..\n"); return; } base = res->base; @@ -278,7 +278,7 @@ if(!(val=phy_detect(base,&PhyAddr))) { - printk(BIOS_DEBUG, "PHY detect fail !!!!\r\n"); + printk(BIOS_DEBUG, "PHY detect fail !!!!\n"); return; } @@ -321,14 +321,14 @@ for(i=0;i<0xff;i+=4){ if((i%16)==0){ - print_debug("\r\n"); + print_debug("\n"); print_debug_hex8(i); print_debug(": "); } print_debug_hex32(pci_read_config32(dev,i)); print_debug(" "); } - print_debug("\r\n"); + print_debug("\n"); } Modified: trunk/src/southbridge/sis/sis966/sis966_sata.c ============================================================================== --- trunk/src/southbridge/sis/sis966/sis966_sata.c Wed Mar 31 16:34:40 2010 (r5341) +++ trunk/src/southbridge/sis/sis966/sis966_sata.c Wed Mar 31 16:47:43 2010 (r5342) @@ -156,14 +156,14 @@ for(i=0;i<0xff;i+=4){ if((i%16)==0){ - print_debug("\r\n"); + print_debug("\n"); print_debug_hex8(i); print_debug(": "); } print_debug_hex32(pci_read_config32(dev,i)); print_debug(" "); } - print_debug("\r\n"); + print_debug("\n"); } #endif Modified: trunk/src/southbridge/sis/sis966/sis966_usb.c ============================================================================== --- trunk/src/southbridge/sis/sis966/sis966_usb.c Wed Mar 31 16:34:40 2010 (r5341) +++ trunk/src/southbridge/sis/sis966/sis966_usb.c Wed Mar 31 16:47:43 2010 (r5342) @@ -81,14 +81,14 @@ for(i=0;i<0xff;i+=4){ if((i%16)==0){ - print_debug("\r\n"); + print_debug("\n"); print_debug_hex8(i); print_debug(": "); } print_debug_hex32(pci_read_config32(dev,i)); print_debug(" "); } - print_debug("\r\n"); + print_debug("\n"); } #endif print_debug("USB 1.1 INIT:<----------\n"); Modified: trunk/src/southbridge/sis/sis966/sis966_usb2.c ============================================================================== --- trunk/src/southbridge/sis/sis966/sis966_usb2.c Wed Mar 31 16:34:40 2010 (r5341) +++ trunk/src/southbridge/sis/sis966/sis966_usb2.c Wed Mar 31 16:47:43 2010 (r5342) @@ -108,14 +108,14 @@ for(i=0;i<0xff;i+=4){ if((i%16)==0){ - print_debug("\r\n"); + print_debug("\n"); print_debug_hex8(i); print_debug(": "); } print_debug_hex32(pci_read_config32(dev,i)); print_debug(" "); } - print_debug("\r\n"); + print_debug("\n"); } #endif print_debug("USB 2.0 INIT:<----------\n"); Modified: trunk/src/southbridge/via/vt8231/vt8231_early_serial.c ============================================================================== --- trunk/src/southbridge/via/vt8231/vt8231_early_serial.c Wed Mar 31 16:34:40 2010 (r5341) +++ trunk/src/southbridge/via/vt8231/vt8231_early_serial.c Wed Mar 31 16:47:43 2010 (r5342) @@ -39,7 +39,7 @@ if (dev == PCI_DEV_INVALID) { outb(7, 0x80); - die("Serial controller not found\r\n"); + die("Serial controller not found\n"); } /* first, you have to enable the superio and superio config. Modified: trunk/src/southbridge/via/vt8231/vt8231_early_smbus.c ============================================================================== --- trunk/src/southbridge/via/vt8231/vt8231_early_smbus.c Wed Mar 31 16:34:40 2010 (r5341) +++ trunk/src/southbridge/via/vt8231/vt8231_early_smbus.c Wed Mar 31 16:47:43 2010 (r5342) @@ -30,7 +30,7 @@ dev = pci_locate_device(PCI_ID(0x1106, 0x8235), 0); if (dev == PCI_DEV_INVALID) { - die("SMBUS controller not found\r\n"); + die("SMBUS controller not found\n"); } // set IO base address to SMBUS_IO_BASE pci_write_config32(dev, 0x90, SMBUS_IO_BASE | 1); @@ -47,9 +47,9 @@ c |= 1; pci_write_config8(dev, 4, c); print_debug_hex8(c); - print_debug(" is the comm register\r\n"); + print_debug(" is the comm register\n"); - print_debug("SMBus controller enabled\r\n"); + print_debug("SMBus controller enabled\n"); } @@ -117,7 +117,7 @@ smbus_wait_until_ready(); print_debug("After reset status "); print_debug_hex8(inb(SMBUS_IO_BASE + SMBHSTSTAT)); - print_debug("\r\n"); + print_debug("\n"); } static void smbus_print_error(unsigned char host_status_register) @@ -125,21 +125,21 @@ print_err("smbus_error: "); print_err_hex8(host_status_register); - print_err("\r\n"); + print_err("\n"); if (host_status_register & (1 << 4)) { - print_err("Interrup/SMI# was Failed Bus Transaction\r\n"); + print_err("Interrup/SMI# was Failed Bus Transaction\n"); } if (host_status_register & (1 << 3)) { - print_err("Bus Error\r\n"); + print_err("Bus Error\n"); } if (host_status_register & (1 << 2)) { - print_err("Device Error\r\n"); + print_err("Device Error\n"); } if (host_status_register & (1 << 1)) { - print_err("Interrupt/SMI# was Successful Completion\r\n"); + print_err("Interrupt/SMI# was Successful Completion\n"); } if (host_status_register & (1 << 0)) { - print_err("Host Busy\r\n"); + print_err("Host Busy\n"); } } Modified: trunk/src/southbridge/via/vt8235/vt8235_early_smbus.c ============================================================================== --- trunk/src/southbridge/via/vt8235/vt8235_early_smbus.c Wed Mar 31 16:34:40 2010 (r5341) +++ trunk/src/southbridge/via/vt8235/vt8235_early_smbus.c Wed Mar 31 16:47:43 2010 (r5342) @@ -36,7 +36,7 @@ PCI_DEVICE_ID_VIA_8235), 0); if (dev == PCI_DEV_INVALID) { - die("SMBUS controller not found\r\n"); + die("SMBUS controller not found\n"); } // set IO base address to SMBUS_IO_BASE @@ -91,7 +91,7 @@ while((c & 1) == 1) { print_debug("c is "); print_debug_hex8(c); - print_debug("\r\n"); + print_debug("\n"); c = inb(SMBUS_IO_BASE + SMBHSTSTAT); /* nop */ } @@ -110,7 +110,7 @@ smbus_wait_until_ready(); print_debug("After reset status "); print_debug_hex8( inb(SMBUS_IO_BASE + SMBHSTSTAT)); - print_debug("\r\n"); + print_debug("\n"); } @@ -137,21 +137,21 @@ print_err("smbus_error: "); print_err_hex8(host_status_register); - print_err("\r\n"); + print_err("\n"); if (host_status_register & (1 << 4)) { - print_err("Interrup/SMI# was Failed Bus Transaction\r\n"); + print_err("Interrup/SMI# was Failed Bus Transaction\n"); } if (host_status_register & (1 << 3)) { - print_err("Bus Error\r\n"); + print_err("Bus Error\n"); } if (host_status_register & (1 << 2)) { - print_err("Device Error\r\n"); + print_err("Device Error\n"); } if (host_status_register & (1 << 1)) { - print_err("Interrupt/SMI# was Successful Completion\r\n"); + print_err("Interrupt/SMI# was Successful Completion\n"); } if (host_status_register & (1 << 0)) { - print_err("Host Busy\r\n"); + print_err("Host Busy\n"); } } Modified: trunk/src/southbridge/via/vt8237r/vt8237r_early_smbus.c ============================================================================== --- trunk/src/southbridge/via/vt8237r/vt8237r_early_smbus.c Wed Mar 31 16:34:40 2010 (r5341) +++ trunk/src/southbridge/via/vt8237r/vt8237r_early_smbus.c Wed Mar 31 16:47:43 2010 (r5342) @@ -39,17 +39,17 @@ return; if (loops >= SMBUS_TIMEOUT) - print_err("SMBus timeout\r\n"); + print_err("SMBus timeout\n"); if (host_status & (1 << 4)) - print_err("Interrupt/SMI# was Failed Bus Transaction\r\n"); + print_err("Interrupt/SMI# was Failed Bus Transaction\n"); if (host_status & (1 << 3)) - print_err("Bus error\r\n"); + print_err("Bus error\n"); if (host_status & (1 << 2)) - print_err("Device error\r\n"); + print_err("Device error\n"); if (host_status & (1 << 1)) - print_debug("Interrupt/SMI# completed successfully\r\n"); + print_debug("Interrupt/SMI# completed successfully\n"); if (host_status & (1 << 0)) - print_err("Host busy\r\n"); + print_err("Host busy\n"); } /** @@ -59,7 +59,7 @@ { int loops; - PRINT_DEBUG("Waiting until SMBus ready\r\n"); + PRINT_DEBUG("Waiting until SMBus ready\n"); loops = 0; /* Yes, this is a mess, but it's the easiest way to do it. */ @@ -81,7 +81,7 @@ PRINT_DEBUG("After reset status: "); PRINT_DEBUG_HEX16(inb(SMBHSTSTAT)); - PRINT_DEBUG("\r\n"); + PRINT_DEBUG("\n"); } /** @@ -98,7 +98,7 @@ PRINT_DEBUG_HEX16(dimm); PRINT_DEBUG(" OFFSET "); PRINT_DEBUG_HEX16(offset); - PRINT_DEBUG("\r\n"); + PRINT_DEBUG("\n"); smbus_reset(); @@ -121,7 +121,7 @@ val = inb(SMBHSTDAT0); PRINT_DEBUG("Read: "); PRINT_DEBUG_HEX16(val); - PRINT_DEBUG("\r\n"); + PRINT_DEBUG("\n"); /* Probably don't have to do this, but it can't hurt. */ smbus_reset(); @@ -144,7 +144,7 @@ dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT8237S_LPC), 0); if (dev == PCI_DEV_INVALID) - die("Power management controller not found\r\n"); + die("Power management controller not found\n"); } /* @@ -189,7 +189,7 @@ ram_slots = ARRAY_SIZE(ctrl->channel0); if (!ram_slots) { - print_err("smbus_fixup() thinks there are no RAM slots!\r\n"); + print_err("smbus_fixup() thinks there are no RAM slots!\n"); return; } @@ -213,9 +213,9 @@ } if (i >= SMBUS_TIMEOUT) - print_err("SMBus timed out while warming up\r\n"); + print_err("SMBus timed out while warming up\n"); else - PRINT_DEBUG("Done\r\n"); + PRINT_DEBUG("Done\n"); } /* FIXME: Better separate the NB and SB, will be done once it works. */ @@ -310,7 +310,7 @@ dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT8237S_LPC), 0); if (dev == PCI_DEV_INVALID) - die("Power management controller not found\r\n"); + die("Power management controller not found\n"); } /* Set ACPI base address to I/O VT8237R_ACPI_IO_BASE. */ @@ -337,7 +337,7 @@ PCI_DEVICE_ID_VIA_VT8237S_LPC), 0); if (dev == PCI_DEV_INVALID) - die("SB not found\r\n"); + die("SB not found\n"); /* Put SPI base 20 d0 fe. */ tmp = pci_read_config32(dev, 0xbc); Modified: trunk/src/southbridge/via/vt82c686/vt82c686_early_serial.c ============================================================================== --- trunk/src/southbridge/via/vt82c686/vt82c686_early_serial.c Wed Mar 31 16:34:40 2010 (r5341) +++ trunk/src/southbridge/via/vt82c686/vt82c686_early_serial.c Wed Mar 31 16:47:43 2010 (r5342) @@ -65,7 +65,7 @@ if (sbdev == PCI_DEV_INVALID) { /* Serial output is not yet working at this point, but * die() emits the POST code 0xff and halts the CPU, too. */ - die("Southbridge not found.\r\n"); + die("Southbridge not found.\n"); } /* Enable Super-I/O (bit 0) and Super-I/O Configuration (bit 1). */ Modified: trunk/src/superio/ite/it8716f/superio.c ============================================================================== --- trunk/src/superio/ite/it8716f/superio.c Wed Mar 31 16:34:40 2010 (r5341) +++ trunk/src/superio/ite/it8716f/superio.c Wed Mar 31 16:47:43 2010 (r5342) @@ -72,13 +72,13 @@ /* Read out current value of FAN_CTL control register (0x14). */ value = pnp_read_index(base, 0x14); - printk(BIOS_DEBUG, "FAN_CTL: reg = 0x%04x, read value = 0x%02x\r\n", + printk(BIOS_DEBUG, "FAN_CTL: reg = 0x%04x, read value = 0x%02x\n", base + 0x14, value); /* Set FAN_CTL control register (0x14) polarity to high, and activate fans 1, 2 and 3. */ pnp_write_index(base, 0x14, value | 0x87); - printk(BIOS_DEBUG, "FAN_CTL: reg = 0x%04x, writing value = 0x%02x\r\n", + printk(BIOS_DEBUG, "FAN_CTL: reg = 0x%04x, writing value = 0x%02x\n", base + 0x14, value | 0x87); } #endif Modified: trunk/src/superio/serverengines/pilot/pilot_early_init.c ============================================================================== --- trunk/src/superio/serverengines/pilot/pilot_early_init.c Wed Mar 31 16:34:40 2010 (r5341) +++ trunk/src/superio/serverengines/pilot/pilot_early_init.c Wed Mar 31 16:47:43 2010 (r5342) @@ -33,9 +33,9 @@ print_debug("Using port: "); print_debug_hex16(port); - print_debug("\r\n"); + print_debug("\n"); pilot_disable_serial(PNP_DEV(port, 0x1)); - print_debug("disable serial 1\r\n"); + print_debug("disable serial 1\n"); /* pnp_enter_ext_func_mode(dev); Modified: trunk/src/superio/smsc/lpc47b272/superio.c ============================================================================== --- trunk/src/superio/smsc/lpc47b272/superio.c Wed Mar 31 16:34:40 2010 (r5341) +++ trunk/src/superio/smsc/lpc47b272/superio.c Wed Mar 31 16:47:43 2010 (r5342) @@ -195,7 +195,7 @@ static void dump_pnp_device(device_t dev) { int register_index; - print_debug("\r\n"); + print_debug("\n"); for(register_index = 0; register_index <= LPC47B272_MAX_CONFIG_REGISTER; register_index++) { uint8_t register_value; @@ -214,10 +214,10 @@ print_debug_char(' '); print_debug_hex8(register_value); if ((register_index & 0x0f) == 0x0f) { - print_debug("\r\n"); + print_debug("\n"); } } - print_debug("\r\n"); + print_debug("\n"); } #endif Modified: trunk/src/superio/smsc/lpc47b397/superio.c ============================================================================== --- trunk/src/superio/smsc/lpc47b397/superio.c Wed Mar 31 16:34:40 2010 (r5341) +++ trunk/src/superio/smsc/lpc47b397/superio.c Wed Mar 31 16:47:43 2010 (r5342) @@ -106,7 +106,7 @@ switch(dev->path.pnp.device) { case LPC47B397_HWM: - printk(BIOS_DEBUG, "lpc47b397 SensorBus Register Access enabled\r\n"); + printk(BIOS_DEBUG, "lpc47b397 SensorBus Register Access enabled\n"); pnp_set_logical_device(dev); enable_hwm_smbus(dev); break; Modified: trunk/src/superio/smsc/lpc47m10x/superio.c ============================================================================== --- trunk/src/superio/smsc/lpc47m10x/superio.c Wed Mar 31 16:34:40 2010 (r5341) +++ trunk/src/superio/smsc/lpc47m10x/superio.c Wed Mar 31 16:47:43 2010 (r5342) @@ -193,7 +193,7 @@ static void dump_pnp_device(device_t dev) { int register_index; - print_debug("\r\n"); + print_debug("\n"); for(register_index = 0; register_index <= LPC47M10X2_MAX_CONFIG_REGISTER; register_index++) { uint8_t register_value; @@ -212,10 +212,10 @@ print_debug_char(' '); print_debug_hex8(register_value); if ((register_index & 0x0f) == 0x0f) { - print_debug("\r\n"); + print_debug("\n"); } } - print_debug("\r\n"); + print_debug("\n"); } #endif Modified: trunk/src/superio/smsc/lpc47n217/superio.c ============================================================================== --- trunk/src/superio/smsc/lpc47n217/superio.c Wed Mar 31 16:34:40 2010 (r5341) +++ trunk/src/superio/smsc/lpc47n217/superio.c Wed Mar 31 16:47:43 2010 (r5342) @@ -361,7 +361,7 @@ static void dump_pnp_device(device_t dev) { int register_index; - print_debug("\r\n"); + print_debug("\n"); for(register_index = 0; register_index <= LPC47N217_MAX_CONFIG_REGISTER; register_index++) { uint8_t register_value; @@ -380,10 +380,10 @@ print_debug_char(' '); print_debug_hex8(register_value); if ((register_index & 0x0f) == 0x0f) { - print_debug("\r\n"); + print_debug("\n"); } } - print_debug("\r\n"); + print_debug("\n"); } #endif Modified: trunk/src/superio/winbond/w83627ehg/superio.c ============================================================================== --- trunk/src/superio/winbond/w83627ehg/superio.c Wed Mar 31 16:34:40 2010 (r5341) +++ trunk/src/superio/winbond/w83627ehg/superio.c Wed Mar 31 16:47:43 2010 (r5342) @@ -100,7 +100,7 @@ value = pnp_read_index(base, reg); value &= 0xff & (~(hwm_reg_values[i + 1])); value |= 0xff & hwm_reg_values[i + 2]; - /* printk(BIOS_DEBUG, "base = 0x%04x, reg = 0x%02x, value = 0x%02x\r\n", base, reg,value); */ + /* printk(BIOS_DEBUG, "base = 0x%04x, reg = 0x%02x, value = 0x%02x\n", base, reg,value); */ pnp_write_index(base, reg, value); } } Modified: trunk/src/superio/winbond/w83627hf/superio.c ============================================================================== --- trunk/src/superio/winbond/w83627hf/superio.c Wed Mar 31 16:34:40 2010 (r5341) +++ trunk/src/superio/winbond/w83627hf/superio.c Wed Mar 31 16:47:43 2010 (r5342) @@ -120,7 +120,7 @@ value &= 0xff & hwm_reg_values[i+1]; value |= 0xff & hwm_reg_values[i+2]; #if 0 - printk(BIOS_DEBUG, "base = 0x%04x, reg = 0x%02x, value = 0x%02x\r\n", base, reg,value); + printk(BIOS_DEBUG, "base = 0x%04x, reg = 0x%02x, value = 0x%02x\n", base, reg,value); #endif pnp_write_index(base, reg, value); }

9 years, 8 months

1
0
0 0

[commit] r5341 - in trunk/src: . arch/i386/lib console include/console mainboard/a-trend/atc-6220 mainboard/a-trend/atc-6240 mainboard/abit/be6-ii_v2_0 mainboard/advantech/pcm-5820 mainboard/amd/db...

by repository service

Author: stepan Date: Wed Mar 31 16:34:40 2010 New Revision: 5341 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5341 Log: This patch drops arch/i386/lib/console.c and arch/i386/lib/console_print.c and makes include/console/console.h and console/console.c usable both in __PRE_RAM__ and coreboot_ram stages. While debugging this, I removed an indirection from the e7520 ram init code (same as we did on a couple of other chipsets, removes some register pressure from romcc) Also, drop remainders of CONFIG_USE_INIT (except the one odd piece of dead code in cache_as_ram.inc) Then some ap_romstage.c fixes, at least the nvidia/l1_2pvv compiled for me with CONFIG_AP_CODE_IN_CAR set in Kconfig which it did not before. Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Myles Watson <mylesgw(a)gmail.com> Deleted: trunk/src/arch/i386/lib/console.c trunk/src/arch/i386/lib/console_print.c Modified: trunk/src/Kconfig trunk/src/console/Makefile.inc trunk/src/console/console.c trunk/src/include/console/console.h trunk/src/mainboard/a-trend/atc-6220/romstage.c trunk/src/mainboard/a-trend/atc-6240/romstage.c trunk/src/mainboard/abit/be6-ii_v2_0/romstage.c trunk/src/mainboard/advantech/pcm-5820/romstage.c trunk/src/mainboard/amd/db800/romstage.c trunk/src/mainboard/amd/dbm690t/romstage.c trunk/src/mainboard/amd/mahogany/romstage.c trunk/src/mainboard/amd/mahogany_fam10/romstage.c trunk/src/mainboard/amd/norwich/romstage.c trunk/src/mainboard/amd/pistachio/romstage.c trunk/src/mainboard/amd/rumba/romstage.c trunk/src/mainboard/amd/serengeti_cheetah/ap_romstage.c trunk/src/mainboard/amd/serengeti_cheetah/romstage.c trunk/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c trunk/src/mainboard/arima/hdama/romstage.c trunk/src/mainboard/artecgroup/dbe61/romstage.c trunk/src/mainboard/asi/mb_5blgp/romstage.c trunk/src/mainboard/asi/mb_5blmp/romstage.c trunk/src/mainboard/asus/a8n_e/romstage.c trunk/src/mainboard/asus/a8v-e_se/romstage.c trunk/src/mainboard/asus/m2v-mx_se/romstage.c trunk/src/mainboard/asus/mew-am/romstage.c trunk/src/mainboard/asus/mew-vm/romstage.c trunk/src/mainboard/asus/p2b-d/romstage.c trunk/src/mainboard/asus/p2b-ds/romstage.c trunk/src/mainboard/asus/p2b-f/romstage.c trunk/src/mainboard/asus/p2b-ls/romstage.c trunk/src/mainboard/asus/p2b/romstage.c trunk/src/mainboard/asus/p3b-f/romstage.c trunk/src/mainboard/axus/tc320/romstage.c trunk/src/mainboard/azza/pt-6ibd/romstage.c trunk/src/mainboard/bcom/winnet100/romstage.c trunk/src/mainboard/bcom/winnetp680/romstage.c trunk/src/mainboard/biostar/m6tba/romstage.c trunk/src/mainboard/broadcom/blast/romstage.c trunk/src/mainboard/compaq/deskpro_en_sff_p600/romstage.c trunk/src/mainboard/dell/s1850/romstage.c trunk/src/mainboard/digitallogic/adl855pc/romstage.c trunk/src/mainboard/digitallogic/msm586seg/romstage.c trunk/src/mainboard/digitallogic/msm800sev/romstage.c trunk/src/mainboard/eaglelion/5bcm/romstage.c trunk/src/mainboard/emulation/qemu-x86/romstage.c trunk/src/mainboard/gigabyte/ga-6bxc/romstage.c trunk/src/mainboard/gigabyte/ga_2761gxdk/ap_romstage.c trunk/src/mainboard/gigabyte/ga_2761gxdk/romstage.c trunk/src/mainboard/gigabyte/m57sli/ap_romstage.c trunk/src/mainboard/gigabyte/m57sli/romstage.c trunk/src/mainboard/hp/dl145_g3/romstage.c trunk/src/mainboard/hp/e_vectra_p2706t/romstage.c trunk/src/mainboard/ibm/e325/romstage.c trunk/src/mainboard/ibm/e326/romstage.c trunk/src/mainboard/iei/juki-511p/romstage.c trunk/src/mainboard/iei/nova4899r/romstage.c trunk/src/mainboard/iei/pcisa-lx-800-r10/romstage.c trunk/src/mainboard/intel/d945gclf/romstage.c trunk/src/mainboard/intel/eagleheights/romstage.c trunk/src/mainboard/intel/jarrell/romstage.c trunk/src/mainboard/intel/mtarvon/romstage.c trunk/src/mainboard/intel/truxton/romstage.c trunk/src/mainboard/intel/xe7501devkit/romstage.c trunk/src/mainboard/iwill/dk8_htx/romstage.c trunk/src/mainboard/iwill/dk8s2/romstage.c trunk/src/mainboard/iwill/dk8x/romstage.c trunk/src/mainboard/jetway/j7f24/romstage.c trunk/src/mainboard/kontron/986lcd-m/romstage.c trunk/src/mainboard/kontron/kt690/romstage.c trunk/src/mainboard/lippert/frontrunner/romstage.c trunk/src/mainboard/lippert/roadrunner-lx/romstage.c trunk/src/mainboard/lippert/spacerunner-lx/romstage.c trunk/src/mainboard/mitac/6513wu/romstage.c trunk/src/mainboard/msi/ms6119/romstage.c trunk/src/mainboard/msi/ms6147/romstage.c trunk/src/mainboard/msi/ms6156/romstage.c trunk/src/mainboard/msi/ms6178/romstage.c trunk/src/mainboard/msi/ms7135/romstage.c trunk/src/mainboard/msi/ms7260/ap_romstage.c trunk/src/mainboard/msi/ms7260/romstage.c trunk/src/mainboard/msi/ms9185/romstage.c trunk/src/mainboard/msi/ms9282/romstage.c trunk/src/mainboard/msi/ms9652_fam10/romstage.c trunk/src/mainboard/nec/powermate2000/romstage.c trunk/src/mainboard/newisys/khepri/romstage.c trunk/src/mainboard/nvidia/l1_2pvv/ap_romstage.c trunk/src/mainboard/nvidia/l1_2pvv/romstage.c trunk/src/mainboard/olpc/btest/romstage.c trunk/src/mainboard/olpc/rev_a/romstage.c trunk/src/mainboard/pcengines/alix1c/romstage.c trunk/src/mainboard/rca/rm4100/romstage.c trunk/src/mainboard/roda/rk886ex/romstage.c trunk/src/mainboard/soyo/sy-6ba-plus-iii/romstage.c trunk/src/mainboard/sunw/ultra40/romstage.c trunk/src/mainboard/supermicro/h8dme/ap_romstage.c trunk/src/mainboard/supermicro/h8dme/romstage.c trunk/src/mainboard/supermicro/h8dmr/ap_romstage.c trunk/src/mainboard/supermicro/h8dmr/romstage.c trunk/src/mainboard/supermicro/h8dmr_fam10/romstage.c trunk/src/mainboard/supermicro/h8qme_fam10/romstage.c trunk/src/mainboard/supermicro/x6dai_g/romstage.c trunk/src/mainboard/supermicro/x6dhe_g/romstage.c trunk/src/mainboard/supermicro/x6dhe_g2/romstage.c trunk/src/mainboard/supermicro/x6dhr_ig/romstage.c trunk/src/mainboard/supermicro/x6dhr_ig2/romstage.c trunk/src/mainboard/technexion/tim5690/romstage.c trunk/src/mainboard/technexion/tim8690/romstage.c trunk/src/mainboard/technologic/ts5300/romstage.c trunk/src/mainboard/televideo/tc7020/romstage.c trunk/src/mainboard/thomson/ip1000/romstage.c trunk/src/mainboard/tyan/s1846/romstage.c trunk/src/mainboard/tyan/s2735/romstage.c trunk/src/mainboard/tyan/s2850/romstage.c trunk/src/mainboard/tyan/s2875/romstage.c trunk/src/mainboard/tyan/s2880/romstage.c trunk/src/mainboard/tyan/s2881/romstage.c trunk/src/mainboard/tyan/s2882/romstage.c trunk/src/mainboard/tyan/s2885/romstage.c trunk/src/mainboard/tyan/s2891/romstage.c trunk/src/mainboard/tyan/s2892/romstage.c trunk/src/mainboard/tyan/s2895/romstage.c trunk/src/mainboard/tyan/s2912/ap_romstage.c trunk/src/mainboard/tyan/s2912/romstage.c trunk/src/mainboard/tyan/s2912_fam10/romstage.c trunk/src/mainboard/tyan/s4880/romstage.c trunk/src/mainboard/tyan/s4882/romstage.c trunk/src/mainboard/via/epia-cn/romstage.c trunk/src/mainboard/via/epia-m/romstage.c trunk/src/mainboard/via/epia-m700/romstage.c trunk/src/mainboard/via/epia-n/romstage.c trunk/src/mainboard/via/epia/romstage.c trunk/src/mainboard/via/pc2500e/romstage.c trunk/src/mainboard/via/vt8454c/romstage.c trunk/src/mainboard/winent/pl6064/romstage.c trunk/src/northbridge/amd/amdk8/raminit_test.c trunk/src/northbridge/intel/e7520/raminit.c trunk/src/northbridge/intel/e7520/raminit.h trunk/src/northbridge/via/vx800/examples/romstage.c Modified: trunk/src/Kconfig ============================================================================== --- trunk/src/Kconfig Wed Mar 31 02:06:12 2010 (r5340) +++ trunk/src/Kconfig Wed Mar 31 16:34:40 2010 (r5341) @@ -796,10 +796,6 @@ bool default n -config USE_INIT - bool - default n - config ENABLE_APIC_EXT_ID bool default n Modified: trunk/src/console/Makefile.inc ============================================================================== --- trunk/src/console/Makefile.inc Wed Mar 31 02:06:12 2010 (r5340) +++ trunk/src/console/Makefile.inc Wed Mar 31 16:34:40 2010 (r5341) @@ -14,3 +14,5 @@ driver-$(CONFIG_CONSOLE_BTEXT) += btext_console.o driver-$(CONFIG_CONSOLE_BTEXT) += font-8x16.o driver-$(CONFIG_CONSOLE_LOGBUF) += logbuf_console.o + +$(obj)/console/console.o : $(obj)/build.h Modified: trunk/src/console/console.c ============================================================================== --- trunk/src/console/console.c Wed Mar 31 02:06:12 2010 (r5340) +++ trunk/src/console/console.c Wed Mar 31 16:34:40 2010 (r5341) @@ -2,8 +2,12 @@ * Bootstrap code for the INTEL */ -#include <arch/io.h> #include <console/console.h> +#include <build.h> +#include <arch/hlt.h> + +#ifndef __PRE_RAM__ +#include <arch/io.h> #include <string.h> #include <pc80/mc146818rtc.h> @@ -86,6 +90,42 @@ void __attribute__((noreturn)) die(const char *msg) { printk(BIOS_EMERG, "%s", msg); - post_code(0xff); - while (1); /* Halt */ + //post_code(0xff); + for (;;) + hlt(); /* Halt */ +} + +#else + +void console_init(void) +{ + static const char console_test[] = + "\r\n\r\ncoreboot-" + COREBOOT_VERSION + COREBOOT_EXTRA_VERSION + " " + COREBOOT_BUILD + " starting...\r\n"; + print_info(console_test); +} + +void post_code(u8 value) +{ +#if !defined(CONFIG_NO_POST) || CONFIG_NO_POST==0 +#if CONFIG_SERIAL_POST==1 + print_emerg("POST: 0x"); + print_emerg_hex8(value); + print_emerg("\r\n"); +#endif + outb(value, 0x80); +#endif } + +void die(const char *str) +{ + print_emerg(str); + do { + hlt(); + } while(1); +} +#endif Modified: trunk/src/include/console/console.h ============================================================================== --- trunk/src/include/console/console.h Wed Mar 31 02:06:12 2010 (r5340) +++ trunk/src/include/console/console.h Wed Mar 31 16:34:40 2010 (r5341) @@ -33,6 +33,7 @@ extern int console_loglevel; #endif /* !__PRE_RAM__ */ +#ifndef __ROMCC__ int do_printk(int msg_level, const char *fmt, ...) __attribute__((format(printf, 2, 3))); #undef WE_CLEANED_UP_ALL_SIDE_EFFECTS @@ -40,6 +41,10 @@ * disabling cache as ram for a maximum console log level of 6 and above while * it worked fine without. In order to catch such issues reliably we are * always doing a function call to do_printk with the full number of arguments. + * Our favorite reason to do it this way was: + * disable_car(); + * printk(BIOS_DEBUG, "CAR disabled\n"); // oops, garbage stack pointer + * move_stack(); * This slightly increases the code size and some unprinted strings will end * up in the final coreboot binary (most of them compressed). If you want to * avoid this, do a @@ -66,35 +71,35 @@ } while(0) #endif -#define print_emerg(STR) printk(BIOS_EMERG, "%s", (STR)) -#define print_alert(STR) printk(BIOS_ALERT, "%s", (STR)) -#define print_crit(STR) printk(BIOS_CRIT, "%s", (STR)) -#define print_err(STR) printk(BIOS_ERR, "%s", (STR)) -#define print_warning(STR) printk(BIOS_WARNING,"%s", (STR)) -#define print_notice(STR) printk(BIOS_NOTICE, "%s", (STR)) -#define print_info(STR) printk(BIOS_INFO, "%s", (STR)) -#define print_debug(STR) printk(BIOS_DEBUG, "%s", (STR)) -#define print_spew(STR) printk(BIOS_SPEW, "%s", (STR)) - -#define print_emerg_char(CH) printk(BIOS_EMERG, "%c", (CH)) -#define print_alert_char(CH) printk(BIOS_ALERT, "%c", (CH)) -#define print_crit_char(CH) printk(BIOS_CRIT, "%c", (CH)) -#define print_err_char(CH) printk(BIOS_ERR, "%c", (CH)) -#define print_warning_char(CH) printk(BIOS_WARNING,"%c", (CH)) -#define print_notice_char(CH) printk(BIOS_NOTICE, "%c", (CH)) -#define print_info_char(CH) printk(BIOS_INFO, "%c", (CH)) -#define print_debug_char(CH) printk(BIOS_DEBUG, "%c", (CH)) -#define print_spew_char(CH) printk(BIOS_SPEW, "%c", (CH)) - -#define print_emerg_hex8(HEX) printk(BIOS_EMERG, "%02x", (HEX)) -#define print_alert_hex8(HEX) printk(BIOS_ALERT, "%02x", (HEX)) -#define print_crit_hex8(HEX) printk(BIOS_CRIT, "%02x", (HEX)) -#define print_err_hex8(HEX) printk(BIOS_ERR, "%02x", (HEX)) -#define print_warning_hex8(HEX) printk(BIOS_WARNING,"%02x", (HEX)) -#define print_notice_hex8(HEX) printk(BIOS_NOTICE, "%02x", (HEX)) -#define print_info_hex8(HEX) printk(BIOS_INFO, "%02x", (HEX)) -#define print_debug_hex8(HEX) printk(BIOS_DEBUG, "%02x", (HEX)) -#define print_spew_hex8(HEX) printk(BIOS_SPEW, "%02x", (HEX)) +#define print_emerg(STR) printk(BIOS_EMERG, "%s", (STR)) +#define print_alert(STR) printk(BIOS_ALERT, "%s", (STR)) +#define print_crit(STR) printk(BIOS_CRIT, "%s", (STR)) +#define print_err(STR) printk(BIOS_ERR, "%s", (STR)) +#define print_warning(STR) printk(BIOS_WARNING,"%s", (STR)) +#define print_notice(STR) printk(BIOS_NOTICE, "%s", (STR)) +#define print_info(STR) printk(BIOS_INFO, "%s", (STR)) +#define print_debug(STR) printk(BIOS_DEBUG, "%s", (STR)) +#define print_spew(STR) printk(BIOS_SPEW, "%s", (STR)) + +#define print_emerg_char(CH) printk(BIOS_EMERG, "%c", (CH)) +#define print_alert_char(CH) printk(BIOS_ALERT, "%c", (CH)) +#define print_crit_char(CH) printk(BIOS_CRIT, "%c", (CH)) +#define print_err_char(CH) printk(BIOS_ERR, "%c", (CH)) +#define print_warning_char(CH) printk(BIOS_WARNING,"%c", (CH)) +#define print_notice_char(CH) printk(BIOS_NOTICE, "%c", (CH)) +#define print_info_char(CH) printk(BIOS_INFO, "%c", (CH)) +#define print_debug_char(CH) printk(BIOS_DEBUG, "%c", (CH)) +#define print_spew_char(CH) printk(BIOS_SPEW, "%c", (CH)) + +#define print_emerg_hex8(HEX) printk(BIOS_EMERG, "%02x", (HEX)) +#define print_alert_hex8(HEX) printk(BIOS_ALERT, "%02x", (HEX)) +#define print_crit_hex8(HEX) printk(BIOS_CRIT, "%02x", (HEX)) +#define print_err_hex8(HEX) printk(BIOS_ERR, "%02x", (HEX)) +#define print_warning_hex8(HEX) printk(BIOS_WARNING,"%02x", (HEX)) +#define print_notice_hex8(HEX) printk(BIOS_NOTICE, "%02x", (HEX)) +#define print_info_hex8(HEX) printk(BIOS_INFO, "%02x", (HEX)) +#define print_debug_hex8(HEX) printk(BIOS_DEBUG, "%02x", (HEX)) +#define print_spew_hex8(HEX) printk(BIOS_SPEW, "%02x", (HEX)) #define print_emerg_hex16(HEX) printk(BIOS_EMERG, "%04x", (HEX)) #define print_alert_hex16(HEX) printk(BIOS_ALERT, "%04x", (HEX)) @@ -115,5 +120,182 @@ #define print_info_hex32(HEX) printk(BIOS_INFO, "%08x", (HEX)) #define print_debug_hex32(HEX) printk(BIOS_DEBUG, "%08x", (HEX)) #define print_spew_hex32(HEX) printk(BIOS_SPEW, "%08x", (HEX)) +#else +/* __ROMCC__ */ +static void __console_tx_byte(unsigned char byte) +{ + uart_tx_byte(byte); +} + +static void __console_tx_nibble(unsigned nibble) +{ + unsigned char digit; + digit = nibble + '0'; + if (digit > '9') { + digit += 39; + } + __console_tx_byte(digit); +} + +static void __console_tx_char(int loglevel, unsigned char byte) +{ + if (ASM_CONSOLE_LOGLEVEL >= loglevel) { + uart_tx_byte(byte); + } +} + +static void __console_tx_hex8(int loglevel, unsigned char value) +{ + if (ASM_CONSOLE_LOGLEVEL >= loglevel) { + __console_tx_nibble((value >> 4U) & 0x0fU); + __console_tx_nibble(value & 0x0fU); + } +} + +static void __console_tx_hex16(int loglevel, unsigned short value) +{ + if (ASM_CONSOLE_LOGLEVEL >= loglevel) { + __console_tx_nibble((value >> 12U) & 0x0fU); + __console_tx_nibble((value >> 8U) & 0x0fU); + __console_tx_nibble((value >> 4U) & 0x0fU); + __console_tx_nibble(value & 0x0fU); + } +} + +static void __console_tx_hex32(int loglevel, unsigned int value) +{ + if (ASM_CONSOLE_LOGLEVEL >= loglevel) { + __console_tx_nibble((value >> 28U) & 0x0fU); + __console_tx_nibble((value >> 24U) & 0x0fU); + __console_tx_nibble((value >> 20U) & 0x0fU); + __console_tx_nibble((value >> 16U) & 0x0fU); + __console_tx_nibble((value >> 12U) & 0x0fU); + __console_tx_nibble((value >> 8U) & 0x0fU); + __console_tx_nibble((value >> 4U) & 0x0fU); + __console_tx_nibble(value & 0x0fU); + } +} + +static void __console_tx_string(int loglevel, const char *str) +{ + if (ASM_CONSOLE_LOGLEVEL >= loglevel) { + unsigned char ch; + while((ch = *str++) != '\0') { + if (ch == '\n') + __console_tx_byte('\r'); + __console_tx_byte(ch); + } + } +} + +#define FUNCTIONS_FOR_PRINT +#ifdef FUNCTIONS_FOR_PRINT +static void print_emerg_char(unsigned char byte) { __console_tx_char(BIOS_EMERG, byte); } +static void print_emerg_hex8(unsigned char value){ __console_tx_hex8(BIOS_EMERG, value); } +static void print_emerg_hex16(unsigned short value){ __console_tx_hex16(BIOS_EMERG, value); } +static void print_emerg_hex32(unsigned int value) { __console_tx_hex32(BIOS_EMERG, value); } +static void print_emerg(const char *str) { __console_tx_string(BIOS_EMERG, str); } + +static void print_alert_char(unsigned char byte) { __console_tx_char(BIOS_ALERT, byte); } +static void print_alert_hex8(unsigned char value) { __console_tx_hex8(BIOS_ALERT, value); } +static void print_alert_hex16(unsigned short value){ __console_tx_hex16(BIOS_ALERT, value); } +static void print_alert_hex32(unsigned int value) { __console_tx_hex32(BIOS_ALERT, value); } +static void print_alert(const char *str) { __console_tx_string(BIOS_ALERT, str); } + +static void print_crit_char(unsigned char byte) { __console_tx_char(BIOS_CRIT, byte); } +static void print_crit_hex8(unsigned char value) { __console_tx_hex8(BIOS_CRIT, value); } +static void print_crit_hex16(unsigned short value){ __console_tx_hex16(BIOS_CRIT, value); } +static void print_crit_hex32(unsigned int value) { __console_tx_hex32(BIOS_CRIT, value); } +static void print_crit(const char *str) { __console_tx_string(BIOS_CRIT, str); } + +static void print_err_char(unsigned char byte) { __console_tx_char(BIOS_ERR, byte); } +static void print_err_hex8(unsigned char value) { __console_tx_hex8(BIOS_ERR, value); } +static void print_err_hex16(unsigned short value){ __console_tx_hex16(BIOS_ERR, value); } +static void print_err_hex32(unsigned int value) { __console_tx_hex32(BIOS_ERR, value); } +static void print_err(const char *str) { __console_tx_string(BIOS_ERR, str); } + +static void print_warning_char(unsigned char byte) { __console_tx_char(BIOS_WARNING, byte); } +static void print_warning_hex8(unsigned char value) { __console_tx_hex8(BIOS_WARNING, value); } +static void print_warning_hex16(unsigned short value){ __console_tx_hex16(BIOS_WARNING, value); } +static void print_warning_hex32(unsigned int value) { __console_tx_hex32(BIOS_WARNING, value); } +static void print_warning(const char *str) { __console_tx_string(BIOS_WARNING, str); } + +static void print_notice_char(unsigned char byte) { __console_tx_char(BIOS_NOTICE, byte); } +static void print_notice_hex8(unsigned char value) { __console_tx_hex8(BIOS_NOTICE, value); } +static void print_notice_hex16(unsigned short value){ __console_tx_hex16(BIOS_NOTICE, value); } +static void print_notice_hex32(unsigned int value) { __console_tx_hex32(BIOS_NOTICE, value); } +static void print_notice(const char *str) { __console_tx_string(BIOS_NOTICE, str); } + +static void print_info_char(unsigned char byte) { __console_tx_char(BIOS_INFO, byte); } +static void print_info_hex8(unsigned char value) { __console_tx_hex8(BIOS_INFO, value); } +static void print_info_hex16(unsigned short value){ __console_tx_hex16(BIOS_INFO, value); } +static void print_info_hex32(unsigned int value) { __console_tx_hex32(BIOS_INFO, value); } +static void print_info(const char *str) { __console_tx_string(BIOS_INFO, str); } + +static void print_debug_char(unsigned char byte) { __console_tx_char(BIOS_DEBUG, byte); } +static void print_debug_hex8(unsigned char value) { __console_tx_hex8(BIOS_DEBUG, value); } +static void print_debug_hex16(unsigned short value){ __console_tx_hex16(BIOS_DEBUG, value); } +static void print_debug_hex32(unsigned int value) { __console_tx_hex32(BIOS_DEBUG, value); } +static void print_debug(const char *str) { __console_tx_string(BIOS_DEBUG, str); } + +static void print_spew_char(unsigned char byte) { __console_tx_char(BIOS_SPEW, byte); } +static void print_spew_hex8(unsigned char value) { __console_tx_hex8(BIOS_SPEW, value); } +static void print_spew_hex16(unsigned short value){ __console_tx_hex16(BIOS_SPEW, value); } +static void print_spew_hex32(unsigned int value) { __console_tx_hex32(BIOS_SPEW, value); } +static void print_spew(const char *str) { __console_tx_string(BIOS_SPEW, str); } + +#else +#define print_emerg(STR) __console_tx_string(BIOS_EMERG, STR) +#define print_alert(STR) __console_tx_string(BIOS_ALERT, STR) +#define print_crit(STR) __console_tx_string(BIOS_CRIT, STR) +#define print_err(STR) __console_tx_string(BIOS_ERR, STR) +#define print_warning(STR) __console_tx_string(BIOS_WARNING, STR) +#define print_notice(STR) __console_tx_string(BIOS_NOTICE, STR) +#define print_info(STR) __console_tx_string(BIOS_INFO, STR) +#define print_debug(STR) __console_tx_string(BIOS_DEBUG, STR) +#define print_spew(STR) __console_tx_string(BIOS_SPEW, STR) + +#define print_emerg_char(CH) __console_tx_char(BIOS_EMERG, CH) +#define print_alert_char(CH) __console_tx_char(BIOS_ALERT, CH) +#define print_crit_char(CH) __console_tx_char(BIOS_CRIT, CH) +#define print_err_char(CH) __console_tx_char(BIOS_ERR, CH) +#define print_warning_char(CH) __console_tx_char(BIOS_WARNING, CH) +#define print_notice_char(CH) __console_tx_char(BIOS_NOTICE, CH) +#define print_info_char(CH) __console_tx_char(BIOS_INFO, CH) +#define print_debug_char(CH) __console_tx_char(BIOS_DEBUG, CH) +#define print_spew_char(CH) __console_tx_char(BIOS_SPEW, CH) + +#define print_emerg_hex8(HEX) __console_tx_hex8(BIOS_EMERG, HEX) +#define print_alert_hex8(HEX) __console_tx_hex8(BIOS_ALERT, HEX) +#define print_crit_hex8(HEX) __console_tx_hex8(BIOS_CRIT, HEX) +#define print_err_hex8(HEX) __console_tx_hex8(BIOS_ERR, HEX) +#define print_warning_hex8(HEX) __console_tx_hex8(BIOS_WARNING, HEX) +#define print_notice_hex8(HEX) __console_tx_hex8(BIOS_NOTICE, HEX) +#define print_info_hex8(HEX) __console_tx_hex8(BIOS_INFO, HEX) +#define print_debug_hex8(HEX) __console_tx_hex8(BIOS_DEBUG, HEX) +#define print_spew_hex8(HEX) __console_tx_hex8(BIOS_SPEW, HEX) + +#define print_emerg_hex16(HEX) __console_tx_hex16(BIOS_EMERG, HEX) +#define print_alert_hex16(HEX) __console_tx_hex16(BIOS_ALERT, HEX) +#define print_crit_hex16(HEX) __console_tx_hex16(BIOS_CRIT, HEX) +#define print_err_hex16(HEX) __console_tx_hex16(BIOS_ERR, HEX) +#define print_warning_hex16(HEX) __console_tx_hex16(BIOS_WARNING, HEX) +#define print_notice_hex16(HEX) __console_tx_hex16(BIOS_NOTICE, HEX) +#define print_info_hex16(HEX) __console_tx_hex16(BIOS_INFO, HEX) +#define print_debug_hex16(HEX) __console_tx_hex16(BIOS_DEBUG, HEX) +#define print_spew_hex16(HEX) __console_tx_hex16(BIOS_SPEW, HEX) + +#define print_emerg_hex32(HEX) __console_tx_hex32(BIOS_EMERG, HEX) +#define print_alert_hex32(HEX) __console_tx_hex32(BIOS_ALERT, HEX) +#define print_crit_hex32(HEX) __console_tx_hex32(BIOS_CRIT, HEX) +#define print_err_hex32(HEX) __console_tx_hex32(BIOS_ERR, HEX) +#define print_warning_hex32(HEX) __console_tx_hex32(BIOS_WARNING, HEX) +#define print_notice_hex32(HEX) __console_tx_hex32(BIOS_NOTICE, HEX) +#define print_info_hex32(HEX) __console_tx_hex32(BIOS_INFO, HEX) +#define print_debug_hex32(HEX) __console_tx_hex32(BIOS_DEBUG, HEX) +#define print_spew_hex32(HEX) __console_tx_hex32(BIOS_SPEW, HEX) +#endif + +#endif #endif /* CONSOLE_CONSOLE_H_ */ Modified: trunk/src/mainboard/a-trend/atc-6220/romstage.c ============================================================================== --- trunk/src/mainboard/a-trend/atc-6220/romstage.c Wed Mar 31 02:06:12 2010 (r5340) +++ trunk/src/mainboard/a-trend/atc-6220/romstage.c Wed Mar 31 16:34:40 2010 (r5341) @@ -26,7 +26,7 @@ #include <arch/hlt.h> #include <stdlib.h> #include "pc80/serial.c" -#include "arch/i386/lib/console.c" +#include "console/console.c" #include "lib/ramtest.c" #include "southbridge/intel/i82371eb/i82371eb_enable_rom.c" #include "southbridge/intel/i82371eb/i82371eb_early_smbus.c" Modified: trunk/src/mainboard/a-trend/atc-6240/romstage.c ============================================================================== --- trunk/src/mainboard/a-trend/atc-6240/romstage.c Wed Mar 31 02:06:12 2010 (r5340) +++ trunk/src/mainboard/a-trend/atc-6240/romstage.c Wed Mar 31 16:34:40 2010 (r5341) @@ -26,7 +26,7 @@ #include <arch/romcc_io.h> #include <arch/hlt.h> #include "pc80/serial.c" -#include "arch/i386/lib/console.c" +#include "console/console.c" #include "lib/ramtest.c" #include "southbridge/intel/i82371eb/i82371eb_enable_rom.c" #include "southbridge/intel/i82371eb/i82371eb_early_smbus.c" Modified: trunk/src/mainboard/abit/be6-ii_v2_0/romstage.c ============================================================================== --- trunk/src/mainboard/abit/be6-ii_v2_0/romstage.c Wed Mar 31 02:06:12 2010 (r5340) +++ trunk/src/mainboard/abit/be6-ii_v2_0/romstage.c Wed Mar 31 16:34:40 2010 (r5341) @@ -26,7 +26,7 @@ #include <arch/romcc_io.h> #include <arch/hlt.h> #include "pc80/serial.c" -#include "arch/i386/lib/console.c" +#include "console/console.c" #include "lib/ramtest.c" #include "southbridge/intel/i82371eb/i82371eb_enable_rom.c" #include "southbridge/intel/i82371eb/i82371eb_early_smbus.c" Modified: trunk/src/mainboard/advantech/pcm-5820/romstage.c ============================================================================== --- trunk/src/mainboard/advantech/pcm-5820/romstage.c Wed Mar 31 02:06:12 2010 (r5340) +++ trunk/src/mainboard/advantech/pcm-5820/romstage.c Wed Mar 31 16:34:40 2010 (r5341) @@ -24,7 +24,7 @@ #include <arch/romcc_io.h> #include <arch/hlt.h> #include "pc80/serial.c" -#include "arch/i386/lib/console.c" +#include "console/console.c" #include "lib/ramtest.c" #include "northbridge/amd/gx1/raminit.c" #include "cpu/x86/bist.h" Modified: trunk/src/mainboard/amd/db800/romstage.c ============================================================================== --- trunk/src/mainboard/amd/db800/romstage.c Wed Mar 31 02:06:12 2010 (r5340) +++ trunk/src/mainboard/amd/db800/romstage.c Wed Mar 31 16:34:40 2010 (r5341) @@ -24,7 +24,7 @@ #include <device/pnp_def.h> #include <arch/hlt.h> #include "pc80/serial.c" -#include "arch/i386/lib/console.c" +#include "console/console.c" #include "lib/ramtest.c" #include "cpu/x86/bist.h" #include "cpu/x86/msr.h" Modified: trunk/src/mainboard/amd/dbm690t/romstage.c ============================================================================== --- trunk/src/mainboard/amd/dbm690t/romstage.c Wed Mar 31 02:06:12 2010 (r5340) +++ trunk/src/mainboard/amd/dbm690t/romstage.c Wed Mar 31 16:34:40 2010 (r5341) @@ -43,7 +43,7 @@ #include "option_table.h" #include "pc80/mc146818rtc_early.c" #include "pc80/serial.c" -#include "arch/i386/lib/console.c" +#include "console/console.c" #define post_code(x) outb(x, 0x80) Modified: trunk/src/mainboard/amd/mahogany/romstage.c ============================================================================== --- trunk/src/mainboard/amd/mahogany/romstage.c Wed Mar 31 02:06:12 2010 (r5340) +++ trunk/src/mainboard/amd/mahogany/romstage.c Wed Mar 31 16:34:40 2010 (r5341) @@ -43,7 +43,7 @@ #include "option_table.h" #include "pc80/mc146818rtc_early.c" #include "pc80/serial.c" -#include "arch/i386/lib/console.c" +#include "console/console.c" #define post_code(x) outb(x, 0x80) Modified: trunk/src/mainboard/amd/mahogany_fam10/romstage.c ============================================================================== --- trunk/src/mainboard/amd/mahogany_fam10/romstage.c Wed Mar 31 02:06:12 2010 (r5340) +++ trunk/src/mainboard/amd/mahogany_fam10/romstage.c Wed Mar 31 16:34:40 2010 (r5341) @@ -47,7 +47,7 @@ #include <cpu/x86/lapic.h> #include "option_table.h" #include "pc80/mc146818rtc_early.c" -#include "arch/i386/lib/console.c" +#include "console/console.c" #include "pc80/serial.c" #include "lib/ramtest.c" #include <cpu/amd/model_10xxx_rev.h> Modified: trunk/src/mainboard/amd/norwich/romstage.c ============================================================================== --- trunk/src/mainboard/amd/norwich/romstage.c Wed Mar 31 02:06:12 2010 (r5340) +++ trunk/src/mainboard/amd/norwich/romstage.c Wed Mar 31 16:34:40 2010 (r5341) @@ -24,7 +24,7 @@ #include <device/pnp_def.h> #include <arch/hlt.h> #include "pc80/serial.c" -#include "arch/i386/lib/console.c" +#include "console/console.c" #include "lib/ramtest.c" #include "cpu/x86/bist.h" #include "cpu/x86/msr.h" Modified: trunk/src/mainboard/amd/pistachio/romstage.c ============================================================================== --- trunk/src/mainboard/amd/pistachio/romstage.c Wed Mar 31 02:06:12 2010 (r5340) +++ trunk/src/mainboard/amd/pistachio/romstage.c Wed Mar 31 16:34:40 2010 (r5341) @@ -37,7 +37,7 @@ #include "option_table.h" #include "pc80/mc146818rtc_early.c" #include "pc80/serial.c" -#include "arch/i386/lib/console.c" +#include "console/console.c" #define post_code(x) outb(x, 0x80) Modified: trunk/src/mainboard/amd/rumba/romstage.c ============================================================================== --- trunk/src/mainboard/amd/rumba/romstage.c Wed Mar 31 02:06:12 2010 (r5340) +++ trunk/src/mainboard/amd/rumba/romstage.c Wed Mar 31 16:34:40 2010 (r5341) @@ -5,7 +5,7 @@ #include <arch/romcc_io.h> #include <arch/hlt.h> #include "pc80/serial.c" -#include "arch/i386/lib/console.c" +#include "console/console.c" #include "lib/ramtest.c" #include "superio/winbond/w83627hf/w83627hf_early_serial.c" #include "cpu/x86/bist.h" Modified: trunk/src/mainboard/amd/serengeti_cheetah/ap_romstage.c ============================================================================== --- trunk/src/mainboard/amd/serengeti_cheetah/ap_romstage.c Wed Mar 31 02:06:12 2010 (r5340) +++ trunk/src/mainboard/amd/serengeti_cheetah/ap_romstage.c Wed Mar 31 16:34:40 2010 (r5341) @@ -23,25 +23,10 @@ #include "pc80/serial.c" #include "./arch/i386/lib/printk_init.c" -#if CONFIG_USE_INIT == 0 - #include "lib/memcpy.c" -#endif - -#include "arch/i386/lib/console.c" +#include "console/console.c" #include "lib/uart8250.c" #include "console/vtxprintf.c" -#if 0 -static void post_code(uint8_t value) { -#if 1 - int i; - for(i=0;i<0x80000;i++) { - outb(value, 0x80); - } -#endif -} -#endif - #include <cpu/amd/model_fxx_rev.h> #include "northbridge/amd/amdk8/raminit.h" #include "cpu/amd/model_fxx/apic_timer.c" Modified: trunk/src/mainboard/amd/serengeti_cheetah/romstage.c ============================================================================== --- trunk/src/mainboard/amd/serengeti_cheetah/romstage.c Wed Mar 31 02:06:12 2010 (r5340) +++ trunk/src/mainboard/amd/serengeti_cheetah/romstage.c Wed Mar 31 16:34:40 2010 (r5341) @@ -40,7 +40,7 @@ } #endif #include "pc80/serial.c" -#include "arch/i386/lib/console.c" +#include "console/console.c" #include <cpu/amd/model_fxx_rev.h> #include "southbridge/amd/amd8111/amd8111_early_smbus.c" #include "northbridge/amd/amdk8/raminit.h" Modified: trunk/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c ============================================================================== --- trunk/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c Wed Mar 31 02:06:12 2010 (r5340) +++ trunk/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c Wed Mar 31 16:34:40 2010 (r5341) @@ -47,7 +47,7 @@ #include <cpu/x86/lapic.h> #include "option_table.h" #include "pc80/mc146818rtc_early.c" -#include "arch/i386/lib/console.c" +#include "console/console.c" #include "pc80/serial.c" #include "lib/ramtest.c" #include <cpu/amd/model_10xxx_rev.h> Modified: trunk/src/mainboard/arima/hdama/romstage.c ============================================================================== --- trunk/src/mainboard/arima/hdama/romstage.c Wed Mar 31 02:06:12 2010 (r5340) +++ trunk/src/mainboard/arima/hdama/romstage.c Wed Mar 31 16:34:40 2010 (r5341) @@ -8,7 +8,7 @@ #include "option_table.h" #include "pc80/mc146818rtc_early.c" #include "pc80/serial.c" -#include "arch/i386/lib/console.c" +#include "console/console.c" #include "lib/ramtest.c" #include <cpu/amd/model_fxx_rev.h> Modified: trunk/src/mainboard/artecgroup/dbe61/romstage.c ============================================================================== --- trunk/src/mainboard/artecgroup/dbe61/romstage.c Wed Mar 31 02:06:12 2010 (r5340) +++ trunk/src/mainboard/artecgroup/dbe61/romstage.c Wed Mar 31 16:34:40 2010 (r5341) @@ -26,7 +26,7 @@ #include <arch/hlt.h> #include <stdlib.h> #include "pc80/serial.c" -#include "arch/i386/lib/console.c" +#include "console/console.c" #include "lib/ramtest.c" #include "cpu/x86/bist.h" #include "cpu/x86/msr.h" Modified: trunk/src/mainboard/asi/mb_5blgp/romstage.c ============================================================================== --- trunk/src/mainboard/asi/mb_5blgp/romstage.c Wed Mar 31 02:06:12 2010 (r5340) +++ trunk/src/mainboard/asi/mb_5blgp/romstage.c Wed Mar 31 16:34:40 2010 (r5341) @@ -24,7 +24,7 @@ #include <arch/romcc_io.h> #include <arch/hlt.h> #include "pc80/serial.c" -#include "arch/i386/lib/console.c" +#include "console/console.c" #include "lib/ramtest.c" #include "northbridge/amd/gx1/raminit.c" #include "cpu/x86/bist.h" Modified: trunk/src/mainboard/asi/mb_5blmp/romstage.c ============================================================================== --- trunk/src/mainboard/asi/mb_5blmp/romstage.c Wed Mar 31 02:06:12 2010 (r5340) +++ trunk/src/mainboard/asi/mb_5blmp/romstage.c Wed Mar 31 16:34:40 2010 (r5341) @@ -25,7 +25,7 @@ #include <arch/romcc_io.h> #include <arch/hlt.h> #include "pc80/serial.c" -#include "arch/i386/lib/console.c" +#include "console/console.c" #include "lib/ramtest.c" #include "northbridge/amd/gx1/raminit.c" #include "superio/nsc/pc87351/pc87351_early_serial.c" Modified: trunk/src/mainboard/asus/a8n_e/romstage.c ============================================================================== --- trunk/src/mainboard/asus/a8n_e/romstage.c Wed Mar 31 02:06:12 2010 (r5340) +++ trunk/src/mainboard/asus/a8n_e/romstage.c Wed Mar 31 16:34:40 2010 (r5341) @@ -49,7 +49,7 @@ #include <cpu/amd/model_fxx_rev.h> #include "pc80/serial.c" -#include "arch/i386/lib/console.c" +#include "console/console.c" #include "lib/ramtest.c" #include "northbridge/amd/amdk8/incoherent_ht.c" #include "southbridge/nvidia/ck804/ck804_early_smbus.c" Modified: trunk/src/mainboard/asus/a8v-e_se/romstage.c ============================================================================== --- trunk/src/mainboard/asus/a8v-e_se/romstage.c Wed Mar 31 02:06:12 2010 (r5340) +++ trunk/src/mainboard/asus/a8v-e_se/romstage.c Wed Mar 31 16:34:40 2010 (r5341) @@ -47,7 +47,7 @@ #include "option_table.h" #include "pc80/mc146818rtc_early.c" #include "pc80/serial.c" -#include "arch/i386/lib/console.c" +#include "console/console.c" #include <cpu/amd/model_fxx_rev.h> #include "northbridge/amd/amdk8/raminit.h" #include "cpu/amd/model_fxx/apic_timer.c" Modified: trunk/src/mainboard/asus/m2v-mx_se/romstage.c ============================================================================== --- trunk/src/mainboard/asus/m2v-mx_se/romstage.c Wed Mar 31 02:06:12 2010 (r5340) +++ trunk/src/mainboard/asus/m2v-mx_se/romstage.c Wed Mar 31 16:34:40 2010 (r5341) @@ -52,7 +52,7 @@ #include "option_table.h" #include "pc80/mc146818rtc_early.c" #include "pc80/serial.c" -#include "arch/i386/lib/console.c" +#include "console/console.c" #include <cpu/amd/model_fxx_rev.h> #include "northbridge/amd/amdk8/raminit.h" #include "cpu/amd/model_fxx/apic_timer.c" Modified: trunk/src/mainboard/asus/mew-am/romstage.c ============================================================================== --- trunk/src/mainboard/asus/mew-am/romstage.c Wed Mar 31 02:06:12 2010 (r5340) +++ trunk/src/mainboard/asus/mew-am/romstage.c Wed Mar 31 16:34:40 2010 (r5341) @@ -26,7 +26,7 @@ #include <arch/romcc_io.h> #include <arch/hlt.h> #include "pc80/serial.c" -#include "arch/i386/lib/console.c" +#include "console/console.c" #include "lib/ramtest.c" #include "southbridge/intel/i82801ax/i82801ax_early_smbus.c" #include "northbridge/intel/i82810/raminit.h" Modified: trunk/src/mainboard/asus/mew-vm/romstage.c ============================================================================== --- trunk/src/mainboard/asus/mew-vm/romstage.c Wed Mar 31 02:06:12 2010 (r5340) +++ trunk/src/mainboard/asus/mew-vm/romstage.c Wed Mar 31 16:34:40 2010 (r5341) @@ -26,7 +26,7 @@ #include <arch/hlt.h> #include <stdlib.h> #include "pc80/serial.c" -#include "arch/i386/lib/console.c" +#include "console/console.c" #include "lib/ramtest.c" #include "superio/smsc/lpc47b272/lpc47b272_early_serial.c" #include "northbridge/intel/i82810/raminit.h" Modified: trunk/src/mainboard/asus/p2b-d/romstage.c ============================================================================== --- trunk/src/mainboard/asus/p2b-d/romstage.c Wed Mar 31 02:06:12 2010 (r5340) +++ trunk/src/mainboard/asus/p2b-d/romstage.c Wed Mar 31 16:34:40 2010 (r5341) @@ -27,7 +27,7 @@ #include <stdlib.h> #include <cpu/x86/lapic.h> #include "pc80/serial.c" -#include "arch/i386/lib/console.c" +#include "console/console.c" #include "lib/ramtest.c" #include "southbridge/intel/i82371eb/i82371eb_enable_rom.c" #include "southbridge/intel/i82371eb/i82371eb_early_smbus.c" Modified: trunk/src/mainboard/asus/p2b-ds/romstage.c ============================================================================== --- trunk/src/mainboard/asus/p2b-ds/romstage.c Wed Mar 31 02:06:12 2010 (r5340) +++ trunk/src/mainboard/asus/p2b-ds/romstage.c Wed Mar 31 16:34:40 2010 (r5341) @@ -27,7 +27,7 @@ #include <stdlib.h> #include <cpu/x86/lapic.h> #include "pc80/serial.c" -#include "arch/i386/lib/console.c" +#include "console/console.c" #include "lib/ramtest.c" #include "southbridge/intel/i82371eb/i82371eb_enable_rom.c" #include "southbridge/intel/i82371eb/i82371eb_early_smbus.c" Modified: trunk/src/mainboard/asus/p2b-f/romstage.c ============================================================================== --- trunk/src/mainboard/asus/p2b-f/romstage.c Wed Mar 31 02:06:12 2010 (r5340) +++ trunk/src/mainboard/asus/p2b-f/romstage.c Wed Mar 31 16:34:40 2010 (r5341) @@ -26,7 +26,7 @@ #include <arch/hlt.h> #include <stdlib.h> #include "pc80/serial.c" -#include "arch/i386/lib/console.c" +#include "console/console.c" #include "lib/ramtest.c" #include "southbridge/intel/i82371eb/i82371eb_enable_rom.c" #include "southbridge/intel/i82371eb/i82371eb_early_smbus.c" Modified: trunk/src/mainboard/asus/p2b-ls/romstage.c ============================================================================== --- trunk/src/mainboard/asus/p2b-ls/romstage.c Wed Mar 31 02:06:12 2010 (r5340) +++ trunk/src/mainboard/asus/p2b-ls/romstage.c Wed Mar 31 16:34:40 2010 (r5341) @@ -26,7 +26,7 @@ #include <arch/hlt.h> #include <stdlib.h> #include "pc80/serial.c" -#include "arch/i386/lib/console.c" +#include "console/console.c" #include "lib/ramtest.c" #include "southbridge/intel/i82371eb/i82371eb_enable_rom.c" #include "southbridge/intel/i82371eb/i82371eb_early_smbus.c" Modified: trunk/src/mainboard/asus/p2b/romstage.c ============================================================================== --- trunk/src/mainboard/asus/p2b/romstage.c Wed Mar 31 02:06:12 2010 (r5340) +++ trunk/src/mainboard/asus/p2b/romstage.c Wed Mar 31 16:34:40 2010 (r5341) @@ -26,7 +26,7 @@ #include <arch/hlt.h> #include <stdlib.h> #include "pc80/serial.c" -#include "arch/i386/lib/console.c" +#include "console/console.c" #include "lib/ramtest.c" #include "southbridge/intel/i82371eb/i82371eb_enable_rom.c" #include "southbridge/intel/i82371eb/i82371eb_early_smbus.c" Modified: trunk/src/mainboard/asus/p3b-f/romstage.c ============================================================================== --- trunk/src/mainboard/asus/p3b-f/romstage.c Wed Mar 31 02:06:12 2010 (r5340) +++ trunk/src/mainboard/asus/p3b-f/romstage.c Wed Mar 31 16:34:40 2010 (r5341) @@ -26,7 +26,7 @@ #include <arch/hlt.h> #include <stdlib.h> #include "pc80/serial.c" -#include "arch/i386/lib/console.c" +#include "console/console.c" #include "lib/ramtest.c" #include "southbridge/intel/i82371eb/i82371eb_enable_rom.c" #include "southbridge/intel/i82371eb/i82371eb_early_smbus.c" Modified: trunk/src/mainboard/axus/tc320/romstage.c ============================================================================== --- trunk/src/mainboard/axus/tc320/romstage.c Wed Mar 31 02:06:12 2010 (r5340) +++ trunk/src/mainboard/axus/tc320/romstage.c Wed Mar 31 16:34:40 2010 (r5341) @@ -25,7 +25,7 @@ #include <arch/romcc_io.h> #include <arch/hlt.h> #include "pc80/serial.c" -#include "arch/i386/lib/console.c" +#include "console/console.c" #include "lib/ramtest.c" #include "northbridge/amd/gx1/raminit.c" #include "superio/nsc/pc97317/pc97317_early_serial.c" Modified: trunk/src/mainboard/azza/pt-6ibd/romstage.c ============================================================================== --- trunk/src/mainboard/azza/pt-6ibd/romstage.c Wed Mar 31 02:06:12 2010 (r5340) +++ trunk/src/mainboard/azza/pt-6ibd/romstage.c Wed Mar 31 16:34:40 2010 (r5341) @@ -26,7 +26,7 @@ #include <arch/hlt.h> #include <stdlib.h> #include "pc80/serial.c" -#include "arch/i386/lib/console.c" +#include "console/console.c" #include "lib/ramtest.c" #include "southbridge/intel/i82371eb/i82371eb_enable_rom.c" #include "southbridge/intel/i82371eb/i82371eb_early_smbus.c" Modified: trunk/src/mainboard/bcom/winnet100/romstage.c ============================================================================== --- trunk/src/mainboard/bcom/winnet100/romstage.c Wed Mar 31 02:06:12 2010 (r5340) +++ trunk/src/mainboard/bcom/winnet100/romstage.c Wed Mar 31 16:34:40 2010 (r5341) @@ -25,7 +25,7 @@ #include <arch/romcc_io.h> #include <arch/hlt.h> #include "pc80/serial.c" -#include "arch/i386/lib/console.c" +#include "console/console.c" #include "lib/ramtest.c" #include "northbridge/amd/gx1/raminit.c" #include "superio/nsc/pc97317/pc97317_early_serial.c" Modified: trunk/src/mainboard/bcom/winnetp680/romstage.c ============================================================================== --- trunk/src/mainboard/bcom/winnetp680/romstage.c Wed Mar 31 02:06:12 2010 (r5340) +++ trunk/src/mainboard/bcom/winnetp680/romstage.c Wed Mar 31 16:34:40 2010 (r5341) @@ -27,7 +27,7 @@ #include <arch/romcc_io.h> #include <arch/hlt.h> #include "pc80/serial.c" -#include "arch/i386/lib/console.c" +#include "console/console.c" #include "lib/ramtest.c" #include "northbridge/via/cn700/raminit.h" #include "cpu/x86/mtrr/earlymtrr.c" Modified: trunk/src/mainboard/biostar/m6tba/romstage.c ============================================================================== --- trunk/src/mainboard/biostar/m6tba/romstage.c Wed Mar 31 02:06:12 2010 (r5340) +++ trunk/src/mainboard/biostar/m6tba/romstage.c Wed Mar 31 16:34:40 2010 (r5341) @@ -26,7 +26,7 @@ #include <arch/hlt.h> #include <stdlib.h> #include "pc80/serial.c" -#include "arch/i386/lib/console.c" +#include "console/console.c" #include "lib/ramtest.c" #include "southbridge/intel/i82371eb/i82371eb_enable_rom.c" #include "southbridge/intel/i82371eb/i82371eb_early_smbus.c" Modified: trunk/src/mainboard/broadcom/blast/romstage.c ============================================================================== --- trunk/src/mainboard/broadcom/blast/romstage.c Wed Mar 31 02:06:12 2010 (r5340) +++ trunk/src/mainboard/broadcom/blast/romstage.c Wed Mar 31 16:34:40 2010 (r5341) @@ -14,7 +14,7 @@ #include "option_table.h" #include "pc80/mc146818rtc_early.c" #include "pc80/serial.c" -#include "arch/i386/lib/console.c" +#include "console/console.c" #include "lib/ramtest.c" #if 0 Modified: trunk/src/mainboard/compaq/deskpro_en_sff_p600/romstage.c ============================================================================== --- trunk/src/mainboard/compaq/deskpro_en_sff_p600/romstage.c Wed Mar 31 02:06:12 2010 (r5340) +++ trunk/src/mainboard/compaq/deskpro_en_sff_p600/romstage.c Wed Mar 31 16:34:40 2010 (r5341) @@ -26,7 +26,7 @@ #include <arch/hlt.h> #include <stdlib.h> #include "pc80/serial.c" -#include "arch/i386/lib/console.c" +#include "console/console.c" #include "lib/ramtest.c" #include "southbridge/intel/i82371eb/i82371eb_enable_rom.c" #include "southbridge/intel/i82371eb/i82371eb_early_smbus.c" Modified: trunk/src/mainboard/dell/s1850/romstage.c ============================================================================== --- trunk/src/mainboard/dell/s1850/romstage.c Wed Mar 31 02:06:12 2010 (r5340) +++ trunk/src/mainboard/dell/s1850/romstage.c Wed Mar 31 16:34:40 2010 (r5341) @@ -8,7 +8,7 @@ #include "option_table.h" #include "pc80/mc146818rtc_early.c" #include "pc80/serial.c" -#include "arch/i386/lib/console.c" +#include "console/console.c" #include "lib/ramtest.c" #include "southbridge/intel/i82801ex/i82801ex_early_smbus.c" #include "northbridge/intel/e7520/raminit.h" @@ -170,10 +170,12 @@ static const struct mem_controller mch[] = { { .node_id = 0, + /* .f0 = PCI_DEV(0, 0x00, 0), .f1 = PCI_DEV(0, 0x00, 1), .f2 = PCI_DEV(0, 0x00, 2), .f3 = PCI_DEV(0, 0x00, 3), + */ /* the wiring on this part is really messed up */ /* this is my best guess so far */ .channel0 = {(0xa<<3)|0, (0xa<<3)|1, (0xa<<3)|2, (0xa<<3)|3, }, Modified: trunk/src/mainboard/digitallogic/adl855pc/romstage.c ============================================================================== --- trunk/src/mainboard/digitallogic/adl855pc/romstage.c Wed Mar 31 02:06:12 2010 (r5340) +++ trunk/src/mainboard/digitallogic/adl855pc/romstage.c Wed Mar 31 16:34:40 2010 (r5341) @@ -12,7 +12,7 @@ #include <stdlib.h> #include "pc80/mc146818rtc_early.c" #include "pc80/serial.c" -#include "arch/i386/lib/console.c" +#include "console/console.c" #include "lib/ramtest.c" #include "southbridge/intel/i82801dx/i82801dx.h" #include "southbridge/intel/i82801dx/i82801dx_early_smbus.c" Modified: trunk/src/mainboard/digitallogic/msm586seg/romstage.c ============================================================================== --- trunk/src/mainboard/digitallogic/msm586seg/romstage.c Wed Mar 31 02:06:12 2010 (r5340) +++ trunk/src/mainboard/digitallogic/msm586seg/romstage.c Wed Mar 31 16:34:40 2010 (r5341) @@ -7,7 +7,7 @@ #include <arch/hlt.h> #include "pc80/mc146818rtc_early.c" #include "pc80/serial.c" -#include "arch/i386/lib/console.c" +#include "console/console.c" #include "lib/ramtest.c" #include "cpu/x86/bist.h" //#include "lib/delay.c" Modified: trunk/src/mainboard/digitallogic/msm800sev/romstage.c ============================================================================== --- trunk/src/mainboard/digitallogic/msm800sev/romstage.c Wed Mar 31 02:06:12 2010 (r5340) +++ trunk/src/mainboard/digitallogic/msm800sev/romstage.c Wed Mar 31 16:34:40 2010 (r5341) @@ -5,7 +5,7 @@ #include <arch/romcc_io.h> #include <arch/hlt.h> #include "pc80/serial.c" -#include "arch/i386/lib/console.c" +#include "console/console.c" #include "lib/ramtest.c" #include "cpu/x86/bist.h" #include "cpu/x86/msr.h" Modified: trunk/src/mainboard/eaglelion/5bcm/romstage.c ============================================================================== --- trunk/src/mainboard/eaglelion/5bcm/romstage.c Wed Mar 31 02:06:12 2010 (r5340) +++ trunk/src/mainboard/eaglelion/5bcm/romstage.c Wed Mar 31 16:34:40 2010 (r5341) @@ -6,7 +6,7 @@ #include <arch/hlt.h> #include <stdlib.h> #include "pc80/serial.c" -#include "arch/i386/lib/console.c" +#include "console/console.c" #include "lib/ramtest.c" //#include "southbridge/intel/i440bx/i440bx_early_smbus.c" #include "superio/nsc/pc97317/pc97317_early_serial.c" Modified: trunk/src/mainboard/emulation/qemu-x86/romstage.c ============================================================================== --- trunk/src/mainboard/emulation/qemu-x86/romstage.c Wed Mar 31 02:06:12 2010 (r5340) +++ trunk/src/mainboard/emulation/qemu-x86/romstage.c Wed Mar 31 16:34:40 2010 (r5341) @@ -8,7 +8,7 @@ #include "option_table.h" #include "pc80/mc146818rtc_early.c" #include "pc80/serial.c" -#include "arch/i386/lib/console.c" +#include "console/console.c" #include "pc80/udelay_io.c" #include "lib/delay.c" #include "cpu/x86/lapic/boot_cpu.c" Modified: trunk/src/mainboard/gigabyte/ga-6bxc/romstage.c ============================================================================== --- trunk/src/mainboard/gigabyte/ga-6bxc/romstage.c Wed Mar 31 02:06:12 2010 (r5340) +++ trunk/src/mainboard/gigabyte/ga-6bxc/romstage.c Wed Mar 31 16:34:40 2010 (r5341) @@ -26,7 +26,7 @@ #include <arch/hlt.h> #include <stdlib.h> #include "pc80/serial.c" -#include "arch/i386/lib/console.c" +#include "console/console.c" #include "lib/ramtest.c" #include "southbridge/intel/i82371eb/i82371eb_enable_rom.c" #include "southbridge/intel/i82371eb/i82371eb_early_smbus.c" Modified: trunk/src/mainboard/gigabyte/ga_2761gxdk/ap_romstage.c ============================================================================== --- trunk/src/mainboard/gigabyte/ga_2761gxdk/ap_romstage.c Wed Mar 31 02:06:12 2010 (r5340) +++ trunk/src/mainboard/gigabyte/ga_2761gxdk/ap_romstage.c Wed Mar 31 16:34:40 2010 (r5341) @@ -45,22 +45,10 @@ #include "pc80/mc146818rtc_early.c" #include "pc80/serial.c" -#if CONFIG_USE_INIT == 0 - #include "lib/memcpy.c" -#endif - -#include "arch/i386/lib/console.c" - -#if 0 -static void post_code(uint8_t value) { -#if 1 - int i; - for(i=0;i<0x80000;i++) { - outb(value, 0x80); - } -#endif -} -#endif +#include "lib/uart8250.c" +#include "arch/i386/lib/printk_init.c" +#include "console/vtxprintf.c" +#include "console/console.c" #include <cpu/amd/model_fxx_rev.h> #include "northbridge/amd/amdk8/raminit.h" Modified: trunk/src/mainboard/gigabyte/ga_2761gxdk/romstage.c ============================================================================== --- trunk/src/mainboard/gigabyte/ga_2761gxdk/romstage.c Wed Mar 31 02:06:12 2010 (r5340) +++ trunk/src/mainboard/gigabyte/ga_2761gxdk/romstage.c Wed Mar 31 16:34:40 2010 (r5341) @@ -54,7 +54,7 @@ #include "pc80/mc146818rtc_early.c" #include "pc80/serial.c" -#include "arch/i386/lib/console.c" +#include "console/console.c" #if CONFIG_USBDEBUG_DIRECT #include "southbridge/sis/sis966/sis966_enable_usbdebug_direct.c" #include "pc80/usbdebug_direct_serial.c" Modified: trunk/src/mainboard/gigabyte/m57sli/ap_romstage.c ============================================================================== --- trunk/src/mainboard/gigabyte/m57sli/ap_romstage.c Wed Mar 31 02:06:12 2010 (r5340) +++ trunk/src/mainboard/gigabyte/m57sli/ap_romstage.c Wed Mar 31 16:34:40 2010 (r5341) @@ -43,22 +43,10 @@ #include "pc80/mc146818rtc_early.c" #include "pc80/serial.c" -#if CONFIG_USE_INIT == 0 - #include "lib/memcpy.c" -#endif - -#include "arch/i386/lib/console.c" - -#if 0 -static void post_code(uint8_t value) { -#if 1 - int i; - for(i=0;i<0x80000;i++) { - outb(value, 0x80); - } -#endif -} -#endif +#include "lib/uart8250.c" +#include "arch/i386/lib/printk_init.c" +#include "console/vtxprintf.c" +#include "console/console.c" #include <cpu/amd/model_fxx_rev.h> #include "northbridge/amd/amdk8/raminit.h" Modified: trunk/src/mainboard/gigabyte/m57sli/romstage.c ============================================================================== --- trunk/src/mainboard/gigabyte/m57sli/romstage.c Wed Mar 31 02:06:12 2010 (r5340) +++ trunk/src/mainboard/gigabyte/m57sli/romstage.c Wed Mar 31 16:34:40 2010 (r5341) @@ -52,7 +52,7 @@ #include "pc80/mc146818rtc_early.c" #include "pc80/serial.c" -#include "arch/i386/lib/console.c" +#include "console/console.c" #if CONFIG_USBDEBUG_DIRECT #include "southbridge/nvidia/mcp55/mcp55_enable_usbdebug_direct.c" #include "pc80/usbdebug_direct_serial.c" Modified: trunk/src/mainboard/hp/dl145_g3/romstage.c ============================================================================== --- trunk/src/mainboard/hp/dl145_g3/romstage.c Wed Mar 31 02:06:12 2010 (r5340) +++ trunk/src/mainboard/hp/dl145_g3/romstage.c Wed Mar 31 16:34:40 2010 (r5341) @@ -58,7 +58,7 @@ #include "pc80/mc146818rtc_early.c" #include "pc80/serial.c" -#include "arch/i386/lib/console.c" +#include "console/console.c" #include "lib/ramtest.c" #include <cpu/amd/model_fxx_rev.h> Modified: trunk/src/mainboard/hp/e_vectra_p2706t/romstage.c ============================================================================== --- trunk/src/mainboard/hp/e_vectra_p2706t/romstage.c Wed Mar 31 02:06:12 2010 (r5340) +++ trunk/src/mainboard/hp/e_vectra_p2706t/romstage.c Wed Mar 31 16:34:40 2010 (r5341) @@ -26,7 +26,7 @@ #include <arch/hlt.h> #include <stdlib.h> #include "pc80/serial.c" -#include "arch/i386/lib/console.c" +#include "console/console.c" #include "lib/ramtest.c" /* TODO: It's a PC87364 actually! */ #include "superio/nsc/pc87360/pc87360_early_serial.c" Modified: trunk/src/mainboard/ibm/e325/romstage.c ============================================================================== --- trunk/src/mainboard/ibm/e325/romstage.c Wed Mar 31 02:06:12 2010 (r5340) +++ trunk/src/mainboard/ibm/e325/romstage.c Wed Mar 31 16:34:40 2010 (r5341) @@ -10,7 +10,7 @@ #include "option_table.h" #include "pc80/mc146818rtc_early.c" #include "pc80/serial.c" -#include "arch/i386/lib/console.c" +#include "console/console.c" #include "lib/ramtest.c" #include <cpu/amd/model_fxx_rev.h> Modified: trunk/src/mainboard/ibm/e326/romstage.c ============================================================================== --- trunk/src/mainboard/ibm/e326/romstage.c Wed Mar 31 02:06:12 2010 (r5340) +++ trunk/src/mainboard/ibm/e326/romstage.c Wed Mar 31 16:34:40 2010 (r5341) @@ -10,7 +10,7 @@ #include "option_table.h" #include "pc80/mc146818rtc_early.c" #include "pc80/serial.c" -#include "arch/i386/lib/console.c" +#include "console/console.c" #include "lib/ramtest.c" #include <cpu/amd/model_fxx_rev.h> Modified: trunk/src/mainboard/iei/juki-511p/romstage.c ============================================================================== --- trunk/src/mainboard/iei/juki-511p/romstage.c Wed Mar 31 02:06:12 2010 (r5340) +++ trunk/src/mainboard/iei/juki-511p/romstage.c Wed Mar 31 16:34:40 2010 (r5341) @@ -25,7 +25,7 @@ #include <arch/romcc_io.h> #include <arch/hlt.h> #include "pc80/serial.c" -#include "arch/i386/lib/console.c" +#include "console/console.c" #include "lib/ramtest.c" #include "superio/winbond/w83977f/w83977f_early_serial.c" #include "southbridge/amd/cs5530/cs5530_enable_rom.c" Modified: trunk/src/mainboard/iei/nova4899r/romstage.c ============================================================================== --- trunk/src/mainboard/iei/nova4899r/romstage.c Wed Mar 31 02:06:12 2010 (r5340) +++ trunk/src/mainboard/iei/nova4899r/romstage.c Wed Mar 31 16:34:40 2010 (r5341) @@ -25,7 +25,7 @@ #include <arch/romcc_io.h> #include <arch/hlt.h> #include "pc80/serial.c" -#include "arch/i386/lib/console.c" +#include "console/console.c" #include "lib/ramtest.c" #include "superio/winbond/w83977tf/w83977tf_early_serial.c" #include "southbridge/amd/cs5530/cs5530_enable_rom.c" Modified: trunk/src/mainboard/iei/pcisa-lx-800-r10/romstage.c ============================================================================== --- trunk/src/mainboard/iei/pcisa-lx-800-r10/romstage.c Wed Mar 31 02:06:12 2010 (r5340) +++ trunk/src/mainboard/iei/pcisa-lx-800-r10/romstage.c Wed Mar 31 16:34:40 2010 (r5341) @@ -24,7 +24,7 @@ #include <device/pnp_def.h> #include <arch/hlt.h> #include "pc80/serial.c" -#include "arch/i386/lib/console.c" +#include "console/console.c" #include "lib/ramtest.c" #include "cpu/x86/bist.h" #include "cpu/x86/msr.h" Modified: trunk/src/mainboard/intel/d945gclf/romstage.c ============================================================================== --- trunk/src/mainboard/intel/d945gclf/romstage.c Wed Mar 31 02:06:12 2010 (r5340) +++ trunk/src/mainboard/intel/d945gclf/romstage.c Wed Mar 31 16:34:40 2010 (r5341) @@ -38,7 +38,7 @@ #include <console/console.h> #include "pc80/serial.c" -#include "arch/i386/lib/console.c" +#include "console/console.c" #include <cpu/x86/bist.h> #if CONFIG_USBDEBUG_DIRECT Modified: trunk/src/mainboard/intel/eagleheights/romstage.c ============================================================================== --- trunk/src/mainboard/intel/eagleheights/romstage.c Wed Mar 31 02:06:12 2010 (r5340) +++ trunk/src/mainboard/intel/eagleheights/romstage.c Wed Mar 31 16:34:40 2010 (r5341) @@ -33,7 +33,7 @@ #include "pc80/mc146818rtc_early.c" #include "pc80/serial.c" -#include "arch/i386/lib/console.c" +#include "console/console.c" #include <cpu/x86/bist.h> #include "lib/ramtest.c" Modified: trunk/src/mainboard/intel/jarrell/romstage.c ============================================================================== --- trunk/src/mainboard/intel/jarrell/romstage.c Wed Mar 31 02:06:12 2010 (r5340) +++ trunk/src/mainboard/intel/jarrell/romstage.c Wed Mar 31 16:34:40 2010 (r5341) @@ -8,7 +8,7 @@ #include "option_table.h" #include "pc80/mc146818rtc_early.c" #include "pc80/serial.c" -#include "arch/i386/lib/console.c" +#include "console/console.c" #include "lib/ramtest.c" #include "southbridge/intel/i82801ex/i82801ex_early_smbus.c" #include "northbridge/intel/e7520/raminit.h" @@ -60,10 +60,12 @@ static const struct mem_controller mch[] = { { .node_id = 0, + /* .f0 = PCI_DEV(0, 0x00, 0), .f1 = PCI_DEV(0, 0x00, 1), .f2 = PCI_DEV(0, 0x00, 2), .f3 = PCI_DEV(0, 0x00, 3), + */ .channel0 = { (0xa<<3)|2, (0xa<<3)|1, (0xa<<3)|0, 0 }, .channel1 = { (0xa<<3)|6, (0xa<<3)|5, (0xa<<3)|4, 0 }, } Modified: trunk/src/mainboard/intel/mtarvon/romstage.c ============================================================================== --- trunk/src/mainboard/intel/mtarvon/romstage.c Wed Mar 31 02:06:12 2010 (r5340) +++ trunk/src/mainboard/intel/mtarvon/romstage.c Wed Mar 31 16:34:40 2010 (r5341) @@ -28,7 +28,7 @@ #include <cpu/x86/lapic.h> #include "pc80/mc146818rtc_early.c" #include "pc80/serial.c" -#include "arch/i386/lib/console.c" +#include "console/console.c" #include "lib/ramtest.c" #include "southbridge/intel/i3100/i3100_early_smbus.c" #include "southbridge/intel/i3100/i3100_early_lpc.c" Modified: trunk/src/mainboard/intel/truxton/romstage.c ============================================================================== --- trunk/src/mainboard/intel/truxton/romstage.c Wed Mar 31 02:06:12 2010 (r5340) +++ trunk/src/mainboard/intel/truxton/romstage.c Wed Mar 31 16:34:40 2010 (r5341) @@ -29,7 +29,7 @@ #include "pc80/mc146818rtc_early.c" #include "pc80/serial.c" #include "pc80/udelay_io.c" -#include "arch/i386/lib/console.c" +#include "console/console.c" #include "lib/ramtest.c" #include "southbridge/intel/i3100/i3100_early_smbus.c" #include "southbridge/intel/i3100/i3100_early_lpc.c" Modified: trunk/src/mainboard/intel/xe7501devkit/romstage.c ============================================================================== --- trunk/src/mainboard/intel/xe7501devkit/romstage.c Wed Mar 31 02:06:12 2010 (r5340) +++ trunk/src/mainboard/intel/xe7501devkit/romstage.c Wed Mar 31 16:34:40 2010 (r5341) @@ -9,7 +9,7 @@ #include "option_table.h" #include "pc80/mc146818rtc_early.c" #include "pc80/serial.c" -#include "arch/i386/lib/console.c" +#include "console/console.c" #include "lib/ramtest.c" #include "southbridge/intel/i82801cx/i82801cx_early_smbus.c" #include "northbridge/intel/e7501/raminit.h" Modified: trunk/src/mainboard/iwill/dk8_htx/romstage.c ============================================================================== --- trunk/src/mainboard/iwill/dk8_htx/romstage.c Wed Mar 31 02:06:12 2010 (r5340) +++ trunk/src/mainboard/iwill/dk8_htx/romstage.c Wed Mar 31 16:34:40 2010 (r5341) @@ -30,7 +30,7 @@ #include "pc80/mc146818rtc_early.c" #include "pc80/serial.c" -#include "arch/i386/lib/console.c" +#include "console/console.c" #include <cpu/amd/model_fxx_rev.h> #include "southbridge/amd/amd8111/amd8111_early_smbus.c" #include "northbridge/amd/amdk8/raminit.h" Modified: trunk/src/mainboard/iwill/dk8s2/romstage.c ============================================================================== --- trunk/src/mainboard/iwill/dk8s2/romstage.c Wed Mar 31 02:06:12 2010 (r5340) +++ trunk/src/mainboard/iwill/dk8s2/romstage.c Wed Mar 31 16:34:40 2010 (r5341) @@ -30,7 +30,7 @@ #include "pc80/mc146818rtc_early.c" #include "pc80/serial.c" -#include "arch/i386/lib/console.c" +#include "console/console.c" #include <cpu/amd/model_fxx_rev.h> #include "southbridge/amd/amd8111/amd8111_early_smbus.c" #include "northbridge/amd/amdk8/raminit.h" Modified: trunk/src/mainboard/iwill/dk8x/romstage.c ============================================================================== --- trunk/src/mainboard/iwill/dk8x/romstage.c Wed Mar 31 02:06:12 2010 (r5340) +++ trunk/src/mainboard/iwill/dk8x/romstage.c Wed Mar 31 16:34:40 2010 (r5341) @@ -30,7 +30,7 @@ #include "pc80/mc146818rtc_early.c" #include "pc80/serial.c" -#include "arch/i386/lib/console.c" +#include "console/console.c" #include <cpu/amd/model_fxx_rev.h> #include "southbridge/amd/amd8111/amd8111_early_smbus.c" #include "northbridge/amd/amdk8/raminit.h" Modified: trunk/src/mainboard/jetway/j7f24/romstage.c ============================================================================== --- trunk/src/mainboard/jetway/j7f24/romstage.c Wed Mar 31 02:06:12 2010 (r5340) +++ trunk/src/mainboard/jetway/j7f24/romstage.c Wed Mar 31 16:34:40 2010 (r5341) @@ -27,7 +27,7 @@ #include <arch/romcc_io.h> #include <arch/hlt.h> #include "pc80/serial.c" -#include "arch/i386/lib/console.c" +#include "console/console.c" #include "lib/ramtest.c" #include "northbridge/via/cn700/raminit.h" #include "cpu/x86/mtrr/earlymtrr.c" Modified: trunk/src/mainboard/kontron/986lcd-m/romstage.c ============================================================================== --- trunk/src/mainboard/kontron/986lcd-m/romstage.c Wed Mar 31 02:06:12 2010 (r5340) +++ trunk/src/mainboard/kontron/986lcd-m/romstage.c Wed Mar 31 16:34:40 2010 (r5341) @@ -47,7 +47,7 @@ #include <console/console.h> #include "pc80/serial.c" -#include "arch/i386/lib/console.c" +#include "console/console.c" #include <cpu/x86/bist.h> #if CONFIG_USBDEBUG_DIRECT Modified: trunk/src/mainboard/kontron/kt690/romstage.c ============================================================================== --- trunk/src/mainboard/kontron/kt690/romstage.c Wed Mar 31 02:06:12 2010 (r5340) +++ trunk/src/mainboard/kontron/kt690/romstage.c Wed Mar 31 16:34:40 2010 (r5341) @@ -44,7 +44,7 @@ #include "option_table.h" #include "pc80/mc146818rtc_early.c" #include "pc80/serial.c" -#include "arch/i386/lib/console.c" +#include "console/console.c" #define post_code(x) outb(x, 0x80) Modified: trunk/src/mainboard/lippert/frontrunner/romstage.c ============================================================================== --- trunk/src/mainboard/lippert/frontrunner/romstage.c Wed Mar 31 02:06:12 2010 (r5340) +++ trunk/src/mainboard/lippert/frontrunner/romstage.c Wed Mar 31 16:34:40 2010 (r5341) @@ -5,7 +5,7 @@ #include <arch/romcc_io.h> #include <arch/hlt.h> #include "pc80/serial.c" -#include "arch/i386/lib/console.c" +#include "console/console.c" #include "lib/ramtest.c" #include "superio/winbond/w83627hf/w83627hf_early_serial.c" #include "cpu/x86/bist.h" Modified: trunk/src/mainboard/lippert/roadrunner-lx/romstage.c ============================================================================== --- trunk/src/mainboard/lippert/roadrunner-lx/romstage.c Wed Mar 31 02:06:12 2010 (r5340) +++ trunk/src/mainboard/lippert/roadrunner-lx/romstage.c Wed Mar 31 16:34:40 2010 (r5341) @@ -28,7 +28,7 @@ #include <device/pnp_def.h> #include <arch/hlt.h> #include "pc80/serial.c" -#include "arch/i386/lib/console.c" +#include "console/console.c" #include "lib/ramtest.c" #include "cpu/x86/bist.h" #include "cpu/x86/msr.h" Modified: trunk/src/mainboard/lippert/spacerunner-lx/romstage.c ============================================================================== --- trunk/src/mainboard/lippert/spacerunner-lx/romstage.c Wed Mar 31 02:06:12 2010 (r5340) +++ trunk/src/mainboard/lippert/spacerunner-lx/romstage.c Wed Mar 31 16:34:40 2010 (r5341) @@ -29,7 +29,7 @@ #include <device/pnp_def.h> #include <arch/hlt.h> #include "pc80/serial.c" -#include "arch/i386/lib/console.c" +#include "console/console.c" #include "lib/ramtest.c" #include "cpu/x86/bist.h" #include "cpu/x86/msr.h" Modified: trunk/src/mainboard/mitac/6513wu/romstage.c ============================================================================== --- trunk/src/mainboard/mitac/6513wu/romstage.c Wed Mar 31 02:06:12 2010 (r5340) +++ trunk/src/mainboard/mitac/6513wu/romstage.c Wed Mar 31 16:34:40 2010 (r5341) @@ -26,7 +26,7 @@ #include <arch/romcc_io.h> #include <arch/hlt.h> #include "pc80/serial.c" -#include "arch/i386/lib/console.c" +#include "console/console.c" #include "lib/ramtest.c" #include "southbridge/intel/i82801ax/i82801ax_early_smbus.c" #include "northbridge/intel/i82810/raminit.h" Modified: trunk/src/mainboard/msi/ms6119/romstage.c ============================================================================== --- trunk/src/mainboard/msi/ms6119/romstage.c Wed Mar 31 02:06:12 2010 (r5340) +++ trunk/src/mainboard/msi/ms6119/romstage.c Wed Mar 31 16:34:40 2010 (r5341) @@ -26,7 +26,7 @@ #include <arch/romcc_io.h> #include <arch/hlt.h> #include "pc80/serial.c" -#include "arch/i386/lib/console.c" +#include "console/console.c" #include "lib/ramtest.c" #include "southbridge/intel/i82371eb/i82371eb_enable_rom.c" #include "southbridge/intel/i82371eb/i82371eb_early_smbus.c" Modified: trunk/src/mainboard/msi/ms6147/romstage.c ============================================================================== --- trunk/src/mainboard/msi/ms6147/romstage.c Wed Mar 31 02:06:12 2010 (r5340) +++ trunk/src/mainboard/msi/ms6147/romstage.c Wed Mar 31 16:34:40 2010 (r5341) @@ -26,7 +26,7 @@ #include <arch/romcc_io.h> #include <arch/hlt.h> #include "pc80/serial.c" -#include "arch/i386/lib/console.c" +#include "console/console.c" #include "lib/ramtest.c" #include "southbridge/intel/i82371eb/i82371eb_enable_rom.c" #include "southbridge/intel/i82371eb/i82371eb_early_smbus.c" Modified: trunk/src/mainboard/msi/ms6156/romstage.c ============================================================================== --- trunk/src/mainboard/msi/ms6156/romstage.c Wed Mar 31 02:06:12 2010 (r5340) +++ trunk/src/mainboard/msi/ms6156/romstage.c Wed Mar 31 16:34:40 2010 (r5341) @@ -26,7 +26,7 @@ #include <arch/romcc_io.h> #include <arch/hlt.h> #include "pc80/serial.c" -#include "arch/i386/lib/console.c" +#include "console/console.c" #include "lib/ramtest.c" #include "southbridge/intel/i82371eb/i82371eb_enable_rom.c" #include "southbridge/intel/i82371eb/i82371eb_early_smbus.c" Modified: trunk/src/mainboard/msi/ms6178/romstage.c ============================================================================== --- trunk/src/mainboard/msi/ms6178/romstage.c Wed Mar 31 02:06:12 2010 (r5340) +++ trunk/src/mainboard/msi/ms6178/romstage.c Wed Mar 31 16:34:40 2010 (r5341) @@ -26,7 +26,7 @@ #include <arch/hlt.h> #include <stdlib.h> #include "pc80/serial.c" -#include "arch/i386/lib/console.c" +#include "console/console.c" #include "lib/ramtest.c" #include "superio/winbond/w83627hf/w83627hf_early_serial.c" #include "northbridge/intel/i82810/raminit.h" Modified: trunk/src/mainboard/msi/ms7135/romstage.c ============================================================================== --- trunk/src/mainboard/msi/ms7135/romstage.c Wed Mar 31 02:06:12 2010 (r5340) +++ trunk/src/mainboard/msi/ms7135/romstage.c Wed Mar 31 16:34:40 2010 (r5341) @@ -51,7 +51,7 @@ #include <cpu/amd/model_fxx_rev.h> #include "pc80/serial.c" -#include "arch/i386/lib/console.c" +#include "console/console.c" #include "lib/ramtest.c" #include "northbridge/amd/amdk8/incoherent_ht.c" #include "southbridge/nvidia/ck804/ck804_early_smbus.c" Modified: trunk/src/mainboard/msi/ms7260/ap_romstage.c ============================================================================== --- trunk/src/mainboard/msi/ms7260/ap_romstage.c Wed Mar 31 02:06:12 2010 (r5340) +++ trunk/src/mainboard/msi/ms7260/ap_romstage.c Wed Mar 31 16:34:40 2010 (r5341) @@ -39,10 +39,8 @@ #include "option_table.h" #include "pc80/mc146818rtc_early.c" #include "pc80/serial.c" -#if CONFIG_USE_INIT == 0 -#include "lib/memcpy.c" -#endif -#include "arch/i386/lib/console.c" + +#include "console/console.c" #include <cpu/amd/model_fxx_rev.h> #include "northbridge/amd/amdk8/raminit.h" #include "cpu/amd/model_fxx/apic_timer.c" Modified: trunk/src/mainboard/msi/ms7260/romstage.c ============================================================================== --- trunk/src/mainboard/msi/ms7260/romstage.c Wed Mar 31 02:06:12 2010 (r5340) +++ trunk/src/mainboard/msi/ms7260/romstage.c Wed Mar 31 16:34:40 2010 (r5341) @@ -56,7 +56,7 @@ #include "pc80/mc146818rtc_early.c" #include "pc80/serial.c" -#include "arch/i386/lib/console.c" +#include "console/console.c" #if CONFIG_USBDEBUG_DIRECT #include "southbridge/nvidia/mcp55/mcp55_enable_usbdebug_direct.c" #include "pc80/usbdebug_direct_serial.c" Modified: trunk/src/mainboard/msi/ms9185/romstage.c ============================================================================== --- trunk/src/mainboard/msi/ms9185/romstage.c Wed Mar 31 02:06:12 2010 (r5340) +++ trunk/src/mainboard/msi/ms9185/romstage.c Wed Mar 31 16:34:40 2010 (r5341) @@ -50,7 +50,7 @@ #include "option_table.h" #include "pc80/mc146818rtc_early.c" #include "pc80/serial.c" -#include "arch/i386/lib/console.c" +#include "console/console.c" #if 0 static void post_code(uint8_t value) { Modified: trunk/src/mainboard/msi/ms9282/romstage.c ============================================================================== --- trunk/src/mainboard/msi/ms9282/romstage.c Wed Mar 31 02:06:12 2010 (r5340) +++ trunk/src/mainboard/msi/ms9282/romstage.c Wed Mar 31 16:34:40 2010 (r5341) @@ -45,7 +45,7 @@ #include "option_table.h" #include "pc80/mc146818rtc_early.c" #include "pc80/serial.c" -#include "arch/i386/lib/console.c" +#include "console/console.c" #include <cpu/amd/model_fxx_rev.h> #include "southbridge/nvidia/mcp55/mcp55_early_smbus.c" Modified: trunk/src/mainboard/msi/ms9652_fam10/romstage.c ============================================================================== --- trunk/src/mainboard/msi/ms9652_fam10/romstage.c Wed Mar 31 02:06:12 2010 (r5340) +++ trunk/src/mainboard/msi/ms9652_fam10/romstage.c Wed Mar 31 16:34:40 2010 (r5341) @@ -46,7 +46,7 @@ #include "option_table.h" #include "pc80/mc146818rtc_early.c" #include "pc80/serial.c" -#include "arch/i386/lib/console.c" +#include "console/console.c" #if CONFIG_USBDEBUG_DIRECT #include "southbridge/nvidia/mcp55/mcp55_enable_usbdebug_direct.c" #include "pc80/usbdebug_direct_serial.c" Modified: trunk/src/mainboard/nec/powermate2000/romstage.c ============================================================================== --- trunk/src/mainboard/nec/powermate2000/romstage.c Wed Mar 31 02:06:12 2010 (r5340) +++ trunk/src/mainboard/nec/powermate2000/romstage.c Wed Mar 31 16:34:40 2010 (r5341) @@ -26,7 +26,7 @@ #include <arch/hlt.h> #include <stdlib.h> #include "pc80/serial.c" -#include "arch/i386/lib/console.c" +#include "console/console.c" #include "lib/ramtest.c" #include "superio/smsc/smscsuperio/smscsuperio_early_serial.c" #include "northbridge/intel/i82810/raminit.h" Modified: trunk/src/mainboard/newisys/khepri/romstage.c ============================================================================== --- trunk/src/mainboard/newisys/khepri/romstage.c Wed Mar 31 02:06:12 2010 (r5340) +++ trunk/src/mainboard/newisys/khepri/romstage.c Wed Mar 31 16:34:40 2010 (r5341) @@ -15,7 +15,7 @@ #include "option_table.h" #include "pc80/mc146818rtc_early.c" #include "pc80/serial.c" -#include "arch/i386/lib/console.c" +#include "console/console.c" #include "lib/ramtest.c" #if 0 Modified: trunk/src/mainboard/nvidia/l1_2pvv/ap_romstage.c ============================================================================== --- trunk/src/mainboard/nvidia/l1_2pvv/ap_romstage.c Wed Mar 31 02:06:12 2010 (r5340) +++ trunk/src/mainboard/nvidia/l1_2pvv/ap_romstage.c Wed Mar 31 16:34:40 2010 (r5341) @@ -43,22 +43,10 @@ #include "pc80/mc146818rtc_early.c" #include "pc80/serial.c" -#if CONFIG_USE_INIT == 0 - #include "lib/memcpy.c" -#endif - -#include "arch/i386/lib/console.c" - -#if 0 -static void post_code(uint8_t value) { -#if 1 - int i; - for(i=0;i<0x80000;i++) { - outb(value, 0x80); - } -#endif -} -#endif +#include "lib/uart8250.c" +#include "arch/i386/lib/printk_init.c" +#include "console/vtxprintf.c" +#include "console/console.c" #include <cpu/amd/model_fxx_rev.h> #include "northbridge/amd/amdk8/raminit.h" Modified: trunk/src/mainboard/nvidia/l1_2pvv/romstage.c ============================================================================== --- trunk/src/mainboard/nvidia/l1_2pvv/romstage.c Wed Mar 31 02:06:12 2010 (r5340) +++ trunk/src/mainboard/nvidia/l1_2pvv/romstage.c Wed Mar 31 16:34:40 2010 (r5341) @@ -52,7 +52,7 @@ #include "pc80/mc146818rtc_early.c" #include "pc80/serial.c" -#include "arch/i386/lib/console.c" +#include "console/console.c" #if CONFIG_USBDEBUG_DIRECT #include "southbridge/nvidia/mcp55/mcp55_enable_usbdebug_direct.c" #include "pc80/usbdebug_direct_serial.c" Modified: trunk/src/mainboard/olpc/btest/romstage.c ============================================================================== --- trunk/src/mainboard/olpc/btest/romstage.c Wed Mar 31 02:06:12 2010 (r5340) +++ trunk/src/mainboard/olpc/btest/romstage.c Wed Mar 31 16:34:40 2010 (r5341) @@ -5,7 +5,7 @@ #include <arch/romcc_io.h> #include <arch/hlt.h> #include "pc80/serial.c" -#include "arch/i386/lib/console.c" +#include "console/console.c" #include "lib/ramtest.c" #include "superio/winbond/w83627hf/w83627hf_early_serial.c" #include "cpu/x86/bist.h" Modified: trunk/src/mainboard/olpc/rev_a/romstage.c ============================================================================== --- trunk/src/mainboard/olpc/rev_a/romstage.c Wed Mar 31 02:06:12 2010 (r5340) +++ trunk/src/mainboard/olpc/rev_a/romstage.c Wed Mar 31 16:34:40 2010 (r5341) @@ -5,7 +5,7 @@ #include <arch/romcc_io.h> #include <arch/hlt.h> #include "pc80/serial.c" -#include "arch/i386/lib/console.c" +#include "console/console.c" #include "lib/ramtest.c" #include "superio/winbond/w83627hf/w83627hf_early_serial.c" #include "cpu/x86/bist.h" Modified: trunk/src/mainboard/pcengines/alix1c/romstage.c ============================================================================== --- trunk/src/mainboard/pcengines/alix1c/romstage.c Wed Mar 31 02:06:12 2010 (r5340) +++ trunk/src/mainboard/pcengines/alix1c/romstage.c Wed Mar 31 16:34:40 2010 (r5341) @@ -25,7 +25,7 @@ #include <arch/romcc_io.h> #include <arch/hlt.h> #include "pc80/serial.c" -#include "arch/i386/lib/console.c" +#include "console/console.c" #include "lib/ramtest.c" #include "cpu/x86/bist.h" #include "cpu/x86/msr.h" Modified: trunk/src/mainboard/rca/rm4100/romstage.c ============================================================================== --- trunk/src/mainboard/rca/rm4100/romstage.c Wed Mar 31 02:06:12 2010 (r5340) +++ trunk/src/mainboard/rca/rm4100/romstage.c Wed Mar 31 16:34:40 2010 (r5341) @@ -27,7 +27,7 @@ #include <arch/hlt.h> #include "pc80/serial.c" #include "pc80/udelay_io.c" -#include "arch/i386/lib/console.c" +#include "console/console.c" #include "lib/ramtest.c" #include "superio/smsc/smscsuperio/smscsuperio_early_serial.c" #include "northbridge/intel/i82830/raminit.h" Modified: trunk/src/mainboard/roda/rk886ex/romstage.c ============================================================================== --- trunk/src/mainboard/roda/rk886ex/romstage.c Wed Mar 31 02:06:12 2010 (r5340) +++ trunk/src/mainboard/roda/rk886ex/romstage.c Wed Mar 31 16:34:40 2010 (r5341) @@ -40,7 +40,7 @@ #include <console/console.h> #include "pc80/serial.c" -#include "arch/i386/lib/console.c" +#include "console/console.c" #include <cpu/x86/bist.h> #if CONFIG_USBDEBUG_DIRECT Modified: trunk/src/mainboard/soyo/sy-6ba-plus-iii/romstage.c ============================================================================== --- trunk/src/mainboard/soyo/sy-6ba-plus-iii/romstage.c Wed Mar 31 02:06:12 2010 (r5340) +++ trunk/src/mainboard/soyo/sy-6ba-plus-iii/romstage.c Wed Mar 31 16:34:40 2010 (r5341) @@ -26,7 +26,7 @@ #include <arch/hlt.h> #include <stdlib.h> #include "pc80/serial.c" -#include "arch/i386/lib/console.c" +#include "console/console.c" #include "lib/ramtest.c" #include "southbridge/intel/i82371eb/i82371eb_enable_rom.c" #include "southbridge/intel/i82371eb/i82371eb_early_smbus.c" Modified: trunk/src/mainboard/sunw/ultra40/romstage.c ============================================================================== --- trunk/src/mainboard/sunw/ultra40/romstage.c Wed Mar 31 02:06:12 2010 (r5340) +++ trunk/src/mainboard/sunw/ultra40/romstage.c Wed Mar 31 16:34:40 2010 (r5341) @@ -17,7 +17,7 @@ #include "option_table.h" #include "pc80/mc146818rtc_early.c" #include "pc80/serial.c" -#include "arch/i386/lib/console.c" +#include "console/console.c" #include "lib/ramtest.c" #include <cpu/amd/model_fxx_rev.h> Modified: trunk/src/mainboard/supermicro/h8dme/ap_romstage.c ============================================================================== --- trunk/src/mainboard/supermicro/h8dme/ap_romstage.c Wed Mar 31 02:06:12 2010 (r5340) +++ trunk/src/mainboard/supermicro/h8dme/ap_romstage.c Wed Mar 31 16:34:40 2010 (r5341) @@ -43,26 +43,11 @@ #include "pc80/mc146818rtc_early.c" #include "pc80/serial.c" -#if CONFIG_USE_INIT == 0 - #include "lib/memcpy.c" -#endif - -#include "arch/i386/lib/console.c" +#include "console/console.c" #include "lib/uart8250.c" #include "console/vtxprintf.c" #include "./arch/i386/lib/printk_init.c" -#if 0 -static void post_code(uint8_t value) { -#if 1 - int i; - for(i=0;i<0x80000;i++) { - outb(value, 0x80); - } -#endif -} -#endif - #include <cpu/amd/model_fxx_rev.h> #include "northbridge/amd/amdk8/raminit.h" #include "cpu/amd/model_fxx/apic_timer.c" Modified: trunk/src/mainboard/supermicro/h8dme/romstage.c ============================================================================== --- trunk/src/mainboard/supermicro/h8dme/romstage.c Wed Mar 31 02:06:12 2010 (r5340) +++ trunk/src/mainboard/supermicro/h8dme/romstage.c Wed Mar 31 16:34:40 2010 (r5341) @@ -50,7 +50,7 @@ #include "southbridge/nvidia/mcp55/mcp55_early_smbus.c" #include "pc80/serial.c" -#include "arch/i386/lib/console.c" +#include "console/console.c" #include "lib/ramtest.c" #include <cpu/amd/model_fxx_rev.h> Modified: trunk/src/mainboard/supermicro/h8dmr/ap_romstage.c ============================================================================== --- trunk/src/mainboard/supermicro/h8dmr/ap_romstage.c Wed Mar 31 02:06:12 2010 (r5340) +++ trunk/src/mainboard/supermicro/h8dmr/ap_romstage.c Wed Mar 31 16:34:40 2010 (r5341) @@ -43,26 +43,11 @@ #include "pc80/mc146818rtc_early.c" #include "pc80/serial.c" -#if CONFIG_USE_INIT == 0 - #include "lib/memcpy.c" -#endif - -#include "arch/i386/lib/console.c" +#include "console/console.c" #include "lib/uart8250.c" #include "console/vtxprintf.c" #include "./arch/i386/lib/printk_init.c" -#if 0 -static void post_code(uint8_t value) { -#if 1 - int i; - for(i=0;i<0x80000;i++) { - outb(value, 0x80); - } -#endif -} -#endif - #include <cpu/amd/model_fxx_rev.h> #include "northbridge/amd/amdk8/raminit.h" #include "cpu/amd/model_fxx/apic_timer.c" Modified: trunk/src/mainboard/supermicro/h8dmr/romstage.c ============================================================================== --- trunk/src/mainboard/supermicro/h8dmr/romstage.c Wed Mar 31 02:06:12 2010 (r5340) +++ trunk/src/mainboard/supermicro/h8dmr/romstage.c Wed Mar 31 16:34:40 2010 (r5341) @@ -53,7 +53,7 @@ #include "southbridge/nvidia/mcp55/mcp55_early_smbus.c" #include "pc80/serial.c" -#include "arch/i386/lib/console.c" +#include "console/console.c" #include "lib/ramtest.c" #include <cpu/amd/model_fxx_rev.h> Modified: trunk/src/mainboard/supermicro/h8dmr_fam10/romstage.c ============================================================================== --- trunk/src/mainboard/supermicro/h8dmr_fam10/romstage.c Wed Mar 31 02:06:12 2010 (r5340) +++ trunk/src/mainboard/supermicro/h8dmr_fam10/romstage.c Wed Mar 31 16:34:40 2010 (r5341) @@ -47,7 +47,7 @@ // for enable the FAN #include "southbridge/nvidia/mcp55/mcp55_early_smbus.c" #include "pc80/serial.c" -#include "arch/i386/lib/console.c" +#include "console/console.c" #include "lib/ramtest.c" #include <cpu/amd/model_10xxx_rev.h> Modified: trunk/src/mainboard/supermicro/h8qme_fam10/romstage.c ============================================================================== --- trunk/src/mainboard/supermicro/h8qme_fam10/romstage.c Wed Mar 31 02:06:12 2010 (r5340) +++ trunk/src/mainboard/supermicro/h8qme_fam10/romstage.c Wed Mar 31 16:34:40 2010 (r5341) @@ -48,7 +48,7 @@ #include "southbridge/nvidia/mcp55/mcp55_early_smbus.c" #include "pc80/serial.c" -#include "arch/i386/lib/console.c" +#include "console/console.c" #include "lib/ramtest.c" #include <cpu/amd/model_10xxx_rev.h> Modified: trunk/src/mainboard/supermicro/x6dai_g/romstage.c ============================================================================== --- trunk/src/mainboard/supermicro/x6dai_g/romstage.c Wed Mar 31 02:06:12 2010 (r5340) +++ trunk/src/mainboard/supermicro/x6dai_g/romstage.c Wed Mar 31 16:34:40 2010 (r5341) @@ -8,7 +8,7 @@ #include "option_table.h" #include "pc80/mc146818rtc_early.c" #include "pc80/serial.c" -#include "arch/i386/lib/console.c" +#include "console/console.c" #include "lib/ramtest.c" #include "southbridge/intel/esb6300/esb6300_early_smbus.c" #include "northbridge/intel/e7525/raminit.h" Modified: trunk/src/mainboard/supermicro/x6dhe_g/romstage.c ============================================================================== --- trunk/src/mainboard/supermicro/x6dhe_g/romstage.c Wed Mar 31 02:06:12 2010 (r5340) +++ trunk/src/mainboard/supermicro/x6dhe_g/romstage.c Wed Mar 31 16:34:40 2010 (r5341) @@ -8,7 +8,7 @@ #include "option_table.h" #include "pc80/mc146818rtc_early.c" #include "pc80/serial.c" -#include "arch/i386/lib/console.c" +#include "console/console.c" #include "lib/ramtest.c" #include "southbridge/intel/esb6300/esb6300_early_smbus.c" #include "northbridge/intel/e7520/raminit.h" @@ -62,10 +62,12 @@ static const struct mem_controller mch[] = { { .node_id = 0, + /* .f0 = PCI_DEV(0, 0x00, 0), .f1 = PCI_DEV(0, 0x00, 1), .f2 = PCI_DEV(0, 0x00, 2), .f3 = PCI_DEV(0, 0x00, 3), + */ .channel0 = {(0xa<<3)|0, (0xa<<3)|1, (0xa<<3)|2, (0xa<<3)|3, }, .channel1 = {(0xa<<3)|4, (0xa<<3)|5, (0xa<<3)|6, (0xa<<3)|7, }, } Modified: trunk/src/mainboard/supermicro/x6dhe_g2/romstage.c ============================================================================== --- trunk/src/mainboard/supermicro/x6dhe_g2/romstage.c Wed Mar 31 02:06:12 2010 (r5340) +++ trunk/src/mainboard/supermicro/x6dhe_g2/romstage.c Wed Mar 31 16:34:40 2010 (r5341) @@ -8,7 +8,7 @@ #include "option_table.h" #include "pc80/mc146818rtc_early.c" #include "pc80/serial.c" -#include "arch/i386/lib/console.c" +#include "console/console.c" #include "lib/ramtest.c" #include "southbridge/intel/i82801ex/i82801ex_early_smbus.c" #include "northbridge/intel/e7520/raminit.h" @@ -62,10 +62,12 @@ static const struct mem_controller mch[] = { { .node_id = 0, + /* .f0 = PCI_DEV(0, 0x00, 0), .f1 = PCI_DEV(0, 0x00, 1), .f2 = PCI_DEV(0, 0x00, 2), .f3 = PCI_DEV(0, 0x00, 3), + */ .channel0 = {(0xa<<3)|3, (0xa<<3)|2, (0xa<<3)|1, (0xa<<3)|0, }, .channel1 = {(0xa<<3)|7, (0xa<<3)|6, (0xa<<3)|5, (0xa<<3)|4, }, Modified: trunk/src/mainboard/supermicro/x6dhr_ig/romstage.c ============================================================================== --- trunk/src/mainboard/supermicro/x6dhr_ig/romstage.c Wed Mar 31 02:06:12 2010 (r5340) +++ trunk/src/mainboard/supermicro/x6dhr_ig/romstage.c Wed Mar 31 16:34:40 2010 (r5341) @@ -8,7 +8,7 @@ #include "option_table.h" #include "pc80/mc146818rtc_early.c" #include "pc80/serial.c" -#include "arch/i386/lib/console.c" +#include "console/console.c" #include "lib/ramtest.c" #include "southbridge/intel/i82801ex/i82801ex_early_smbus.c" #include "northbridge/intel/e7520/raminit.h" @@ -63,10 +63,12 @@ static const struct mem_controller mch[] = { { .node_id = 0, + /* .f0 = PCI_DEV(0, 0x00, 0), .f1 = PCI_DEV(0, 0x00, 1), .f2 = PCI_DEV(0, 0x00, 2), .f3 = PCI_DEV(0, 0x00, 3), + */ .channel0 = {(0xa<<3)|3, (0xa<<3)|2, (0xa<<3)|1, (0xa<<3)|0, }, .channel1 = {(0xa<<3)|7, (0xa<<3)|6, (0xa<<3)|5, (0xa<<3)|4, }, } Modified: trunk/src/mainboard/supermicro/x6dhr_ig2/romstage.c ============================================================================== --- trunk/src/mainboard/supermicro/x6dhr_ig2/romstage.c Wed Mar 31 02:06:12 2010 (r5340) +++ trunk/src/mainboard/supermicro/x6dhr_ig2/romstage.c Wed Mar 31 16:34:40 2010 (r5341) @@ -8,7 +8,7 @@ #include "option_table.h" #include "pc80/mc146818rtc_early.c" #include "pc80/serial.c" -#include "arch/i386/lib/console.c" +#include "console/console.c" #include "lib/ramtest.c" #include "southbridge/intel/i82801ex/i82801ex_early_smbus.c" #include "northbridge/intel/e7520/raminit.h" @@ -63,10 +63,12 @@ static const struct mem_controller mch[] = { { .node_id = 0, + /* .f0 = PCI_DEV(0, 0x00, 0), .f1 = PCI_DEV(0, 0x00, 1), .f2 = PCI_DEV(0, 0x00, 2), .f3 = PCI_DEV(0, 0x00, 3), + */ .channel0 = {(0xa<<3)|3, (0xa<<3)|2, (0xa<<3)|1, (0xa<<3)|0, }, .channel1 = {(0xa<<3)|7, (0xa<<3)|6, (0xa<<3)|5, (0xa<<3)|4, }, } Modified: trunk/src/mainboard/technexion/tim5690/romstage.c ============================================================================== --- trunk/src/mainboard/technexion/tim5690/romstage.c Wed Mar 31 02:06:12 2010 (r5340) +++ trunk/src/mainboard/technexion/tim5690/romstage.c Wed Mar 31 16:34:40 2010 (r5341) @@ -43,7 +43,7 @@ #include "option_table.h" #include "pc80/mc146818rtc_early.c" #include "pc80/serial.c" -#include "arch/i386/lib/console.c" +#include "console/console.c" #define post_code(x) outb(x, 0x80) Modified: trunk/src/mainboard/technexion/tim8690/romstage.c ============================================================================== --- trunk/src/mainboard/technexion/tim8690/romstage.c Wed Mar 31 02:06:12 2010 (r5340) +++ trunk/src/mainboard/technexion/tim8690/romstage.c Wed Mar 31 16:34:40 2010 (r5341) @@ -43,7 +43,7 @@ #include "option_table.h" #include "pc80/mc146818rtc_early.c" #include "pc80/serial.c" -#include "arch/i386/lib/console.c" +#include "console/console.c" #define post_code(x) outb(x, 0x80) Modified: trunk/src/mainboard/technologic/ts5300/romstage.c ============================================================================== --- trunk/src/mainboard/technologic/ts5300/romstage.c Wed Mar 31 02:06:12 2010 (r5340) +++ trunk/src/mainboard/technologic/ts5300/romstage.c Wed Mar 31 16:34:40 2010 (r5341) @@ -13,7 +13,7 @@ #include <arch/hlt.h> #include "pc80/mc146818rtc_early.c" #include "pc80/serial.c" -#include "arch/i386/lib/console.c" +#include "console/console.c" #include "lib/ramtest.c" #include "cpu/x86/bist.h" Modified: trunk/src/mainboard/televideo/tc7020/romstage.c ============================================================================== --- trunk/src/mainboard/televideo/tc7020/romstage.c Wed Mar 31 02:06:12 2010 (r5340) +++ trunk/src/mainboard/televideo/tc7020/romstage.c Wed Mar 31 16:34:40 2010 (r5341) @@ -25,7 +25,7 @@ #include <arch/romcc_io.h> #include <arch/hlt.h> #include "pc80/serial.c" -#include "arch/i386/lib/console.c" +#include "console/console.c" #include "lib/ramtest.c" #include "northbridge/amd/gx1/raminit.c" #include "superio/nsc/pc97317/pc97317_early_serial.c" Modified: trunk/src/mainboard/thomson/ip1000/romstage.c ============================================================================== --- trunk/src/mainboard/thomson/ip1000/romstage.c Wed Mar 31 02:06:12 2010 (r5340) +++ trunk/src/mainboard/thomson/ip1000/romstage.c Wed Mar 31 16:34:40 2010 (r5341) @@ -28,7 +28,7 @@ #include <arch/llshell.h> #include "pc80/serial.c" #include "pc80/udelay_io.c" -#include "arch/i386/lib/console.c" +#include "console/console.c" #include "lib/ramtest.c" #include "superio/smsc/smscsuperio/smscsuperio_early_serial.c" #include "northbridge/intel/i82830/raminit.h" Modified: trunk/src/mainboard/tyan/s1846/romstage.c ============================================================================== --- trunk/src/mainboard/tyan/s1846/romstage.c Wed Mar 31 02:06:12 2010 (r5340) +++ trunk/src/mainboard/tyan/s1846/romstage.c Wed Mar 31 16:34:40 2010 (r5341) @@ -26,7 +26,7 @@ #include <arch/hlt.h> #include <stdlib.h> #include "pc80/serial.c" -#include "arch/i386/lib/console.c" +#include "console/console.c" #include "lib/ramtest.c" #include "southbridge/intel/i82371eb/i82371eb_enable_rom.c" #include "southbridge/intel/i82371eb/i82371eb_early_smbus.c" Modified: trunk/src/mainboard/tyan/s2735/romstage.c ============================================================================== --- trunk/src/mainboard/tyan/s2735/romstage.c Wed Mar 31 02:06:12 2010 (r5340) +++ trunk/src/mainboard/tyan/s2735/romstage.c Wed Mar 31 16:34:40 2010 (r5341) @@ -9,20 +9,9 @@ #include "option_table.h" #include "pc80/mc146818rtc_early.c" #include "pc80/serial.c" -#include "arch/i386/lib/console.c" +#include "console/console.c" #include "lib/ramtest.c" -#if 0 -static void post_code(uint8_t value) { -#if 1 - int i; - for(i=0;i<0x80000;i++) { - outb(value, 0x80); - } -#endif -} -#endif - #include "southbridge/intel/i82801ex/i82801ex_early_smbus.c" #include "northbridge/intel/e7501/raminit.h" @@ -139,7 +128,7 @@ "movl %%esp, %0\n\t" : "=a" (v_esp) ); -#if CONFIG_USE_INIT +#if CONFIG_USE_PRINTK_IN_CAR printk(BIOS_DEBUG, "v_esp=%08x\r\n", v_esp); #else print_debug("v_esp="); print_debug_hex32(v_esp); print_debug("\r\n"); @@ -151,7 +140,7 @@ cpu_reset_x: -#if CONFIG_USE_INIT +#if CONFIG_USE_PRINTK_IN_CAR printk(BIOS_DEBUG, "cpu_reset = %08x\r\n",cpu_reset); #else print_debug("cpu_reset = "); print_debug_hex32(cpu_reset); print_debug("\r\n"); @@ -200,7 +189,7 @@ { print_debug("Use Ram as Stack now - \r\n"); } -#if CONFIG_USE_INIT +#if CONFIG_USE_PRINTK_IN_CAR printk(BIOS_DEBUG, "new_cpu_reset = %08x\r\n", new_cpu_reset); #else print_debug("new_cpu_reset = "); print_debug_hex32(new_cpu_reset); print_debug("\r\n"); Modified: trunk/src/mainboard/tyan/s2850/romstage.c ============================================================================== --- trunk/src/mainboard/tyan/s2850/romstage.c Wed Mar 31 02:06:12 2010 (r5340) +++ trunk/src/mainboard/tyan/s2850/romstage.c Wed Mar 31 16:34:40 2010 (r5341) @@ -10,7 +10,7 @@ #include "option_table.h" #include "pc80/mc146818rtc_early.c" #include "pc80/serial.c" -#include "arch/i386/lib/console.c" +#include "console/console.c" #include "lib/ramtest.c" #if 0 Modified: trunk/src/mainboard/tyan/s2875/romstage.c ============================================================================== --- trunk/src/mainboard/tyan/s2875/romstage.c Wed Mar 31 02:06:12 2010 (r5340) +++ trunk/src/mainboard/tyan/s2875/romstage.c Wed Mar 31 16:34:40 2010 (r5341) @@ -10,7 +10,7 @@ #include "option_table.h" #include "pc80/mc146818rtc_early.c" #include "pc80/serial.c" -#include "arch/i386/lib/console.c" +#include "console/console.c" #include "lib/ramtest.c" #include <cpu/amd/model_fxx_rev.h> Modified: trunk/src/mainboard/tyan/s2880/romstage.c ============================================================================== --- trunk/src/mainboard/tyan/s2880/romstage.c Wed Mar 31 02:06:12 2010 (r5340) +++ trunk/src/mainboard/tyan/s2880/romstage.c Wed Mar 31 16:34:40 2010 (r5341) @@ -10,7 +10,7 @@ #include "option_table.h" #include "pc80/mc146818rtc_early.c" #include "pc80/serial.c" -#include "arch/i386/lib/console.c" +#include "console/console.c" #include "lib/ramtest.c" #include <cpu/amd/model_fxx_rev.h> Modified: trunk/src/mainboard/tyan/s2881/romstage.c ============================================================================== --- trunk/src/mainboard/tyan/s2881/romstage.c Wed Mar 31 02:06:12 2010 (r5340) +++ trunk/src/mainboard/tyan/s2881/romstage.c Wed Mar 31 16:34:40 2010 (r5341) @@ -14,7 +14,7 @@ #include "option_table.h" #include "pc80/mc146818rtc_early.c" #include "pc80/serial.c" -#include "arch/i386/lib/console.c" +#include "console/console.c" #include "lib/ramtest.c" #if 0 Modified: trunk/src/mainboard/tyan/s2882/romstage.c ============================================================================== --- trunk/src/mainboard/tyan/s2882/romstage.c Wed Mar 31 02:06:12 2010 (r5340) +++ trunk/src/mainboard/tyan/s2882/romstage.c Wed Mar 31 16:34:40 2010 (r5341) @@ -10,7 +10,7 @@ #include "option_table.h" #include "pc80/mc146818rtc_early.c" #include "pc80/serial.c" -#include "arch/i386/lib/console.c" +#include "console/console.c" #include "lib/ramtest.c" #include <cpu/amd/model_fxx_rev.h> Modified: trunk/src/mainboard/tyan/s2885/romstage.c ============================================================================== --- trunk/src/mainboard/tyan/s2885/romstage.c Wed Mar 31 02:06:12 2010 (r5340) +++ trunk/src/mainboard/tyan/s2885/romstage.c Wed Mar 31 16:34:40 2010 (r5341) @@ -9,7 +9,7 @@ #include "option_table.h" #include "pc80/mc146818rtc_early.c" #include "pc80/serial.c" -#include "arch/i386/lib/console.c" +#include "console/console.c" #include "lib/ramtest.c" #if 0 Modified: trunk/src/mainboard/tyan/s2891/romstage.c ============================================================================== --- trunk/src/mainboard/tyan/s2891/romstage.c Wed Mar 31 02:06:12 2010 (r5340) +++ trunk/src/mainboard/tyan/s2891/romstage.c Wed Mar 31 16:34:40 2010 (r5341) @@ -15,7 +15,7 @@ #include "option_table.h" #include "pc80/mc146818rtc_early.c" #include "pc80/serial.c" -#include "arch/i386/lib/console.c" +#include "console/console.c" #include "lib/ramtest.c" #include <cpu/amd/model_fxx_rev.h> Modified: trunk/src/mainboard/tyan/s2892/romstage.c ============================================================================== --- trunk/src/mainboard/tyan/s2892/romstage.c Wed Mar 31 02:06:12 2010 (r5340) +++ trunk/src/mainboard/tyan/s2892/romstage.c Wed Mar 31 16:34:40 2010 (r5341) @@ -15,7 +15,7 @@ #include "pc80/mc146818rtc_early.c" #include "pc80/serial.c" -#include "arch/i386/lib/console.c" +#include "console/console.c" #include "lib/ramtest.c" #include <cpu/amd/model_fxx_rev.h> Modified: trunk/src/mainboard/tyan/s2895/romstage.c ============================================================================== --- trunk/src/mainboard/tyan/s2895/romstage.c Wed Mar 31 02:06:12 2010 (r5340) +++ trunk/src/mainboard/tyan/s2895/romstage.c Wed Mar 31 16:34:40 2010 (r5341) @@ -17,7 +17,7 @@ #include "pc80/mc146818rtc_early.c" #include "pc80/serial.c" -#include "arch/i386/lib/console.c" +#include "console/console.c" #include "lib/ramtest.c" #include <cpu/amd/model_fxx_rev.h> Modified: trunk/src/mainboard/tyan/s2912/ap_romstage.c ============================================================================== --- trunk/src/mainboard/tyan/s2912/ap_romstage.c Wed Mar 31 02:06:12 2010 (r5340) +++ trunk/src/mainboard/tyan/s2912/ap_romstage.c Wed Mar 31 16:34:40 2010 (r5341) @@ -43,11 +43,7 @@ #include "pc80/mc146818rtc_early.c" #include "pc80/serial.c" -#if CONFIG_USE_INIT == 0 - #include "lib/memcpy.c" -#endif - -#include "arch/i386/lib/console.c" +#include "console/console.c" #include <cpu/amd/model_fxx_rev.h> #include "northbridge/amd/amdk8/raminit.h" Modified: trunk/src/mainboard/tyan/s2912/romstage.c ============================================================================== --- trunk/src/mainboard/tyan/s2912/romstage.c Wed Mar 31 02:06:12 2010 (r5340) +++ trunk/src/mainboard/tyan/s2912/romstage.c Wed Mar 31 16:34:40 2010 (r5341) @@ -52,7 +52,7 @@ #include "pc80/mc146818rtc_early.c" #include "pc80/serial.c" -#include "arch/i386/lib/console.c" +#include "console/console.c" #if CONFIG_USBDEBUG_DIRECT #include "southbridge/nvidia/mcp55/mcp55_enable_usbdebug_direct.c" #include "pc80/usbdebug_direct_serial.c" Modified: trunk/src/mainboard/tyan/s2912_fam10/romstage.c ============================================================================== --- trunk/src/mainboard/tyan/s2912_fam10/romstage.c Wed Mar 31 02:06:12 2010 (r5340) +++ trunk/src/mainboard/tyan/s2912_fam10/romstage.c Wed Mar 31 16:34:40 2010 (r5341) @@ -46,7 +46,7 @@ #include "option_table.h" #include "pc80/mc146818rtc_early.c" #include "pc80/serial.c" -#include "arch/i386/lib/console.c" +#include "console/console.c" #if CONFIG_USBDEBUG_DIRECT #include "southbridge/nvidia/mcp55/mcp55_enable_usbdebug_direct.c" #include "pc80/usbdebug_direct_serial.c" Modified: trunk/src/mainboard/tyan/s4880/romstage.c ============================================================================== --- trunk/src/mainboard/tyan/s4880/romstage.c Wed Mar 31 02:06:12 2010 (r5340) +++ trunk/src/mainboard/tyan/s4880/romstage.c Wed Mar 31 16:34:40 2010 (r5341) @@ -10,7 +10,7 @@ #include "option_table.h" #include "pc80/mc146818rtc_early.c" #include "pc80/serial.c" -#include "arch/i386/lib/console.c" +#include "console/console.c" #include "lib/ramtest.c" #include <cpu/amd/model_fxx_rev.h> Modified: trunk/src/mainboard/tyan/s4882/romstage.c ============================================================================== --- trunk/src/mainboard/tyan/s4882/romstage.c Wed Mar 31 02:06:12 2010 (r5340) +++ trunk/src/mainboard/tyan/s4882/romstage.c Wed Mar 31 16:34:40 2010 (r5341) @@ -9,7 +9,7 @@ #include "option_table.h" #include "pc80/mc146818rtc_early.c" #include "pc80/serial.c" -#include "arch/i386/lib/console.c" +#include "console/console.c" #include "lib/ramtest.c" #include <cpu/amd/model_fxx_rev.h> Modified: trunk/src/mainboard/via/epia-cn/romstage.c ============================================================================== --- trunk/src/mainboard/via/epia-cn/romstage.c Wed Mar 31 02:06:12 2010 (r5340) +++ trunk/src/mainboard/via/epia-cn/romstage.c Wed Mar 31 16:34:40 2010 (r5341) @@ -27,7 +27,7 @@ #include <arch/romcc_io.h> #include <arch/hlt.h> #include "pc80/serial.c" -#include "arch/i386/lib/console.c" +#include "console/console.c" #include "lib/ramtest.c" #include "northbridge/via/cn700/raminit.h" #include "cpu/x86/mtrr/earlymtrr.c" Modified: trunk/src/mainboard/via/epia-m/romstage.c ============================================================================== --- trunk/src/mainboard/via/epia-m/romstage.c Wed Mar 31 02:06:12 2010 (r5340) +++ trunk/src/mainboard/via/epia-m/romstage.c Wed Mar 31 16:34:40 2010 (r5341) @@ -10,7 +10,7 @@ #include <arch/hlt.h> #include <stdlib.h> #include "pc80/serial.c" -#include "arch/i386/lib/console.c" +#include "console/console.c" #include "lib/ramtest.c" #include "northbridge/via/vt8623/raminit.h" #include "cpu/x86/mtrr/earlymtrr.c" Modified: trunk/src/mainboard/via/epia-m700/romstage.c ============================================================================== --- trunk/src/mainboard/via/epia-m700/romstage.c Wed Mar 31 02:06:12 2010 (r5340) +++ trunk/src/mainboard/via/epia-m700/romstage.c Wed Mar 31 16:34:40 2010 (r5341) @@ -33,16 +33,14 @@ #include <arch/romcc_io.h> #include <arch/hlt.h> #include "pc80/serial.c" -#include "arch/i386/lib/console.c" +#include "console/console.c" #include "lib/ramtest.c" #include "northbridge/via/vx800/vx800.h" #include "cpu/x86/mtrr/earlymtrr.c" #include "cpu/x86/bist.h" #include "pc80/udelay_io.c" #include "lib/delay.c" -#if CONFIG_USE_INIT == 0 #include <string.h> -#endif #include "cpu/x86/lapic/boot_cpu.c" /* This file contains the board-special SI value for raminit.c. */ @@ -726,7 +724,7 @@ */ unsigned v_esp; __asm__ volatile ("movl %%esp, %0\n\t":"=a" (v_esp)); -#if CONFIG_USE_INIT +#if CONFIG_USE_PRINTK_IN_CAR printk(BIOS_DEBUG, "v_esp=%08x\r\n", v_esp); #else print_debug("v_esp="); @@ -745,7 +743,7 @@ */ cpu_reset = 0; -#if CONFIG_USE_INIT +#if CONFIG_USE_PRINTK_IN_CAR printk(BIOS_DEBUG, "cpu_reset = %08x\r\n", cpu_reset); #else print_debug("cpu_reset = "); @@ -795,7 +793,7 @@ else print_debug("Use Ram as Stack now - \r\n"); -#if CONFIG_USE_INIT +#if CONFIG_USE_PRINTK_IN_CAR printk(BIOS_DEBUG, "new_cpu_reset = %08x\r\n", new_cpu_reset); #else print_debug("new_cpu_reset = "); Modified: trunk/src/mainboard/via/epia-n/romstage.c ============================================================================== --- trunk/src/mainboard/via/epia-n/romstage.c Wed Mar 31 02:06:12 2010 (r5340) +++ trunk/src/mainboard/via/epia-n/romstage.c Wed Mar 31 16:34:40 2010 (r5341) @@ -27,7 +27,7 @@ #include <arch/romcc_io.h> #include <arch/hlt.h> #include "pc80/serial.c" -#include "arch/i386/lib/console.c" +#include "console/console.c" #include "lib/ramtest.c" #include "northbridge/via/cn400/raminit.h" #include "cpu/x86/mtrr/earlymtrr.c" Modified: trunk/src/mainboard/via/epia/romstage.c ============================================================================== --- trunk/src/mainboard/via/epia/romstage.c Wed Mar 31 02:06:12 2010 (r5340) +++ trunk/src/mainboard/via/epia/romstage.c Wed Mar 31 16:34:40 2010 (r5341) @@ -6,7 +6,7 @@ #include <arch/hlt.h> #include <stdlib.h> #include "pc80/serial.c" -#include "arch/i386/lib/console.c" +#include "console/console.c" #include "lib/ramtest.c" #include "northbridge/via/vt8601/raminit.h" #include "cpu/x86/mtrr/earlymtrr.c" Modified: trunk/src/mainboard/via/pc2500e/romstage.c ============================================================================== --- trunk/src/mainboard/via/pc2500e/romstage.c Wed Mar 31 02:06:12 2010 (r5340) +++ trunk/src/mainboard/via/pc2500e/romstage.c Wed Mar 31 16:34:40 2010 (r5341) @@ -28,7 +28,7 @@ #include "option_table.h" #include "pc80/mc146818rtc_early.c" #include "pc80/serial.c" -#include "arch/i386/lib/console.c" +#include "console/console.c" #include "lib/ramtest.c" #include "northbridge/via/cn700/raminit.h" #include "cpu/x86/mtrr/earlymtrr.c" Modified: trunk/src/mainboard/via/vt8454c/romstage.c ============================================================================== --- trunk/src/mainboard/via/vt8454c/romstage.c Wed Mar 31 02:06:12 2010 (r5340) +++ trunk/src/mainboard/via/vt8454c/romstage.c Wed Mar 31 16:34:40 2010 (r5341) @@ -27,7 +27,7 @@ #include <arch/romcc_io.h> #include <arch/hlt.h> #include "pc80/serial.c" -#include "arch/i386/lib/console.c" +#include "console/console.c" #include "lib/ramtest.c" #include "northbridge/via/cx700/raminit.h" #include "cpu/x86/mtrr/earlymtrr.c" Modified: trunk/src/mainboard/winent/pl6064/romstage.c ============================================================================== --- trunk/src/mainboard/winent/pl6064/romstage.c Wed Mar 31 02:06:12 2010 (r5340) +++ trunk/src/mainboard/winent/pl6064/romstage.c Wed Mar 31 16:34:40 2010 (r5341) @@ -25,7 +25,7 @@ #include <device/pnp_def.h> #include <arch/hlt.h> #include "pc80/serial.c" -#include "arch/i386/lib/console.c" +#include "console/console.c" #include "lib/ramtest.c" #include "cpu/x86/bist.h" #include "cpu/x86/msr.h" Modified: trunk/src/northbridge/amd/amdk8/raminit_test.c ============================================================================== --- trunk/src/northbridge/amd/amdk8/raminit_test.c Wed Mar 31 02:06:12 2010 (r5340) +++ trunk/src/northbridge/amd/amdk8/raminit_test.c Wed Mar 31 16:34:40 2010 (r5341) @@ -124,7 +124,7 @@ { longjmp(end_buf, 2); } -#include "../../../arch/i386/lib/console.c" +#include "console/console.c" unsigned long log2(unsigned long x) { Modified: trunk/src/northbridge/intel/e7520/raminit.c ============================================================================== --- trunk/src/northbridge/intel/e7520/raminit.c Wed Mar 31 02:06:12 2010 (r5340) +++ trunk/src/northbridge/intel/e7520/raminit.c Wed Mar 31 16:34:40 2010 (r5341) @@ -67,7 +67,7 @@ device_t dev; unsigned where; unsigned long reg; - dev = (register_values[i] & ~0xff) - PCI_DEV(0, 0x00, 0) + ctrl->f0; + dev = (register_values[i] & ~0xff) - PCI_DEV(0, 0x00, 0) + PCI_DEV(0, 0x00, 0); where = register_values[i] & 0xff; reg = pci_read_config32(dev, where); reg &= register_values[i+1]; @@ -181,27 +181,27 @@ sz.side1 -= 29; cum += (1 << sz.side1); /* DRB = 0x60 */ - pci_write_config8(ctrl->f0, DRB + (i*2), cum); + pci_write_config8(PCI_DEV(0, 0x00, 0), DRB + (i*2), cum); if( sz.side2 > 28) { sz.side2 -= 29; cum += (1 << sz.side2); } - pci_write_config8(ctrl->f0, DRB+1 + (i*2), cum); + pci_write_config8(PCI_DEV(0, 0x00, 0), DRB+1 + (i*2), cum); } else { - pci_write_config8(ctrl->f0, DRB + (i*2), cum); - pci_write_config8(ctrl->f0, DRB+1 + (i*2), cum); + pci_write_config8(PCI_DEV(0, 0x00, 0), DRB + (i*2), cum); + pci_write_config8(PCI_DEV(0, 0x00, 0), DRB+1 + (i*2), cum); } } /* set TOM top of memory 0xcc */ - pci_write_config16(ctrl->f0, TOM, cum); + pci_write_config16(PCI_DEV(0, 0x00, 0), TOM, cum); /* set TOLM top of low memory */ if(cum > 0x18) { cum = 0x18; } cum <<= 11; /* 0xc4 TOLM */ - pci_write_config16(ctrl->f0, TOLM, cum); + pci_write_config16(PCI_DEV(0, 0x00, 0), TOLM, cum); return 0; } @@ -279,7 +279,7 @@ } /* 0x70 DRA */ - pci_write_config32(ctrl->f0, DRA, dra); + pci_write_config32(PCI_DEV(0, 0x00, 0), DRA, dra); goto out; val_err: @@ -309,7 +309,7 @@ static const int latency_indicies[] = { 26, 23, 9 }; /* 0x78 DRT */ - drt = pci_read_config32(ctrl->f0, DRT); + drt = pci_read_config32(PCI_DEV(0, 0x00, 0), DRT); drt &= 3; /* save bits 1:0 */ for(first_dimm = 0; first_dimm < 4; first_dimm++) { @@ -542,7 +542,7 @@ } /* 0x78 DRT */ - pci_write_config32(ctrl->f0, DRT, drt); + pci_write_config32(PCI_DEV(0, 0x00, 0), DRT, drt); return(cas_latency); } @@ -563,7 +563,7 @@ static const unsigned char fsb_conversion[4] = {3,1,3,2}; /* 0x7c DRC */ - drc = pci_read_config32(ctrl->f0, DRC); + drc = pci_read_config32(PCI_DEV(0, 0x00, 0), DRC); for(cnt=0; cnt < 4; cnt++) { if (!(dimm_mask & (1 << cnt))) { continue; @@ -727,12 +727,12 @@ /* Set up northbridge values */ /* ODT enable */ - pci_write_config32(ctrl->f0, 0x88, 0xf0000180); + pci_write_config32(PCI_DEV(0, 0x00, 0), 0x88, 0xf0000180); /* Figure out which slots are Empty, Single, or Double sided */ for(i=0,t4=0,c2=0;i<8;i+=2) { - c1 = pci_read_config8(ctrl->f0, DRB+i); + c1 = pci_read_config8(PCI_DEV(0, 0x00, 0), DRB+i); if(c1 == c2) continue; - c2 = pci_read_config8(ctrl->f0, DRB+1+i); + c2 = pci_read_config8(PCI_DEV(0, 0x00, 0), DRB+1+i); if(c1 == c2) t4 |= (1 << (i*4)); else @@ -778,7 +778,7 @@ print_debug_hex32(data32); print_debug("\r\n"); - pci_write_config32(ctrl->f0, 0xb0, data32); + pci_write_config32(PCI_DEV(0, 0x00, 0), 0xb0, data32); for(dimm=0;dimm<8;dimm+=1) { @@ -1079,10 +1079,10 @@ /* 0x80 */ #ifdef DIMM_MAP_LOGICAL - pci_write_config32(ctrl->f0, DRM, + pci_write_config32(PCI_DEV(0, 0x00, 0), DRM, 0x00210000 | DIMM_MAP_LOGICAL); #else - pci_write_config32(ctrl->f0, DRM, 0x00211248); + pci_write_config32(PCI_DEV(0, 0x00, 0), DRM, 0x00211248); #endif /* set dram type and Front Side Bus freq. */ drc = spd_set_dram_controller_mode(ctrl, mask); @@ -1097,20 +1097,20 @@ /* drc bits 1:0 = DIMM speed, bits 3:2 = FSB speed */ for(iptr = gearing[(drc&3)+((((drc>>2)&3)-1)*3)].clkgr,cnt=0; cnt<4;cnt++) { - pci_write_config32(ctrl->f0, 0xa0+(cnt*4), iptr[cnt]); + pci_write_config32(PCI_DEV(0, 0x00, 0), 0xa0+(cnt*4), iptr[cnt]); } /* 0x7c DRC */ - pci_write_config32(ctrl->f0, DRC, data32); + pci_write_config32(PCI_DEV(0, 0x00, 0), DRC, data32); /* turn the clocks on */ /* 0x8c CKDIS */ - pci_write_config16(ctrl->f0, CKDIS, 0x0000); + pci_write_config16(PCI_DEV(0, 0x00, 0), CKDIS, 0x0000); /* 0x9a DDRCSR Take subsystem out of idle */ - data16 = pci_read_config16(ctrl->f0, DDRCSR); + data16 = pci_read_config16(PCI_DEV(0, 0x00, 0), DDRCSR); data16 &= ~(7 << 12); data16 |= (3 << 12); /* use dual channel lock step */ - pci_write_config16(ctrl->f0, DDRCSR, data16); + pci_write_config16(PCI_DEV(0, 0x00, 0), DDRCSR, data16); /* program row size DRB */ spd_set_ram_size(ctrl, mask); @@ -1287,23 +1287,23 @@ set_on_dimm_termination_enable(ctrl); } else { /* ddr */ - pci_write_config32(ctrl->f0, 0x88, 0xa0000000 ); + pci_write_config32(PCI_DEV(0, 0x00, 0), 0x88, 0xa0000000 ); } /* receive enable calibration */ set_receive_enable(ctrl); /* DQS */ - pci_write_config32(ctrl->f0, 0x94, 0x3904a100 ); + pci_write_config32(PCI_DEV(0, 0x00, 0), 0x94, 0x3904a100 ); for(i = 0, cnt = (BAR+0x200); i < 24; i++, cnt+=4) { write32(cnt, dqs_data[i]); } - pci_write_config32(ctrl->f0, 0x94, 0x3904a100 ); + pci_write_config32(PCI_DEV(0, 0x00, 0), 0x94, 0x3904a100 ); /* Enable refresh */ /* 0x7c DRC */ data32 = drc & ~(3 << 20); /* clear ECC mode */ - pci_write_config32(ctrl->f0, DRC, data32); + pci_write_config32(PCI_DEV(0, 0x00, 0), DRC, data32); write32(BAR+DCALCSR, 0x0008000f); /* clear memory and init ECC */ @@ -1320,13 +1320,13 @@ } /* Bring memory subsystem on line */ - data32 = pci_read_config32(ctrl->f0, 0x98); + data32 = pci_read_config32(PCI_DEV(0, 0x00, 0), 0x98); data32 |= (1 << 31); - pci_write_config32(ctrl->f0, 0x98, data32); + pci_write_config32(PCI_DEV(0, 0x00, 0), 0x98, data32); /* wait for completion */ print_debug("Waiting for mem complete\r\n"); while(1) { - data32 = pci_read_config32(ctrl->f0, 0x98); + data32 = pci_read_config32(PCI_DEV(0, 0x00, 0), 0x98); if( (data32 & (1<<31)) == 0) break; } @@ -1336,17 +1336,17 @@ /* 0x7c DRC */ drc |= (1 << 29); data32 = drc & ~(3 << 20); /* clear ECC mode */ - pci_write_config32(ctrl->f0, DRC, data32); + pci_write_config32(PCI_DEV(0, 0x00, 0), DRC, data32); /* Set the ecc mode */ - pci_write_config32(ctrl->f0, DRC, drc); + pci_write_config32(PCI_DEV(0, 0x00, 0), DRC, drc); /* Enable memory scrubbing */ /* 0x52 MCHSCRB */ - data16 = pci_read_config16(ctrl->f0, MCHSCRB); + data16 = pci_read_config16(PCI_DEV(0, 0x00, 0), MCHSCRB); data16 &= ~0x0f; data16 |= ((2 << 2) | (2 << 0)); - pci_write_config16(ctrl->f0, MCHSCRB, data16); + pci_write_config16(PCI_DEV(0, 0x00, 0), MCHSCRB, data16); /* The memory is now setup, use it */ cache_lbmem(MTRR_TYPE_WRBACK); Modified: trunk/src/northbridge/intel/e7520/raminit.h ============================================================================== --- trunk/src/northbridge/intel/e7520/raminit.h Wed Mar 31 02:06:12 2010 (r5340) +++ trunk/src/northbridge/intel/e7520/raminit.h Wed Mar 31 16:34:40 2010 (r5341) @@ -4,9 +4,9 @@ #define DIMM_SOCKETS 4 struct mem_controller { unsigned node_id; - device_t f0, f1, f2, f3; - uint16_t channel0[DIMM_SOCKETS]; - uint16_t channel1[DIMM_SOCKETS]; + // device_t f0, f1, f2, f3; + u16 channel0[DIMM_SOCKETS]; + u16 channel1[DIMM_SOCKETS]; }; #endif /* RAMINIT_H */ Modified: trunk/src/northbridge/via/vx800/examples/romstage.c ============================================================================== --- trunk/src/northbridge/via/vx800/examples/romstage.c Wed Mar 31 02:06:12 2010 (r5340) +++ trunk/src/northbridge/via/vx800/examples/romstage.c Wed Mar 31 16:34:40 2010 (r5341) @@ -31,16 +31,14 @@ #include <arch/romcc_io.h> #include <arch/hlt.h> #include "pc80/serial.c" -#include "arch/i386/lib/console.c" +#include "console/console.c" #include "lib/ramtest.c" #include "northbridge/via/vx800/vx800.h" #include "cpu/x86/mtrr/earlymtrr.c" #include "cpu/x86/bist.h" #include "pc80/udelay_io.c" #include "lib/delay.c" -#if CONFIG_USE_INIT == 0 #include "lib/memcpy.c" -#endif #include "cpu/x86/lapic/boot_cpu.c" #include "driving_clk_phase_data.c" @@ -573,7 +571,7 @@ unsigned v_esp; __asm__ volatile ("movl %%esp, %0\n\t":"=a" (v_esp) ); -#if CONFIG_USE_INIT +#if CONFIG_USE_PRINTK_IN_CAR printk(BIOS_DEBUG, "v_esp=%08x\r\n", v_esp); #else print_debug("v_esp="); @@ -589,7 +587,7 @@ // it seems that cpu_reset is not used before this, so I just reset it, (this is because the s3 resume, setting in mtrr and copy data may destroy //stack cpu_reset = 0; -#if CONFIG_USE_INIT +#if CONFIG_USE_PRINTK_IN_CAR printk(BIOS_DEBUG, "cpu_reset = %08x\r\n", cpu_reset); #else print_debug("cpu_reset = "); @@ -641,7 +639,7 @@ } else { print_debug("Use Ram as Stack now - \r\n"); } -#if CONFIG_USE_INIT +#if CONFIG_USE_PRINTK_IN_CAR printk(BIOS_DEBUG, "new_cpu_reset = %08x\r\n", new_cpu_reset); #else print_debug("new_cpu_reset = ");

9 years, 8 months

1
0
0 0

[PATCH] unify arch/i386/lib/console.c and console/console.c

by Stefan Reinauer

One step closer to a single place of console functions in coreboot. Sorry for the other stuff that sneaked in. -- coresystems GmbH • Brahmsstr. 16 • D-79104 Freiburg i. Br. Tel.: +49 761 7668825 • Fax: +49 761 7664613 Email: info(a)coresystems.de • http://www.coresystems.de/ Registergericht: Amtsgericht Freiburg • HRB 7656 Geschäftsführer: Stefan Reinauer • Ust-IdNr.: DE245674866

9 years, 8 months

2
1
0 0

build service results for r5340

by coreboot information

Dear coreboot readers! This is the automatic build system of coreboot. The developer "stepan" checked in revision 5340 to the coreboot repository. This caused the following changes: Change Log: mini part of the patch on the mailing list to fix the boards again Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Build Log: Compilation of a-trend:atc-6220 has been fixed Compilation of a-trend:atc-6240 has been fixed Compilation of abit:be6-ii_v2_0 has been fixed Compilation of advantech:pcm-5820 has been fixed Compilation of amd:db800 has been fixed Compilation of amd:dbm690t has been fixed Compilation of amd:mahogany has been fixed Compilation of amd:mahogany_fam10 has been fixed Compilation of amd:norwich has been fixed Compilation of amd:pistachio has been fixed Compilation of amd:rumba has been fixed Compilation of amd:serengeti_cheetah has been fixed Compilation of amd:serengeti_cheetah_fam10 has been fixed Compilation of arima:hdama has been fixed Compilation of artecgroup:dbe61 has been fixed Compilation of asi:mb_5blgp has been fixed Compilation of asi:mb_5blmp has been fixed Compilation of asus:a8n_e has been fixed Compilation of asus:a8v-e_se has been fixed Compilation of asus:m2v-mx_se has been fixed Compilation of asus:mew-am has been fixed Compilation of asus:mew-vm has been fixed Compilation of asus:p2b has been fixed Compilation of asus:p2b-d is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5340&device=p2b-d&vendor... Compilation of asus:p2b-ds is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5340&device=p2b-ds&vendo... Compilation of asus:p2b-f has been fixed Compilation of asus:p2b-ls has been fixed Compilation of asus:p3b-f has been fixed Compilation of axus:tc320 has been fixed Compilation of azza:pt-6ibd has been fixed Compilation of bcom:winnet100 has been fixed Compilation of bcom:winnetp680 has been fixed Compilation of biostar:m6tba has been fixed Compilation of broadcom:blast has been fixed Compilation of compaq:deskpro_en_sff_p600 has been fixed Compilation of dell:s1850 has been fixed Compilation of digitallogic:adl855pc has been fixed Compilation of digitallogic:msm586seg has been fixed Compilation of digitallogic:msm800sev has been fixed Compilation of eaglelion:5bcm has been fixed Compilation of emulation:qemu-x86 has been fixed Compilation of gigabyte:ga-6bxc has been fixed Compilation of gigabyte:ga_2761gxdk has been fixed Compilation of gigabyte:m57sli has been fixed Compilation of hp:dl145_g3 has been fixed Compilation of hp:e_vectra_p2706t has been fixed Compilation of ibm:e325 has been fixed Compilation of ibm:e326 has been fixed Compilation of iei:juki-511p has been fixed Compilation of iei:nova4899r has been fixed Compilation of iei:pcisa-lx-800-r10 has been fixed Compilation of intel:d945gclf has been fixed Compilation of intel:eagleheights has been fixed Compilation of intel:jarrell has been fixed Compilation of intel:mtarvon has been fixed Compilation of intel:truxton has been fixed Compilation of intel:xe7501devkit has been fixed Compilation of iwill:dk8_htx has been fixed Compilation of iwill:dk8s2 has been fixed Compilation of iwill:dk8x has been fixed Compilation of jetway:j7f24 has been fixed Compilation of kontron:986lcd-m has been fixed Compilation of kontron:kt690 has been fixed Compilation of lippert:frontrunner has been fixed Compilation of lippert:roadrunner-lx has been fixed Compilation of lippert:spacerunner-lx has been fixed Compilation of mitac:6513wu has been fixed Compilation of msi:ms6119 has been fixed Compilation of msi:ms6147 has been fixed Compilation of msi:ms6156 has been fixed Compilation of msi:ms6178 has been fixed Compilation of msi:ms7135 has been fixed Compilation of msi:ms7260 has been fixed Compilation of msi:ms9185 has been fixed Compilation of msi:ms9282 has been fixed Compilation of msi:ms9652_fam10 has been fixed Compilation of nec:powermate2000 has been fixed Compilation of newisys:khepri has been fixed Compilation of nvidia:l1_2pvv has been fixed Compilation of olpc:btest has been fixed Compilation of olpc:rev_a has been fixed Compilation of pcengines:alix1c has been fixed Compilation of rca:rm4100 has been fixed Compilation of roda:rk886ex has been fixed Compilation of soyo:sy-6ba-plus-iii has been fixed Compilation of sunw:ultra40 has been fixed Compilation of supermicro:h8dme has been fixed Compilation of supermicro:h8dmr has been fixed Compilation of supermicro:h8dmr_fam10 has been fixed Compilation of supermicro:h8qme_fam10 has been fixed Compilation of supermicro:x6dai_g has been fixed Compilation of supermicro:x6dhe_g has been fixed Compilation of supermicro:x6dhe_g2 has been fixed Compilation of supermicro:x6dhr_ig has been fixed Compilation of supermicro:x6dhr_ig2 has been fixed Compilation of technexion:tim5690 has been fixed Compilation of technexion:tim8690 has been fixed Compilation of technologic:ts5300 has been fixed Compilation of televideo:tc7020 has been fixed Compilation of thomson:ip1000 has been fixed Compilation of tyan:s1846 has been fixed Compilation of tyan:s2735 has been fixed Compilation of tyan:s2850 has been fixed Compilation of tyan:s2875 has been fixed Compilation of tyan:s2880 has been fixed Compilation of tyan:s2881 has been fixed Compilation of tyan:s2882 has been fixed Compilation of tyan:s2885 has been fixed Compilation of tyan:s2891 has been fixed Compilation of tyan:s2892 has been fixed Compilation of tyan:s2895 has been fixed Compilation of tyan:s2912 has been fixed Compilation of tyan:s2912_fam10 has been fixed Compilation of tyan:s4880 has been fixed Compilation of tyan:s4882 has been fixed Compilation of via:epia has been fixed Compilation of via:epia-cn has been fixed Compilation of via:epia-m has been fixed Compilation of via:epia-m700 has been fixed Compilation of via:epia-n has been fixed Compilation of via:pc2500e has been fixed Compilation of via:vt8454c has been fixed Compilation of winent:pl6064 has been fixed If something broke during this checkin please be a pain in stepan's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

9 years, 8 months

1
0
0 0

build service results for r5339

by coreboot information

9 years, 8 months

1
0
0 0

[commit] r5340 - trunk/src/include/console

by repository service

Author: stepan Date: Wed Mar 31 02:06:12 2010 New Revision: 5340 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5340 Log: mini part of the patch on the mailing list to fix the boards again Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/src/include/console/console.h Modified: trunk/src/include/console/console.h ============================================================================== --- trunk/src/include/console/console.h Wed Mar 31 00:21:06 2010 (r5339) +++ trunk/src/include/console/console.h Wed Mar 31 02:06:12 2010 (r5340) @@ -4,6 +4,7 @@ #include <stdint.h> #include <console/loglevel.h> +#ifndef __PRE_RAM__ void console_init(void); void console_tx_byte(unsigned char byte); void console_tx_flush(void); @@ -11,6 +12,9 @@ int console_tst_byte(void); void post_code(uint8_t value); void __attribute__ ((noreturn)) die(const char *msg); +#if CONFIG_CONSOLE_VGA == 1 +void vga_console_init(void); +#endif struct console_driver { void (*init)(void); @@ -27,6 +31,8 @@ extern struct console_driver econsole_drivers[]; extern int console_loglevel; +#endif /* !__PRE_RAM__ */ + int do_printk(int msg_level, const char *fmt, ...) __attribute__((format(printf, 2, 3))); #undef WE_CLEANED_UP_ALL_SIDE_EFFECTS @@ -110,8 +116,4 @@ #define print_debug_hex32(HEX) printk(BIOS_DEBUG, "%08x", (HEX)) #define print_spew_hex32(HEX) printk(BIOS_SPEW, "%08x", (HEX)) -#if CONFIG_CONSOLE_VGA == 1 -void vga_console_init(void); -#endif - #endif /* CONSOLE_CONSOLE_H_ */

9 years, 8 months

1
0
0 0

build service results for r5338

by coreboot information

9 years, 8 months

1
0
0 0

build service results for r5337

by coreboot information

9 years, 8 months

1
0
0 0

2019

2018

2017

2016

2015

2014

2013

2012

2011

2010

2009

2008

2007

2006

2005

2004

2003

2002

coreboot March 2010