coreboot March 2010

coreboot@coreboot.org

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434 discussions

[patch] Buildrom support for Asus M2V-MX SE
by Cristi Magherusan 18 Apr '10

18 Apr '10

Here's the patch: http://panzer.utcluj.ro/cgi-bin/cgit.cgi/avatt/patch/?id=1f45b765097fd8ba21… Signed-off by: Cristi Măgherușan <cristi.magherusan(a)net.utcluj.ro> I'm unable to say which others may worth it, but someone who's interested by buildrom can also cherry-pick some changesets/patches from my git repos at http://panzer.utcluj.ro/cgi-bin/cgit.cgi/ and include them in the main buildrom repo. A few of them are merged in the buildrom repo, while others are still in AVATT (I'm using braid to track my buildrom repo from AVATT, so it's easy to do it), but they will be merged eventually when I have some spare time.. From 1f45b765097fd8ba2139a078bd57679e16ac4699 Mon Sep 17 00:00:00 2001 From: Cristi Măgherușan <cristi.magherusan(a)net.utcluj.ro> Date: Thu, 16 Jul 2009 18:16:13 +0000 Subject: Added support for my Asus M2V-MX SE --- diff --git a/buildrom/buildrom-devel/config/platforms/Config.in b/buildrom/buildrom-devel/config/platforms/Config.in index e8a0a8b..1fa6a12 100644 --- a/buildrom/buildrom-devel/config/platforms/Config.in +++ b/buildrom/buildrom-devel/config/platforms/Config.in @@ -104,6 +104,13 @@ config PLATFORM_ASUS_A8N_E select PLATFORM select PLATFORM_SUPPORT_64BIT +config PLATFORM_ASUS_M2V_MX_SE + bool "ASUS M2V-MX SE" + depends on VENDOR_ASUS + depends on COREBOOT_V2 + select PLATFORM + select PLATFORM_SUPPORT_64BIT + config PLATFORM_GA_2761GXDK bool "GIGABYTE GA-2761GXDK" depends on VENDOR_GIGABYTE diff --git a/buildrom/buildrom-devel/config/platforms/asus_m2v-mx_se.conf b/buildrom/buildrom-devel/config/platforms/asus_m2v-mx_se.conf new file mode 100644 index 0000000..a78863e --- a/dev/null +++ b/buildrom/buildrom-devel/config/platforms/asus_m2v-mx_se.conf @@ -0,0 +1,28 @@ +# Support for the ASUS A8V-E SE board + +#### Platform configuration + +ifeq ($(CONFIG_TARGET_64BIT),y) +TARGET_ARCH=x86_64 +CFLAGS_platform = +else +TARGET_ARCH=i686 +CFLAGS_platform = +endif + +# kernel configuration (for LAB) + +# TODO + +UCLIBC_ARCH=$(TARGET_ARCH) + +# Etherboot configuration + +ETHERBOOT_ARCH=i386 + +# coreboot configuration + +COREBOOT_VENDOR=asus +COREBOOT_BOARD=m2v-mx_se +CBV2_TDIR=m2v-mx_se +CBV2_TAG=4426 diff --git a/buildrom/buildrom-devel/config/platforms/platforms.conf b/buildrom/buildrom-devel/config/platforms/platforms.conf index 733ca73..f5f62f8 100644 --- a/buildrom/buildrom-devel/config/platforms/platforms.conf +++ b/buildrom/buildrom-devel/config/platforms/platforms.conf @@ -23,6 +23,7 @@ PLATFORM-$(CONFIG_PLATFORM_DBE61) = dbe61.conf PLATFORM-$(CONFIG_PLATFORM_GA_M57SLI_S4) = m57sli.conf PLATFORM-$(CONFIG_PLATFORM_ASUS_A8V_E_SE) = asus_a8v-e_se.conf PLATFORM-$(CONFIG_PLATFORM_ASUS_A8N_E) = asus_a8n-e.conf +PLATFORM-$(CONFIG_PLATFORM_ASUS_M2V_MX_SE) = asus_m2v-mx_se.conf PLATFORM-$(CONFIG_PLATFORM_TYAN_S2881) = tyan-s2881.conf PLATFORM-$(CONFIG_PLATFORM_TYAN_S2882) = tyan-s2882.conf PLATFORM-$(CONFIG_PLATFORM_TYAN_S2891) = tyan-s2891.conf -- Ing. Cristi Măgherușan, System/Network Engineer Technical University of Cluj-Napoca, Romania http://cc.utcluj.ro +40264 401247

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#108: Add int 10 VESA video driver to libpayload
by coreboot 15 Apr '10

15 Apr '10

#108: Add int 10 VESA video driver to libpayload ---------------------------------+------------------------------------------ Reporter: stuge | Owner: somebody Type: enhancement | Status: new Priority: major | Milestone: Component: libpayload | Version: Keywords: video | Dependencies: Patchstatus: there is no patch | ---------------------------------+------------------------------------------ -- Ticket URL: <http://tracker.coreboot.org/trac/coreboot/ticket/108> coreboot <http://www.coreboot.org/>

1 1

#129: Add support for high_tables_base for all chipsets that don't support it yet.
by coreboot 15 Apr '10

15 Apr '10

#129: Add support for high_tables_base for all chipsets that don't support it yet. ---------------------------------+------------------------------------------ Reporter: oxygene | Owner: somebody Type: defect | Status: new Priority: critical | Milestone: Component: coreboot | Version: v2 Keywords: | Dependencies: Patchstatus: there is no patch | ---------------------------------+------------------------------------------ Without tables in high memory, seabios won't run on your chipset properly. it overwrites your tables in the F segment, as seabios itself lives there. Also, once there is support for high_tables_base everywhere, the code in src/arch/i386/boot/tables.c can be cleaned up and simplified considerably. -- Ticket URL: <http://tracker.coreboot.org/trac/coreboot/ticket/129> coreboot <http://www.coreboot.org/>

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#139: flashrom: -c option should be case insensitive
by coreboot 15 Apr '10

15 Apr '10

#139: flashrom: -c option should be case insensitive ---------------------------------+------------------------------------------ Reporter: uwe | Owner: somebody Type: enhancement | Status: new Priority: minor | Milestone: Component: flashrom | Version: Keywords: | Dependencies: Patchstatus: there is no patch | ---------------------------------+------------------------------------------ flashrom's -c option requires you to enter extact chip names. It should probably be case insensitive for easier usage. -- Ticket URL: <http://tracker.coreboot.org/trac/coreboot/ticket/139> coreboot <http://www.coreboot.org/>

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#148: Component defaults to adlo for new tickets in the tracker
by coreboot 15 Apr '10

15 Apr '10

#148: Component defaults to adlo for new tickets in the tracker ------------------------------------+--------------------------------------- Reporter: stuge | Owner: somebody Type: defect | Status: new Priority: minor | Milestone: Component: wiki/website/tracker | Version: v2 Keywords: | Dependencies: Patchstatus: there is no patch | ------------------------------------+--------------------------------------- Maybe coreboot would be better -- Ticket URL: <http://tracker.coreboot.org/trac/coreboot/ticket/148> coreboot <http://www.coreboot.org/>

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#150: AMD DB800 dev board PLL strapping leaves CPU and GLIU in non-optimal clock
by coreboot 15 Apr '10

15 Apr '10

#150: AMD DB800 dev board PLL strapping leaves CPU and GLIU in non-optimal clock -------------------------------------------+-------------------------------- Reporter: edwin_beasant@… | Owner: somebody Type: enhancement | Status: new Priority: minor | Milestone: Component: coreboot | Version: v2 Keywords: | Dependencies: Patchstatus: patch needs review | -------------------------------------------+-------------------------------- The AMD DB800 board PLL strappings are left open as supplied, and leave the CPU/Memory in the sub-optimal 400MHz CPU,266MHz GLIU configuration. This requires a manual PLL strapping to achieve 500Mhz CPU and 400MHz GLIU as is normally used in the dev-kits (and the commercial GeodeRom). These are the correct (manual) strappings for a DB800: #define PLLMSRhi 0x000005DD #define PLLMSRlo 0x00DE60EE Patch attached. -- Ticket URL: <http://tracker.coreboot.org/trac/coreboot/ticket/150> coreboot <http://www.coreboot.org/>

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#156: Add Layout File capability to v3 and LAR tool
by coreboot 15 Apr '10

15 Apr '10

#156: Add Layout File capability to v3 and LAR tool --------------------------------------------+------------------------------- Reporter: edwin_beasant@… | Owner: stepan@… Type: enhancement | Status: new Priority: major | Milestone: Component: coreboot | Keywords: flashrom lar layout image v3 Dependencies: | Patchstatus: patch needs review --------------------------------------------+------------------------------- This patch adds the ability to specify a layout file within the v3 Kconfig menu system, and then to enable LAR to read and setup a flash image with respect to this layout file. This operates by padding the blank space with '(padding)' images, using a similar method to the zero padding that LAR uses to finalise an image. I have also included the patch to optionally disable fallback booting: this speeds things up a bit on the DB800 board which seems to have RTC byte read/write issues somewhere... The layout file format is the same as current flashrom. It also allows addition/specification of the VSA within the Kconfig setup for Geode targets, which will then be added to the LAR in a sensible place. Example tested layout for 49LF008A device: 00000000:0003ffff fallback 00040000:0004ffff vsa 00050000:0008ffff normal 000f0000:000f0000 bootblock Note that the fallback image is 'below' the normal image: This allows for the fallback image to be 'golden': if you repeatedly flash the only the 'normal' area, you will always have a working accessible VSA and fallback image if the normal flash fails. This does not prevent you from flashing the fallback image (just ba cautious)... This has been tested as working on the Zoom DB800 development platform. Comments and review please! -- Ticket URL: <http://tracker.coreboot.org/trac/coreboot/ticket/156> coreboot <http://www.coreboot.org/>

1 4

#157: utils/inteltool has outdated pciutils check in Makefile
by coreboot 15 Apr '10

15 Apr '10

#157: utils/inteltool has outdated pciutils check in Makefile --------------------------+------------------------------------------------- Reporter: anonymous | Owner: stepan@… Type: defect | Status: new Priority: minor | Milestone: Component: misc | Keywords: Dependencies: | Patchstatus: there is no patch --------------------------+------------------------------------------------- The current test compile bails out with: undefined reference to `pci_alloc' If i simply remove the test inteltool compiles and runs as expected. -- Ticket URL: <http://tracker.coreboot.org/trac/coreboot/ticket/157> coreboot <http://www.coreboot.org/>

1 2

#158: buildrom svn error
by coreboot 15 Apr '10

15 Apr '10

#158: buildrom svn error --------------------------------------------+------------------------------- Reporter: vibert <vib_chr@…> | Owner: stepan@… Type: defect | Status: new Priority: major | Milestone: Component: coreboot | Keywords: Dependencies: | Patchstatus: there is no patch --------------------------------------------+------------------------------- Hello, I have an error when I build buildrom:svn missing. How to correct the problem, thank you. -- Ticket URL: <http://tracker.coreboot.org/trac/coreboot/ticket/158> coreboot <http://www.coreboot.org/>

1 1

#159: Fails to build working ROM for IP1000
by coreboot 15 Apr '10

15 Apr '10

#159: Fails to build working ROM for IP1000 --------------------------+------------------------------------------------- Reporter: anonymous | Owner: stepan@… Type: defect | Status: new Priority: major | Milestone: Component: coreboot | Keywords: Dependencies: | Patchstatus: there is no patch --------------------------+------------------------------------------------- Following default directions to build coreboot results in ROM image that fails to run FILO or boot Linux on IP1000T board. -- Ticket URL: <https://tracker.coreboot.org/trac/coreboot/ticket/159> coreboot <http://www.coreboot.org/>

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coreboot March 2010