coreboot March 2010

coreboot@coreboot.org

61 participants
434 discussions

workaround for mahogany_fam10. Not a signed-off-by
by Bao, Zheng 11 Sep '10

11 Sep '10

This is for the mahogany_fam10 I just sent. It is not a signed-off-by patch. We need to work it out about this problem. Index: src/northbridge/amd/amdht/h3finit.c =================================================================== --- src/northbridge/amd/amdht/h3finit.c (revision 4521) +++ src/northbridge/amd/amdht/h3finit.c (working copy) @@ -1104,6 +1104,7 @@ AmdPCIRead(currentPtr, &temp); } while (!IS_HT_SLAVE_CAPABILITY(temp)); +#if (CONFIG_HT_CHAIN_UNITID_BASE != 0) AmdPCIReadBits(currentPtr, 25, 21, &unitIDcnt); if ((unitIDcnt + currentBUID > 31) || ((secBus == 0) && (unitIDcnt + currentBUID > 24))) { @@ -1145,7 +1146,7 @@ STOP_HERE; break; } - +#endif AmdPCIReadBits(currentPtr, 26, 26, &temp); pDat->PortList[pDat->TotalLinks*2+1].Link = (u8)temp; pDat->PortList[pDat->TotalLinks*2+1].Pointer = currentPtr; @@ -1156,6 +1157,11 @@ depth++; pDat->TotalLinks++; currentBUID += unitIDcnt; +#if CONFIG_HT_CHAIN_UNITID_BASE == 0 + STOP_HERE; + break; +#endif + } if (pDat->HtBlock->AMD_CB_EventNotify) {

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filo and usb boot
by Masoud Fatollahy 18 Aug '10

18 Aug '10

Hi, Why is it problem to boot from an usb port when we are using linuxbios and filo. as I can see all usb code are there, what is missing? Thanks, /Masoud

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#154: Flashing BIOSes from Fujitsu/Siemens is not supported
by coreboot 25 Jul '10

25 Jul '10

#154: Flashing BIOSes from Fujitsu/Siemens is not supported ---------------------------------------+------------------------------------ Reporter: johannesobermayr@… | Owner: carldani Type: enhancement | Status: new Priority: major | Milestone: Component: flashrom | Version: Keywords: | Dependencies: Patchstatus: there is no patch | ---------------------------------------+------------------------------------ As summary says I cannot flash BIOSes provided by Fujitsu/Siemens. You can see BIOS architecture from Fujitsu/Siemens if you download for example this BIOS package (for D1326): http://dl- extern3.treiberupdate.de/download2/123525.EXE I also could not find a suitable converter... -- Ticket URL: <http://tracker.coreboot.org/trac/coreboot/ticket/154> coreboot <http://www.coreboot.org/>

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#134: flashrom crashes acer aspire one laptop
by coreboot 23 Jul '10

23 Jul '10

#134: flashrom crashes acer aspire one laptop -----------------------------------------------------------+---------------- Reporter: Timo Juhani Lindfors <timo.lindfors@…> | Owner: somebody Type: defect | Status: new Priority: minor | Milestone: Component: flashrom | Version: v2 Keywords: aspire laptop | Dependencies: Patchstatus: there is no patch | -----------------------------------------------------------+---------------- I ran the "flashrom" command on my acer aspire one laptop. The display turned black and the system did not respond to even sysrq after that. (Fortunately the system boots after powercycling.) This is debian stable with flashrom package that has version "0.0+r3397-1". -- Ticket URL: <http://tracker.coreboot.org/trac/coreboot/ticket/134> coreboot <http://www.coreboot.org/>

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Re: [coreboot] SeaBIOS and hp dl145g3
by Kevin O'Connor 26 May '10

26 May '10

On Wed, Apr 29, 2009 at 04:53:13PM +0200, samuel wrote: > Hi Kevin, > > I have tried Seabios on my hp dl145 g3 (the patches from mondrian) and > it works really well now > I was able to load the vga rom and i have output on the screen. Great! > One single problem... It doesn't seem to find the sata controller... > > bootlog with coreboot and seabios: > http://merlin.ugent.be/~samuel/dl145g3/corebootwithseabios.log There isn't much SeaBIOS info in that log - can you recompile with CONFIG_DEBUG_LEVEL set to 6? > > lspci -vnn : http://merlin.ugent.be/~samuel/dl145g3/info/lspci-vnn.txt > > and the original patch from mondrian to add support for the dl145g3 to filo: > http://merlin.ugent.be/~samuel/dl145g3/patch/filo_dl145_sata.patch > > It looks rather simple but I don't see what i have to change in > seabios to support the device. > > The pci id (0x104 is already in pci_ids.h of seabios) so i would think > it should just work. Myles thought it could be related to the fact > that his sata interface of this mainboard does not support a legacy > IDE interface mode. > > You have any ideas how i could quickly add support for the hp dl145 g3 > to SeaBIOS?? The equivalent patch in SeaBIOS would look like: --- a/src/ata.c +++ b/src/ata.c @@ -841,7 +845,8 @@ ata_init() int count=0; int bdf, max; foreachpci(bdf, max) { - if (pci_config_readw(bdf, PCI_CLASS_DEVICE) != PCI_CLASS_STORAGE_IDE) + u16 class = pci_config_readw(bdf, PCI_CLASS_DEVICE); + if (class != PCI_CLASS_STORAGE_IDE && class != PCI_CLASS_STORAGE_RAID) continue; if (count >= ARRAY_SIZE(ATA.channels)) break; -Kevin

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#146: memalign faild with 4k boundary
by coreboot 05 May '10

05 May '10

#146: memalign faild with 4k boundary -------------------------------------+-------------------------------------- Reporter: wangqingpei@… | Owner: somebody Type: defect | Status: new Priority: blocker | Milestone: Component: libpayload | Version: v2 Keywords: memalign crashed | Dependencies: Patchstatus: there is no patch | -------------------------------------+-------------------------------------- with libpayload/libc/malloc.c memalign, it crash if tring to memalign with 4kb about 4k boundary -- Ticket URL: <http://tracker.coreboot.org/trac/coreboot/ticket/146> coreboot <http://www.coreboot.org/>

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#153: resume from suspend on epia-m
by coreboot 03 May '10

03 May '10

#153: resume from suspend on epia-m ---------------------------------------+------------------------------------ Reporter: bam <mybigspam@…> | Owner: stepan Type: defect | Status: new Priority: major | Milestone: Component: coreboot | Version: v2 Keywords: s3 suspend epia | Dependencies: Patchstatus: there is no patch | ---------------------------------------+------------------------------------ When I enter suspend mode from linux, the board suspends, but the led is stayed on instead of blinking. On waking up (on button or wol) the board reboots.[[BR]] I've follow instructions in [http://www.coreboot.org/VIA_EPIA-M#Advanced_ACPI] on changing dsdt.c. -- Ticket URL: <http://tracker.coreboot.org/trac/coreboot/ticket/153> coreboot <http://www.coreboot.org/>

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#142: remove #warnings in the code
by coreboot 03 May '10

03 May '10

#142: remove #warnings in the code ---------------------------------+------------------------------------------ Reporter: myles | Owner: somebody Type: defect | Status: new Priority: major | Milestone: Component: coreboot | Version: v2 Keywords: | Dependencies: Patchstatus: there is no patch | ---------------------------------+------------------------------------------ #warnings in the code should be converted to tickets in trac, or fixed. Compiler warnings don't seem to be useful to get things fixed. They also obscure real warnings. The medium-term goal would be to have warning-free compilation. After that -Werror would be nice. It seems like a small thing to ask that code compile without warnings. -- Ticket URL: <http://tracker.coreboot.org/trac/coreboot/ticket/142> coreboot <http://www.coreboot.org/>

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[PATCH] RAMTOP fixes
by Myles Watson 27 Apr '10

27 Apr '10

I think we should clean up memory allocation. There are multiple places in the code where RAMTOP is used as an offset into ram and cast to a struct. I think if something is important enough that it needs to be allocated separately from the stack, it should show up in the ldscripts, not just in the code. What's important enough? K8 page tables for APs? EHCI debug? Sysinfo structs? Signed-off-by: Myles Watson <mylesgw(a)gmail.com> Thanks, Myles

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#149: AMD DB800 Hangs at "Decompressing Coreboot to Ram"
by coreboot 20 Apr '10

20 Apr '10

#149: AMD DB800 Hangs at "Decompressing Coreboot to Ram" -------------------------------------------+-------------------------------- Reporter: edwin_beasant@… | Owner: somebody Type: defect | Status: new Priority: major | Milestone: Component: coreboot | Version: v2 Keywords: | Dependencies: Patchstatus: patch needs review | -------------------------------------------+-------------------------------- A vanilla build of r4971 appears to hang at the "Decompressing Coreboot to Ram" message when run on the Zoom DB800 development board. After tearing this down, it appears that the code pre "call cbfs_and_run_core" (and post done_cache_as ram_main) in cache_as_ram.inc for the geode appears to have gained some code from the crt0.S.lb generic i386 infrastructure. From the end of "done_cache_as_ram_main" to the point of calling cbfs_and_run_core appears to attempt to "reset" the stack after flushing the cache. This causes the subsequent calls to printk_debug() (or related functions) to fail. (CONSOLE_DEBUG_TX_STRING would also appear to not clean up after itself) Solution is to leave the stack as is until the copy to ram has completed. Patch attached as tested working on Zoom AMD DB800 board, 256MB of RAM, 1024k Flash (SST 49LF008A). -- Ticket URL: <http://tracker.coreboot.org/trac/coreboot/ticket/149> coreboot <http://www.coreboot.org/>

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coreboot March 2010