I am trying to setup Smartlink/Revnetek DBE61 to boot from LAN.
I am following this tutorial: http://wiki.thincan.org/Building_Coreboot_v3
Which Coreboot v3 revision should I use?
I plan on building Etherboot payload with Rom-o-matic.
Which Etherboot version must I use as a payload?
[resent from different email address]
BTW, I'm <paul(a)astro.gla.ac.uk> and also <paul.millar(a)desy.de>. Both
addresses will work, but I try to keep the DESY account for work stuff. I'm
also subscribed to the coreboot mailing list, but I'm not always up-to-date
with the latest developments :)
On Sunday 07 March 2010 21:47:21 Carl-Daniel Hailfinger wrote:
> I'm one of the developers of flashrom <http://www.flashrom.org/> which
> aims to be a generic utility for programming all kinds of flash EEPROMs
> on your mainboard, on storage/network/graphics cards, and in external
> There is some interest in integrating parts of your firebrand code to
> support a Willem backend/driver for flashrom. Would that be OK with you?
> flashrom is GPLv2.
I think that's an excellent idea. The code-base is available under LGPL v2.1
and was written with as a library to facilitate people using it in their own
software. That said, I believe the supplied CLI tool is the only code that
links against the library, so if the API proves problematic, we can try to
adjust it to match.
Incidentally, the project is now also available from the SVN repository here:
Google Summer of Code 2010 is approaching quickly. I hope
coreboot/flashrom are going to participate again, and to do that, we
have to apply between 2010-03-08 and 2010-03-12 (March 8 - March 12).
Do we want to participate?
Who is willing to mentor?
Any developers who want to apply as students?
Who will serve as organization administrator?
Are there any good ideas for GSoC (coreboot or flashrom)?
On 3/8/10 10:48 PM, Karl-Heinz Nirschl wrote:
> i've just compiled the crossgcc. but how do i make the build system
> use it. is there a coreboot way of doing it?
coreboot should just pick it up... the script util/xcompile/xcompile
should create an according .xcompile file in the coreboot root directory
(Hm, this message seems to not have made it through. Resending...)
I've just recently brought my development environment up to speed with
the latest coreboot version -- which is very nice! -- and caught a
couple of minor issues. I'm not sure I fully understand the underlying
logic behind the different CAR setup routines in
src/cpu/amd/car/cache_as_ram.inc, but the attached patch is required to
make the S2912 board choose the correct code path. I've also upped the
MAX_CPUS setting to 12 to accommodate 6-core Istanbul CPUs. This might
make sense for other fam10 boards as well.
Signed-off-by: Arne Georg Gleditsch <arne.gleditsch(a)numascale.com>
On 3/8/10 9:45 PM, Karl-Heinz Nirschl wrote:
> thanks for your reply. i thought
> src/northbridge/intel/i945/early_init.c is executed after stage1_main
> somewhere in real main. i've put a lot of postcodes bevor that
> - one in front of stage1_main and and one in real_main. shouldn't i see these?
>From your description I can't tell. But 0x23 is the last post code
before the call into stage1_main(). stage1_main() calls real_main()
which calls into early_init.c.,