coreboot March 2010

coreboot@coreboot.org

61 participants
434 discussions

[commit] r5190 - trunk/src/northbridge/intel/i945
by repository service 05 Mar '10

05 Mar '10

Author: stepan Date: Fri Mar 5 19:25:19 2010 New Revision: 5190 URL: http://tracker.coreboot.org/trac/coreboot/changeset/5190 Log: i945 mini patch: - don't skip the reset on S4 violations. Specs ask us to do this so we do it - hlt on waiting for reset instead of hot looping. Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/src/northbridge/intel/i945/raminit.c Modified: trunk/src/northbridge/intel/i945/raminit.c ============================================================================== --- trunk/src/northbridge/intel/i945/raminit.c Fri Mar 5 19:03:49 2010 (r5189) +++ trunk/src/northbridge/intel/i945/raminit.c Fri Mar 5 19:25:19 2010 (r5190) @@ -236,8 +236,9 @@ if (reg8 & ((1<<7)|(1<<2))) { if (reg8 & (1<<2)) { printk_debug("SLP S4# Assertion Width Violation.\n"); - + /* Write back clears bit 2 */ pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa2, reg8); + do_reset = 1; } @@ -257,7 +258,7 @@ printk_debug("Reset required.\n"); outb(0x00, 0xcf9); outb(0x0e, 0xcf9); - for (;;) ; /* Wait for reset! */ + for (;;) asm("hlt"); /* Wait for reset! */ } }

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[commit] r5189 - trunk/src/arch/i386/init
by repository service 05 Mar '10

05 Mar '10

Author: stepan Date: Fri Mar 5 19:03:49 2010 New Revision: 5189 URL: http://tracker.coreboot.org/trac/coreboot/changeset/5189 Log: Fix creation of coreboot.bootblock when -O2 is specified instead of -Os (4GB image issue). According to some GCC folks -Os should be considered a buggy and unreliable code path, so at least keep -O2 working. coreboot_ram is only 4KB bigger. Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/src/arch/i386/init/ldscript_fallback_cbfs.lb Modified: trunk/src/arch/i386/init/ldscript_fallback_cbfs.lb ============================================================================== --- trunk/src/arch/i386/init/ldscript_fallback_cbfs.lb Fri Mar 5 17:31:41 2010 (r5188) +++ trunk/src/arch/i386/init/ldscript_fallback_cbfs.lb Fri Mar 5 19:03:49 2010 (r5189) @@ -47,6 +47,7 @@ *(.rom.data); *(.init.rodata.*); *(.init.text); + *(.rodata); *(.rodata.*); *(.rom.data.*); . = ALIGN(16);

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Re: [coreboot] [PATCH] ASUS P2B-LS support, RAM detection for 440BX, add Slot 1 CPU, Microcode for Intel Tualatin CPUs
by Joseph Smith 05 Mar '10

05 Mar '10

On Fri, 05 Mar 2010 15:24:25 +0100, Stefan Reinauer <stepan(a)coresystems.de> wrote: > On 3/5/10 3:15 PM, Joseph Smith wrote: >> >> >> On Fri, 05 Mar 2010 13:04:27 +0000, Mark Marshall <mark.marshall(a)csr.com> >> wrote: >> >>> Joseph Smith wrote: >>> >>>> On 03/05/2010 03:03 AM, Mark Marshall wrote: >>>> >>>>> On 04/03/10 13:10, Joseph Smith wrote: >>>>> >>>>>> On 03/04/2010 07:38 AM, Joseph Smith wrote: >>>>>> >>>>>>> On 03/04/2010 07:30 AM, Uwe Hermann wrote: >>>>>>> >>>>>>>> On Thu, Mar 04, 2010 at 10:05:57AM +0000, Mark Marshall wrote: >>>>>>>> >>>>>>>>> On 03/03/10 04:19, Keith Hui wrote: >>>>>>>>> The first problem is that this motherboard only has three DIMM >>>>>>>>> slots. This means you have to set SDRAMC to something different; >>>>>>>>> 0x0103 works for me. >>>>>>>>> >>>>>>>>> >>>>>>>> Hm, seems to be determined by SDRAMPWR + MMCONFIG, and MMCONFIG >>>>>>>> seems to >>>>>>>> be a hardware-strap (so we can check it), but not sure about >>>>>>>> >>> SDRAMPWR. >>> >>>>>>>> >>>>>>>>> >>>>>> I think a simple SPD probe would work, if the correct value is >>>>>> >> returned >> >>>>>> you know you have memory in that slot, otherwise if 0xff is returned >>>>>> then no memory is present. Do this probe for as many slots as the 440 >>>>>> supports. Then set your registers based on that. >>>>>> >>>>> The issue here is the number of DIMM slots on the motherboard, not the >>>>> number of sticks in the slots. Some 440BX boards have four slots, > while >>>>> others only have three. >>>>> >>>>> MM >>>>> >>>>> >>>> That is fine. Then if 440bx datasheet says it supports 4 slots, then >>>> that should be the standard. >>>> >>>> >>> Please check this section of the 440BX data sheet. >>> >>> 3.3.24 SDRAMC—SDRAM Control Register (Device 0) >>> >>> We are interested in bit 4. >>> >>> SDRAMPWR. The SDRAMPWR bit controls how the CKE signals are driven >>> for different DRAM configurations. For a 3 DIMM configuration, >>> SDRAMPWR should be set to ‘0’. For a 4 DIMM configuration, >>> SDRAMPWR should be set to ‘1’. In this case the 82443BX drives a >>> single CKE signal (GCKE). The combination of SDRAMPWR and MMCONFIG >>> (DRAMC register) determine the functioning of the CKE signals. >>> Refer to the DRAMC register (Section 3.3.15, “DRAMC—DRAM >>> Control Register (Device 0)” on page 3-19) for more details. >>> >>> Note: When PCIRST# assertion occurs during POS/STR, these bits >>> are not reset to 0. >>> >>> As far as I can tell we cannot auto-detect this. Some (many) >>> 440BX boards only have three DIMM slots, and in these cases the >>> clocks are routed differently to the boards with four DIMM slots. >>> >>> >> That's easy... so you do something like this: >> >> slot4_detect = (spd_read_byte((DIMM_SPD_BASE + 3), SPD_MEMORY_TYPE); >> >> if (slot4_detect != 0xff) { >> >> /* We have 4 slots */ >> ----Set bit 4 in SDRAMPWR---- >> #define DIMM_SOCKETS 4 >> } else { >> >> /* We have 3 slots */ >> ----Set bit 4 in SDRAMPWR---- >> #define DIMM_SOCKETS 3 >> } >> >> Hope that helps. >> > > Will a mainboard with three modules but 4 slots work like this? Can > someone try? If we can autodetect it, we should. If we can't I think > encoding the number of slots in Kconfig is fine. > I think so, from what I understand the clocks are routed in a daisy chain so to speak. So if there is 4 physical slots and the system is only configured for three it should work ok. Also this routine will be determined at every start up so if you put a sdram module in the fourth slot it will be re-configured for 4 slots. Anyways the only way to know if this will work is to test it so can someone please test? Also, one could always use serialice on a 4 slot system with factory bios to see how they deterime it.... One could try a dump with three DIMMS and then a dump with four DIMMS and compare the results. -- Thanks, Joseph Smith Set-Top-Linux www.settoplinux.org

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Re: [coreboot] Supermicro H8QME-2+ mct_d fatal exit.
by Andrew Goodbody 05 Mar '10

05 Mar '10

Sorry, neglected to send original reply to list. Knut Kujat wrote: > Andrew Goodbody escribió: >> Knut Kujat wrote: >>> Any suggestions ? >> The vendor BIOS is doing some initialisation that coreboot is not. >> This init survives a short shutdown but is lost after a longer period >> without power. > Yes, vendor BIOS must be doing something different when initializing > ram. But why is coreboot working just fine up here in the lab even if I > let it unplugged the whole night next morning I plug it back on and it > works! Don't focus on that too much. It's probably to do with the environment, or even just coincidence. >> Is there a multiplexer on the SMBUS? > I honestly don't know, I have: A multiplexer on the SMBUS was just something that occurred to me. To find it you would need to actually use the SMBUS controller to scan the SMBUS for devices. This is not a trivial task but I think there may be tools out there to help you. A better approach would be to start by actually debugging what is going wrong in RAM init. That will tell you the area to investigate for differences. Andrew

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[commit] r5188 - in trunk/src/mainboard/asus: . p2b-ls
by repository service 05 Mar '10

05 Mar '10

Author: uwe Date: Fri Mar 5 17:31:41 2010 New Revision: 5188 URL: http://tracker.coreboot.org/trac/coreboot/changeset/5188 Log: Add support for the ASUS P2B-LS mainboard. Signed-off-by: Keith Hui <buurin(a)gmail.com> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Added: trunk/src/mainboard/asus/p2b-ls/ trunk/src/mainboard/asus/p2b-ls/Kconfig trunk/src/mainboard/asus/p2b-ls/chip.h trunk/src/mainboard/asus/p2b-ls/devicetree.cb trunk/src/mainboard/asus/p2b-ls/irq_tables.c trunk/src/mainboard/asus/p2b-ls/mainboard.c trunk/src/mainboard/asus/p2b-ls/romstage.c Modified: trunk/src/mainboard/asus/Kconfig Modified: trunk/src/mainboard/asus/Kconfig ============================================================================== --- trunk/src/mainboard/asus/Kconfig Fri Mar 5 17:18:38 2010 (r5187) +++ trunk/src/mainboard/asus/Kconfig Fri Mar 5 17:31:41 2010 (r5188) @@ -27,6 +27,7 @@ source "src/mainboard/asus/p2b/Kconfig" source "src/mainboard/asus/p2b-d/Kconfig" source "src/mainboard/asus/p2b-ds/Kconfig" +source "src/mainboard/asus/p2b-ls/Kconfig" source "src/mainboard/asus/p2b-f/Kconfig" source "src/mainboard/asus/p3b-f/Kconfig" source "src/mainboard/asus/m2v-mx_se/Kconfig" Added: trunk/src/mainboard/asus/p2b-ls/Kconfig ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/mainboard/asus/p2b-ls/Kconfig Fri Mar 5 17:31:41 2010 (r5188) @@ -0,0 +1,52 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2010 Keith Hui <buurin(a)gmail.com> +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +config BOARD_ASUS_P2B_LS + bool "P2B-LS" + select ARCH_X86 + select CPU_INTEL_SLOT_1 + select NORTHBRIDGE_INTEL_I440BX + select SOUTHBRIDGE_INTEL_I82371EB + select SUPERIO_WINBOND_W83977TF + select ROMCC + select HAVE_PIRQ_TABLE + select UDELAY_TSC + select BOARD_ROMSIZE_KB_256 + +config MAINBOARD_DIR + string + default asus/p2b-ls + depends on BOARD_ASUS_P2B_LS + +config MAINBOARD_PART_NUMBER + string + default "P2B-LS" + depends on BOARD_ASUS_P2B_LS + +config HAVE_OPTION_TABLE + bool + default n + depends on BOARD_ASUS_P2B_LS + +config IRQ_SLOT_COUNT + int + default 8 + depends on BOARD_ASUS_P2B_LS + Added: trunk/src/mainboard/asus/p2b-ls/chip.h ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/mainboard/asus/p2b-ls/chip.h Fri Mar 5 17:31:41 2010 (r5188) @@ -0,0 +1,22 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007 Uwe Hermann <uwe(a)hermann-uwe.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +extern struct chip_operations mainboard_ops; +struct mainboard_config {}; Added: trunk/src/mainboard/asus/p2b-ls/devicetree.cb ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/mainboard/asus/p2b-ls/devicetree.cb Fri Mar 5 17:31:41 2010 (r5188) @@ -0,0 +1,59 @@ +chip northbridge/intel/i440bx # Northbridge + device apic_cluster 0 on # APIC cluster + chip cpu/intel/slot_1 # CPU + device apic 0 on end # APIC + end + end + device pci_domain 0 on # PCI domain + device pci 0.0 on end # Host bridge + device pci 1.0 on end # PCI/AGP bridge + chip southbridge/intel/i82371eb # Southbridge + device pci 4.0 on # ISA bridge + chip superio/winbond/w83977tf # Super I/O (FIXME: It's W83977EF!) + device pnp 3f0.0 on # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 3f0.1 on # Parallel port + io 0x60 = 0x378 + irq 0x70 = 7 + end + device pnp 3f0.2 on # COM1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 3f0.3 on # COM2 / IR + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 3f0.5 on # PS/2 keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 # PS/2 keyboard interrupt + irq 0x72 = 12 # PS/2 mouse interrupt + end + device pnp 3f0.7 on # GPIO 1 + end + device pnp 3f0.8 on # GPIO 2 + end + device pnp 3f0.a on # ACPI + end + end + end + device pci 4.1 on end # IDE + device pci 4.2 on end # USB + device pci 4.3 on end # ACPI + device pci 6.0 on end # Onboard SCSI + device pci 7.0 on end # Onboard LAN + register "ide0_enable" = "1" + register "ide1_enable" = "1" + register "ide_legacy_enable" = "1" + # Enable UDMA/33 for higher speed if your IDE device(s) support it. + register "ide0_drive0_udma33_enable" = "0" + register "ide0_drive1_udma33_enable" = "0" + register "ide1_drive0_udma33_enable" = "0" + register "ide1_drive1_udma33_enable" = "0" + end + end +end Added: trunk/src/mainboard/asus/p2b-ls/irq_tables.c ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/mainboard/asus/p2b-ls/irq_tables.c Fri Mar 5 17:31:41 2010 (r5188) @@ -0,0 +1,54 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2010 Keith Hui <buurin(a)gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/pirq_routing.h> + +const struct irq_routing_table intel_irq_routing_table = { + PIRQ_SIGNATURE, + PIRQ_VERSION, + 32 + 16 * CONFIG_IRQ_SLOT_COUNT,/* Max. number of devices on the bus */ + 0x00, /* Interrupt router bus */ + (0x04 << 3) | 0x0, /* Interrupt router device */ + 0, /* IRQs devoted exclusively to PCI usage */ + 0x8086, /* Vendor */ + 0x122e, /* Device */ + 0, /* Miniport */ + { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */ + 0x10, /* Checksum (has to be set to some value that + * would give 0 after the sum of all bytes + * for this structure (including checksum). + */ + { + /* bus, dev | fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ + {0x00, (0x0c << 3) | 0x0, {{0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x1eb8}, {0x63, 0x1eb8}}, 0x1, 0x0}, + {0x00, (0x0b << 3) | 0x0, {{0x61, 0x1eb8}, {0x62, 0x1eb8}, {0x63, 0x1eb8}, {0x60, 0x1eb8}}, 0x2, 0x0}, + {0x00, (0x0a << 3) | 0x0, {{0x62, 0x1eb8}, {0x63, 0x1eb8}, {0x60, 0x1eb8}, {0x61, 0x1eb8}}, 0x3, 0x0}, + {0x00, (0x09 << 3) | 0x0, {{0x63, 0x1eb8}, {0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x1eb8}}, 0x4, 0x0}, + {0x00, (0x04 << 3) | 0x0, {{0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x1eb8}, {0x63, 0x1eb8}}, 0x0, 0x0}, + {0x00, (0x01 << 3) | 0x0, {{0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x1eb8}, {0x63, 0x1eb8}}, 0x0, 0x0}, + {0x00, (0x06 << 3) | 0x0, {{0x63, 0x1eb8}, {0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x1eb8}}, 0x0, 0x0}, + {0x00, (0x07 << 3) | 0x0, {{0x62, 0x1eb8}, {0x63, 0x1eb8}, {0x60, 0x1eb8}, {0x61, 0x1eb8}}, 0x0, 0x0}, + } +}; + +unsigned long write_pirq_routing_table(unsigned long addr) +{ + return copy_pirq_routing_table(addr); +} Added: trunk/src/mainboard/asus/p2b-ls/mainboard.c ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/mainboard/asus/p2b-ls/mainboard.c Fri Mar 5 17:31:41 2010 (r5188) @@ -0,0 +1,26 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007 Uwe Hermann <uwe(a)hermann-uwe.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <device/device.h> +#include "chip.h" + +struct chip_operations mainboard_ops = { + CHIP_NAME("ASUS P2B-LS Mainboard") +}; Added: trunk/src/mainboard/asus/p2b-ls/romstage.c ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/mainboard/asus/p2b-ls/romstage.c Fri Mar 5 17:31:41 2010 (r5188) @@ -0,0 +1,75 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007 Uwe Hermann <uwe(a)hermann-uwe.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#define ASSEMBLY 1 +#define __PRE_RAM__ + +#include <stdint.h> +#include <device/pci_def.h> +#include <arch/io.h> +#include <device/pnp_def.h> +#include <arch/romcc_io.h> +#include <arch/hlt.h> +#include <stdlib.h> +#include "pc80/serial.c" +#include "arch/i386/lib/console.c" +#include "lib/ramtest.c" +#include "southbridge/intel/i82371eb/i82371eb_enable_rom.c" +#include "southbridge/intel/i82371eb/i82371eb_early_smbus.c" +#include "northbridge/intel/i440bx/raminit.h" +#include "lib/debug.c" +#include "pc80/udelay_io.c" +#include "lib/delay.c" +#include "cpu/x86/mtrr/earlymtrr.c" +#include "cpu/x86/bist.h" +/* FIXME: The ASUS P2B-LS has a Winbond W83977EF, actually. */ +#include "superio/winbond/w83977tf/w83977tf_early_serial.c" + +#define SERIAL_DEV PNP_DEV(0x3f0, W83977TF_SP1) + +static inline int spd_read_byte(unsigned int device, unsigned int address) +{ + return smbus_read_byte(device, address); +} + +#include "northbridge/intel/i440bx/raminit.c" +#include "northbridge/intel/i440bx/debug.c" + +static void main(unsigned long bist) +{ + if (bist == 0) + early_mtrr_init(); + + /* FIXME: The ASUS P2B-LS has a Winbond W83977EF, actually. */ + w83977tf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + uart_init(); + console_init(); + report_bist_failure(bist); + + /* Enable access to the full ROM chip, needed very early by CBFS. */ + i82371eb_enable_rom(PCI_DEV(0, 4, 0)); /* ISA bridge at 00:04.0. */ + + enable_smbus(); + /* dump_spd_registers(); */ + sdram_set_registers(); + sdram_set_spd_registers(); + sdram_enable(); + /* ram_check(0, 640 * 1024); */ +}

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[commit] r5187 - in trunk/src/cpu/intel: . slot_1
by repository service 05 Mar '10

05 Mar '10

Author: uwe Date: Fri Mar 5 17:18:38 2010 New Revision: 5187 URL: http://tracker.coreboot.org/trac/coreboot/changeset/5187 Log: Add proper Slot 1 CPU support code/infrastructure. Signed-off-by: Keith Hui <buurin(a)gmail.com> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Added: trunk/src/cpu/intel/slot_1/ trunk/src/cpu/intel/slot_1/Kconfig trunk/src/cpu/intel/slot_1/Makefile.inc trunk/src/cpu/intel/slot_1/chip.h trunk/src/cpu/intel/slot_1/slot_1.c Modified: trunk/src/cpu/intel/Kconfig trunk/src/cpu/intel/Makefile.inc Modified: trunk/src/cpu/intel/Kconfig ============================================================================== --- trunk/src/cpu/intel/Kconfig Fri Mar 5 11:20:28 2010 (r5186) +++ trunk/src/cpu/intel/Kconfig Fri Mar 5 17:18:38 2010 (r5187) @@ -8,6 +8,7 @@ source src/cpu/intel/bga956/Kconfig source src/cpu/intel/ep80579/Kconfig source src/cpu/intel/slot_2/Kconfig +source src/cpu/intel/slot_1/Kconfig source src/cpu/intel/socket_mFCPGA478/Kconfig source src/cpu/intel/socket_mPGA478/Kconfig source src/cpu/intel/socket_mPGA479M/Kconfig Modified: trunk/src/cpu/intel/Makefile.inc ============================================================================== --- trunk/src/cpu/intel/Makefile.inc Fri Mar 5 11:20:28 2010 (r5186) +++ trunk/src/cpu/intel/Makefile.inc Fri Mar 5 17:18:38 2010 (r5187) @@ -13,6 +13,7 @@ subdirs-$(CONFIG_CPU_INTEL_SOCKET_MPGA604) += socket_mPGA604 subdirs-$(CONFIG_CPU_INTEL_SOCKET_PGA370) += socket_PGA370 subdirs-$(CONFIG_CPU_INTEL_SLOT_2) += slot_2 +subdirs-$(CONFIG_CPU_INTEL_SLOT_1) += slot_1 #socket_mPGA604_533Mhz #socket_mPGA604_800Mhz Added: trunk/src/cpu/intel/slot_1/Kconfig ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/cpu/intel/slot_1/Kconfig Fri Mar 5 17:18:38 2010 (r5187) @@ -0,0 +1,33 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2010 Keith Hui <buurin(a)gmail.com> +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +config CPU_INTEL_SLOT_1 + bool + +config DCACHE_RAM_BASE + hex + default 0xc0000 + depends on CPU_INTEL_SLOT_1 + +config DCACHE_RAM_SIZE + hex + default 0x01000 + depends on CPU_INTEL_SLOT_1 + Added: trunk/src/cpu/intel/slot_1/Makefile.inc ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/cpu/intel/slot_1/Makefile.inc Fri Mar 5 17:18:38 2010 (r5187) @@ -0,0 +1,29 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2009 Uwe Hermann <uwe(a)hermann-uwe.de> +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +obj-y += slot_1.o +subdirs-y += ../model_6xx +subdirs-y += ../../x86/tsc +subdirs-y += ../../x86/mtrr +subdirs-y += ../../x86/lapic +subdirs-y += ../../x86/cache +subdirs-y += ../../x86/smm +subdirs-y += ../microcode + Added: trunk/src/cpu/intel/slot_1/chip.h ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/cpu/intel/slot_1/chip.h Fri Mar 5 17:18:38 2010 (r5187) @@ -0,0 +1,24 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2010 Keith Hui <buurin(a)gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +extern struct chip_operations cpu_intel_slot_1_ops; + +struct cpu_intel_slot_1_config { +}; Added: trunk/src/cpu/intel/slot_1/slot_1.c ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/cpu/intel/slot_1/slot_1.c Fri Mar 5 17:18:38 2010 (r5187) @@ -0,0 +1,26 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2010 Keith Hui <buurin(a)gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <device/device.h> +#include "chip.h" + +struct chip_operations cpu_intel_slot_1_ops = { + CHIP_NAME("Slot 1 CPU") +};

1 0

[PATCH] ulzma delay
by Arne Georg Gleditsch 05 Mar '10

05 Mar '10

Hi, In the same way as unrv2b used to, ulzma exhibits very bad instruction fetch behavior on my Opteron CPUs/Tyan S2912 board. I'm not entirely sure what causes this, and despite having spent significant time digging through it I'm not able to mend this by adjusting MTRRs or other cache settings. So I've taken the easy route, and patched ulzma to copy LzmaDecode to the stack before executing. This brings running time for fallback stage uncompress from nearly two minutes to 50ms here. I'm also seeing weird performance behavior from memset -- this is not consistent, and just started appearing at some point in my development here. I assume this has something to do with alignment, but I was frankly not in the mood to start debugging this as well. I've included a patch that reduces memset to "rep stosb" under x86, which eliminates the worst-case behavior (in the order of minutes spent in cbfs_load_stage) I was seeing here. Signed-off-by: Arne Georg Gleditsch <arne.gleditsch(a)numascale.com> -- Arne.

1 0

[PATCH] Tyan S2912 Fam10
by Arne Georg Gleditsch 05 Mar '10

05 Mar '10

Hi all, I've just recently brought my development environment up to speed with the latest coreboot version -- which is very nice! -- and caught a couple of minor issues. I'm not sure I fully understand the underlying logic behind the different CAR setup routines in src/cpu/amd/car/cache_as_ram.inc, but the attached patch is required to make the S2912 board choose the correct code path. I've also upped the MAX_CPUS setting to 12 to accommodate 6-core Istanbul CPUs. This might make sense for other fam10 boards as well. Signed-off-by: Arne Georg Gleditsch <arne.gleditsch(a)numascale.com> -- Arne.

1 0

YABEL debug broken again
by Joseph Smith 05 Mar '10

05 Mar '10

Well it looks like YABEL debug is broken again..... util/x86emu/yabel/vbe.c:600: error: 'vbe_mode_info_t' has no member named 'attributes' util/x86emu/yabel/vbe.c:604: error: 'vbe_mode_info_t' has no member named 'attributes' util/x86emu/yabel/vbe.c:607: error: 'vbe_mode_info_t' has no member named 'attributes' util/x86emu/yabel/vbe.c:607: error: 'vbe_mode_info_t' has no member named 'attributes' util/x86emu/yabel/vbe.c:612: error: 'vbe_mode_info_t' has no member named 'attributes' util/x86emu/yabel/vbe.c:615: error: 'vbe_mode_info_t' has no member named 'attributes' util/x86emu/yabel/vbe.c:618: error: 'vbe_mode_info_t' has no member named 'attributes' util/x86emu/yabel/vbe.c:621: error: 'vbe_mode_info_t' has no member named 'x_resolution' util/x86emu/yabel/vbe.c:621: error: 'vbe_mode_info_t' has no member named 'y_resolution' util/x86emu/yabel/vbe.c:624: error: 'vbe_mode_info_t' has no member named 'x_charsize' util/x86emu/yabel/vbe.c:624: error: 'vbe_mode_info_t' has no member named 'y_charsize' util/x86emu/yabel/vbe.c:626: error: 'vbe_mode_info_t' has no member named 'bits_per_pixel' util/x86emu/yabel/vbe.c:628: error: 'vbe_mode_info_t' has no member named 'memory_model' util/x86emu/yabel/vbe.c:630: error: 'vbe_mode_info_t' has no member named 'framebuffer_address' util/x86emu/yabel/vbe.c:647: error: 'vbe_mode_info_t' has no member named 'x_resolution' util/x86emu/yabel/vbe.c:647: error: 'vbe_mode_info_t' has no member named 'y_resolution' util/x86emu/yabel/vbe.c:647: error: 'vbe_mode_info_t' has no member named 'bits_per_pixel' util/x86emu/yabel/vbe.c:647: error: 'vbe_mode_info_t' has no member named 'framebuffer_address' make: *** [util/x86emu/yabel/vbe.o] Error 1 last part of buildlog attached. Any ideas? -- Thanks, Joseph Smith Set-Top-Linux www.settoplinux.org

4 13

[commit] r5186 - trunk
by repository service 05 Mar '10

05 Mar '10

Author: stepan Date: Fri Mar 5 11:20:28 2010 New Revision: 5186 URL: http://tracker.coreboot.org/trac/coreboot/changeset/5186 Log: This patch fixes two things: - -m32 is already defined by xcompile if the compiler is a 64bit compiler so drop it from the Makefile. - allow "obj-.. += foo.o" for util/, too. Otherwise the source files in util/x86emu/ put their objects in util/ instead of $(obj)/util Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/Makefile Modified: trunk/Makefile ============================================================================== --- trunk/Makefile Fri Mar 5 11:03:50 2010 (r5185) +++ trunk/Makefile Fri Mar 5 11:20:28 2010 (r5186) @@ -119,7 +119,7 @@ crt0s:= ldscripts:= types:=obj initobj driver smmobj -includemakefiles=$(foreach type,$(2), $(eval $(type)-y:=)) $(eval subdirs-y:=) $(eval -include $(1)) $(if $(strip $(3)),$(foreach type,$(2),$(eval $(type)s+=$$(patsubst src/%,$(obj)/%,$$(addprefix $(dir $(1)),$$($(type)-y)))))) $(eval subdirs+=$$(subst $(PWD)/,,$$(abspath $$(addprefix $(dir $(1)),$$(subdirs-y))))) +includemakefiles=$(foreach type,$(2), $(eval $(type)-y:=)) $(eval subdirs-y:=) $(eval -include $(1)) $(if $(strip $(3)),$(foreach type,$(2),$(eval $(type)s+=$$(patsubst util/%,$(obj)/util/%,$$(patsubst src/%,$(obj)/%,$$(addprefix $(dir $(1)),$$($(type)-y))))))) $(eval subdirs+=$$(subst $(PWD)/,,$$(abspath $$(addprefix $(dir $(1)),$$(subdirs-y))))) evaluate_subdirs=$(eval cursubdirs:=$(subdirs)) $(eval subdirs:=) $(foreach dir,$(cursubdirs),$(eval $(call includemakefiles,$(dir)/Makefile.inc,$(types),$(1)))) $(if $(subdirs),$(eval $(call evaluate_subdirs, $(1)))) # collect all object files eligible for building @@ -148,55 +148,63 @@ $(CPP) -D__ACPI__ -P $(CPPFLAGS) -include $(obj)/config.h -I$(src) -I$(src)/mainboard/$(MAINBOARDDIR) $$< -o $$(basename $$(a)).asl iasl -p $$(basename $$@) -tc $$(basename $$(a)).asl mv $$(basename $$(a)).hex $$(basename $$(a)).c - $(CC) -m32 $$(CFLAGS) $$(if $$(subst dsdt,,$$(basename $$(notdir $$@))), -DAmlCode=AmlCode_$$(basename $$(notdir $$@))) -c -o $$@ $$(basename $$(a)).c + $(CC) $$(CFLAGS) $$(if $$(subst dsdt,,$$(basename $$(notdir $$@))), -DAmlCode=AmlCode_$$(basename $$(notdir $$@))) -c -o $$@ $$(basename $$(a)).c endef define objs_c_template +$(obj)/$(1)%.o: $(1)%.c $(obj)/config.h + @printf " CC $$(subst $$(obj)/,,$$(@))\n" + $(CC) $$(CFLAGS) -c -o $$@ $$< + $(obj)/$(1)%.o: src/$(1)%.c $(obj)/config.h @printf " CC $$(subst $$(obj)/,,$$(@))\n" - $(CC) -m32 $$(CFLAGS) -c -o $$@ $$< + $(CC) $$(CFLAGS) -c -o $$@ $$< endef define objs_S_template +$(obj)/$(1)%.o: $(1)%.S $(obj)/config.h + @printf " CC $$(subst $$(obj)/,,$$(@))\n" + $(CC) -DASSEMBLY $$(CFLAGS) -c -o $$@ $$< + $(obj)/$(1)%.o: src/$(1)%.S $(obj)/config.h @printf " CC $$(subst $$(obj)/,,$$(@))\n" - $(CC) -m32 -DASSEMBLY $$(CFLAGS) -c -o $$@ $$< + $(CC) -DASSEMBLY $$(CFLAGS) -c -o $$@ $$< endef define initobjs_c_template $(obj)/$(1)%.initobj.o: src/$(1)%.c $(obj)/config.h @printf " CC $$(subst $$(obj)/,,$$(@))\n" - $(CC) -m32 $$(CFLAGS) -c -o $$@ $$< + $(CC) $$(CFLAGS) -c -o $$@ $$< endef define initobjs_S_template $(obj)/$(1)%.initobj.o: src/$(1)%.S $(obj)/config.h @printf " CC $$(subst $$(obj)/,,$$(@))\n" - $(CC) -m32 -DASSEMBLY $$(CFLAGS) -c -o $$@ $$< + $(CC) -DASSEMBLY $$(CFLAGS) -c -o $$@ $$< endef define drivers_c_template $(obj)/$(1)%.driver.o: src/$(1)%.c $(obj)/config.h @printf " CC $$(subst $$(obj)/,,$$(@))\n" - $(CC) -m32 $$(CFLAGS) -c -o $$@ $$< + $(CC) $$(CFLAGS) -c -o $$@ $$< endef define drivers_S_template $(obj)/$(1)%.driver.o: src/$(1)%.S @printf " CC $$(subst $$(obj)/,,$$(@))\n" - $(CC) -m32 -DASSEMBLY $$(CFLAGS) -c -o $$@ $$< + $(CC) -DASSEMBLY $$(CFLAGS) -c -o $$@ $$< endef define smmobjs_c_template $(obj)/$(1)%.smmobj.o: src/$(1)%.c @printf " CC $$(subst $$(obj)/,,$$(@))\n" - $(CC) -m32 $$(CFLAGS) -c -o $$@ $$< + $(CC) $$(CFLAGS) -c -o $$@ $$< endef define smmobjs_S_template $(obj)/$(1)%.smmobj.o: src/$(1)%.S @printf " CC $$(subst $$(obj)/,,$$(@))\n" - $(CC) -m32 $$(CFLAGS) -c -o $$@ $$< + $(CC) $$(CFLAGS) -c -o $$@ $$< endef usetemplate=$(foreach d,$(sort $(dir $($(1)))),$(eval $(call $(1)_$(2)_template,$(subst $(obj)/,,$(d)))))

1 0

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coreboot March 2010