Hi all,
I've just recently brought my development environment up to speed with
the latest coreboot version -- which is very nice! -- and caught a
couple of minor issues. I'm not sure I fully understand the underlying
logic behind the different CAR setup routines in
src/cpu/amd/car/cache_as_ram.inc, but the attached patch is required to
make the S2912 board choose the correct code path. I've also upped the
MAX_CPUS setting to 12 to accommodate 6-core Istanbul CPUs. This might
make sense for other fam10 boards as well.
Signed-off-by: Arne Georg Gleditsch <arne.gleditsch(a)numascale.com>
--
Arne.
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