coreboot March 2010

coreboot@coreboot.org

61 participants
434 discussions

[flashrom] flashrom on non-x86 hosts
by Carl-Daniel Hailfinger 05 Mar '10

05 Mar '10

Hi, [I wish to apologize for the crossposting, but AFAICS quite a few coreboot developers are not subscribed to the flashrom list yet. Followup is set to flashrom(a)flashrom.org and I'll make sure your replies will be whitelisted and end up on the flashrom list.] flashrom has reached a state where pretty much all hardware access is now done in an OS-independent and hardware-independent way. Does flashrom still work on non-x86 architectures? I remember people using it on non-x86, but only PPC is mentioned near flashrom/flash_and_burn. Endianness might be an issue with the current code, but since I lack the hardware, I have no way to test. Please send any test/compile results as reply to this mail, and I'll try to address any bugs/problems as they turn up. Thank you! Regards, Carl-Daniel

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MSI K9VGM-V(MS-7253)....
by Chi Min Wang 04 Mar '10

04 Mar '10

2 2

Details for choice of motherboard
by anand bhagwantrao 04 Mar '10

04 Mar '10

Hello frnds.. I want to have coreboot in my motherboard. pls let me know the same specification motherboard as Intel BOXDG43NB LGA 775 Intel G43 ATX Intel Motherboard but apart from Intel. Thank you all..

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HELP: Porting i830 RAM init to 440BX, now it won't compile
by Keith Hui 03 Mar '10

03 Mar '10

Hi, I need help getting this "patch" to compile. This is my attempt at porting Joseph Smith's i830 RAM init code to 440BX. Apply this patch and you have my 440BX part of the code. Which is where all the trouble is. I changed motherboard target to P2B-F, P3B-F (both of which which I haven't touched), and my under-development P2B-LS targets and they all fail. I need to figure out why romcc won't compile this. I wrote some stubs that I use to test this code under userspace with dummy SPD dumps from a dozen of my DIMM modules. I define TESTJIG when I'm compiling raminit.c to use these stubs for my own userspace testing. gcc is used to compile both my stubs and raminit.c for those tests and they all compile and seems to run fine. Now I need to boot test it. This code needs some expansion for i440bx because it supports a number of features not present in i830. Below are output of make when I tried to compile: ramtest.c:6.0: warning: Replacing undefined macro: CONFIG_SSE2 with 0 ramtest.c:56.0: warning: Replacing undefined macro: CONFIG_SSE2 with 0 raminit.c:605.46: raminit.c:789.32: romstage.c:96.32: 0xd28680 or Internal compiler error: non dominated rhs use point 0xd288d0? make: *** [/usr/src/coreboot/build/mainboard/asus/p2b-ls/romstage.inc] Aborted The part of raminit.c that croaks is: ... if (value == SPD_MEMORY_TYPE_EDO) { edosd |= 0x02; PRINT_DEBUG("EDO"); } else if (value == SPD_MEMORY_TYPE_SDRAM) { edosd |= 0x04; // <<< ABORT! PRINT_DEBUG("SDRAM"); // <<< ABORT! } ... Let me add another few questions here. I want to add code to have coreboot talk to the clock chip to find out its FSB in order to select the fastest memory timing from SPD data. 440BX only has official support for 100MHz, but they often are taken to 133MHz and beyond - my two boards are tested stable to 140MHz. I know the clock chip sits on SMBus, and have a fixed address at 0x69. That's with the clock chip my board uses. Where should this code be placed? The vendor BIOS placed the PIIX4E power management device base port at 0xE400, and its SMBus base port at 0xE800. Coreboot has its SMBus base port at 0x0F00. If I want to change the base port to match vendor BIOS, where should it be made? Any help appreciated. Thanks Keith

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Re: [coreboot] Re unsuported Motherboard
by Joao Mamede 03 Mar '10

03 Mar '10

Joao Mamede wrote: > > a socket to plug in a BIOS and buy a BIOS external writer. Can I > > have recommendations on where to buy? > Peter Stuge wrote: What's your budget? farnell.com should have PLCC sockets and maybe even flash chips. bios-repair.co.uk has flash chips, and maybe PLCC sockets. For programmer it would probably be simplest to use another mainboard which is compatible with flashrom. Can we remove BIOS with the machine turned on? Meaning: We boot with the good one, we remove it, we insert the second machine chip and flash it. Does it work? About the compatibility, I have a motherboard with a socket that has a award BIOS, is the chip/socket the same for AMI? Are they compatible? I'm sorry for the "noob" questions, but I don't really know much about BIOS. Check which flash chip is in the system, if it's an SPI chip then your best bet is to order the sockets from bios-repair.co.uk instead, I haven't seen SO-8 sockets easily available anywhere else. //Peter

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Re unsuported Motherboard
by Joao Mamede 02 Mar '10

02 Mar '10

On 1/4/10 12:17 PM, Joao Mamede wrote: >/ Hello I want to use coreboot in an old laptop (in order to />/ replace/upgrade a fried graphics card). />/ Both the southern and northernbridges are suported />/ The laptop is the A8js from asus. />/ />/ Here's an lspci />/ 00:00.0 Host bridge: Intel Corporation Mobile 945GM/PM/GMS/940GML and />/ 945GT Express Memory Controller Hub (rev 03) />/ 00:1f.0 ISA bridge: Intel Corporation 82801GBM (ICH7-M) LPC Interface />/ Bridge (rev 02) / >/ />/ I can't find a socketed bios in the motherboard...so I guess I have />/ one try. />/ Can anyone help me out in making a target build(I wouldn't bother you />/ and try to do it myself if I had more than one chance). />/ It's either make it work and make me happy, or put the laptop in the />/ garbage..independently of frying the bios or not. />/ Thank you / Chances are good to get coreboot running on this laptop, its components seem to be mostly supported by coreboot. However, the chance of getting everything working on the first try are zero. The chances to get the system at least to boot on the first try and always keep the system in a working, updatable state are almost zero, too. So if you attempt to port coreboot to this machine, you will need to create some kind of recovery mechanism. You could solder a socket to the mainboard, or a plug to reflash the machine externally. However, to get started, I suggest that you find out what flash chip you have on the board, so you can determine what recovery mechanism is suitable. (The flashrom utility from www.flashrom.org will help you with that) Also, a dump of superiotool -ed will help you a lot. Does the machine have a serial port? Stefan The machine has no serial port. I think it's a socketed bios(from the pics of the disassembly tech manual). However I have to disassemble everything in order to acess the BIOS Is there a way to plug a chip that has a wire coming to the outside to a machine that contains or the BIOS chip or and emulation of one? I'll do all the dumps, etc and post here again.

2 2

Fam10 breakage
by Myles Watson 01 Mar '10

01 Mar '10

Rev 5132 works for me on SimNOW with 1 fam10 processor. Current head gets stuck in an infinite loop setting fixed MTRRs. Any clues while I'm bisecting? Thanks, Myles

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[commit] r5184 - in trunk/src/mainboard: msi/ms9652_fam10 tyan/s2912_fam10
by repository service 01 Mar '10

01 Mar '10

Author: uwe Date: Mon Mar 1 21:16:38 2010 New Revision: 5184 URL: http://tracker.coreboot.org/trac/coreboot/changeset/5184 Log: Whitespace changes to make s2912_fam10/ms9652_fam10 more similar. Also, fix another typo in the ms9652 board name. Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Modified: trunk/src/mainboard/msi/ms9652_fam10/Kconfig trunk/src/mainboard/msi/ms9652_fam10/resourcemap.c trunk/src/mainboard/msi/ms9652_fam10/romstage.c trunk/src/mainboard/msi/ms9652_fam10/spd_addr.h trunk/src/mainboard/tyan/s2912_fam10/Kconfig trunk/src/mainboard/tyan/s2912_fam10/get_bus_conf.c trunk/src/mainboard/tyan/s2912_fam10/mptable.c trunk/src/mainboard/tyan/s2912_fam10/romstage.c Modified: trunk/src/mainboard/msi/ms9652_fam10/Kconfig ============================================================================== --- trunk/src/mainboard/msi/ms9652_fam10/Kconfig Mon Mar 1 18:21:15 2010 (r5183) +++ trunk/src/mainboard/msi/ms9652_fam10/Kconfig Mon Mar 1 21:16:38 2010 (r5184) @@ -134,7 +134,7 @@ config MAINBOARD_PART_NUMBER string - default "MS-9252" + default "MS-9652" depends on BOARD_MSI_MS9652_FAM10 config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID Modified: trunk/src/mainboard/msi/ms9652_fam10/resourcemap.c ============================================================================== --- trunk/src/mainboard/msi/ms9652_fam10/resourcemap.c Mon Mar 1 18:21:15 2010 (r5183) +++ trunk/src/mainboard/msi/ms9652_fam10/resourcemap.c Mon Mar 1 21:16:38 2010 (r5184) @@ -161,7 +161,7 @@ * 1 = base/limit registers i are read-only * [ 7: 4] Reserved * [31: 8] Memory-Mapped I/O Base Address i (39-16) - * This field defines the upper address bits of a 40bit address + * This field defines the upper address bits of a 40bit address * that defines the start of memory-mapped I/O region i */ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x80), 0x000000f0, 0x00000000, @@ -218,7 +218,7 @@ * [ 3: 2] Reserved * [ 4: 4] VGA Enable * 0 = VGA matches Disabled - * 1 = matches all address < 64K and where A[9:0] is in the + * 1 = matches all address < 64K and where A[9:0] is in the * range 3B0-3BB or 3C0-3DF independen of the base & limit registers * [ 5: 5] ISA Enable * 0 = ISA matches Disabled @@ -226,7 +226,7 @@ * from matching agains this base/limit pair * [11: 6] Reserved * [24:12] PCI I/O Base i - * This field defines the start of PCI I/O region n + * This field defines the start of PCI I/O region n * [31:25] Reserved */ /* Verified against board configuration registers after normal proprietary BIOS boot */ Modified: trunk/src/mainboard/msi/ms9652_fam10/romstage.c ============================================================================== --- trunk/src/mainboard/msi/ms9652_fam10/romstage.c Mon Mar 1 18:21:15 2010 (r5183) +++ trunk/src/mainboard/msi/ms9652_fam10/romstage.c Mon Mar 1 21:16:38 2010 (r5184) @@ -50,9 +50,9 @@ #include "pc80/mc146818rtc_early.c" #include "pc80/serial.c" - static void post_code(u8 value) { - outb(value, 0x80); - } +static void post_code(u8 value) { + outb(value, 0x80); +} #if CONFIG_USE_FAILOVER_IMAGE==0 #include "arch/i386/lib/console.c" @@ -153,20 +153,17 @@ static void sio_setup(void) { - - unsigned value; - uint32_t dword; - uint8_t byte; - - byte = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b); - byte |= 0x20; - pci_write_config8(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b, byte); - - dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0); - dword |= (1<<0); - pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0, dword); - - + unsigned value; + uint32_t dword; + uint8_t byte; + + byte = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b); + byte |= 0x20; + pci_write_config8(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b, byte); + + dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0); + dword |= (1<<0); + pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0, dword); } void failover_process(unsigned long bist, unsigned long cpu_init_detectedx) @@ -281,10 +278,10 @@ #endif val = cpuid_eax(1); - printk_debug("BSP Family_Model: %08x \n", val); + printk_debug("BSP Family_Model: %08x\n", val); printk_debug("*sysinfo range: ["); print_debug_hex32((u32)sysinfo); print_debug(","); print_debug_hex32((u32)sysinfo+sizeof(struct sys_info)); print_debug("]\n"); - printk_debug("bsp_apicid = %02x \n", bsp_apicid); - printk_debug("cpu_init_detectedx = %08x \n", cpu_init_detectedx); + printk_debug("bsp_apicid = %02x\n", bsp_apicid); + printk_debug("cpu_init_detectedx = %08x\n", cpu_init_detectedx); /* Setup sysinfo defaults */ set_sysinfo_in_ram(0); @@ -300,12 +297,12 @@ /* Setup nodes PCI space and start core 0 AP init. */ finalize_node_setup(sysinfo); - printk_debug("finalize_node_setup done \n"); + printk_debug("finalize_node_setup done\n"); /* Setup any mainboard PCI settings etc. */ - printk_debug("setup_mb_resource_map begin \n"); + printk_debug("setup_mb_resource_map begin\n"); setup_mb_resource_map(); - printk_debug("setup_mb_resource_map end \n"); + printk_debug("setup_mb_resource_map end\n"); post_code(0x36); /* wait for all the APs core0 started by finalize_node_setup. */ @@ -329,7 +326,7 @@ #if FAM10_SET_FIDVID == 1 msr = rdmsr(0xc0010071); - printk_debug("\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo); + printk_debug("\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); /* FIXME: The sb fid change may survive the warm reset and only * need to be done once.*/ @@ -347,7 +344,7 @@ /* show final fid and vid */ msr=rdmsr(0xc0010071); - printk_debug("End FIDVIDMSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo); + printk_debug("End FIDVIDMSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); #endif wants_reset = mcp55_early_setup_x(); Modified: trunk/src/mainboard/msi/ms9652_fam10/spd_addr.h ============================================================================== --- trunk/src/mainboard/msi/ms9652_fam10/spd_addr.h Mon Mar 1 18:21:15 2010 (r5183) +++ trunk/src/mainboard/msi/ms9652_fam10/spd_addr.h Mon Mar 1 21:16:38 2010 (r5184) @@ -19,7 +19,7 @@ /** * This file defines the SPD addresses for the mainboard. Must be included in - * cache_as_ram_auto.c + * romstage.c */ #define RC00 0 Modified: trunk/src/mainboard/tyan/s2912_fam10/Kconfig ============================================================================== --- trunk/src/mainboard/tyan/s2912_fam10/Kconfig Mon Mar 1 18:21:15 2010 (r5183) +++ trunk/src/mainboard/tyan/s2912_fam10/Kconfig Mon Mar 1 21:16:38 2010 (r5184) @@ -27,7 +27,7 @@ hex default 0xc4000 depends on BOARD_TYAN_S2912_FAM10 - + config DCACHE_RAM_SIZE hex default 0x0c000 @@ -39,7 +39,7 @@ depends on BOARD_TYAN_S2912_FAM10 config APIC_ID_OFFSET - hex + hex default 0 depends on BOARD_TYAN_S2912_FAM10 @@ -65,7 +65,7 @@ config LB_CKS_LOC int - default 123 + default 123 depends on BOARD_TYAN_S2912_FAM10 config MAINBOARD_PART_NUMBER @@ -75,7 +75,7 @@ config PCI_64BIT_PREF_MEM bool - default n + default n depends on BOARD_TYAN_S2912_FAM10 config HAVE_FALLBACK_BOOT @@ -104,7 +104,7 @@ depends on BOARD_TYAN_S2912_FAM10 config HW_MEM_HOLE_SIZE_AUTO_INC - bool + bool default n depends on BOARD_TYAN_S2912_FAM10 @@ -114,7 +114,7 @@ depends on BOARD_TYAN_S2912_FAM10 config HT_CHAIN_END_UNITID_BASE - hex + hex default 0x20 depends on BOARD_TYAN_S2912_FAM10 @@ -124,12 +124,12 @@ depends on BOARD_TYAN_S2912_FAM10 config SERIAL_CPU_INIT - bool + bool default n depends on BOARD_TYAN_S2912_FAM10 config WAIT_BEFORE_CPUS_INIT - bool + bool default n depends on BOARD_TYAN_S2912_FAM10 Modified: trunk/src/mainboard/tyan/s2912_fam10/get_bus_conf.c ============================================================================== --- trunk/src/mainboard/tyan/s2912_fam10/get_bus_conf.c Mon Mar 1 18:21:15 2010 (r5183) +++ trunk/src/mainboard/tyan/s2912_fam10/get_bus_conf.c Mon Mar 1 21:16:38 2010 (r5184) @@ -68,7 +68,6 @@ void get_bus_conf(void) { - unsigned apicid_base; struct mb_sysconf_t *m; @@ -134,5 +133,4 @@ apicid_base = CONFIG_MAX_PHYSICAL_CPUS; #endif m->apicid_mcp55 = apicid_base+0; - } Modified: trunk/src/mainboard/tyan/s2912_fam10/mptable.c ============================================================================== --- trunk/src/mainboard/tyan/s2912_fam10/mptable.c Mon Mar 1 18:21:15 2010 (r5183) +++ trunk/src/mainboard/tyan/s2912_fam10/mptable.c Mon Mar 1 21:16:38 2010 (r5184) @@ -100,7 +100,7 @@ } - /*I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ + /*I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x0, m->apicid_mcp55, 0x0); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x1, m->apicid_mcp55, 0x1); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x0, m->apicid_mcp55, 0x2); Modified: trunk/src/mainboard/tyan/s2912_fam10/romstage.c ============================================================================== --- trunk/src/mainboard/tyan/s2912_fam10/romstage.c Mon Mar 1 18:21:15 2010 (r5183) +++ trunk/src/mainboard/tyan/s2912_fam10/romstage.c Mon Mar 1 21:16:38 2010 (r5184) @@ -150,10 +150,8 @@ #include "southbridge/nvidia/mcp55/mcp55_enable_rom.c" #include "northbridge/amd/amdfam10/early_ht.c" - static void sio_setup(void) { - unsigned value; uint32_t dword; uint8_t byte; @@ -278,10 +276,10 @@ #endif val = cpuid_eax(1); - printk_debug("BSP Family_Model: %08x \n", val); + printk_debug("BSP Family_Model: %08x\n", val); printk_debug("*sysinfo range: ["); print_debug_hex32((u32)sysinfo); print_debug(","); print_debug_hex32((u32)sysinfo+sizeof(struct sys_info)); print_debug("]\n"); - printk_debug("bsp_apicid = %02x \n", bsp_apicid); - printk_debug("cpu_init_detectedx = %08x \n", cpu_init_detectedx); + printk_debug("bsp_apicid = %02x\n", bsp_apicid); + printk_debug("cpu_init_detectedx = %08x\n", cpu_init_detectedx); /* Setup sysinfo defaults */ set_sysinfo_in_ram(0); @@ -322,7 +320,7 @@ #if FAM10_SET_FIDVID == 1 msr = rdmsr(0xc0010071); - printk_debug("\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo); + printk_debug("\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); /* FIXME: The sb fid change may survive the warm reset and only * need to be done once.*/ @@ -340,7 +338,7 @@ /* show final fid and vid */ msr=rdmsr(0xc0010071); - printk_debug("End FIDVIDMSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo); + printk_debug("End FIDVIDMSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); #endif wants_reset = mcp55_early_setup_x();

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[PATCH] cbfs, smaller api, more types
by Stefan Reinauer 01 Mar '10

01 Mar '10

See patch

7 17

[commit] r5183 - in trunk/src/mainboard: amd/dbm690t/acpi amd/pistachio/acpi kontron/kt690/acpi technexion/tim5690/acpi technexion/tim8690/acpi
by repository service 01 Mar '10

01 Mar '10

Author: uwe Date: Mon Mar 1 18:21:15 2010 New Revision: 5183 URL: http://tracker.coreboot.org/trac/coreboot/changeset/5183 Log: Drop unused doit.sh files (trivial). Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Deleted: trunk/src/mainboard/amd/dbm690t/acpi/doit.sh trunk/src/mainboard/amd/pistachio/acpi/doit.sh trunk/src/mainboard/kontron/kt690/acpi/doit.sh trunk/src/mainboard/technexion/tim5690/acpi/doit.sh trunk/src/mainboard/technexion/tim8690/acpi/doit.sh

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coreboot March 2010