coreboot March 2010

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434 discussions

[PATCH] build.h generation
by Stefan Reinauer 15 Mar '10

15 Mar '10

See patch -- coresystems GmbH • Brahmsstr. 16 • D-79104 Freiburg i. Br. Tel.: +49 761 7668825 • Fax: +49 761 7664613 Email: info(a)coresystems.de • http://www.coresystems.de/ Registergericht: Amtsgericht Freiburg • HRB 7656 Geschäftsführer: Stefan Reinauer • Ust-IdNr.: DE245674866

2 1

build service results for r5210
by coreboot information 14 Mar '10

14 Mar '10

Dear coreboot readers! This is the automatic build system of coreboot. The developer "oxygene" checked in revision 5210 to the coreboot repository. This caused the following changes: Change Log: Fix segfault of romcc when complex assignment operators were applied to non-trivial LHSs, eg. c[4] |= 1; Signed-off-by: Patrick Georgi <patrick.georgi(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Build Log: Compilation of a-trend:atc-6220 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5210&device=atc-6220&vendo… Compilation of a-trend:atc-6240 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5210&device=atc-6240&vendo… Compilation of abit:be6-ii_v2_0 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5210&device=be6-ii_v2_0&ve… Compilation of advantech:pcm-5820 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5210&device=pcm-5820&vendo… Compilation of amd:rumba has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5210&device=rumba&vendor=a… Compilation of amd:serengeti_cheetah_fam10 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5210&device=serengeti_chee… Compilation of asi:mb_5blgp has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5210&device=mb_5blgp&vendo… Compilation of asi:mb_5blmp has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5210&device=mb_5blmp&vendo… Compilation of asus:mew-am has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5210&device=mew-am&vendor=… Compilation of asus:mew-vm has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5210&device=mew-vm&vendor=… Compilation of asus:p2b has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5210&device=p2b&vendor=asu… Compilation of asus:p2b-d has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5210&device=p2b-d&vendor=a… Compilation of asus:p2b-ds has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5210&device=p2b-ds&vendor=… Compilation of asus:p2b-f has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5210&device=p2b-f&vendor=a… Compilation of asus:p2b-ls has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5210&device=p2b-ls&vendor=… Compilation of asus:p3b-f has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5210&device=p3b-f&vendor=a… Compilation of axus:tc320 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5210&device=tc320&vendor=a… Compilation of azza:pt-6ibd has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5210&device=pt-6ibd&vendor… Compilation of bcom:winnet100 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5210&device=winnet100&vend… Compilation of biostar:m6tba has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5210&device=m6tba&vendor=b… Compilation of compaq:deskpro_en_sff_p600 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5210&device=deskpro_en_sff… Compilation of dell:s1850 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5210&device=s1850&vendor=d… Compilation of digitallogic:adl855pc has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5210&device=adl855pc&vendo… Compilation of digitallogic:msm586seg has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5210&device=msm586seg&vend… Compilation of eaglelion:5bcm has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5210&device=5bcm&vendor=ea… Compilation of gigabyte:ga-6bxc has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5210&device=ga-6bxc&vendor… Compilation of hp:e_vectra_p2706t has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5210&device=e_vectra_p2706… Compilation of iei:juki-511p has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5210&device=juki-511p&vend… Compilation of iei:nova4899r has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5210&device=nova4899r&vend… Compilation of intel:jarrell has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5210&device=jarrell&vendor… Compilation of intel:mtarvon has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5210&device=mtarvon&vendor… Compilation of intel:truxton has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5210&device=truxton&vendor… Compilation of intel:xe7501devkit has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5210&device=xe7501devkit&v… Compilation of lippert:frontrunner has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5210&device=frontrunner&ve… Compilation of mitac:6513wu has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5210&device=6513wu&vendor=… Compilation of msi:ms6119 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5210&device=ms6119&vendor=… Compilation of msi:ms6147 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5210&device=ms6147&vendor=… Compilation of msi:ms6156 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5210&device=ms6156&vendor=… Compilation of msi:ms6178 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5210&device=ms6178&vendor=… Compilation of msi:ms9652_fam10 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5210&device=ms9652_fam10&v… Compilation of nec:powermate2000 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5210&device=powermate2000&… Compilation of olpc:btest has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5210&device=btest&vendor=o… Compilation of olpc:rev_a has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5210&device=rev_a&vendor=o… Compilation of rca:rm4100 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5210&device=rm4100&vendor=… Compilation of soyo:sy-6ba-plus-iii has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5210&device=sy-6ba-plus-ii… Compilation of supermicro:h8dmr_fam10 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5210&device=h8dmr_fam10&ve… Compilation of supermicro:h8qme_fam10 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5210&device=h8qme_fam10&ve… Compilation of supermicro:x6dai_g has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5210&device=x6dai_g&vendor… Compilation of supermicro:x6dhe_g has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5210&device=x6dhe_g&vendor… Compilation of supermicro:x6dhe_g2 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5210&device=x6dhe_g2&vendo… Compilation of supermicro:x6dhr_ig has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5210&device=x6dhr_ig&vendo… Compilation of supermicro:x6dhr_ig2 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5210&device=x6dhr_ig2&vend… Compilation of technologic:ts5300 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5210&device=ts5300&vendor=… Compilation of televideo:tc7020 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5210&device=tc7020&vendor=… Compilation of thomson:ip1000 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5210&device=ip1000&vendor=… Compilation of tyan:s1846 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5210&device=s1846&vendor=t… Compilation of tyan:s2912_fam10 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5210&device=s2912_fam10&ve… Compilation of via:epia-cn has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5210&device=epia-cn&vendor… Compilation of via:pc2500e has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5210&device=pc2500e&vendor… If something broke during this checkin please be a pain in oxygene's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

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[commit] r5210 - trunk/util/romcc
by repository service 14 Mar '10

14 Mar '10

Author: oxygene Date: Sun Mar 14 23:20:57 2010 New Revision: 5210 URL: http://tracker.coreboot.org/trac/coreboot/changeset/5210 Log: Fix segfault of romcc when complex assignment operators were applied to non-trivial LHSs, eg. c[4] |= 1; Signed-off-by: Patrick Georgi <patrick.georgi(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/util/romcc/romcc.c Modified: trunk/util/romcc/romcc.c ============================================================================== --- trunk/util/romcc/romcc.c Sun Mar 14 22:31:05 2010 (r5209) +++ trunk/util/romcc/romcc.c Sun Mar 14 23:20:57 2010 (r5210) @@ -1896,12 +1896,16 @@ return; if (!user) return; - ptr = &used->use; - while(*ptr) { - if ((*ptr)->member == user) { - return; + if (used->use == (void*)-1) + used->use = 0; + if (used->use) { + ptr = &used->use; + while(*ptr) { + if ((*ptr)->member == user) { + return; + } + ptr = &(*ptr)->next; } - ptr = &(*ptr)->next; } /* Append new to the head of the list, * copy_func and rename_block_variables @@ -11599,19 +11603,19 @@ } def = write_expr(state, left, triple(state, op, left->type, - read_expr(state, left), right)); + read_expr(state, copy_triple(state, left)), right)); break; case TOK_PLUSEQ: lvalue(state, left); eat(state, TOK_PLUSEQ); def = write_expr(state, left, - mk_add_expr(state, left, assignment_expr(state))); + mk_add_expr(state, copy_triple(state, left), assignment_expr(state))); break; case TOK_MINUSEQ: lvalue(state, left); eat(state, TOK_MINUSEQ); def = write_expr(state, left, - mk_sub_expr(state, left, assignment_expr(state))); + mk_sub_expr(state, copy_triple(state, left), assignment_expr(state))); break; case TOK_SLEQ: case TOK_SREQ: @@ -11635,7 +11639,7 @@ } def = write_expr(state, left, triple(state, op, left->type, - read_expr(state, left), right)); + read_expr(state, copy_triple(state,left)), right)); break; } return def;

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[PATCH] (not really) move util/x86emu out of util
by Stefan Reinauer 14 Mar '10

14 Mar '10

Hi, it was reason for workaround rules already, and it's somewhat ugly: util/x86emu is the only part of coreboot that is linked into coreboot itself that lives in util/. It's not a utility and it does not really belong where it lives. Thus, I suggest moving it to src/ ---> svn mv util/x86emu src/devices/oprom (plus necessary Makefile/Kconfig/#include changes to get it building again). Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> -- coresystems GmbH • Brahmsstr. 16 • D-79104 Freiburg i. Br. Tel.: +49 761 7668825 • Fax: +49 761 7664613 Email: info(a)coresystems.de • http://www.coresystems.de/ Registergericht: Amtsgericht Freiburg • HRB 7656 Geschäftsführer: Stefan Reinauer • Ust-IdNr.: DE245674866

3 2

[commit] r5209 - trunk/src
by repository service 14 Mar '10

14 Mar '10

Author: oxygene Date: Sun Mar 14 22:31:05 2010 New Revision: 5209 URL: http://tracker.coreboot.org/trac/coreboot/changeset/5209 Log: Move deprecated Kconfig options to their own file, so it's clear that they should be gone. More can (and should) be added, but this is a start. Of course, eliminating the uses of the flags (and then the flags themselves) that are in Kconfig.deprecated_options is a noble task for the future :-) Signed-off-by: Patrick Georgi <patrick.georgi(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Added: trunk/src/Kconfig.deprecated_options Modified: trunk/src/Kconfig Modified: trunk/src/Kconfig ============================================================================== --- trunk/src/Kconfig Sun Mar 14 22:25:03 2010 (r5208) +++ trunk/src/Kconfig Sun Mar 14 22:31:05 2010 (r5209) @@ -283,28 +283,6 @@ This variable specifies whether a given board has a hard_reset function, no matter if it's provided by board code or chipset code. -config BOARD_HAS_HARD_RESET - bool - default n - help - This variable specifies whether a given board has a reset.c - file containing a hard_reset() function. - -config BOARD_HAS_FADT - bool - default n - help - This variable specifies whether a given board has a board-local - FADT in fadt.c. Long-term, those should be moved to appropriate - chipset components (eg. southbridge) - -config HAVE_BUS_CONFIG - bool - default n - help - This variable specifies whether a given board has a get_bus_conf.c - file containing bus configuration data. - config HAVE_INIT_TIMER bool default n if UDELAY_IO @@ -841,3 +819,5 @@ config ID_SECTION_OFFSET hex default 0x10 + +source src/Kconfig.deprecated_options Added: trunk/src/Kconfig.deprecated_options ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/Kconfig.deprecated_options Sun Mar 14 22:31:05 2010 (r5209) @@ -0,0 +1,33 @@ +# Options in this file are meant to be deprecated. Avoid their use +# if possible, and if you find the time, or touch the general area +# for other purposes, please consider removing their uses. + +# It might be possible to consolidate hard_reset() to southbridges, +# given that it (usually) uses its registers. +# The long term goal would be to eliminate hard_reset from boards. +config BOARD_HAS_HARD_RESET + bool + default n + help + This variable specifies whether a given board has a reset.c + file containing a hard_reset() function. + +# It might be possible to consolidate FADTs to southbridges. This would +# improve code reuse in the tree. +config BOARD_HAS_FADT + bool + default n + help + This variable specifies whether a given board has a board-local + FADT in fadt.c. Long-term, those should be moved to appropriate + chipset components (eg. southbridge) + +# There ought to be a better place to put data than code. Also, make this +# (or a similar) framework more universally usable, so all boards benefit +# from sharing data between the various tables. +config HAVE_BUS_CONFIG + bool + default n + help + This variable specifies whether a given board has a get_bus_conf.c + file containing information about bus routing.

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[commit] r5208 - in trunk: . src src/arch/i386 src/cpu/x86/smm util/abuild
by repository service 14 Mar '10

14 Mar '10

Author: oxygene Date: Sun Mar 14 22:25:03 2010 New Revision: 5208 URL: http://tracker.coreboot.org/trac/coreboot/changeset/5208 Log: Add scan-build support to the build system. When configured in Kconfig, just running "make" calls scan-build as appropriate (however, it does not check for the presence of scan-build) The target directory for the scan-build report is configurable and defaults to the scan-build default of /tmp/scan-build-$date-$num abuild is adapted to properly run scanbuild when ran with the -sb option. Signed-off-by: Patrick Georgi <patrick.georgi(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/ (props changed) trunk/Makefile trunk/src/Kconfig trunk/src/arch/i386/Makefile.inc trunk/src/cpu/x86/smm/Makefile.inc trunk/util/abuild/abuild Modified: trunk/Makefile ============================================================================== --- trunk/Makefile Sun Mar 14 18:01:08 2010 (r5207) +++ trunk/Makefile Sun Mar 14 22:25:03 2010 (r5208) @@ -19,8 +19,16 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## +ifeq ($(INNER_SCANBUILD),y) +CC_real:=$(CC) +endif $(if $(wildcard .xcompile),,$(eval $(shell bash util/xcompile/xcompile > .xcompile))) include .xcompile +ifeq ($(INNER_SCANBUILD),y) +CC:=$(CC_real) +HOSTCC:=$(CC_real) --hostcc +HOSTCXX:=$(CC_real) --hostcxx +endif export top := $(PWD) export src := $(top)/src @@ -90,7 +98,25 @@ # The primary target needs to be here before we include the # other files +ifeq ($(INNER_SCANBUILD),y) +CONFIG_SCANBUILD_ENABLE:= +endif + +ifeq ($(CONFIG_SCANBUILD_ENABLE),y) +ifneq ($(CONFIG_SCANBUILD_REPORT_LOCATION),) +CONFIG_SCANBUILD_REPORT_LOCATION:=-o $(CONFIG_SCANBUILD_REPORT_LOCATION) +endif +all: + echo '#!/bin/sh' > .ccwrap + echo 'CC="$(CC)"' >> .ccwrap + echo 'if [ "$$1" = "--hostcc" ]; then shift; CC="$(HOSTCC)"; fi' >> .ccwrap + echo 'if [ "$$1" = "--hostcxx" ]; then shift; CC="$(HOSTCXX)"; fi' >> .ccwrap + echo 'eval $$CC $$*' >> .ccwrap + chmod +x .ccwrap + scan-build $(CONFIG_SCANBUILD_REPORT_LOCATION) -analyze-headers --use-cc=$(top)/.ccwrap --use-c++=$(top)/.ccwrap $(MAKE) INNER_SCANBUILD=y +else all: coreboot +endif ####################################################################### @@ -110,7 +136,12 @@ (cd $(obj)/mainboard/$(MAINBOARDDIR) ; PYTHONPATH=$(top)/util/sconfig export PYTHONPATH; python config.py $(MAINBOARDDIR) $(top) $(obj)/mainboard/$(MAINBOARDDIR)) $(obj)/mainboard/$(MAINBOARDDIR)/static.o: $(obj)/mainboard/$(MAINBOARDDIR)/static.c -# + @printf " CC $(subst $(obj)/,,$(@))\n" + $(CC) $(CFLAGS) -c -o $@ $< + +$(obj)/arch/i386/../../option_table.o: $(obj)/arch/i386/../../option_table.c + @printf " CC $(subst $(obj)/,,$(@))\n" + $(CC) $(CFLAGS) -c -o $@ $< objs:=$(obj)/mainboard/$(MAINBOARDDIR)/static.o initobjs:= @@ -325,7 +356,7 @@ $(MAKE) -C util/sconfig clean clean: clean-for-update - rm -f $(obj)/coreboot* + rm -f $(obj)/coreboot* .ccwrap distclean: clean rm -rf $(obj) Modified: trunk/src/Kconfig ============================================================================== --- trunk/src/Kconfig Sun Mar 14 18:01:08 2010 (r5207) +++ trunk/src/Kconfig Sun Mar 14 22:25:03 2010 (r5208) @@ -46,6 +46,20 @@ Select the prefix to all files put into the image. It's "fallback" by default, "normal" is a common alternative. +config SCANBUILD_ENABLE + bool "build with scan-build for static analysis" + default n + help + Changes the build process to scan-build is used. + Requires scan-build in path. + +config SCANBUILD_REPORT_LOCATION + string "directory to put scan-build report in" + default "" + depends on SCANBUILD_ENABLE + help + Where the scan-build report should be stored + endmenu source src/mainboard/Kconfig Modified: trunk/src/arch/i386/Makefile.inc ============================================================================== --- trunk/src/arch/i386/Makefile.inc Sun Mar 14 18:01:08 2010 (r5207) +++ trunk/src/arch/i386/Makefile.inc Sun Mar 14 22:25:03 2010 (r5208) @@ -60,7 +60,7 @@ $(obj)/coreboot_ram.o: $(obj)/arch/i386/lib/c_start.o $(drivers) $(obj)/coreboot.a $(LIBGCC_FILE_NAME) @printf " CC $(subst $(obj)/,,$(@))\n" - $(CC) -nostdlib -r -o $@ $(obj)/arch/i386/lib/c_start.o $(drivers) -Wl,-$ $(obj)/coreboot.a $(LIBGCC_FILE_NAME) -Wl,-$ + $(CC) -nostdlib -r -o $@ $(obj)/arch/i386/lib/c_start.o $(drivers) -Wl,--start-group $(obj)/coreboot.a $(LIBGCC_FILE_NAME) -Wl,--end-group $(obj)/coreboot.a: $(objs) @printf " AR $(subst $(obj)/,,$(@))\n" Modified: trunk/src/cpu/x86/smm/Makefile.inc ============================================================================== --- trunk/src/cpu/x86/smm/Makefile.inc Sun Mar 14 18:01:08 2010 (r5207) +++ trunk/src/cpu/x86/smm/Makefile.inc Sun Mar 14 22:25:03 2010 (r5208) @@ -38,5 +38,9 @@ $(obj)/cpu/x86/smm/smm_bin.c: $(obj)/cpu/x86/smm/smm (echo 'unsigned char smm[] = {'; od -vtx1 $(obj)/cpu/x86/smm/smm | sed -e 's,^[0-9]* *,,' -e 's:[0-9a-f][0-9a-f] :0x&,:g' -e 's:[0-9a-f][0-9a-f]$$:0x&,:'; echo '}; unsigned int smm_len = '; wc -c $(obj)/cpu/x86/smm/smm |awk '{print $$1;}' ; echo ';') > $@ +$(obj)/cpu/x86/smm/smm_bin.o: $(obj)/cpu/x86/smm/smm_bin.c + @printf " CC $(subst $(obj)/,,$(@))\n" + $(CC) $(CFLAGS) -c -o $@ $< + endif Modified: trunk/util/abuild/abuild ============================================================================== --- trunk/util/abuild/abuild Sun Mar 14 18:01:08 2010 (r5207) +++ trunk/util/abuild/abuild Sun Mar 14 22:25:03 2010 (r5208) @@ -173,6 +173,12 @@ echo "CONFIG_DEFAULT_CONSOLE_LOGLEVEL_$loglevel=y" >> .config echo "CONFIG_DEFAULT_CONSOLE_LOGLEVEL=$loglevel" >> .config fi + + if [ "$scanbuild" = "true" ]; then + printf "(scan-build enabled) " + echo "CONFIG_SCANBUILD_ENABLE=y" >> .config + echo "CONFIG_SCANBUILD_REPORT_LOCATION=\"$TARGET/scan-build-results-tmp\"" >> .config + fi fi yes "" | $MAKE oldconfig obj=${build_dir} > ${build_dir}/config.log @@ -364,21 +370,6 @@ CC="$CC -fno-stack-protector" fi - if [ "$scanbuild" = "true" ]; then - ccwrap=`mktemp` - mkdir -p $TARGET/${VENDOR}_${MAINBOARD} - mkdir -p $TARGET/scan-build-results-tmp - mv $ccwrap $TARGET/${VENDOR}_${MAINBOARD} - ccwrap=$TARGET/${VENDOR}_${MAINBOARD}/`basename $ccwrap` - echo '#!/bin/sh' > $ccwrap - echo $CC' "$@"' >> $ccwrap - chmod +x $ccwrap - origMAKE=$MAKE - MAKE="scan-build --use-cc=$ccwrap -o $TARGET/scan-build-results-tmp -analyze-headers $MAKE GCC=$ccwrap" - CC="\$(CC)" - HOSTCC="CCC_CC=$HOSTCC \$(CC)" - fi - built_successfully $VENDOR $MAINBOARD && \ { printf " ( mainboard/$VENDOR/$MAINBOARD previously ok )\n\n"

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[PATCH]Add scan-build support to coreboot-v4
by Patrick Georgi 14 Mar '10

14 Mar '10

Hi, attached patch adds scan-build support to coreboot-v4. It's configurable using Kconfig and defaults to off. If set, it expects scan-build to be around and runs it. The target directory for the scan-build report is configurable. If not set, the default (/tmp/scan-build-$date-$number) is used. Also, abuild is adapted to make use of the feature when running with the -sb flag. While adding it, I discovered an issue in the build system that I worked around in this patch, and will fix in a future patch: $(obj)/$path/$file.c -> $(obj)/$path/$file.o rules rely on implicit default rules in make. For some reasons, these are missing when make is invoked by make. There should also be some path normalization for object file paths (using $(abspath)), so the option_table.c rule hack can go. Maybe it's a good idea to avoid reading in all Makefile.incs in the outer make in a scan-build based build, but it's probably not worth the trouble (it's harder to keep make clean and the likes working with such an optimization) Signed-off-by: Patrick Georgi <patrick.georgi(a)coresystems.de>

2 1

[commit] r5207 - trunk/src/southbridge/intel/i82801dx
by repository service 14 Mar '10

14 Mar '10

Author: stepan Date: Sun Mar 14 18:01:08 2010 New Revision: 5207 URL: http://tracker.coreboot.org/trac/coreboot/changeset/5207 Log: ICH4 update, fix ATA init, drop SATA (chipset doesn't have SATA) fix some PCI IDs, enable USB bus mastering, add some license headers, ... LPC code needs another look, but I think we're getting there. Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Joseph Smith <joe(a)settoplinux.org> Deleted: trunk/src/southbridge/intel/i82801dx/i82801dx_nic.c trunk/src/southbridge/intel/i82801dx/i82801dx_sata.c Modified: trunk/src/southbridge/intel/i82801dx/Kconfig trunk/src/southbridge/intel/i82801dx/Makefile.inc trunk/src/southbridge/intel/i82801dx/chip.h trunk/src/southbridge/intel/i82801dx/cmos_failover.c trunk/src/southbridge/intel/i82801dx/i82801dx.c trunk/src/southbridge/intel/i82801dx/i82801dx.h trunk/src/southbridge/intel/i82801dx/i82801dx_early_smbus.c trunk/src/southbridge/intel/i82801dx/i82801dx_ide.c trunk/src/southbridge/intel/i82801dx/i82801dx_lpc.c trunk/src/southbridge/intel/i82801dx/i82801dx_pci.c trunk/src/southbridge/intel/i82801dx/i82801dx_reset.c trunk/src/southbridge/intel/i82801dx/i82801dx_smbus.c trunk/src/southbridge/intel/i82801dx/i82801dx_tco_timer.c trunk/src/southbridge/intel/i82801dx/i82801dx_usb.c trunk/src/southbridge/intel/i82801dx/i82801dx_usb2.c Modified: trunk/src/southbridge/intel/i82801dx/Kconfig ============================================================================== --- trunk/src/southbridge/intel/i82801dx/Kconfig Sat Mar 13 23:07:15 2010 (r5206) +++ trunk/src/southbridge/intel/i82801dx/Kconfig Sun Mar 14 18:01:08 2010 (r5207) @@ -1,3 +1,24 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2008-2009 coresystems GmbH +## +## This program is free software; you can redistribute it and/or +## modify it under the terms of the GNU General Public License as +## published by the Free Software Foundation; version 2 of +## the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, +## MA 02110-1301 USA +## + config SOUTHBRIDGE_INTEL_I82801DX bool select IOAPIC Modified: trunk/src/southbridge/intel/i82801dx/Makefile.inc ============================================================================== --- trunk/src/southbridge/intel/i82801dx/Makefile.inc Sat Mar 13 23:07:15 2010 (r5206) +++ trunk/src/southbridge/intel/i82801dx/Makefile.inc Sun Mar 14 18:01:08 2010 (r5207) @@ -1,12 +1,33 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2008-2009 coresystems GmbH +## +## This program is free software; you can redistribute it and/or +## modify it under the terms of the GNU General Public License as +## published by the Free Software Foundation; version 2 of +## the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, +## MA 02110-1301 USA +## + driver-y += i82801dx.o -driver-y += i82801dx_usb.o -driver-y += i82801dx_lpc.o -driver-y += i82801dx_ide.o -driver-y += i82801dx_usb2.o driver-y += i82801dx_ac97.o -#driver-y += i82801dx_nic.o +driver-y += i82801dx_ide.o +driver-y += i82801dx_lpc.o #driver-y += i82801dx_pci.o -obj-y += i82801dx_reset.o +driver-y += i82801dx_usb.o +driver-y += i82801dx_usb2.o +obj-y += i82801dx_reset.o obj-$(CONFIG_HAVE_SMI_HANDLER) += i82801dx_smi.o + smmobj-$(CONFIG_HAVE_SMI_HANDLER) += i82801dx_smihandler.o Modified: trunk/src/southbridge/intel/i82801dx/chip.h ============================================================================== --- trunk/src/southbridge/intel/i82801dx/chip.h Sat Mar 13 23:07:15 2010 (r5206) +++ trunk/src/southbridge/intel/i82801dx/chip.h Sun Mar 14 18:01:08 2010 (r5207) @@ -1,8 +1,27 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2004 Eric Biederman + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + #ifndef I82801DX_CHIP_H #define I82801DX_CHIP_H -struct southbridge_intel_i82801dx_config -{ +struct southbridge_intel_i82801dx_config { int enable_usb; int enable_native_ide; /** @@ -24,4 +43,4 @@ extern struct chip_operations southbridge_intel_i82801dx_ops; -#endif /* I82801DBM_CHIP_H */ +#endif /* I82801DBM_CHIP_H */ Modified: trunk/src/southbridge/intel/i82801dx/cmos_failover.c ============================================================================== --- trunk/src/southbridge/intel/i82801dx/cmos_failover.c Sat Mar 13 23:07:15 2010 (r5206) +++ trunk/src/southbridge/intel/i82801dx/cmos_failover.c Sun Mar 14 18:01:08 2010 (r5207) @@ -1,16 +1,35 @@ -//kind of cmos_err for ich5 +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2004 Ron G. Minnich + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +// kind of cmos_err for ICH4 #define RTC_FAILED (1 <<2) #define GEN_PMCON_3 0xa4 -static void check_cmos_failed(void) +static void check_cmos_failed(void) { - - uint8_t byte; - byte = pci_read_config8(PCI_DEV(0,0x1f,0),GEN_PMCON_3); - if( byte & RTC_FAILED){ -//clear bit 1 and bit 2 - byte = cmos_read(RTC_BOOT_BYTE); - byte &= 0x0c; - byte |= CONFIG_MAX_REBOOT_CNT << 4; - cmos_write(byte, RTC_BOOT_BYTE); - } + u8 byte; + byte = pci_read_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3); + if (byte & RTC_FAILED) { + //clear bit 1 and bit 2 + byte = cmos_read(RTC_BOOT_BYTE); + byte &= 0x0c; + byte |= CONFIG_MAX_REBOOT_CNT << 4; + cmos_write(byte, RTC_BOOT_BYTE); + } } Modified: trunk/src/southbridge/intel/i82801dx/i82801dx.c ============================================================================== --- trunk/src/southbridge/intel/i82801dx/i82801dx.c Sat Mar 13 23:07:15 2010 (r5206) +++ trunk/src/southbridge/intel/i82801dx/i82801dx.c Sun Mar 14 18:01:08 2010 (r5207) @@ -1,3 +1,23 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2004 Ron G. Minnich + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + #include <console/console.h> #include <device/device.h> #include <device/pci.h> @@ -10,48 +30,49 @@ uint8_t bHasDisableBit = 0; uint16_t cur_disable_mask, new_disable_mask; -// all 82801dbm devices are in bus 0 - unsigned int devfn = PCI_DEVFN(0x1f, 0); // lpc - device_t lpc_dev = dev_find_slot(0, devfn); // 0 +// all 82801dbm devices are in bus 0 + unsigned int devfn = PCI_DEVFN(0x1f, 0); // lpc + device_t lpc_dev = dev_find_slot(0, devfn); // 0 if (!lpc_dev) return; // Calculate disable bit position for specified device:function // NOTE: For ICH-4, only the following devices can be disabled: - // D31: F0, F1, F3, F5, F6, - // D29: F0, F1, F2, F7 + // D31: F0, F1, F3, F5, F6, + // D29: F0, F1, F2, F7 - if (PCI_SLOT(dev->path.pci.devfn) == 31) { - index = PCI_FUNC(dev->path.pci.devfn); + if (PCI_SLOT(dev->path.pci.devfn) == 31) { + index = PCI_FUNC(dev->path.pci.devfn); switch (index) { - case 0: - case 1: - case 3: - case 5: - case 6: - bHasDisableBit = 1; - break; - - default: - break; + case 0: + case 1: + case 3: + case 5: + case 6: + bHasDisableBit = 1; + break; + + default: + break; }; - + if (index == 0) - index = 14; // D31:F0 bit is an exception + index = 14; // D31:F0 bit is an exception - } else if (PCI_SLOT(dev->path.pci.devfn) == 29) { - index = 8 + PCI_FUNC(dev->path.pci.devfn); + } else if (PCI_SLOT(dev->path.pci.devfn) == 29) { + index = 8 + PCI_FUNC(dev->path.pci.devfn); - if ((PCI_FUNC(dev->path.pci.devfn) < 3) || (PCI_FUNC(dev->path.pci.devfn) == 7)) + if ((PCI_FUNC(dev->path.pci.devfn) < 3) + || (PCI_FUNC(dev->path.pci.devfn) == 7)) bHasDisableBit = 1; - } + } if (bHasDisableBit) { cur_disable_mask = pci_read_config16(lpc_dev, FUNC_DIS); - new_disable_mask = cur_disable_mask & ~(1<<index); // enable it + new_disable_mask = cur_disable_mask & ~(1 << index); // enable it if (!dev->enabled) { - new_disable_mask |= (1<<index); // disable it + new_disable_mask |= (1 << index); // disable it } if (new_disable_mask != cur_disable_mask) { pci_write_config16(lpc_dev, FUNC_DIS, new_disable_mask); @@ -61,5 +82,5 @@ struct chip_operations southbridge_intel_i82801dx_ops = { CHIP_NAME("Intel ICH4/ICH4-M (82801Dx) Series Southbridge") - .enable_dev = i82801dx_enable, + .enable_dev = i82801dx_enable, }; Modified: trunk/src/southbridge/intel/i82801dx/i82801dx.h ============================================================================== --- trunk/src/southbridge/intel/i82801dx/i82801dx.h Sat Mar 13 23:07:15 2010 (r5206) +++ trunk/src/southbridge/intel/i82801dx/i82801dx.h Sun Mar 14 18:01:08 2010 (r5207) @@ -1,3 +1,25 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2004 Ron G. Minnich + * Copyright (C) 2004 Eric Biederman + * Copyright (C) 2008-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + /* the problem: we have 82801dbm support in fb1, and 82801er in fb2. * fb1 code is what we want, fb2 structure is needed however. * so we need to get fb1 code for 82801dbm into fb2 structure. @@ -23,15 +45,23 @@ #endif /* -000 = Non-combined. P0 is primary master. P1 is secondary master. -001 = Non-combined. P0 is secondary master. P1 is primary master. -100 = Combined. P0 is primary master. P1 is primary slave. IDE is secondary; Primary IDE channel -disabled. -101 = Combined. P0 is primary slave. P1 is primary master. IDE is secondary. -110 = Combined. IDE is primary. P0 is secondary master. P1 is secondary slave; Secondary IDE -channel disabled. -111 = Combined. IDE is primary. P0 is secondary slave. P1 is secondary master. -*/ + * 000 = Non-combined. P0 is primary master. P1 is secondary master. + * 001 = Non-combined. P0 is secondary master. P1 is primary master. + * 100 = Combined. P0 is primary master. P1 is primary slave. IDE is secondary; + * Primary IDE channel disabled. + * 101 = Combined. P0 is primary slave. P1 is primary master. IDE is secondary. + * 110 = Combined. IDE is primary. P0 is secondary master. P1 is secondary + * slave; Secondary IDE channel disabled. + * 111 = Combined. IDE is primary. P0 is secondary slave. P1 is secondary master. + */ +/* PCI Configuration Space (D31:F1) */ +#define IDE_TIM_PRI 0x40 /* IDE timings, primary */ +#define IDE_TIM_SEC 0x42 /* IDE timings, secondary */ + +/* IDE_TIM bits */ +#define IDE_DECODE_ENABLE (1 << 15) + + #define PCI_DMA_CFG 0x90 #define SERIRQ_CNTL 0x64 Modified: trunk/src/southbridge/intel/i82801dx/i82801dx_early_smbus.c ============================================================================== --- trunk/src/southbridge/intel/i82801dx/i82801dx_early_smbus.c Sat Mar 13 23:07:15 2010 (r5206) +++ trunk/src/southbridge/intel/i82801dx/i82801dx_early_smbus.c Sun Mar 14 18:01:08 2010 (r5207) @@ -1,3 +1,22 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2004 Ronald G. Minnich + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ //#define SMBUS_IO_BASE 0x1000 //#define SMBUS_IO_BASE 0x0f00 @@ -12,7 +31,7 @@ #define SMBTRNSADD 0x9 #define SMBSLVDATA 0xa #define SMLINK_PIN_CTL 0xe -#define SMBUS_PIN_CTL 0xf +#define SMBUS_PIN_CTL 0xf /* Between 1-10 seconds, We should never timeout normally * Longer than this is just painful when a timeout condition occurs. @@ -28,15 +47,14 @@ pci_write_config32(dev, 0x20, SMBUS_IO_BASE | 1); /* Set smbus enable */ pci_write_config8(dev, 0x40, 0x01); - /* Set smbus iospace enable */ + /* Set smbus iospace enable */ pci_write_config16(dev, 0x4, 0x01); - /* Disable interrupt generation */ + /* Disable interrupt generation */ outb(0, SMBUS_IO_BASE + SMBHSTCTL); /* clear any lingering errors, so the transaction will run */ outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT); } - static inline void smbus_delay(void) { outb(0x80, 0x80); @@ -53,8 +71,8 @@ if ((val & 1)) { break; } - } while(--loops); - return loops?0:-4; + } while (--loops); + return loops ? 0 : -4; } static int smbus_wait_until_ready(void) @@ -68,12 +86,12 @@ if ((val & 1) == 0) { break; } - if(loops == (SMBUS_TIMEOUT / 2)) { - outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), - SMBUS_IO_BASE + SMBHSTSTAT); + if (loops == (SMBUS_TIMEOUT / 2)) { + outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), + SMBUS_IO_BASE + SMBHSTSTAT); } - } while(--loops); - return loops?0:-2; + } while (--loops); + return loops ? 0 : -2; } static int smbus_wait_until_done(void) @@ -83,16 +101,16 @@ do { unsigned char val; smbus_delay(); - + val = inb(SMBUS_IO_BASE + SMBHSTSTAT); - if ( (val & 1) == 0) { + if ((val & 1) == 0) { break; } - if ((val & ~((1<<6)|(1<<0)) ) != 0 ) { + if ((val & ~((1 << 6) | (1 << 0))) != 0) { break; } - } while(--loops); - return loops?0:-3; + } while (--loops); + return loops ? 0 : -3; } static int smbus_read_byte(unsigned device, unsigned address) @@ -101,12 +119,12 @@ unsigned char global_status_register; unsigned char byte; - /*print_err("smbus_read_byte\r\n");*/ + /*print_err("smbus_read_byte\r\n"); */ if (smbus_wait_until_ready() < 0) { print_err_hex8(-2); return -2; } - + /* setup transaction */ /* disable interrupts */ outb(inb(SMBUS_IO_BASE + SMBHSTCTL) & 0xfe, SMBUS_IO_BASE + SMBHSTCTL); @@ -115,16 +133,18 @@ /* set the command/address... */ outb(address & 0xFF, SMBUS_IO_BASE + SMBHSTCMD); /* set up for a byte data read */ - outb((inb(SMBUS_IO_BASE + SMBHSTCTL) & 0xe3) | (0x2<<2), SMBUS_IO_BASE + SMBHSTCTL); + outb((inb(SMBUS_IO_BASE + SMBHSTCTL) & 0xe3) | (0x2 << 2), + SMBUS_IO_BASE + SMBHSTCTL); /* clear any lingering errors, so the transaction will run */ outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT); - /* clear the data byte...*/ + /* clear the data byte... */ outb(0, SMBUS_IO_BASE + SMBHSTDAT0); /* start a byte read, with interrupts disabled */ - outb((inb(SMBUS_IO_BASE + SMBHSTCTL) | 0x40), SMBUS_IO_BASE + SMBHSTCTL); + outb((inb(SMBUS_IO_BASE + SMBHSTCTL) | 0x40), + SMBUS_IO_BASE + SMBHSTCTL); /* poll for it to start */ if (smbus_wait_until_active() < 0) { print_err_hex8(-4); @@ -137,7 +157,7 @@ return -3; } - global_status_register = inb(SMBUS_IO_BASE + SMBHSTSTAT) & ~(1<<6); /* Ignore the In Use Status... */ + global_status_register = inb(SMBUS_IO_BASE + SMBHSTSTAT) & ~(1 << 6); /* Ignore the In Use Status... */ /* read results of transaction */ byte = inb(SMBUS_IO_BASE + SMBHSTDAT0); @@ -153,15 +173,17 @@ */ return byte; } + #if 0 -static void smbus_write_byte(unsigned device, unsigned address, unsigned char val) +static void smbus_write_byte(unsigned device, unsigned address, + unsigned char val) { if (smbus_wait_until_ready() < 0) { return; } /* by LYH */ - outb(0x37,SMBUS_IO_BASE + SMBHSTSTAT); + outb(0x37, SMBUS_IO_BASE + SMBHSTSTAT); /* set the device I'm talking too */ outw(((device & 0x7f) << 1) | 0, SMBUS_IO_BASE + SMBHSTADDR); Modified: trunk/src/southbridge/intel/i82801dx/i82801dx_ide.c ============================================================================== --- trunk/src/southbridge/intel/i82801dx/i82801dx_ide.c Sat Mar 13 23:07:15 2010 (r5206) +++ trunk/src/southbridge/intel/i82801dx/i82801dx_ide.c Sun Mar 14 18:01:08 2010 (r5207) @@ -1,3 +1,23 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2004 Ronald G. Minnich + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + #include <console/console.h> #include <device/device.h> #include <device/pci.h> @@ -5,49 +25,58 @@ #include <device/pci_ops.h> #include "i82801dx.h" +typedef struct southbridge_intel_i82801dx_config config_t; static void ide_init(struct device *dev) { -#if ICH5_SATA_ADDRESS_MAP<=1 - /* Enable ide devices so the linux ide driver will work */ - uint16_t word; - uint8_t byte; - int enable_a=1, enable_b=1; + /* Get the chip configuration */ + config_t *config = dev->chip_info; + /* Enable IDE devices so the Linux IDE driver will work. */ + uint16_t ideTimingConfig; - word = pci_read_config16(dev, 0x40); - word &= ~((1 << 15)); - if (enable_a) { - /* Enable first ide interface */ - word |= (1<<15); - printk_debug("IDE0 "); + ideTimingConfig = pci_read_config16(dev, IDE_TIM_PRI); + ideTimingConfig &= ~IDE_DECODE_ENABLE; + if (!config || config->ide0_enable) { + /* Enable primary IDE interface. */ + ideTimingConfig |= IDE_DECODE_ENABLE; + printk_debug("IDE0: Primary IDE interface is enabled\n"); + } else { + printk_info("IDE0: Primary IDE interface is disabled\n"); } - pci_write_config16(dev, 0x40, word); - - word = pci_read_config16(dev, 0x42); - word &= ~((1 << 15)); - if (enable_b) { - /* Enable secondary ide interface */ - word |= (1<<15); - printk_debug("IDE1 "); - } - pci_write_config16(dev, 0x42, word); -#endif + pci_write_config16(dev, IDE_TIM_PRI, ideTimingConfig); + ideTimingConfig = pci_read_config16(dev, IDE_TIM_SEC); + ideTimingConfig &= ~IDE_DECODE_ENABLE; + if (!config || config->ide1_enable) { + /* Enable secondary IDE interface. */ + ideTimingConfig |= IDE_DECODE_ENABLE; + printk_debug("IDE1: Secondary IDE interface is enabled\n"); + } else { + printk_info("IDE1: Secondary IDE interface is disabled\n"); + } + pci_write_config16(dev, IDE_TIM_SEC, ideTimingConfig); } -static struct device_operations ide_ops = { - .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, +static struct device_operations ide_ops = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, - .init = ide_init, - .scan_bus = 0, - .enable = i82801dx_enable, + .init = ide_init, + .scan_bus = 0, + .enable = i82801dx_enable, }; -static const struct pci_driver ide_driver __pci_driver = { - .ops = &ide_ops, +/* 82801DB */ +static const struct pci_driver i82801db_ide __pci_driver = { + .ops = &ide_ops, .vendor = PCI_VENDOR_ID_INTEL, - .device = PCI_DEVICE_ID_INTEL_82801DBM_IDE, + .device = 0x24cb, }; +/* 82801DBM */ +static const struct pci_driver i82801dbm_ide __pci_driver = { + .ops = &ide_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = 0x24ca, +}; Modified: trunk/src/southbridge/intel/i82801dx/i82801dx_lpc.c ============================================================================== --- trunk/src/southbridge/intel/i82801dx/i82801dx_lpc.c Sat Mar 13 23:07:15 2010 (r5206) +++ trunk/src/southbridge/intel/i82801dx/i82801dx_lpc.c Sun Mar 14 18:01:08 2010 (r5207) @@ -1,7 +1,25 @@ /* - * (C) 2003 Linux Networx, SuSE Linux AG - * (C) 2004 Tyan Computer + * This file is part of the coreboot project. + * + * Copyright (C) 2003 Linux Networx + * Copyright (C) 2004 SuSE Linux AG + * Copyright (C) 2004 Tyan Computer + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ + #include <console/console.h> #include <device/device.h> #include <device/pci.h> @@ -12,113 +30,113 @@ #include <arch/io.h> #include "i82801dx.h" - - #define NMI_OFF 0 -void i82801dx_enable_ioapic( struct device *dev) +void i82801dx_enable_ioapic(struct device *dev) { - uint32_t dword; - volatile uint32_t *ioapic_sba = (volatile uint32_t *)0xfec00000; - volatile uint32_t *ioapic_sbd = (volatile uint32_t *)0xfec00010; - - dword = pci_read_config32(dev, GEN_CNTL); - dword |= (3 << 7); /* enable ioapic */ - dword |= (1 <<13); /* coprocessor error enable */ - dword |= (1 << 1); /* delay transaction enable */ - dword |= (1 << 2); /* DMA collection buf enable */ - pci_write_config32(dev, GEN_CNTL, dword); - printk_debug("ioapic southbridge enabled %x\n",dword); - *ioapic_sba=0; - *ioapic_sbd=(2<<24); - //lyh *ioapic_sba=3; - //lyh *ioapic_sbd=1; - *ioapic_sba=0; - dword=*ioapic_sbd; - printk_debug("Southbridge apic id = %x\n",dword); - if(dword!=(2<<24)) - die(""); - //lyh *ioapic_sba=3; - //lyh dword=*ioapic_sbd; - //lyh printk_debug("Southbridge apic DT = %x\n",dword); - //lyh if(dword!=1) - //lyh die(""); - + u32 dword; + volatile u32 *ioapic_sba = (volatile u32 *)0xfec00000; + volatile u32 *ioapic_sbd = (volatile u32 *)0xfec00010; + + dword = pci_read_config32(dev, GEN_CNTL); + dword |= (3 << 7); /* enable ioapic */ + dword |= (1 << 13); /* coprocessor error enable */ + dword |= (1 << 1); /* delay transaction enable */ + dword |= (1 << 2); /* DMA collection buf enable */ + pci_write_config32(dev, GEN_CNTL, dword); + printk_debug("ioapic southbridge enabled %x\n", dword); + *ioapic_sba = 0; + *ioapic_sbd = (2 << 24); + //lyh *ioapic_sba=3; + //lyh *ioapic_sbd=1; + *ioapic_sba = 0; + dword = *ioapic_sbd; + printk_debug("Southbridge apic id = %x\n", dword); + if (dword != (2 << 24)) + die(""); + //lyh *ioapic_sba=3; + //lyh dword=*ioapic_sbd; + //lyh printk_debug("Southbridge apic DT = %x\n",dword); + //lyh if(dword!=1) + //lyh die(""); } -void i82801dx_enable_serial_irqs( struct device *dev) -{ - pci_write_config8(dev, SERIRQ_CNTL, (1 << 7)|(1 << 6)|((21 - 17) << 2)|(0<< 0)); -} -void i82801dx_lpc_route_dma( struct device *dev, uint8_t mask) -{ - uint16_t word; - int i; - word = pci_read_config16(dev, PCI_DMA_CFG); - word &= ((1 << 10) - (1 << 8)); - for(i = 0; i < 8; i++) { - if (i == 4) - continue; - word |= ((mask & (1 << i))? 3:1) << (i*2); - } - pci_write_config16(dev, PCI_DMA_CFG, word); + +void i82801dx_enable_serial_irqs(struct device *dev) +{ + pci_write_config8(dev, SERIRQ_CNTL, + (1 << 7) | (1 << 6) | ((21 - 17) << 2) | (0 << 0)); +} + +void i82801dx_lpc_route_dma(struct device *dev, u8 mask) +{ + u16 word; + int i; + word = pci_read_config16(dev, PCI_DMA_CFG); + word &= ((1 << 10) - (1 << 8)); + for (i = 0; i < 8; i++) { + if (i == 4) + continue; + word |= ((mask & (1 << i)) ? 3 : 1) << (i * 2); + } + pci_write_config16(dev, PCI_DMA_CFG, word); } + void i82801dx_rtc_init(struct device *dev) { - uint8_t byte; - uint32_t dword; - int rtc_failed; - byte = pci_read_config8(dev, GEN_PMCON_3); - rtc_failed = byte & RTC_FAILED; - if (rtc_failed) { - byte &= ~(1 << 1); /* preserve the power fail state */ - pci_write_config8(dev, GEN_PMCON_3, byte); - } - dword = pci_read_config32(dev, GEN_STS); - rtc_failed |= dword & (1 << 2); - rtc_init(rtc_failed); + u8 byte; + u32 dword; + int rtc_failed; + byte = pci_read_config8(dev, GEN_PMCON_3); + rtc_failed = byte & RTC_FAILED; + if (rtc_failed) { + byte &= ~(1 << 1); /* preserve the power fail state */ + pci_write_config8(dev, GEN_PMCON_3, byte); + } + dword = pci_read_config32(dev, GEN_STS); + rtc_failed |= dword & (1 << 2); + rtc_init(rtc_failed); } - void i82801dx_1f0_misc(struct device *dev) { - pci_write_config16(dev, PCICMD, 0x014f); - pci_write_config32(dev, PMBASE, 0x00001001); - pci_write_config8(dev, ACPI_CNTL, 0x10); - pci_write_config32(dev, GPIO_BASE, 0x00001181); - pci_write_config8(dev, GPIO_CNTL, 0x10); - pci_write_config32(dev, PIRQA_ROUT, 0x0A05030B); - pci_write_config8(dev, PIRQE_ROUT, 0x07); - pci_write_config8(dev, RTC_CONF, 0x04); - pci_write_config8(dev, COM_DEC, 0x10); //lyh E0-> - pci_write_config16(dev, LPC_EN, 0x000F); //LYH 000D-> + pci_write_config16(dev, PCICMD, 0x014f); + pci_write_config32(dev, PMBASE, 0x00001001); + pci_write_config8(dev, ACPI_CNTL, 0x10); + pci_write_config32(dev, GPIO_BASE, 0x00001181); + pci_write_config8(dev, GPIO_CNTL, 0x10); + pci_write_config32(dev, PIRQA_ROUT, 0x0A05030B); + pci_write_config8(dev, PIRQE_ROUT, 0x07); + pci_write_config8(dev, RTC_CONF, 0x04); + pci_write_config8(dev, COM_DEC, 0x10); //lyh E0-> + pci_write_config16(dev, LPC_EN, 0x000F); //LYH 000D-> } static void enable_hpet(struct device *dev) { const unsigned long hpet_address = 0xfed0000; - uint32_t dword; - uint32_t code = (0 & 0x3); - - dword = pci_read_config32(dev, GEN_CNTL); - dword |= (1 << 17); /* enable hpet */ + u32 dword; + u32 code = (0 & 0x3); + + dword = pci_read_config32(dev, GEN_CNTL); + dword |= (1 << 17); /* enable hpet */ /*Bits [16:15]Memory Address Range - 00 FED0_0000h - FED0_03FFh - 01 FED0_1000h - FED0_13FFh - 10 FED0_2000h - FED0_23FFh - 11 FED0_3000h - FED0_33FFh*/ + 00 FED0_0000h - FED0_03FFh + 01 FED0_1000h - FED0_13FFh + 10 FED0_2000h - FED0_23FFh + 11 FED0_3000h - FED0_33FFh */ - dword &= ~(3 << 15); /* clear it */ - dword |= (code<<15); + dword &= ~(3 << 15); /* clear it */ + dword |= (code << 15); - printk_debug("enabling HPET @0x%x\n", hpet_address | (code <<12) ); + printk_debug("enabling HPET @0x%x\n", hpet_address | (code << 12)); } static void lpc_init(struct device *dev) { - uint8_t byte; - int pwr_on=-1; + u8 byte; + int pwr_on = -1; int nmi_option; /* IO APIC initialization */ @@ -126,24 +144,24 @@ i82801dx_enable_serial_irqs(dev); -#ifdef SUSPICIOUS_LOOKING_CODE +#ifdef SUSPICIOUS_LOOKING_CODE // The ICH-4 datasheet does not mention this configuration register. // This code may have been inherited (incorrectly) from code for the AMD 766 southbridge, // which *does* support this functionality. /* posted memory write enable */ byte = pci_read_config8(dev, 0x46); - pci_write_config8(dev, 0x46, byte | (1<<0)); + pci_write_config8(dev, 0x46, byte | (1 << 0)); #endif /* power after power fail */ - /* FIXME this doesn't work! */ - /* Which state do we want to goto after g3 (power restored)? - * 0 == S0 Full On - * 1 == S5 Soft Off - */ - pci_write_config8(dev, GEN_PMCON_3, pwr_on?0:1); - printk_info("set power %s after power fail\n", pwr_on?"on":"off"); + /* FIXME this doesn't work! */ + /* Which state do we want to goto after g3 (power restored)? + * 0 == S0 Full On + * 1 == S5 Soft Off + */ + pci_write_config8(dev, GEN_PMCON_3, pwr_on ? 0 : 1); + printk_info("set power %s after power fail\n", pwr_on ? "on" : "off"); #if 0 /* Enable Error reporting */ /* Set up sync flood detected */ @@ -153,18 +171,18 @@ #endif /* Set up NMI on errors */ - byte = inb(0x61); - byte &= ~(1 << 3); /* IOCHK# NMI Enable */ - byte &= ~(1 << 2); /* PCI SERR# Enable */ - outb(byte, 0x61); - byte = inb(0x70); + byte = inb(0x61); + byte &= ~(1 << 3); /* IOCHK# NMI Enable */ + byte &= ~(1 << 2); /* PCI SERR# Enable */ + outb(byte, 0x61); + byte = inb(0x70); nmi_option = NMI_OFF; get_option(&nmi_option, "nmi"); - if (nmi_option) { - byte &= ~(1 << 7); /* set NMI */ - outb(byte, 0x70); + if (nmi_option) { + byte &= ~(1 << 7); /* set NMI */ + outb(byte, 0x70); } - + /* Initialize the real time clock */ i82801dx_rtc_init(dev); @@ -190,15 +208,15 @@ res->base = 0; res->size = 0x1000; res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | - IORESOURCE_ASSIGNED | IORESOURCE_FIXED; + IORESOURCE_ASSIGNED | IORESOURCE_FIXED; res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0)); res->base = 0xff800000; - res->size = 0x00800000; /* 8 MB for flash */ + res->size = 0x00800000; /* 8 MB for flash */ res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | - IORESOURCE_ASSIGNED | IORESOURCE_FIXED; + IORESOURCE_ASSIGNED | IORESOURCE_FIXED; - res = new_resource(dev, 3); /* IOAPIC */ + res = new_resource(dev, 3); /* IOAPIC */ res->base = 0xfec00000; res->size = 0x00001000; res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; @@ -210,17 +228,25 @@ enable_childrens_resources(dev); } -static struct device_operations lpc_ops = { - .read_resources = i82801dx_lpc_read_resources, - .set_resources = pci_dev_set_resources, +static struct device_operations lpc_ops = { + .read_resources = i82801dx_lpc_read_resources, + .set_resources = pci_dev_set_resources, .enable_resources = i82801dx_lpc_enable_resources, - .init = lpc_init, - .scan_bus = scan_static_bus, - .enable = i82801dx_enable, + .init = lpc_init, + .scan_bus = scan_static_bus, + .enable = i82801dx_enable, +}; + +/* 82801DB/DBL */ +static const struct pci_driver lpc_driver_db __pci_driver = { + .ops = &lpc_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = PCI_DEVICE_ID_INTEL_82801DB_LPC, }; -static const struct pci_driver lpc_driver __pci_driver = { - .ops = &lpc_ops, +/* 82801DBM */ +static const struct pci_driver lpc_driver_dbm __pci_driver = { + .ops = &lpc_ops, .vendor = PCI_VENDOR_ID_INTEL, .device = PCI_DEVICE_ID_INTEL_82801DBM_LPC, }; Modified: trunk/src/southbridge/intel/i82801dx/i82801dx_pci.c ============================================================================== --- trunk/src/southbridge/intel/i82801dx/i82801dx_pci.c Sat Mar 13 23:07:15 2010 (r5206) +++ trunk/src/southbridge/intel/i82801dx/i82801dx_pci.c Sun Mar 14 18:01:08 2010 (r5207) @@ -1,3 +1,22 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2004 Ronald G. Minnich + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + #include <console/console.h> #include <device/device.h> #include <device/pci.h> @@ -11,23 +30,29 @@ uint32_t dword; /* System error enable */ dword = pci_read_config32(dev, 0x04); - dword |= (1<<8); /* SERR# Enable */ - dword |= (1<<6); /* Parity Error Response */ + dword |= (1 << 8); /* SERR# Enable */ + dword |= (1 << 6); /* Parity Error Response */ pci_write_config32(dev, 0x04, dword); - } -static struct device_operations pci_ops = { - .read_resources = pci_bus_read_resources, - .set_resources = pci_dev_set_resources, +static struct device_operations pci_ops = { + .read_resources = pci_bus_read_resources, + .set_resources = pci_dev_set_resources, .enable_resources = pci_bus_enable_resources, - .init = pci_init, - .scan_bus = pci_scan_bridge, + .init = pci_init, + .scan_bus = pci_scan_bridge, }; -static const struct pci_driver pci_driver __pci_driver = { - .ops = &pci_ops, +/* 82801DB */ +static const struct pci_driver pci_driver_db __pci_driver = { + .ops = &pci_ops, .vendor = PCI_VENDOR_ID_INTEL, - .device = PCI_DEVICE_ID_INTEL_82801DBM_PCI, + .device = PCI_DEVICE_ID_INTEL_82801DB_PCI, }; +/* 82801DBM/DBL */ +static const struct pci_driver pci_driver_dbm __pci_driver = { + .ops = &pci_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = PCI_DEVICE_ID_INTEL_82801DBM_PCI, +}; Modified: trunk/src/southbridge/intel/i82801dx/i82801dx_reset.c ============================================================================== --- trunk/src/southbridge/intel/i82801dx/i82801dx_reset.c Sat Mar 13 23:07:15 2010 (r5206) +++ trunk/src/southbridge/intel/i82801dx/i82801dx_reset.c Sun Mar 14 18:01:08 2010 (r5207) @@ -1,7 +1,26 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2004 Ronald G. Minnich + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + #include <arch/io.h> void hard_reset(void) { - /* Try rebooting through port 0xcf9 */ - outb((0 <<3)|(1<<2)|(1<<1), 0xcf9); + /* Try rebooting through port 0xcf9 */ + outb((0 << 3) | (1 << 2) | (1 << 1), 0xcf9); } Modified: trunk/src/southbridge/intel/i82801dx/i82801dx_smbus.c ============================================================================== --- trunk/src/southbridge/intel/i82801dx/i82801dx_smbus.c Sat Mar 13 23:07:15 2010 (r5206) +++ trunk/src/southbridge/intel/i82801dx/i82801dx_smbus.c Sun Mar 14 18:01:08 2010 (r5207) @@ -1,3 +1,22 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2004 Ronald G. Minnich + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + #include "i82801dx.h" #include <smbus.h> #include <pci.h> @@ -6,29 +25,18 @@ #define PM_BUS 0 #define PM_DEVFN PCI_DEVFN(0x1f,3) -#if 0 -#define SMBUS_IO_BASE 0x1000 -#define SMBHSTSTAT 0 -#define SMBHSTCTL 2 -#define SMBHSTCMD 3 -#define SMBHSTADD 4 -#define SMBHSTDAT0 5 -#define SMBHSTDAT1 6 -#define SMBBLKDAT 7 -#endif - void smbus_enable(void) { unsigned char byte; /* iobase addr */ pcibios_write_config_dword(PM_BUS, PM_DEVFN, 0x20, SMBUS_IO_BASE | 1); /* smbus enable */ - pcibios_write_config_byte(PM_BUS, PM_DEVFN, 0x40, 1); + pcibios_write_config_byte(PM_BUS, PM_DEVFN, 0x40, 1); /* iospace enable */ pcibios_write_config_word(PM_BUS, PM_DEVFN, 0x4, 1); - /* Disable interrupt generation */ - outb(0, SMBUS_IO_BASE + SMBHSTCTL); + /* Disable interrupt generation */ + outb(0, SMBUS_IO_BASE + SMBHSTCTL); } @@ -39,7 +47,7 @@ static void smbus_wait_until_ready(void) { - while((inb(SMBUS_IO_BASE + SMBHSTSTAT) & 1) == 1) { + while ((inb(SMBUS_IO_BASE + SMBHSTSTAT) & 1) == 1) { /* nop */ } } @@ -50,8 +58,8 @@ do { byte = inb(SMBUS_IO_BASE + SMBHSTSTAT); } - while((byte &1) == 1); - while( (byte & ~1) == 0) { + while ((byte & 1) == 1); + while ((byte & ~1) == 0) { byte = inb(SMBUS_IO_BASE + SMBHSTSTAT); } } @@ -71,16 +79,18 @@ /* set the command/address... */ outb(address & 0xFF, SMBUS_IO_BASE + SMBHSTCMD); /* set up for a byte data read */ - outb((inb(SMBUS_IO_BASE + SMBHSTCTL) & 0xE3) | (0x2 << 2), SMBUS_IO_BASE + SMBHSTCTL); + outb((inb(SMBUS_IO_BASE + SMBHSTCTL) & 0xE3) | (0x2 << 2), + SMBUS_IO_BASE + SMBHSTCTL); /* clear any lingering errors, so the transaction will run */ outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT); - /* clear the data byte...*/ + /* clear the data byte... */ outb(0, SMBUS_IO_BASE + SMBHSTDAT0); /* start the command */ - outb((inb(SMBUS_IO_BASE + SMBHSTCTL) | 0x40), SMBUS_IO_BASE + SMBHSTCTL); + outb((inb(SMBUS_IO_BASE + SMBHSTCTL) | 0x40), + SMBUS_IO_BASE + SMBHSTCTL); /* poll for transaction completion */ smbus_wait_until_done(); Modified: trunk/src/southbridge/intel/i82801dx/i82801dx_tco_timer.c ============================================================================== --- trunk/src/southbridge/intel/i82801dx/i82801dx_tco_timer.c Sat Mar 13 23:07:15 2010 (r5206) +++ trunk/src/southbridge/intel/i82801dx/i82801dx_tco_timer.c Sun Mar 14 18:01:08 2010 (r5207) @@ -3,9 +3,10 @@ * * Copyright (C) 2008 Joseph Smith <joe(a)settoplinux.org> * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of @@ -14,8 +15,8 @@ * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - * + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA */ static void i82801dx_halt_tco_timer(void) @@ -33,5 +34,6 @@ pci_write_config8(dev, ACPI_CNTL, 0x10); /* Halt the TCO timer, preventing SMI and automatic reboot */ - outw(inw(PMBASE_ADDR + TCOBASE + TCO1_CNT) | (1 << 11), PMBASE_ADDR + TCOBASE + TCO1_CNT); + outw(inw(PMBASE_ADDR + TCOBASE + TCO1_CNT) | (1 << 11), + PMBASE_ADDR + TCOBASE + TCO1_CNT); } Modified: trunk/src/southbridge/intel/i82801dx/i82801dx_usb.c ============================================================================== --- trunk/src/southbridge/intel/i82801dx/i82801dx_usb.c Sat Mar 13 23:07:15 2010 (r5206) +++ trunk/src/southbridge/intel/i82801dx/i82801dx_usb.c Sun Mar 14 18:01:08 2010 (r5207) @@ -1,3 +1,24 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2004 Ronald G. Minnich + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + #include <console/console.h> #include <device/device.h> #include <device/pci.h> @@ -7,43 +28,41 @@ static void usb_init(struct device *dev) { - - -#if 0 - uint32_t cmd; + u32 cmd; printk_debug("USB: Setting up controller.. "); cmd = pci_read_config32(dev, PCI_COMMAND); - pci_write_config32(dev, PCI_COMMAND, - cmd | PCI_COMMAND_IO | PCI_COMMAND_MEMORY | - PCI_COMMAND_MASTER | PCI_COMMAND_INVALIDATE); - - + pci_write_config32(dev, PCI_COMMAND, + cmd | PCI_COMMAND_IO | PCI_COMMAND_MEMORY | + PCI_COMMAND_MASTER | PCI_COMMAND_INVALIDATE); printk_debug("done.\n"); -#endif - } -static struct device_operations usb_ops = { - .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, +static struct device_operations usb_ops = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, - .init = usb_init, - .scan_bus = 0, - .enable = i82801dx_enable, + .init = usb_init, + .scan_bus = 0, + .enable = i82801dx_enable, }; +/* 82801DB/DBL/DBM USB1 */ static const struct pci_driver usb_driver_1 __pci_driver = { - .ops = &usb_ops, + .ops = &usb_ops, .vendor = PCI_VENDOR_ID_INTEL, - .device = PCI_DEVICE_ID_INTEL_82801DBM_USB1, + .device = PCI_DEVICE_ID_INTEL_82801DB_USB1, }; + +/* 82801DB/DBL/DBM USB2 */ static const struct pci_driver usb_driver_2 __pci_driver = { - .ops = &usb_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = PCI_DEVICE_ID_INTEL_82801DBM_USB2, + .ops = &usb_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = PCI_DEVICE_ID_INTEL_82801DB_USB2, }; + +/* 82801DB/DBL/DBM USB3 */ static const struct pci_driver usb_driver_3 __pci_driver = { - .ops = &usb_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = PCI_DEVICE_ID_INTEL_82801DBM_USB3, + .ops = &usb_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = PCI_DEVICE_ID_INTEL_82801DB_USB3, }; Modified: trunk/src/southbridge/intel/i82801dx/i82801dx_usb2.c ============================================================================== --- trunk/src/southbridge/intel/i82801dx/i82801dx_usb2.c Sat Mar 13 23:07:15 2010 (r5206) +++ trunk/src/southbridge/intel/i82801dx/i82801dx_usb2.c Sun Mar 14 18:01:08 2010 (r5207) @@ -1,4 +1,23 @@ -//2003 Copywright Tyan +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2003 Tyan + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ #include <console/console.h> #include <device/device.h> @@ -9,32 +28,27 @@ static void usb2_init(struct device *dev) { - - -#if 0 - uint32_t cmd; + u32 cmd; printk_debug("USB: Setting up controller.. "); cmd = pci_read_config32(dev, PCI_COMMAND); - pci_write_config32(dev, PCI_COMMAND, - cmd | PCI_COMMAND_IO | PCI_COMMAND_MEMORY | - PCI_COMMAND_MASTER | PCI_COMMAND_INVALIDATE); - - + pci_write_config32(dev, PCI_COMMAND, + cmd | PCI_COMMAND_IO | PCI_COMMAND_MEMORY | + PCI_COMMAND_MASTER | PCI_COMMAND_INVALIDATE); printk_debug("done.\n"); -#endif } -static struct device_operations usb2_ops = { - .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, +static struct device_operations usb2_ops = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, - .init = usb2_init, - .scan_bus = 0, - .enable = i82801dx_enable, + .init = usb2_init, + .scan_bus = 0, + .enable = i82801dx_enable, }; +/* 82801DB/DBM USB 2.0 */ static const struct pci_driver usb2_driver __pci_driver = { - .ops = &usb2_ops, + .ops = &usb2_ops, .vendor = PCI_VENDOR_ID_INTEL, - .device = PCI_DEVICE_ID_INTEL_82801DBM_EHCI, + .device = PCI_DEVICE_ID_INTEL_82801DB_EHCI, };

1 0

[PATCH] Implement DRAM buffer strength programming for 440BX
by Keith Hui 14 Mar '10

14 Mar '10

> > Below are debug outputs of my new RAM init code. As you can see it > > isn't quite working. Can this output help in finding out why? > No. You'll have to run a diff between the old (working?) and the new > code and do a binary search over the changes to find out what's causing > the trouble. > > Stefan Thank you! With your hint, I realized that I have made too many changes at once and will have to make and test them one by one instead. The result is this patch. It implements a full SDRAM buffer strength programming algorithm in set_dram_buffer_strength(), checked against my P2B-LS factory BIOS. With this in place, I now have 133MHz (!) stability with three 256MB PC133 modules, and can boot Fedora 11 all the way to the init daemon (actually upstart, but that's another story). Not to login prompt yet. We'll find out why later. This again assumes a 4-DIMM board because that's all I have. I need someone with a 3-DIMM board to test it. As a bonus, there's a big comment block within that illustrates the algorithm. :-) Signed-off-by: Keith Hui <buurin(a)gmail.com>

1 0

[commit] r5206 - in trunk/src: . arch/i386 arch/i386/include/arch arch/i386/llshell mainboard/thomson/ip1000
by repository service 13 Mar '10

13 Mar '10

Author: oxygene Date: Sat Mar 13 23:07:15 2010 New Revision: 5206 URL: http://tracker.coreboot.org/trac/coreboot/changeset/5206 Log: Fix llshell Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Patrick Georgi <patrick.georgi(a)coresystems.de> Added: trunk/src/arch/i386/include/arch/llshell.h trunk/src/arch/i386/llshell/console.inc trunk/src/arch/i386/llshell/pci.inc trunk/src/arch/i386/llshell/ramtest.inc Modified: trunk/src/Kconfig trunk/src/arch/i386/Makefile.inc trunk/src/arch/i386/llshell/llshell.inc trunk/src/mainboard/thomson/ip1000/romstage.c Modified: trunk/src/Kconfig ============================================================================== --- trunk/src/Kconfig Sat Mar 13 21:36:11 2010 (r5205) +++ trunk/src/Kconfig Sat Mar 13 23:07:15 2010 (r5206) @@ -793,6 +793,14 @@ If unsure, say N. +config LLSHELL + bool "Built-in low-level shell" + default n + help + If enabled, you will have a low level shell to examine your machine. + Put llshell() in your (romstage) code to start the shell. + See src/arch/i386/llshell/llshell.inc for details. + endmenu config LIFT_BSP_APIC_ID Modified: trunk/src/arch/i386/Makefile.inc ============================================================================== --- trunk/src/arch/i386/Makefile.inc Sat Mar 13 21:36:11 2010 (r5205) +++ trunk/src/arch/i386/Makefile.inc Sat Mar 13 23:07:15 2010 (r5206) @@ -148,6 +148,11 @@ crt0s += $(obj)/mainboard/$(MAINBOARDDIR)/failover.inc endif endif + +ifeq ($(CONFIG_LLSHELL),y) +crt0s += $(src)/arch/i386/llshell/llshell.inc +endif + crt0s += $(obj)/mainboard/$(MAINBOARDDIR)/romstage.inc ifeq ($(CONFIG_SSE),y) Added: trunk/src/arch/i386/include/arch/llshell.h ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/arch/i386/include/arch/llshell.h Sat Mar 13 23:07:15 2010 (r5206) @@ -0,0 +1,11 @@ +#ifndef __ARCH_LLSHELL__ +#define __ARCH_LLSHELL__ + + +#if CONFIG_LLSHELL +#define llshell() asm("jmp low_level_shell"); +#else +#define llshell() print_debug("LLSHELL not active.\n"); +#endif + +#endif Added: trunk/src/arch/i386/llshell/console.inc ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/arch/i386/llshell/console.inc Sat Mar 13 23:07:15 2010 (r5206) @@ -0,0 +1,515 @@ +// #include <loglevel.h> + +jmp console0 + +#define __STR(X) #X +#define STR(X) __STR(X) + + +#undef STR + /* uses: ax, dx */ +#if defined(SERIAL_CONSOLE) +#define __CONSOLE_INLINE_TX_AL TTYS0_TX_AL +#else +#define __CONSOLE_INLINE_TX_AL +#endif + + /* uses: esp, ax, dx */ +#define __CONSOLE_TX_CHAR(byte) \ + mov byte, %al ; \ + CALLSP(console_tx_al) + + /* uses: ax, dx */ +#define __CONSOLE_INLINE_TX_CHAR(byte) \ + mov byte, %al ; \ + __CONSOLE_INLINE_TX_AL + + /* uses: esp, ax, edx */ +#define __CONSOLE_TX_HEX8(byte) \ + mov byte, %al ; \ + CALLSP(console_tx_hex8) + + /* uses: byte, ax, dx */ +#define __CONSOLE_INLINE_TX_HEX8(byte) \ + movb byte, %dl ; \ + shll $16, %edx ; \ + shr $4, %al ; \ + add $'0', %al ; \ + cmp $'9', %al ; \ + jle 9f ; \ + add $39, %al ; \ +9: ; \ + __CONSOLE_INLINE_TX_AL ; \ + shrl $16, %edx ; \ + movb %dl, %al ; \ + and $0x0f, %al ; \ + add $'0', %al ; \ + cmp $'9', %al ; \ + jle 9f ; \ + add $39, %al ; \ +9: ; \ + __CONSOLE_INLINE_TX_AL + + /* uses: esp, eax, ebx, dx */ +#define __CONSOLE_TX_HEX32(lword) \ + mov lword, %eax ; \ + CALLSP(console_tx_hex32) + + /* uses: eax, lword, dx */ +#define __CONSOLE_INLINE_TX_HEX32(lword) \ + mov lword, %eax ; \ + shr $28, %eax ; \ + add $'0', %al ; \ + cmp $'9', %al ; \ + jle 9f ; \ + add $39, %al ; \ +9: ; \ + __CONSOLE_INLINE_TX_AL ; \ + ; \ + mov lword, %eax ; \ + shr $24, %eax ; \ + and $0x0f, %al ; \ + add $'0', %al ; \ + cmp $'9', %al ; \ + jle 9f ; \ + add $39, %al ; \ +9: ; \ + __CONSOLE_INLINE_TX_AL ; \ + ; \ + mov lword, %eax ; \ + shr $20, %eax ; \ + and $0x0f, %al ; \ + add $'0', %al ; \ + cmp $'9', %al ; \ + jle 9f ; \ + add $39, %al ; \ +9: ; \ + __CONSOLE_INLINE_TX_AL ; \ + ; \ + mov lword, %eax ; \ + shr $16, %eax ; \ + and $0x0f, %al ; \ + add $'0', %al ; \ + cmp $'9', %al ; \ + jle 9f ; \ + add $39, %al ; \ +9: ; \ + __CONSOLE_INLINE_TX_AL ; \ + ; \ + mov lword, %eax ; \ + shr $12, %eax ; \ + and $0x0f, %al ; \ + add $'0', %al ; \ + cmp $'9', %al ; \ + jle 9f ; \ + add $39, %al ; \ +9: ; \ + __CONSOLE_INLINE_TX_AL ; \ + ; \ + mov lword, %eax ; \ + shr $8, %eax ; \ + and $0x0f, %al ; \ + add $'0', %al ; \ + cmp $'9', %al ; \ + jle 9f ; \ + add $39, %al ; \ +9: ; \ + __CONSOLE_INLINE_TX_AL ; \ + ; \ + mov lword, %eax ; \ + shr $4, %eax ; \ + and $0x0f, %al ; \ + add $'0', %al ; \ + cmp $'9', %al ; \ + jle 9f ; \ + add $39, %al ; \ +9: ; \ + __CONSOLE_INLINE_TX_AL ; \ + ; \ + mov lword, %eax ; \ + and $0x0f, %al ; \ + add $'0', %al ; \ + cmp $'9', %al ; \ + jle 9f ; \ + add $39, %al ; \ +9: ; \ + __CONSOLE_INLINE_TX_AL + + + /* uses: esp, ebx, ax, dx */ +#define __CONSOLE_TX_STRING(string) \ + mov string, %ebx ; \ + CALLSP(console_tx_string) + + /* uses: ebx, ax, dx */ +#define __CONSOLE_INLINE_TX_STRING(string) \ + movl string, %ebx ; \ +10: movb (%ebx), %al ; \ + incl %ebx ; \ + testb %al, %al ; \ + jz 11f ; \ + __CONSOLE_INLINE_TX_AL ; \ + jmp 10b ; \ +11: + + +#define CONSOLE_EMERG_TX_CHAR(byte) __CONSOLE_TX_CHAR(byte) +#define CONSOLE_EMERG_INLINE_TX_CHAR(byte) __CONSOLE_INLINE_TX_CHAR(byte) +#define CONSOLE_EMERG_TX_HEX8(byte) __CONSOLE_TX_HEX8(byte) +#define CONSOLE_EMERG_INLINE_TX_HEX8(byte) __CONSOLE_INLINE_TX_HEX8(byte) +#define CONSOLE_EMERG_TX_HEX32(lword) __CONSOLE_TX_HEX32(lword) +#define CONSOLE_EMERG_INLINE_TX_HEX32(lword) __CONSOLE_INLINE_TX_HEX32(lword) +#define CONSOLE_EMERG_TX_STRING(string) __CONSOLE_TX_STRING(string) +#define CONSOLE_EMERG_INLINE_TX_STRING(string) __CONSOLE_INLINE_TX_STRING(string) + +#define CONSOLE_ALERT_TX_CHAR(byte) __CONSOLE_TX_CHAR(byte) +#define CONSOLE_ALERT_INLINE_TX_CHAR(byte) __CONSOLE_INLINE_TX_CHAR(byte) +#define CONSOLE_ALERT_TX_HEX8(byte) __CONSOLE_TX_HEX8(byte) +#define CONSOLE_ALERT_INLINE_TX_HEX8(byte) __CONSOLE_INLINE_TX_HEX8(byte) +#define CONSOLE_ALERT_TX_HEX32(lword) __CONSOLE_TX_HEX32(lword) +#define CONSOLE_ALERT_INLINE_TX_HEX32(lword) __CONSOLE_INLINE_TX_HEX32(lword) +#define CONSOLE_ALERT_TX_STRING(string) __CONSOLE_TX_STRING(string) +#define CONSOLE_ALERT_INLINE_TX_STRING(string) __CONSOLE_INLINE_TX_STRING(string) + +#define CONSOLE_CRIT_TX_CHAR(byte) __CONSOLE_TX_CHAR(byte) +#define CONSOLE_CRIT_INLINE_TX_CHAR(byte) __CONSOLE_INLINE_TX_CHAR(byte) +#define CONSOLE_CRIT_TX_HEX8(byte) __CONSOLE_TX_HEX8(byte) +#define CONSOLE_CRIT_INLINE_TX_HEX8(byte) __CONSOLE_INLINE_TX_HEX8(byte) +#define CONSOLE_CRIT_TX_HEX32(lword) __CONSOLE_TX_HEX32(lword) +#define CONSOLE_CRIT_INLINE_TX_HEX32(lword) __CONSOLE_INLINE_TX_HEX32(lword) +#define CONSOLE_CRIT_TX_STRING(string) __CONSOLE_TX_STRING(string) +#define CONSOLE_CRIT_INLINE_TX_STRING(string) __CONSOLE_INLINE_TX_STRING(string) + +#define CONSOLE_ERR_TX_CHAR(byte) __CONSOLE_TX_CHAR(byte) +#define CONSOLE_ERR_INLINE_TX_CHAR(byte) __CONSOLE_INLINE_TX_CHAR(byte) +#define CONSOLE_ERR_TX_HEX8(byte) __CONSOLE_TX_HEX8(byte) +#define CONSOLE_ERR_INLINE_TX_HEX8(byte) __CONSOLE_INLINE_TX_HEX8(byte) +#define CONSOLE_ERR_TX_HEX32(lword) __CONSOLE_TX_HEX32(lword) +#define CONSOLE_ERR_INLINE_TX_HEX32(lword) __CONSOLE_INLINE_TX_HEX32(lword) +#define CONSOLE_ERR_TX_STRING(string) __CONSOLE_TX_STRING(string) +#define CONSOLE_ERR_INLINE_TX_STRING(string) __CONSOLE_INLINE_TX_STRING(string) + +#define CONSOLE_WARNING_TX_CHAR(byte) __CONSOLE_TX_CHAR(byte) +#define CONSOLE_WARNING_INLINE_TX_CHAR(byte) __CONSOLE_INLINE_TX_CHAR(byte) +#define CONSOLE_WARNING_TX_HEX8(byte) __CONSOLE_TX_HEX8(byte) +#define CONSOLE_WARNING_INLINE_TX_HEX8(byte) __CONSOLE_INLINE_TX_HEX8(byte) +#define CONSOLE_WARNING_TX_HEX32(lword) __CONSOLE_TX_HEX32(lword) +#define CONSOLE_WARNING_INLINE_TX_HEX32(lword) __CONSOLE_INLINE_TX_HEX32(lword) +#define CONSOLE_WARNING_TX_STRING(string) __CONSOLE_TX_STRING(string) +#define CONSOLE_WARNING_INLINE_TX_STRING(string) __CONSOLE_INLINE_TX_STRING(string) + +#define CONSOLE_NOTICE_TX_CHAR(byte) __CONSOLE_TX_CHAR(byte) +#define CONSOLE_NOTICE_INLINE_TX_CHAR(byte) __CONSOLE_INLINE_TX_CHAR(byte) +#define CONSOLE_NOTICE_TX_HEX8(byte) __CONSOLE_TX_HEX8(byte) +#define CONSOLE_NOTICE_INLINE_TX_HEX8(byte) __CONSOLE_INLINE_TX_HEX8(byte) +#define CONSOLE_NOTICE_TX_HEX32(lword) __CONSOLE_TX_HEX32(lword) +#define CONSOLE_NOTICE_INLINE_TX_HEX32(lword) __CONSOLE_INLINE_TX_HEX32(lword) +#define CONSOLE_NOTICE_TX_STRING(string) __CONSOLE_TX_STRING(string) +#define CONSOLE_NOTICE_INLINE_TX_STRING(string) __CONSOLE_INLINE_TX_STRING(string) + +#define CONSOLE_INFO_TX_CHAR(byte) __CONSOLE_TX_CHAR(byte) +#define CONSOLE_INFO_INLINE_TX_CHAR(byte) __CONSOLE_INLINE_TX_CHAR(byte) +#define CONSOLE_INFO_TX_HEX8(byte) __CONSOLE_TX_HEX8(byte) +#define CONSOLE_INFO_INLINE_TX_HEX8(byte) __CONSOLE_INLINE_TX_HEX8(byte) +#define CONSOLE_INFO_TX_HEX32(lword) __CONSOLE_TX_HEX32(lword) +#define CONSOLE_INFO_INLINE_TX_HEX32(lword) __CONSOLE_INLINE_TX_HEX32(lword) +#define CONSOLE_INFO_TX_STRING(string) __CONSOLE_TX_STRING(string) +#define CONSOLE_INFO_INLINE_TX_STRING(string) __CONSOLE_INLINE_TX_STRING(string) + +#define CONSOLE_DEBUG_TX_CHAR(byte) __CONSOLE_TX_CHAR(byte) +#define CONSOLE_DEBUG_INLINE_TX_CHAR(byte) __CONSOLE_INLINE_TX_CHAR(byte) +#define CONSOLE_DEBUG_TX_HEX8(byte) __CONSOLE_TX_HEX8(byte) +#define CONSOLE_DEBUG_INLINE_TX_HEX8(byte) __CONSOLE_INLINE_TX_HEX8(byte) +#define CONSOLE_DEBUG_TX_HEX32(lword) __CONSOLE_TX_HEX32(lword) +#define CONSOLE_DEBUG_INLINE_TX_HEX32(lword) __CONSOLE_INLINE_TX_HEX32(lword) +#define CONSOLE_DEBUG_TX_STRING(string) __CONSOLE_TX_STRING(string) +#define CONSOLE_DEBUG_INLINE_TX_STRING(string) __CONSOLE_INLINE_TX_STRING(string) + +#define CONSOLE_SPEW_TX_CHAR(byte) __CONSOLE_TX_CHAR(byte) +#define CONSOLE_SPEW_INLINE_TX_CHAR(byte) __CONSOLE_INLINE_TX_CHAR(byte) +#define CONSOLE_SPEW_TX_HEX8(byte) __CONSOLE_TX_HEX8(byte) +#define CONSOLE_SPEW_INLINE_TX_HEX8(byte) __CONSOLE_INLINE_TX_HEX8(byte) +#define CONSOLE_SPEW_TX_HEX32(lword) __CONSOLE_TX_HEX32(lword) +#define CONSOLE_SPEW_INLINE_TX_HEX32(lword) __CONSOLE_INLINE_TX_HEX32(lword) +#define CONSOLE_SPEW_TX_STRING(string) __CONSOLE_TX_STRING(string) +#define CONSOLE_SPEW_INLINE_TX_STRING(string) __CONSOLE_INLINE_TX_STRING(string) + +#if 0 +#if ASM_CONSOLE_LOGLEVEL <= BIOS_EMERG +#undef CONSOLE_EMERG_TX_CHAR +#undef CONSOLE_EMERG_INLINE_TX_CHAR +#undef CONSOLE_EMERG_TX_HEX8 +#undef CONSOLE_EMERG_INLINE_TX_HEX8 +#undef CONSOLE_EMERG_TX_HEX32 +#undef CONSOLE_EMERG_INLINE_TX_HEX32 +#undef CONSOLE_EMERG_TX_STRING +#undef CONSOLE_EMERG_INLINE_TX_STRING +#define CONSOLE_EMERG_TX_CHAR(byte) +#define CONSOLE_EMERG_INLINE_TX_CHAR(byte) +#define CONSOLE_EMERG_TX_HEX8(byte) +#define CONSOLE_EMERG_INLINE_TX_HEX8(byte) +#define CONSOLE_EMERG_TX_HEX32(lword) +#define CONSOLE_EMERG_INLINE_TX_HEX32(lword) +#define CONSOLE_EMERG_TX_STRING(string) +#define CONSOLE_EMERG_INLINE_TX_STRING(string) +#endif + + +#if ASM_CONSOLE_LOGLEVEL <= BIOS_ALERT +#undef CONSOLE_ALERT_TX_CHAR +#undef CONSOLE_ALERT_INLINE_TX_CHAR +#undef CONSOLE_ALERT_TX_HEX8 +#undef CONSOLE_ALERT_INLINE_TX_HEX8 +#undef CONSOLE_ALERT_TX_HEX32 +#undef CONSOLE_ALERT_INLINE_TX_HEX32 +#undef CONSOLE_ALERT_TX_STRING +#undef CONSOLE_ALERT_INLINE_TX_STRING +#define CONSOLE_ALERT_TX_CHAR(byte) +#define CONSOLE_ALERT_INLINE_TX_CHAR(byte) +#define CONSOLE_ALERT_TX_HEX8(byte) +#define CONSOLE_ALERT_INLINE_TX_HEX8(byte) +#define CONSOLE_ALERT_TX_HEX32(lword) +#define CONSOLE_ALERT_INLINE_TX_HEX32(lword) +#define CONSOLE_ALERT_TX_STRING(string) +#define CONSOLE_ALERT_INLINE_TX_STRING(string) +#endif + +#if ASM_CONSOLE_LOGLEVEL <= BIOS_CRIT +#undef CONSOLE_CRIT_TX_CHAR +#undef CONSOLE_CRIT_INLINE_TX_CHAR +#undef CONSOLE_CRIT_TX_HEX8 +#undef CONSOLE_CRIT_INLINE_TX_HEX8 +#undef CONSOLE_CRIT_TX_HEX32 +#undef CONSOLE_CRIT_INLINE_TX_HEX32 +#undef CONSOLE_CRIT_TX_STRING +#undef CONSOLE_CRIT_INLINE_TX_STRING +#define CONSOLE_CRIT_TX_CHAR(byte) +#define CONSOLE_CRIT_INLINE_TX_CHAR(byte) +#define CONSOLE_CRIT_TX_HEX8(byte) +#define CONSOLE_CRIT_INLINE_TX_HEX8(byte) +#define CONSOLE_CRIT_TX_HEX32(lword) +#define CONSOLE_CRIT_INLINE_TX_HEX32(lword) +#define CONSOLE_CRIT_TX_STRING(string) +#define CONSOLE_CRIT_INLINE_TX_STRING(string) +#endif + +#if ASM_CONSOLE_LOGLEVEL <= BIOS_ERR +#undef CONSOLE_ERR_TX_CHAR +#undef CONSOLE_ERR_INLINE_TX_CHAR +#undef CONSOLE_ERR_TX_HEX8 +#undef CONSOLE_ERR_INLINE_TX_HEX8 +#undef CONSOLE_ERR_TX_HEX32 +#undef CONSOLE_ERR_INLINE_TX_HEX32 +#undef CONSOLE_ERR_TX_STRING +#undef CONSOLE_ERR_INLINE_TX_STRING +#define CONSOLE_ERR_TX_CHAR(byte) +#define CONSOLE_ERR_INLINE_TX_CHAR(byte) +#define CONSOLE_ERR_TX_HEX8(byte) +#define CONSOLE_ERR_INLINE_TX_HEX8(byte) +#define CONSOLE_ERR_TX_HEX32(lword) +#define CONSOLE_ERR_INLINE_TX_HEX32(lword) +#define CONSOLE_ERR_TX_STRING(string) +#define CONSOLE_ERR_INLINE_TX_STRING(string) +#endif + +#if ASM_CONSOLE_LOGLEVEL <= BIOS_WARNING +#undef CONSOLE_WARNING_TX_CHAR +#undef CONSOLE_WARNING_INLINE_TX_CHAR +#undef CONSOLE_WARNING_TX_HEX8 +#undef CONSOLE_WARNING_INLINE_TX_HEX8 +#undef CONSOLE_WARNING_TX_HEX32 +#undef CONSOLE_WARNING_INLINE_TX_HEX32 +#undef CONSOLE_WARNING_TX_STRING +#undef CONSOLE_WARNING_INLINE_TX_STRING +#define CONSOLE_WARNING_TX_CHAR(byte) +#define CONSOLE_WARNING_INLINE_TX_CHAR(byte) +#define CONSOLE_WARNING_TX_HEX8(byte) +#define CONSOLE_WARNING_INLINE_TX_HEX8(byte) +#define CONSOLE_WARNING_TX_HEX32(lword) +#define CONSOLE_WARNING_INLINE_TX_HEX32(lword) +#define CONSOLE_WARNING_TX_STRING(string) +#define CONSOLE_WARNING_INLINE_TX_STRING(string) +#endif + +#if ASM_CONSOLE_LOGLEVEL <= BIOS_NOTICE +#undef CONSOLE_NOTICE_TX_CHAR +#undef CONSOLE_NOTICE_INLINE_TX_CHAR +#undef CONSOLE_NOTICE_TX_HEX8 +#undef CONSOLE_NOTICE_INLINE_TX_HEX8 +#undef CONSOLE_NOTICE_TX_HEX32 +#undef CONSOLE_NOTICE_INLINE_TX_HEX32 +#undef CONSOLE_NOTICE_TX_STRING +#undef CONSOLE_NOTICE_INLINE_TX_STRING +#define CONSOLE_NOTICE_TX_CHAR(byte) +#define CONSOLE_NOTICE_INLINE_TX_CHAR(byte) +#define CONSOLE_NOTICE_TX_HEX8(byte) +#define CONSOLE_NOTICE_INLINE_TX_HEX8(byte) +#define CONSOLE_NOTICE_TX_HEX32(lword) +#define CONSOLE_NOTICE_INLINE_TX_HEX32(lword) +#define CONSOLE_NOTICE_TX_STRING(string) +#define CONSOLE_NOTICE_INLINE_TX_STRING(string) +#endif + +#if ASM_CONSOLE_LOGLEVEL <= BIOS_INFO +#undef CONSOLE_INFO_TX_CHAR +#undef CONSOLE_INFO_INLINE_TX_CHAR +#undef CONSOLE_INFO_TX_HEX8 +#undef CONSOLE_INFO_INLINE_TX_HEX8 +#undef CONSOLE_INFO_TX_HEX32 +#undef CONSOLE_INFO_INLINE_TX_HEX32 +#undef CONSOLE_INFO_TX_STRING +#undef CONSOLE_INFO_INLINE_TX_STRING +#define CONSOLE_INFO_TX_CHAR(byte) +#define CONSOLE_INFO_INLINE_TX_CHAR(byte) +#define CONSOLE_INFO_TX_HEX8(byte) +#define CONSOLE_INFO_INLINE_TX_HEX8(byte) +#define CONSOLE_INFO_TX_HEX32(lword) +#define CONSOLE_INFO_INLINE_TX_HEX32(lword) +#define CONSOLE_INFO_TX_STRING(string) +#define CONSOLE_INFO_INLINE_TX_STRING(string) +#endif + +#if ASM_CONSOLE_LOGLEVEL <= BIOS_DEBUG +#undef CONSOLE_DEBUG_TX_CHAR +#undef CONSOLE_DEBUG_INLINE_TX_CHAR +#undef CONSOLE_DEBUG_TX_HEX8 +#undef CONSOLE_DEBUG_INLINE_TX_HEX8 +#undef CONSOLE_DEBUG_TX_HEX32 +#undef CONSOLE_DEBUG_INLINE_TX_HEX32 +#undef CONSOLE_DEBUG_TX_STRING +#undef CONSOLE_DEBUG_INLINE_TX_STRING +#define CONSOLE_DEBUG_TX_CHAR(byte) +#define CONSOLE_DEBUG_INLINE_TX_CHAR(byte) +#define CONSOLE_DEBUG_TX_HEX8(byte) +#define CONSOLE_DEBUG_INLINE_TX_HEX8(byte) +#define CONSOLE_DEBUG_TX_HEX32(lword) +#define CONSOLE_DEBUG_INLINE_TX_HEX32(lword) +#define CONSOLE_DEBUG_TX_STRING(string) +#define CONSOLE_DEBUG_INLINE_TX_STRING(string) +#endif + +#if ASM_CONSOLE_LOGLEVEL <= BIOS_SPEW +#undef CONSOLE_SPEW_TX_CHAR +#undef CONSOLE_SPEW_INLINE_TX_CHAR +#undef CONSOLE_SPEW_TX_HEX8 +#undef CONSOLE_SPEW_INLINE_TX_HEX8 +#undef CONSOLE_SPEW_TX_HEX32 +#undef CONSOLE_SPEW_INLINE_TX_HEX32 +#undef CONSOLE_SPEW_TX_STRING +#undef CONSOLE_SPEW_INLINE_TX_STRING +#define CONSOLE_SPEW_TX_CHAR(byte) +#define CONSOLE_SPEW_INLINE_TX_CHAR(byte) +#define CONSOLE_SPEW_TX_HEX8(byte) +#define CONSOLE_SPEW_INLINE_TX_HEX8(byte) +#define CONSOLE_SPEW_TX_HEX32(lword) +#define CONSOLE_SPEW_INLINE_TX_HEX32(lword) +#define CONSOLE_SPEW_TX_STRING(string) +#define CONSOLE_SPEW_INLINE_TX_STRING(string) +#endif +#endif + + /* uses: esp, ax, dx */ +console_tx_al: + __CONSOLE_INLINE_TX_AL + RETSP + + /* uses: esp, ax, edx */ +console_tx_hex8: + __CONSOLE_INLINE_TX_HEX8(%al) + RETSP + + + /* uses: esp, ebx, eax, dx */ +console_tx_hex32: + mov %eax, %ebx + shr $28, %eax + add $'0', %al + cmp $'9', %al + jle 9f + add $39, %al +9: + __CONSOLE_INLINE_TX_AL + + mov %ebx, %eax + shr $24, %eax + and $0x0f, %al + add $'0', %al + cmp $'9', %al + jle 9f + add $39, %al +9: + __CONSOLE_INLINE_TX_AL + + mov %ebx, %eax + shr $20, %eax + and $0x0f, %al + add $'0', %al + cmp $'9', %al + jle 9f + add $39, %al +9: + __CONSOLE_INLINE_TX_AL + + mov %ebx, %eax + shr $16, %eax + and $0x0f, %al + add $'0', %al + cmp $'9', %al + jle 9f + add $39, %al +9: + __CONSOLE_INLINE_TX_AL + + mov %ebx, %eax + shr $12, %eax + and $0x0f, %al + add $'0', %al + cmp $'9', %al + jle 9f + add $39, %al +9: + __CONSOLE_INLINE_TX_AL + + mov %ebx, %eax + shr $8, %eax + and $0x0f, %al + add $'0', %al + cmp $'9', %al + jle 9f + add $39, %al +9: + __CONSOLE_INLINE_TX_AL + + mov %ebx, %eax + shr $4, %eax + and $0x0f, %al + add $'0', %al + cmp $'9', %al + jle 9f + add $39, %al +9: + __CONSOLE_INLINE_TX_AL + + mov %ebx, %eax + and $0x0f, %al + add $'0', %al + cmp $'9', %al + jle 9f + add $39, %al +9: + __CONSOLE_INLINE_TX_AL + RETSP + + /* Uses esp, ebx, ax, dx */ + +console_tx_string: + mov (%ebx), %al + inc %ebx + cmp $0, %al + jne 9f + RETSP +9: + __CONSOLE_INLINE_TX_AL + jmp console_tx_string + +console0: Modified: trunk/src/arch/i386/llshell/llshell.inc ============================================================================== --- trunk/src/arch/i386/llshell/llshell.inc Sat Mar 13 21:36:11 2010 (r5205) +++ trunk/src/arch/i386/llshell/llshell.inc Sat Mar 13 23:07:15 2010 (r5206) @@ -1,3 +1,7 @@ +#include "console.inc" +#include "pci.inc" +#include "ramtest.inc" + jmp llshell_out // (c) 2004 Bryan Chafy, This program is released under the GPL Added: trunk/src/arch/i386/llshell/pci.inc ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/arch/i386/llshell/pci.inc Sat Mar 13 23:07:15 2010 (r5206) @@ -0,0 +1,229 @@ + + /* + * Macro: PCI_WRITE_CONFIG_BYTE + * Arguments: %eax address to write to (includes bus, device, function, &offset) + * %dl byte to write + * + * Results: none + * + * Trashed: %eax, %edx + * Effects: writes a single byte to pci config space + * + * Notes: This routine is optimized for minimal register usage. + * And the tricks it does cannot scale beyond writing a single byte. + * + * What it does is almost simple. + * It preserves %eax (baring special bits) until it is written + * out to the appropriate port. And hides the data byte + * in the high half of edx. + * + * In %edx[3] it stores the byte to write. + * In %edx[2] it stores the lower three bits of the address. + */ + + +#define PCI_WRITE_CONFIG_BYTE \ + shll $8, %edx ; \ + movb %al, %dl ; \ + andb $0x3, %dl ; \ + shll $16, %edx ; \ + \ + orl $0x80000000, %eax ; \ + andl $0xfffffffc, %eax ; \ + movw $0xcf8, %dx ; \ + outl %eax, %dx ; \ + \ + shrl $16, %edx ; \ + movb %dh, %al ; \ + movb $0, %dh ; \ + addl $0xcfc, %edx ; \ + outb %al, %dx + + + /* + * Macro: PCI_WRITE_CONFIG_WORD + * Arguments: %eax address to write to (includes bus, device, function, &offset) + * %ecx word to write + * + * Results: none + * + * Trashed: %eax, %edx + * Preserved: %ecx + * Effects: writes a single byte to pci config space + * + * Notes: This routine is optimized for minimal register usage. + * + * What it does is almost simple. + * It preserves %eax (baring special bits) until it is written + * out to the appropriate port. And hides the least significant + * bits of the address in the high half of edx. + * + * In %edx[2] it stores the lower three bits of the address. + */ + + +#define PCI_WRITE_CONFIG_WORD \ + movb %al, %dl ; \ + andl $0x3, %edx ; \ + shll $16, %edx ; \ + \ + orl $0x80000000, %eax ; \ + andl $0xfffffffc, %eax ; \ + movw $0xcf8, %dx ; \ + outl %eax, %dx ; \ + \ + shrl $16, %edx ; \ + movl %ecx, %eax ; \ + addl $0xcfc, %edx ; \ + outw %ax, %dx + + + + /* + * Macro: PCI_WRITE_CONFIG_DWORD + * Arguments: %eax address to write to (includes bus, device, function, &offset) + * %ecx dword to write + * + * Results: none + * + * Trashed: %eax, %edx + * Preserved: %ecx + * Effects: writes a single byte to pci config space + * + * Notes: This routine is optimized for minimal register usage. + * + * What it does is almost simple. + * It preserves %eax (baring special bits) until it is written + * out to the appropriate port. And hides the least significant + * bits of the address in the high half of edx. + * + * In %edx[2] it stores the lower three bits of the address. + */ + + +#define PCI_WRITE_CONFIG_DWORD \ + movb %al, %dl ; \ + andl $0x3, %edx ; \ + shll $16, %edx ; \ + \ + orl $0x80000000, %eax ; \ + andl $0xfffffffc, %eax ; \ + movw $0xcf8, %dx ; \ + outl %eax, %dx ; \ + \ + shrl $16, %edx ; \ + movl %ecx, %eax ; \ + addl $0xcfc, %edx ; \ + outl %eax, %dx + + + + + /* + * Macro: PCI_READ_CONFIG_BYTE + * Arguments: %eax address to read from (includes bus, device, function, &offset) + * + * Results: %al Byte read + * + * Trashed: %eax, %edx + * Effects: reads a single byte from pci config space + * + * Notes: This routine is optimized for minimal register usage. + * + * What it does is almost simple. + * It preserves %eax (baring special bits) until it is written + * out to the appropriate port. And hides the least significant + * bits of the address in the high half of edx. + * + * In %edx[2] it stores the lower three bits of the address. + */ + + +#define PCI_READ_CONFIG_BYTE \ + movb %al, %dl ; \ + andl $0x3, %edx ; \ + shll $16, %edx ; \ + \ + orl $0x80000000, %eax ; \ + andl $0xfffffffc, %eax ; \ + movw $0xcf8, %dx ; \ + outl %eax, %dx ; \ + \ + shrl $16, %edx ; \ + addl $0xcfc, %edx ; \ + inb %dx, %al + + + + /* + * Macro: PCI_READ_CONFIG_WORD + * Arguments: %eax address to read from (includes bus, device, function, &offset) + * + * Results: %ax word read + * + * Trashed: %eax, %edx + * Effects: reads a 2 bytes from pci config space + * + * Notes: This routine is optimized for minimal register usage. + * + * What it does is almost simple. + * It preserves %eax (baring special bits) until it is written + * out to the appropriate port. And hides the least significant + * bits of the address in the high half of edx. + * + * In %edx[2] it stores the lower three bits of the address. + */ + + +#define PCI_READ_CONFIG_WORD \ + movb %al, %dl ; \ + andl $0x3, %edx ; \ + shll $16, %edx ; \ + \ + orl $0x80000000, %eax ; \ + andl $0xfffffffc, %eax ; \ + movw $0xcf8, %dx ; \ + outl %eax, %dx ; \ + \ + shrl $16, %edx ; \ + addl $0xcfc, %edx ; \ + inw %dx, %ax + + + + /* + * Macro: PCI_READ_CONFIG_DWORD + * Arguments: %eax address to read from (includes bus, device, function, &offset) + * + * Results: %eax + * + * Trashed: %edx + * Effects: reads 4 bytes from pci config space + * + * Notes: This routine is optimized for minimal register usage. + * + * What it does is almost simple. + * It preserves %eax (baring special bits) until it is written + * out to the appropriate port. And hides the least significant + * bits of the address in the high half of edx. + * + * In %edx[2] it stores the lower three bits of the address. + */ + + +#define PCI_READ_CONFIG_DWORD \ + movb %al, %dl ; \ + andl $0x3, %edx ; \ + shll $16, %edx ; \ + \ + orl $0x80000000, %eax ; \ + andl $0xfffffffc, %eax ; \ + movw $0xcf8, %dx ; \ + outl %eax, %dx ; \ + \ + shrl $16, %edx ; \ + addl $0xcfc, %edx ; \ + inl %dx, %eax + + + Added: trunk/src/arch/i386/llshell/ramtest.inc ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/arch/i386/llshell/ramtest.inc Sat Mar 13 23:07:15 2010 (r5206) @@ -0,0 +1,125 @@ + /* + * This is much more of a "Is my SDRAM properly configured?" + * test than a "Is my SDRAM faulty?" test. Not all bits + * are tested. -Tyson + */ + + jmp rt_skip +#define RAMTEST 1 +#if RAMTEST + .section ".rom.data" + +rt_test: .string "Testing SDRAM : " +rt_fill: .string "SDRAM fill:\r\n" +rt_verify: .string "SDRAM verify:\r\n" +rt_toomany: .string "Too many errors.\r\n" +rt_done: .string "Done.\r\n" + .previous +#endif + +ramtest: +#if RAMTEST + mov %eax, %esi + mov %ebx, %edi + mov %esp, %ebp + + CONSOLE_INFO_TX_STRING($rt_test) + CONSOLE_INFO_TX_HEX32(%esi) + CONSOLE_INFO_TX_CHAR($'-') + CONSOLE_INFO_TX_HEX32(%edi) + CONSOLE_INFO_TX_CHAR($'\r') + CONSOLE_INFO_TX_CHAR($'\n') + + /* ============== Fill ram block ==== */ + + CONSOLE_INFO_TX_STRING($rt_fill) + + mov %esi, %ebx +1: + cmp $0, %bx + jne 2f + + /* Display address being filled */ + /* CONSOLE_INFO_TX_HEX32(arg) will overwrite %ebx with arg */ + + CONSOLE_INFO_TX_HEX32(%ebx) + CONSOLE_INFO_TX_CHAR($'\r') +2: +#if i786 + /* Use a non temporal store to go faster and + * to bypass the cache. + */ + movnti %ebx, (%ebx) +#else + mov %ebx, (%ebx) +#endif + add $4, %ebx + cmp %edi, %ebx + jl 1b + + /* Display final address */ + + CONSOLE_INFO_TX_HEX32(%edi) + CONSOLE_INFO_TX_CHAR($'\r') + CONSOLE_INFO_TX_CHAR($'\n') + + /* ========= Verify ram block ========== */ + + CONSOLE_INFO_TX_STRING($rt_verify) + mov %esi, %ebx + +1: + cmp $0, %bx + jne 2f + + /* Display address being tested */ + + CONSOLE_INFO_TX_HEX32(%ebx) + CONSOLE_INFO_TX_CHAR($'\r') +2: + cmp %ebx, (%ebx) + jne 4f +3: + add $4, %ebx + cmp %edi, %ebx + jl 1b + + /* Display final address */ + CONSOLE_INFO_TX_HEX32(%edi) + CONSOLE_INFO_TX_CHAR($'\r') + CONSOLE_INFO_TX_CHAR($'\n') + jmp 6f + +4: + /* Display address with error */ + + CONSOLE_INFO_TX_HEX32(%ebx) + CONSOLE_INFO_TX_CHAR($':') + + /* Display data in address with error */ + + /* CONSOLE_INFO_TX_HEX32(arg) will overwrite %ebx with arg */ + + mov %ebx, %esi + mov 0(%ebx), %eax + CONSOLE_INFO_TX_HEX32(%eax) + mov %esi, %ebx + + CONSOLE_INFO_TX_CHAR($'\r') + CONSOLE_INFO_TX_CHAR($'\n') + sub $1, %ecx + jz 5f + jmp 3b +5: + CONSOLE_INFO_TX_STRING($rt_toomany) + intel_chip_post_macro(0xf1) + jmp .Lhlt + +6: + CONSOLE_INFO_TX_STRING($rt_done) + mov %ebp, %esp + +#endif + RETSP + +rt_skip: Modified: trunk/src/mainboard/thomson/ip1000/romstage.c ============================================================================== --- trunk/src/mainboard/thomson/ip1000/romstage.c Sat Mar 13 21:36:11 2010 (r5205) +++ trunk/src/mainboard/thomson/ip1000/romstage.c Sat Mar 13 23:07:15 2010 (r5206) @@ -28,6 +28,7 @@ #include <device/pnp_def.h> #include <arch/romcc_io.h> #include <arch/hlt.h> +#include <arch/llshell.h> #include "pc80/serial.c" #include "pc80/udelay_io.c" #include "arch/i386/lib/console.c" @@ -129,6 +130,9 @@ /* Initialize memory */ sdram_initialize(); +#if CONFIG_LLSHELL + llshell(); +#endif /* Check RAM. */ /* ram_check(0, 640 * 1024); */ /* ram_check(64512 * 1024, 65536 * 1024); */

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coreboot March 2010