coreboot March 2010

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[commit] r5205 - in trunk/src/mainboard: a-trend/atc-6220 a-trend/atc-6240 abit/be6-ii_v2_0 asus/p2b asus/p2b-d asus/p2b-ds asus/p2b-f asus/p3b-f azza/pt-6ibd biostar/m6tba compaq/deskpro_en_sff_p6...
by repository service 13 Mar '10

13 Mar '10

Author: uwe Date: Sat Mar 13 21:36:11 2010 New Revision: 5205 URL: http://tracker.coreboot.org/trac/coreboot/changeset/5205 Log: Use CPU_INTEL_SLOT_1 for Slot 1 boards (trivial). This fixes a longstanding TODO item. Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Modified: trunk/src/mainboard/a-trend/atc-6220/Kconfig trunk/src/mainboard/a-trend/atc-6220/devicetree.cb trunk/src/mainboard/a-trend/atc-6240/Kconfig trunk/src/mainboard/a-trend/atc-6240/devicetree.cb trunk/src/mainboard/abit/be6-ii_v2_0/Kconfig trunk/src/mainboard/abit/be6-ii_v2_0/devicetree.cb trunk/src/mainboard/asus/p2b-d/Kconfig trunk/src/mainboard/asus/p2b-d/devicetree.cb trunk/src/mainboard/asus/p2b-ds/Kconfig trunk/src/mainboard/asus/p2b-ds/devicetree.cb trunk/src/mainboard/asus/p2b-f/Kconfig trunk/src/mainboard/asus/p2b-f/devicetree.cb trunk/src/mainboard/asus/p2b/Kconfig trunk/src/mainboard/asus/p2b/devicetree.cb trunk/src/mainboard/asus/p3b-f/Kconfig trunk/src/mainboard/asus/p3b-f/devicetree.cb trunk/src/mainboard/azza/pt-6ibd/Kconfig trunk/src/mainboard/azza/pt-6ibd/devicetree.cb trunk/src/mainboard/biostar/m6tba/Kconfig trunk/src/mainboard/biostar/m6tba/devicetree.cb trunk/src/mainboard/compaq/deskpro_en_sff_p600/Kconfig trunk/src/mainboard/compaq/deskpro_en_sff_p600/devicetree.cb trunk/src/mainboard/gigabyte/ga-6bxc/Kconfig trunk/src/mainboard/gigabyte/ga-6bxc/devicetree.cb trunk/src/mainboard/msi/ms6119/Kconfig trunk/src/mainboard/msi/ms6119/devicetree.cb trunk/src/mainboard/msi/ms6147/Kconfig trunk/src/mainboard/msi/ms6147/devicetree.cb trunk/src/mainboard/msi/ms6156/Kconfig trunk/src/mainboard/msi/ms6156/devicetree.cb trunk/src/mainboard/soyo/sy-6ba-plus-iii/Kconfig trunk/src/mainboard/soyo/sy-6ba-plus-iii/devicetree.cb trunk/src/mainboard/tyan/s1846/Kconfig trunk/src/mainboard/tyan/s1846/devicetree.cb Modified: trunk/src/mainboard/a-trend/atc-6220/Kconfig ============================================================================== --- trunk/src/mainboard/a-trend/atc-6220/Kconfig Sat Mar 13 21:16:48 2010 (r5204) +++ trunk/src/mainboard/a-trend/atc-6220/Kconfig Sat Mar 13 21:36:11 2010 (r5205) @@ -21,7 +21,7 @@ config BOARD_A_TREND_ATC_6220 bool "ATC-6220" select ARCH_X86 - select CPU_INTEL_SLOT_2 + select CPU_INTEL_SLOT_1 select NORTHBRIDGE_INTEL_I440BX select SOUTHBRIDGE_INTEL_I82371EB select SUPERIO_WINBOND_W83977TF Modified: trunk/src/mainboard/a-trend/atc-6220/devicetree.cb ============================================================================== --- trunk/src/mainboard/a-trend/atc-6220/devicetree.cb Sat Mar 13 21:16:48 2010 (r5204) +++ trunk/src/mainboard/a-trend/atc-6220/devicetree.cb Sat Mar 13 21:36:11 2010 (r5205) @@ -1,6 +1,6 @@ chip northbridge/intel/i440bx # Northbridge device apic_cluster 0 on # APIC cluster - chip cpu/intel/slot_2 # CPU (FIXME: It's slot 1, actually) + chip cpu/intel/slot_1 # CPU device apic 0 on end # APIC end end Modified: trunk/src/mainboard/a-trend/atc-6240/Kconfig ============================================================================== --- trunk/src/mainboard/a-trend/atc-6240/Kconfig Sat Mar 13 21:16:48 2010 (r5204) +++ trunk/src/mainboard/a-trend/atc-6240/Kconfig Sat Mar 13 21:36:11 2010 (r5205) @@ -21,7 +21,7 @@ config BOARD_A_TREND_ATC_6240 bool "ATC-6240" select ARCH_X86 - select CPU_INTEL_SLOT_2 + select CPU_INTEL_SLOT_1 select NORTHBRIDGE_INTEL_I440BX select SOUTHBRIDGE_INTEL_I82371EB select SUPERIO_WINBOND_W83627HF Modified: trunk/src/mainboard/a-trend/atc-6240/devicetree.cb ============================================================================== --- trunk/src/mainboard/a-trend/atc-6240/devicetree.cb Sat Mar 13 21:16:48 2010 (r5204) +++ trunk/src/mainboard/a-trend/atc-6240/devicetree.cb Sat Mar 13 21:36:11 2010 (r5205) @@ -1,6 +1,6 @@ chip northbridge/intel/i440bx # Northbridge device apic_cluster 0 on # APIC cluster - chip cpu/intel/slot_2 # CPU (FIXME: It's slot 1, actually) + chip cpu/intel/slot_1 # CPU device apic 0 on end # APIC end end Modified: trunk/src/mainboard/abit/be6-ii_v2_0/Kconfig ============================================================================== --- trunk/src/mainboard/abit/be6-ii_v2_0/Kconfig Sat Mar 13 21:16:48 2010 (r5204) +++ trunk/src/mainboard/abit/be6-ii_v2_0/Kconfig Sat Mar 13 21:36:11 2010 (r5205) @@ -21,7 +21,7 @@ config BOARD_ABIT_BE6_II_V2_0 bool "BE6-II V2.0" select ARCH_X86 - select CPU_INTEL_SLOT_2 + select CPU_INTEL_SLOT_1 select NORTHBRIDGE_INTEL_I440BX select SOUTHBRIDGE_INTEL_I82371EB select SUPERIO_WINBOND_W83977TF Modified: trunk/src/mainboard/abit/be6-ii_v2_0/devicetree.cb ============================================================================== --- trunk/src/mainboard/abit/be6-ii_v2_0/devicetree.cb Sat Mar 13 21:16:48 2010 (r5204) +++ trunk/src/mainboard/abit/be6-ii_v2_0/devicetree.cb Sat Mar 13 21:36:11 2010 (r5205) @@ -1,6 +1,6 @@ chip northbridge/intel/i440bx # Northbridge device apic_cluster 0 on # APIC cluster - chip cpu/intel/slot_2 # CPU (FIXME: It's slot 1, actually) + chip cpu/intel/slot_1 # CPU device apic 0 on end # APIC end end Modified: trunk/src/mainboard/asus/p2b-d/Kconfig ============================================================================== --- trunk/src/mainboard/asus/p2b-d/Kconfig Sat Mar 13 21:16:48 2010 (r5204) +++ trunk/src/mainboard/asus/p2b-d/Kconfig Sat Mar 13 21:36:11 2010 (r5205) @@ -21,7 +21,7 @@ config BOARD_ASUS_P2B_D bool "P2B-D" select ARCH_X86 - select CPU_INTEL_SLOT_2 + select CPU_INTEL_SLOT_1 select NORTHBRIDGE_INTEL_I440BX select SOUTHBRIDGE_INTEL_I82371EB select SUPERIO_WINBOND_W83977TF Modified: trunk/src/mainboard/asus/p2b-d/devicetree.cb ============================================================================== --- trunk/src/mainboard/asus/p2b-d/devicetree.cb Sat Mar 13 21:16:48 2010 (r5204) +++ trunk/src/mainboard/asus/p2b-d/devicetree.cb Sat Mar 13 21:36:11 2010 (r5205) @@ -1,9 +1,9 @@ chip northbridge/intel/i440bx # Northbridge device apic_cluster 0 on # APIC cluster - chip cpu/intel/slot_2 # CPU (FIXME: It's slot 1, actually) + chip cpu/intel/slot_1 # CPU device apic 0 on end # APIC end - chip cpu/intel/slot_2 # CPU (FIXME: It's slot 1, actually) + chip cpu/intel/slot_1 # CPU device apic 1 on end # APIC end end Modified: trunk/src/mainboard/asus/p2b-ds/Kconfig ============================================================================== --- trunk/src/mainboard/asus/p2b-ds/Kconfig Sat Mar 13 21:16:48 2010 (r5204) +++ trunk/src/mainboard/asus/p2b-ds/Kconfig Sat Mar 13 21:36:11 2010 (r5205) @@ -21,7 +21,7 @@ config BOARD_ASUS_P2B_DS bool "P2B-DS" select ARCH_X86 - select CPU_INTEL_SLOT_2 + select CPU_INTEL_SLOT_1 select NORTHBRIDGE_INTEL_I440BX select SOUTHBRIDGE_INTEL_I82371EB select SUPERIO_WINBOND_W83977TF Modified: trunk/src/mainboard/asus/p2b-ds/devicetree.cb ============================================================================== --- trunk/src/mainboard/asus/p2b-ds/devicetree.cb Sat Mar 13 21:16:48 2010 (r5204) +++ trunk/src/mainboard/asus/p2b-ds/devicetree.cb Sat Mar 13 21:36:11 2010 (r5205) @@ -1,9 +1,9 @@ chip northbridge/intel/i440bx # Northbridge device apic_cluster 0 on # APIC cluster - chip cpu/intel/slot_2 # CPU (FIXME: It's slot 1, actually) + chip cpu/intel/slot_1 # CPU device apic 0 on end # APIC end - chip cpu/intel/slot_2 # CPU (FIXME: It's slot 1, actually) + chip cpu/intel/slot_1 # CPU device apic 1 on end # APIC end end Modified: trunk/src/mainboard/asus/p2b-f/Kconfig ============================================================================== --- trunk/src/mainboard/asus/p2b-f/Kconfig Sat Mar 13 21:16:48 2010 (r5204) +++ trunk/src/mainboard/asus/p2b-f/Kconfig Sat Mar 13 21:36:11 2010 (r5205) @@ -21,7 +21,7 @@ config BOARD_ASUS_P2B_F bool "P2B-F" select ARCH_X86 - select CPU_INTEL_SLOT_2 + select CPU_INTEL_SLOT_1 select NORTHBRIDGE_INTEL_I440BX select SOUTHBRIDGE_INTEL_I82371EB select SUPERIO_WINBOND_W83977TF Modified: trunk/src/mainboard/asus/p2b-f/devicetree.cb ============================================================================== --- trunk/src/mainboard/asus/p2b-f/devicetree.cb Sat Mar 13 21:16:48 2010 (r5204) +++ trunk/src/mainboard/asus/p2b-f/devicetree.cb Sat Mar 13 21:36:11 2010 (r5205) @@ -1,6 +1,6 @@ chip northbridge/intel/i440bx # Northbridge device apic_cluster 0 on # APIC cluster - chip cpu/intel/slot_2 # CPU (FIXME: It's slot 1, actually) + chip cpu/intel/slot_1 # CPU device apic 0 on end # APIC end end Modified: trunk/src/mainboard/asus/p2b/Kconfig ============================================================================== --- trunk/src/mainboard/asus/p2b/Kconfig Sat Mar 13 21:16:48 2010 (r5204) +++ trunk/src/mainboard/asus/p2b/Kconfig Sat Mar 13 21:36:11 2010 (r5205) @@ -21,7 +21,7 @@ config BOARD_ASUS_P2B bool "P2B" select ARCH_X86 - select CPU_INTEL_SLOT_2 + select CPU_INTEL_SLOT_1 select NORTHBRIDGE_INTEL_I440BX select SOUTHBRIDGE_INTEL_I82371EB select SUPERIO_WINBOND_W83977TF Modified: trunk/src/mainboard/asus/p2b/devicetree.cb ============================================================================== --- trunk/src/mainboard/asus/p2b/devicetree.cb Sat Mar 13 21:16:48 2010 (r5204) +++ trunk/src/mainboard/asus/p2b/devicetree.cb Sat Mar 13 21:36:11 2010 (r5205) @@ -1,6 +1,6 @@ chip northbridge/intel/i440bx # Northbridge device apic_cluster 0 on # APIC cluster - chip cpu/intel/slot_2 # CPU (FIXME: It's slot 1, actually) + chip cpu/intel/slot_1 # CPU device apic 0 on end # APIC end end Modified: trunk/src/mainboard/asus/p3b-f/Kconfig ============================================================================== --- trunk/src/mainboard/asus/p3b-f/Kconfig Sat Mar 13 21:16:48 2010 (r5204) +++ trunk/src/mainboard/asus/p3b-f/Kconfig Sat Mar 13 21:36:11 2010 (r5205) @@ -21,7 +21,7 @@ config BOARD_ASUS_P3B_F bool "P3B-F" select ARCH_X86 - select CPU_INTEL_SLOT_2 + select CPU_INTEL_SLOT_1 select NORTHBRIDGE_INTEL_I440BX select SOUTHBRIDGE_INTEL_I82371EB select SUPERIO_WINBOND_W83977TF Modified: trunk/src/mainboard/asus/p3b-f/devicetree.cb ============================================================================== --- trunk/src/mainboard/asus/p3b-f/devicetree.cb Sat Mar 13 21:16:48 2010 (r5204) +++ trunk/src/mainboard/asus/p3b-f/devicetree.cb Sat Mar 13 21:36:11 2010 (r5205) @@ -1,6 +1,6 @@ chip northbridge/intel/i440bx # Northbridge device apic_cluster 0 on # APIC cluster - chip cpu/intel/slot_2 # CPU (FIXME: It's slot 1, actually) + chip cpu/intel/slot_1 # CPU device apic 0 on end # APIC end end Modified: trunk/src/mainboard/azza/pt-6ibd/Kconfig ============================================================================== --- trunk/src/mainboard/azza/pt-6ibd/Kconfig Sat Mar 13 21:16:48 2010 (r5204) +++ trunk/src/mainboard/azza/pt-6ibd/Kconfig Sat Mar 13 21:36:11 2010 (r5205) @@ -21,7 +21,7 @@ config BOARD_AZZA_PT_6IBD bool "PT-6IBD" select ARCH_X86 - select CPU_INTEL_SLOT_2 + select CPU_INTEL_SLOT_1 select NORTHBRIDGE_INTEL_I440BX select SOUTHBRIDGE_INTEL_I82371EB select SUPERIO_WINBOND_W83977TF Modified: trunk/src/mainboard/azza/pt-6ibd/devicetree.cb ============================================================================== --- trunk/src/mainboard/azza/pt-6ibd/devicetree.cb Sat Mar 13 21:16:48 2010 (r5204) +++ trunk/src/mainboard/azza/pt-6ibd/devicetree.cb Sat Mar 13 21:36:11 2010 (r5205) @@ -1,6 +1,6 @@ chip northbridge/intel/i440bx # Northbridge device apic_cluster 0 on # APIC cluster - chip cpu/intel/slot_2 # CPU (FIXME: It's slot 1, actually) + chip cpu/intel/slot_1 # CPU device apic 0 on end # APIC end end Modified: trunk/src/mainboard/biostar/m6tba/Kconfig ============================================================================== --- trunk/src/mainboard/biostar/m6tba/Kconfig Sat Mar 13 21:16:48 2010 (r5204) +++ trunk/src/mainboard/biostar/m6tba/Kconfig Sat Mar 13 21:36:11 2010 (r5205) @@ -21,7 +21,7 @@ config BOARD_BIOSTAR_M6TBA bool "M6TBA" select ARCH_X86 - select CPU_INTEL_SLOT_2 + select CPU_INTEL_SLOT_1 select NORTHBRIDGE_INTEL_I440BX select SOUTHBRIDGE_INTEL_I82371EB select SUPERIO_SMSC_SMSCSUPERIO Modified: trunk/src/mainboard/biostar/m6tba/devicetree.cb ============================================================================== --- trunk/src/mainboard/biostar/m6tba/devicetree.cb Sat Mar 13 21:16:48 2010 (r5204) +++ trunk/src/mainboard/biostar/m6tba/devicetree.cb Sat Mar 13 21:36:11 2010 (r5205) @@ -1,6 +1,6 @@ chip northbridge/intel/i440bx # Northbridge device apic_cluster 0 on # APIC cluster - chip cpu/intel/slot_2 # CPU (FIXME: It's slot 1, actually) + chip cpu/intel/slot_1 # CPU device apic 0 on end # APIC end end Modified: trunk/src/mainboard/compaq/deskpro_en_sff_p600/Kconfig ============================================================================== --- trunk/src/mainboard/compaq/deskpro_en_sff_p600/Kconfig Sat Mar 13 21:16:48 2010 (r5204) +++ trunk/src/mainboard/compaq/deskpro_en_sff_p600/Kconfig Sat Mar 13 21:36:11 2010 (r5205) @@ -21,7 +21,7 @@ config BOARD_COMPAQ_DESKPRO_EN_SFF_P600 bool "Deskpro EN SFF P600" select ARCH_X86 - select CPU_INTEL_SLOT_2 + select CPU_INTEL_SLOT_1 select NORTHBRIDGE_INTEL_I440BX select SOUTHBRIDGE_INTEL_I82371EB # should be SUPERIO_NSC_PC97307! Modified: trunk/src/mainboard/compaq/deskpro_en_sff_p600/devicetree.cb ============================================================================== --- trunk/src/mainboard/compaq/deskpro_en_sff_p600/devicetree.cb Sat Mar 13 21:16:48 2010 (r5204) +++ trunk/src/mainboard/compaq/deskpro_en_sff_p600/devicetree.cb Sat Mar 13 21:36:11 2010 (r5205) @@ -1,6 +1,6 @@ chip northbridge/intel/i440bx # Northbridge device apic_cluster 0 on # APIC cluster - chip cpu/intel/slot_2 # CPU (FIXME: It's slot 1, actually) + chip cpu/intel/slot_1 # CPU device apic 0 on end # APIC end end Modified: trunk/src/mainboard/gigabyte/ga-6bxc/Kconfig ============================================================================== --- trunk/src/mainboard/gigabyte/ga-6bxc/Kconfig Sat Mar 13 21:16:48 2010 (r5204) +++ trunk/src/mainboard/gigabyte/ga-6bxc/Kconfig Sat Mar 13 21:36:11 2010 (r5205) @@ -21,7 +21,7 @@ config BOARD_GIGABYTE_GA_6BXC bool "GA-6BXC" select ARCH_X86 - select CPU_INTEL_SLOT_2 + select CPU_INTEL_SLOT_1 select NORTHBRIDGE_INTEL_I440BX select SOUTHBRIDGE_INTEL_I82371EB select SUPERIO_ITE_IT8671F Modified: trunk/src/mainboard/gigabyte/ga-6bxc/devicetree.cb ============================================================================== --- trunk/src/mainboard/gigabyte/ga-6bxc/devicetree.cb Sat Mar 13 21:16:48 2010 (r5204) +++ trunk/src/mainboard/gigabyte/ga-6bxc/devicetree.cb Sat Mar 13 21:36:11 2010 (r5205) @@ -1,6 +1,6 @@ chip northbridge/intel/i440bx # Northbridge device apic_cluster 0 on # APIC cluster - chip cpu/intel/slot_2 # CPU (FIXME: It's slot 1, actually) + chip cpu/intel/slot_1 # CPU device apic 0 on end # APIC end end Modified: trunk/src/mainboard/msi/ms6119/Kconfig ============================================================================== --- trunk/src/mainboard/msi/ms6119/Kconfig Sat Mar 13 21:16:48 2010 (r5204) +++ trunk/src/mainboard/msi/ms6119/Kconfig Sat Mar 13 21:36:11 2010 (r5205) @@ -21,7 +21,7 @@ config BOARD_MSI_MS_6119 bool "MS-6119" select ARCH_X86 - select CPU_INTEL_SLOT_2 + select CPU_INTEL_SLOT_1 select NORTHBRIDGE_INTEL_I440BX select SOUTHBRIDGE_INTEL_I82371EB select SUPERIO_WINBOND_W83977TF Modified: trunk/src/mainboard/msi/ms6119/devicetree.cb ============================================================================== --- trunk/src/mainboard/msi/ms6119/devicetree.cb Sat Mar 13 21:16:48 2010 (r5204) +++ trunk/src/mainboard/msi/ms6119/devicetree.cb Sat Mar 13 21:36:11 2010 (r5205) @@ -1,6 +1,6 @@ chip northbridge/intel/i440bx # Northbridge device apic_cluster 0 on # APIC cluster - chip cpu/intel/slot_2 # CPU (FIXME: It's slot 1, actually) + chip cpu/intel/slot_1 # CPU device apic 0 on end # APIC end end Modified: trunk/src/mainboard/msi/ms6147/Kconfig ============================================================================== --- trunk/src/mainboard/msi/ms6147/Kconfig Sat Mar 13 21:16:48 2010 (r5204) +++ trunk/src/mainboard/msi/ms6147/Kconfig Sat Mar 13 21:36:11 2010 (r5205) @@ -21,7 +21,7 @@ config BOARD_MSI_MS_6147 bool "MS-6147" select ARCH_X86 - select CPU_INTEL_SLOT_2 + select CPU_INTEL_SLOT_1 select NORTHBRIDGE_INTEL_I440BX select SOUTHBRIDGE_INTEL_I82371EB select SUPERIO_WINBOND_W83977TF Modified: trunk/src/mainboard/msi/ms6147/devicetree.cb ============================================================================== --- trunk/src/mainboard/msi/ms6147/devicetree.cb Sat Mar 13 21:16:48 2010 (r5204) +++ trunk/src/mainboard/msi/ms6147/devicetree.cb Sat Mar 13 21:36:11 2010 (r5205) @@ -1,6 +1,6 @@ chip northbridge/intel/i440bx # Northbridge device apic_cluster 0 on # APIC cluster - chip cpu/intel/slot_2 # CPU (FIXME: It's slot 1, actually) + chip cpu/intel/slot_1 # CPU device apic 0 on end # APIC end end Modified: trunk/src/mainboard/msi/ms6156/Kconfig ============================================================================== --- trunk/src/mainboard/msi/ms6156/Kconfig Sat Mar 13 21:16:48 2010 (r5204) +++ trunk/src/mainboard/msi/ms6156/Kconfig Sat Mar 13 21:36:11 2010 (r5205) @@ -21,7 +21,7 @@ config BOARD_MSI_MS_6156 bool "MS-6156" select ARCH_X86 - select CPU_INTEL_SLOT_2 + select CPU_INTEL_SLOT_1 select NORTHBRIDGE_INTEL_I440BX select SOUTHBRIDGE_INTEL_I82371EB select SUPERIO_WINBOND_W83977TF Modified: trunk/src/mainboard/msi/ms6156/devicetree.cb ============================================================================== --- trunk/src/mainboard/msi/ms6156/devicetree.cb Sat Mar 13 21:16:48 2010 (r5204) +++ trunk/src/mainboard/msi/ms6156/devicetree.cb Sat Mar 13 21:36:11 2010 (r5205) @@ -20,7 +20,7 @@ chip northbridge/intel/i440bx # Northbridge device apic_cluster 0 on # APIC cluster - chip cpu/intel/slot_2 # CPU (FIXME: It's slot 1, actually) + chip cpu/intel/slot_1 # CPU device apic 0 on end # APIC end end Modified: trunk/src/mainboard/soyo/sy-6ba-plus-iii/Kconfig ============================================================================== --- trunk/src/mainboard/soyo/sy-6ba-plus-iii/Kconfig Sat Mar 13 21:16:48 2010 (r5204) +++ trunk/src/mainboard/soyo/sy-6ba-plus-iii/Kconfig Sat Mar 13 21:36:11 2010 (r5205) @@ -21,7 +21,7 @@ config BOARD_SOYO_SY_6BA_PLUS_III bool "SY-6BA+ III" select ARCH_X86 - select CPU_INTEL_SLOT_2 + select CPU_INTEL_SLOT_1 select NORTHBRIDGE_INTEL_I440BX select SOUTHBRIDGE_INTEL_I82371EB select SUPERIO_ITE_IT8671F Modified: trunk/src/mainboard/soyo/sy-6ba-plus-iii/devicetree.cb ============================================================================== --- trunk/src/mainboard/soyo/sy-6ba-plus-iii/devicetree.cb Sat Mar 13 21:16:48 2010 (r5204) +++ trunk/src/mainboard/soyo/sy-6ba-plus-iii/devicetree.cb Sat Mar 13 21:36:11 2010 (r5205) @@ -20,7 +20,7 @@ chip northbridge/intel/i440bx # Northbridge device apic_cluster 0 on # APIC cluster - chip cpu/intel/slot_2 # CPU (FIXME: It's slot 1, actually) + chip cpu/intel/slot_1 # CPU device apic 0 on end # APIC end end Modified: trunk/src/mainboard/tyan/s1846/Kconfig ============================================================================== --- trunk/src/mainboard/tyan/s1846/Kconfig Sat Mar 13 21:16:48 2010 (r5204) +++ trunk/src/mainboard/tyan/s1846/Kconfig Sat Mar 13 21:36:11 2010 (r5205) @@ -21,7 +21,7 @@ config BOARD_TYAN_S1846 bool "S1846 (Tsunami ATX)" select ARCH_X86 - select CPU_INTEL_SLOT_2 + select CPU_INTEL_SLOT_1 select NORTHBRIDGE_INTEL_I440BX select SOUTHBRIDGE_INTEL_I82371EB select SUPERIO_NSC_PC87309 Modified: trunk/src/mainboard/tyan/s1846/devicetree.cb ============================================================================== --- trunk/src/mainboard/tyan/s1846/devicetree.cb Sat Mar 13 21:16:48 2010 (r5204) +++ trunk/src/mainboard/tyan/s1846/devicetree.cb Sat Mar 13 21:36:11 2010 (r5205) @@ -1,6 +1,6 @@ chip northbridge/intel/i440bx # Northbridge device apic_cluster 0 on # APIC cluster - chip cpu/intel/slot_2 # CPU (FIXME: It's slot 1, actually) + chip cpu/intel/slot_1 # CPU device apic 0 on end # APIC end end

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[commit] r5204 - in trunk/src: mainboard/asus/p2b-d mainboard/asus/p2b-ds mainboard/asus/p2b-ls mainboard/asus/p3b-f northbridge/intel/i440bx
by repository service 13 Mar '10

13 Mar '10

Author: uwe Date: Sat Mar 13 21:16:48 2010 New Revision: 5204 URL: http://tracker.coreboot.org/trac/coreboot/changeset/5204 Log: Add SDRAMPWR_4DIMM Kconfig option (not user-visible in menuconfig). Each Intel 440BX board should select this option if it has 4 DIMM slots on the PCB, and _not_ select it (it defaults to 'n') if it has 3 DIMMs on the PCB. Signed-off-by: Keith Hui <buurin(a)gmail.com> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Modified: trunk/src/mainboard/asus/p2b-d/Kconfig trunk/src/mainboard/asus/p2b-ds/Kconfig trunk/src/mainboard/asus/p2b-ls/Kconfig trunk/src/mainboard/asus/p3b-f/Kconfig trunk/src/northbridge/intel/i440bx/Kconfig trunk/src/northbridge/intel/i440bx/raminit.c Modified: trunk/src/mainboard/asus/p2b-d/Kconfig ============================================================================== --- trunk/src/mainboard/asus/p2b-d/Kconfig Sat Mar 13 13:54:58 2010 (r5203) +++ trunk/src/mainboard/asus/p2b-d/Kconfig Sat Mar 13 21:16:48 2010 (r5204) @@ -31,6 +31,7 @@ select SMP select UDELAY_TSC select BOARD_ROMSIZE_KB_256 + select SDRAMPWR_4DIMM config MAINBOARD_DIR string Modified: trunk/src/mainboard/asus/p2b-ds/Kconfig ============================================================================== --- trunk/src/mainboard/asus/p2b-ds/Kconfig Sat Mar 13 13:54:58 2010 (r5203) +++ trunk/src/mainboard/asus/p2b-ds/Kconfig Sat Mar 13 21:16:48 2010 (r5204) @@ -31,6 +31,7 @@ select SMP select UDELAY_TSC select BOARD_ROMSIZE_KB_256 + select SDRAMPWR_4DIMM config MAINBOARD_DIR string Modified: trunk/src/mainboard/asus/p2b-ls/Kconfig ============================================================================== --- trunk/src/mainboard/asus/p2b-ls/Kconfig Sat Mar 13 13:54:58 2010 (r5203) +++ trunk/src/mainboard/asus/p2b-ls/Kconfig Sat Mar 13 21:16:48 2010 (r5204) @@ -29,6 +29,7 @@ select HAVE_PIRQ_TABLE select UDELAY_TSC select BOARD_ROMSIZE_KB_256 + select SDRAMPWR_4DIMM config MAINBOARD_DIR string Modified: trunk/src/mainboard/asus/p3b-f/Kconfig ============================================================================== --- trunk/src/mainboard/asus/p3b-f/Kconfig Sat Mar 13 13:54:58 2010 (r5203) +++ trunk/src/mainboard/asus/p3b-f/Kconfig Sat Mar 13 21:16:48 2010 (r5204) @@ -29,6 +29,7 @@ select HAVE_PIRQ_TABLE select UDELAY_TSC select BOARD_ROMSIZE_KB_256 + select SDRAMPWR_4DIMM config MAINBOARD_DIR string Modified: trunk/src/northbridge/intel/i440bx/Kconfig ============================================================================== --- trunk/src/northbridge/intel/i440bx/Kconfig Sat Mar 13 13:54:58 2010 (r5203) +++ trunk/src/northbridge/intel/i440bx/Kconfig Sat Mar 13 21:16:48 2010 (r5204) @@ -22,3 +22,16 @@ bool select HAVE_HIGH_TABLES +config SDRAMPWR_4DIMM + bool + depends on NORTHBRIDGE_INTEL_I440BX + default n + help + This option affects how the SDRAMC register is programmed. + Memory clock signals will not be routed properly if this option + is set wrong. + + If your board has 4 DIMM slots, you must use select this option, in + your Kconfig file of the board. On boards with 3 DIMM slots, + do _not_ select this option. + Modified: trunk/src/northbridge/intel/i440bx/raminit.c ============================================================================== --- trunk/src/northbridge/intel/i440bx/raminit.c Sat Mar 13 13:54:58 2010 (r5203) +++ trunk/src/northbridge/intel/i440bx/raminit.c Sat Mar 13 21:16:48 2010 (r5204) @@ -292,7 +292,11 @@ * 0 = 3 clocks of RAS# precharge * 1 = 2 clocks of RAS# precharge */ - SDRAMC + 0, 0x00, 0x00, +#if CONFIG_SDRAMPWR_4DIMM + SDRAMC + 0, 0x00, 0x10, /* The board has 4 DIMM slots. */ +#else + SDRAMC + 0, 0x00, 0x00, /* The board has 3 DIMM slots.*/ +#endif SDRAMC + 1, 0x00, 0x00, /* PGPOL - Paging Policy Register

1 0

Re: [coreboot] RAM support for 440BX
by Keith Hui 13 Mar '10

13 Mar '10

Below are debug outputs of my new RAM init code. As you can see it isn't quite working. Can this output help in finding out why? I had to remove a bunch of debugging messages as romcc is finally running out of registers. The code is again attached for reference. Stick used is a 128MB PC133 DIMM in slot 0. Thanks Keith coreboot-4.0-r5202M Fri Mar 12 23:12:55 EST 2010 starting... SMBus controller enabled Found DIMM in slot 00 dra = 04 Northbridge following SDRAM init: PCI: 00:00.00 00: 86 80 90 71 06 00 10 22 03 00 00 06 00 00 00 00 10: 08 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 a0 00 00 00 00 00 00 00 00 00 00 00 40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 50: 0c 8a 04 03 00 00 00 08 03 30 33 33 33 33 33 33 60: 08 10 10 10 10 10 10 10 00 ec 3f 00 a0 fa 00 00 70: 00 1f 02 38 05 00 17 01 03 03 00 38 10 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 80 00 00 00 04 61 00 00 00 05 00 00 00 00 00 00 a0: 02 00 10 00 03 02 00 1f 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 18 0c 84 ff 1f 00 00 00 d0: 00 00 00 00 00 00 00 00 0c 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 f8 00 00 20 0f 00 00 00 00 00 00 RAM Enable 1: Apply NOP CAS latency: 02 Sending RAM command 0x0001 to 0x00000000 Sending RAM command 0x0001 to 0x04000000 RAM Enable 2: Precharge all CAS latency: 02 Sending RAM command 0x0002 to 0x00000000 Sending RAM command 0x0002 to 0x04000000 RAM Enable 3: CBR CAS latency: 02 Sending RAM command 0x0004 to 0x00000000 Sending RAM command 0x0004 to 0x04000000 CAS latency: 02 Sending RAM command 0x0004 to 0x00000000 Sending RAM command 0x0004 to 0x04000000 CAS latency: 02 Sending RAM command 0x0004 to 0x00000000 Sending RAM command 0x0004 to 0x04000000 CAS latency: 02 Sending RAM command 0x0004 to 0x00000000 Sending RAM command 0x0004 to 0x04000000 CAS latency: 02 Sending RAM command 0x0004 to 0x00000000 Sending RAM command 0x0004 to 0x04000000 CAS latency: 02 Sending RAM command 0x0004 to 0x00000000 Sending RAM command 0x0004 to 0x04000000 CAS latency: 02 Sending RAM command 0x0004 to 0x00000000 Sending RAM command 0x0004 to 0x04000000 CAS latency: 02 Sending RAM command 0x0004 to 0x00000000 Sending RAM command 0x0004 to 0x04000000 RAM Enable 4: Mode register set CAS latency: 02 Sending RAM command 0x0003 to 0x00000150 Sending RAM command 0x0003 to 0x04000150 RAM Enable 5: Normal operation RAM Enable 6: Enable refresh Enabling refresh (DRAMC = 0x09) for DIMM 00 Testing DRAM : 00000000-000a0000 DRAM fill: 00000000-000a0000 000a0000 DRAM filled DRAM verify: 00000000-000a0000 Fail: @0x00000000 Read value=0x0009ff80 Fail: @0x00000004 Read value=0x0009fffc Fail: @0x00000008 Read value=0x0009ff80 Fail: @0x0000000c Read value=0x0009fffc Fail: @0x00000010 Read value=0x0009ff80 Fail: @0x00000014 Read value=0x0009fffc Fail: @0x00000018 Read value=0x0009ff80 Fail: @0x0000001c Read value=0x0009fffc Fail: @0x00000020 Read value=0x0009ff80 Fail: @0x00000024 Read value=0x0009fffc Fail: @0x00000028 Read value=0x0009ff80 Fail: @0x0000002c Read value=0x0009fffc Fail: @0x00000030 Read value=0x0009ff80 Fail: @0x00000034 Read value=0x0009fffc Fail: @0x00000038 Read value=0x0009ff80 Fail: @0x0000003c Read value=0x0009fffc Fail: @0x00000040 Read value=0x0009ff80 Fail: @0x00000044 Read value=0x0009fffc Fail: @0x00000048 Read value=0x0009ff80 Fail: @0x0000004c Read value=0x0009fffc Fail: @0x00000050 Read value=0x0009ff80 Fail: @0x00000054 Read value=0x0009fffc Fail: @0x00000058 Read value=0x0009ff80 Fail: @0x0000005c Read value=0x0009fffc Fail: @0x00000060 Read value=0x0009ff80 Fail: @0x00000064 Read value=0x0009fffc Fail: @0x00000068 Read value=0x0009ff80 Fail: @0x0000006c Read value=0x0009fffc Fail: @0x00000070 Read value=0x0009ff80 Fail: @0x00000074 Read value=0x0009fffc Fail: @0x00000078 Read value=0x0009ff80 Fail: @0x0000007c Read value=0x0009fffc Fail: @0x00000080 Read value=0x0009ff80 Fail: @0x00000084 Read value=0x0009fffc Fail: @0x00000088 Read value=0x0009ff80 Fail: @0x0000008c Read value=0x0009fffc Fail: @0x00000090 Read value=0x0009ff80 Fail: @0x00000094 Read value=0x0009fffc Fail: @0x00000098 Read value=0x0009ff80 Fail: @0x0000009c Read value=0x0009fffc Fail: @0x000000a0 Read value=0x0009ff80 Fail: @0x000000a4 Read value=0x0009fffc Fail: @0x000000a8 Read value=0x0009ff80 Fail: @0x000000ac Read value=0x0009fffc Fail: @0x000000b0 Read value=0x0009ff80 Fail: @0x000000b4 Read value=0x0009fffc Fail: @0x000000b8 Read value=0x0009ff80 Fail: @0x000000bc Read value=0x0009fffc Fail: @0x000000c0 Read value=0x0009ff80 Fail: @0x000000c4 Read value=0x0009fffc Fail: @0x000000c8 Read value=0x0009ff80 Fail: @0x000000cc Read value=0x0009fffc Fail: @0x000000d0 Read value=0x0009ff80 Fail: @0x000000d4 Read value=0x0009fffc Fail: @0x000000d8 Read value=0x0009ff80 Fail: @0x000000dc Read value=0x0009fffc Fail: @0x000000e0 Read value=0x0009ff80 Fail: @0x000000e4 Read value=0x0009fffc Fail: @0x000000e8 Read value=0x0009ff80 Fail: @0x000000ec Read value=0x0009fffc Fail: @0x000000f0 Read value=0x0009ff80 Fail: @0x000000f4 Read value=0x0009fffc Fail: @0x000000f8 Read value=0x0009ff80 Fail: @0x000000fc Read value=0x0009fffc Fail: @0x00000100 Read value=0x0009ff80 Fail: @0x00000104 Read value=0x0009fffc Fail: @0x00000108 Read value=0x0009ff80 Fail: @0x0000010c Read value=0x0009fffc Fail: @0x00000110 Read value=0x0009ff80 Fail: @0x00000114 Read value=0x0009fffc Fail: @0x00000118 Read value=0x0009ff80 Fail: @0x0000011c Read value=0x0009fffc Fail: @0x00000120 Read value=0x0009ff80 Fail: @0x00000124 Read value=0x0009fffc Fail: @0x00000128 Read value=0x0009ff80 Fail: @0x0000012c Read value=0x0009fffc Fail: @0x00000130 Read value=0x0009ff80 Fail: @0x00000134 Read value=0x0009fffc Fail: @0x00000138 Read value=0x0009ff80 Fail: @0x0000013c Read value=0x0009fffc Fail: @0x00000140 Read value=0x0009ff80 Fail: @0x00000144 Read value=0x0009fffc Fail: @0x00000148 Read value=0x0009ff80 Fail: @0x0000014c Read value=0x0009fffc Fail: @0x00000150 Read value=0x0009ff80 Fail: @0x00000154 Read value=0x0009fffc Fail: @0x00000158 Read value=0x0009ff80 Fail: @0x0000015c Read value=0x0009fffc Fail: @0x00000160 Read value=0x0009ff80 Fail: @0x00000164 Read value=0x0009fffc Fail: @0x00000168 Read value=0x0009ff80 Fail: @0x0000016c Read value=0x0009fffc Fail: @0x00000170 Read value=0x0009ff80 Fail: @0x00000174 Read value=0x0009fffc Fail: @0x00000178 Read value=0x0009ff80 Fail: @0x0000017c Read value=0x0009fffc Fail: @0x00000180 Read value=0x0009ff80 Fail: @0x00000184 Read value=0x0009fffc Fail: @0x00000188 Read value=0x0009ff80 Fail: @0x0000018c Read value=0x0009fffc Fail: @0x00000190 Read value=0x0009ff80 Fail: @0x00000194 Read value=0x0009fffc Fail: @0x00000198 Read value=0x0009ff80 Fail: @0x0000019c Read value=0x0009fffc Fail: @0x000001a0 Read value=0x0009ff80 Fail: @0x000001a4 Read value=0x0009fffc Fail: @0x000001a8 Read value=0x0009ff80 Fail: @0x000001ac Read value=0x0009fffc Fail: @0x000001b0 Read value=0x0009ff80 Fail: @0x000001b4 Read value=0x0009fffc Fail: @0x000001b8 Read value=0x0009ff80 Fail: @0x000001bc Read value=0x0009fffc Fail: @0x000001c0 Read value=0x0009ff80 Fail: @0x000001c4 Read value=0x0009fffc Fail: @0x000001c8 Read value=0x0009ff80 Fail: @0x000001cc Read value=0x0009fffc Fail: @0x000001d0 Read value=0x0009ff80 Fail: @0x000001d4 Read value=0x0009fffc Fail: @0x000001d8 Read value=0x0009ff80 Fail: @0x000001dc Read value=0x0009fffc Fail: @0x000001e0 Read value=0x0009ff80 Fail: @0x000001e4 Read value=0x0009fffc Fail: @0x000001e8 Read value=0x0009ff80 Fail: @0x000001ec Read value=0x0009fffc Fail: @0x000001f0 Read value=0x0009ff80 Fail: @0x000001f4 Read value=0x0009fffc Fail: @0x000001f8 Read value=0x0009ff80 Fail: @0x000001fc Read value=0x0009fffc Fail: @0x00000200 Read value=0x0009ff80 Fail: @0x00000204 Read value=0x0009fffc Fail: @0x00000208 Read value=0x0009ff80 Fail: @0x0000020c Read value=0x0009fffc Fail: @0x00000210 Read value=0x0009ff80 Fail: @0x00000214 Read value=0x0009fffc Fail: @0x00000218 Read value=0x0009ff80 Fail: @0x0000021c Read value=0x0009fffc Fail: @0x00000220 Read value=0x0009ff80 Fail: @0x00000224 Read value=0x0009fffc Fail: @0x00000228 Read value=0x0009ff80 Fail: @0x0000022c Read value=0x0009fffc Fail: @0x00000230 Read value=0x0009ff80 Fail: @0x00000234 Read value=0x0009fffc Fail: @0x00000238 Read value=0x0009ff80 Fail: @0x0000023c Read value=0x0009fffc Fail: @0x00000240 Read value=0x0009ff80 Fail: @0x00000244 Read value=0x0009fffc Fail: @0x00000248 Read value=0x0009ff80 Fail: @0x0000024c Read value=0x0009fffc Fail: @0x00000250 Read value=0x0009ff80 Fail: @0x00000254 Read value=0x0009fffc Fail: @0x00000258 Read value=0x0009ff80 Fail: @0x0000025c Read value=0x0009fffc Fail: @0x00000260 Read value=0x0009ff80 Fail: @0x00000264 Read value=0x0009fffc Fail: @0x00000268 Read value=0x0009ff80 Fail: @0x0000026c Read value=0x0009fffc Fail: @0x00000270 Read value=0x0009ff80 Fail: @0x00000274 Read value=0x0009fffc Fail: @0x00000278 Read value=0x0009ff80 Fail: @0x0000027c Read value=0x0009fffc Fail: @0x00000280 Read value=0x0009ff80 Fail: @0x00000284 Read value=0x0009fffc Fail: @0x00000288 Read value=0x0009ff80 Fail: @0x0000028c Read value=0x0009fffc Fail: @0x00000290 Read value=0x0009ff80 Fail: @0x00000294 Read value=0x0009fffc Fail: @0x00000298 Read value=0x0009ff80 Fail: @0x0000029c Read value=0x0009fffc Fail: @0x000002a0 Read value=0x0009ff80 Fail: @0x000002a4 Read value=0x0009fffc Fail: @0x000002a8 Read value=0x0009ff80 Fail: @0x000002ac Read value=0x0009fffc Fail: @0x000002b0 Read value=0x0009ff80 Fail: @0x000002b4 Read value=0x0009fffc Fail: @0x000002b8 Read value=0x0009ff80 Fail: @0x000002bc Read value=0x0009fffc Fail: @0x000002c0 Read value=0x0009ff80 Fail: @0x000002c4 Read value=0x0009fffc Fail: @0x000002c8 Read value=0x0009ff80 Fail: @0x000002cc Read value=0x0009fffc Fail: @0x000002d0 Read value=0x0009ff80 Fail: @0x000002d4 Read value=0x0009fffc Fail: @0x000002d8 Read value=0x0009ff80 Fail: @0x000002dc Read value=0x0009fffc Fail: @0x000002e0 Read value=0x0009ff80 Fail: @0x000002e4 Read value=0x0009fffc Fail: @0x000002e8 Read value=0x0009ff80 Fail: @0x000002ec Read value=0x0009fffc Fail: @0x000002f0 Read value=0x0009ff80 Fail: @0x000002f4 Read value=0x0009fffc Fail: @0x000002f8 Read value=0x0009ff80 Fail: @0x000002fc Read value=0x0009fffc Fail: @0x00000300 Read value=0x0009ff80 Fail: @0x00000304 Read value=0x0009fffc Fail: @0x00000308 Read value=0x0009ff80 Fail: @0x0000030c Read value=0x0009fffc Fail: @0x00000310 Read value=0x0009ff80 Fail: @0x00000314 Read value=0x0009fffc Fail: @0x00000318 Read value=0x0009ff80 Fail: @0x0000031c Read value=0x0009fffc Fail: @0x00000320 Read value=0x0009ff80 Fail: @0x00000324 Read value=0x0009fffc Fail: @0x00000328 Read value=0x0009ff80 Fail: @0x0000032c Read value=0x0009fffc Fail: @0x00000330 Read value=0x0009ff80 Fail: @0x00000334 Read value=0x0009fffc Fail: @0x00000338 Read value=0x0009ff80 Fail: @0x0000033c Read value=0x0009fffc Fail: @0x00000340 Read value=0x0009ff80 Fail: @0x00000344 Read value=0x0009fffc Fail: @0x00000348 Read value=0x0009ff80 Fail: @0x0000034c Read value=0x0009fffc Fail: @0x00000350 Read value=0x0009ff80 Fail: @0x00000354 Read value=0x0009fffc Fail: @0x00000358 Read value=0x0009ff80 Fail: @0x0000035c Read value=0x0009fffc Fail: @0x00000360 Read value=0x0009ff80 Fail: @0x00000364 Read value=0x0009fffc Fail: @0x00000368 Read value=0x0009ff80 Fail: @0x0000036c Read value=0x0009fffc Fail: @0x00000370 Read value=0x0009ff80 Fail: @0x00000374 Read value=0x0009fffc Fail: @0x00000378 Read value=0x0009ff80 Fail: @0x0000037c Read value=0x0009fffc Fail: @0x00000380 Read value=0x0009ff80 Fail: @0x00000384 Read value=0x0009fffc Fail: @0x00000388 Read value=0x0009ff80 Fail: @0x0000038c Read value=0x0009fffc Fail: @0x00000390 Read value=0x0009ff80 Fail: @0x00000394 Read value=0x0009fffc Fail: @0x00000398 Read value=0x0009ff80 Fail: @0x0000039c Read value=0x0009fffc Fail: @0x000003a0 Read value=0x0009ff80 Fail: @0x000003a4 Read value=0x0009fffc Fail: @0x000003a8 Read value=0x0009ff80 Fail: @0x000003ac Read value=0x0009fffc Fail: @0x000003b0 Read value=0x0009ff80 Fail: @0x000003b4 Read value=0x0009fffc Fail: @0x000003b8 Read value=0x0009ff80 Fail: @0x000003bc Read value=0x0009fffc Fail: @0x000003c0 Read value=0x0009ff80 Fail: @0x000003c4 Read value=0x0009fffc Fail: @0x000003c8 Read value=0x0009ff80 Fail: @0x000003cc Read value=0x0009fffc Fail: @0x000003d0 Read value=0x0009ff80 Fail: @0x000003d4 Read value=0x0009fffc Fail: @0x000003d8 Read value=0x0009ff80 Fail: @0x000003dc Read value=0x0009fffc Fail: @0x000003e0 Read value=0x0009ff80 Fail: @0x000003e4 Read value=0x0009fffc Fail: @0x000003e8 Read value=0x0009ff80 Fail: @0x000003ec Read value=0x0009fffc Fail: @0x000003f0 Read value=0x0009ff80 Fail: @0x000003f4 Read value=0x0009fffc Fail: @0x000003f8 Read value=0x0009ff80 Fail: @0x000003fc Read value=0x0009fffc Fail: @0x00000400 Read value=0x0009ff80 Aborting. 00000400 DRAM did _NOT_ verify! DRAM ERROR

2 1

[commit] r5203 - trunk/src/mainboard/supermicro/h8qme_fam10
by repository service 13 Mar '10

13 Mar '10

Author: oxygene Date: Sat Mar 13 13:54:58 2010 New Revision: 5203 URL: http://tracker.coreboot.org/trac/coreboot/changeset/5203 Log: Fix supermicro/h8qme_fam10 by enabling SPD ROM properly. Also configure GPIOs so the power LED is working. Some whitespace cleanups (but by no means comprehensive) Signed-off-by: Knut Kujat <knuku(a)gap.upv.es> Acked-by: Myles Watson <mylesgw(a)gmail.com> Modified: trunk/src/mainboard/supermicro/h8qme_fam10/romstage.c Modified: trunk/src/mainboard/supermicro/h8qme_fam10/romstage.c ============================================================================== --- trunk/src/mainboard/supermicro/h8qme_fam10/romstage.c Thu Mar 11 23:12:10 2010 (r5202) +++ trunk/src/mainboard/supermicro/h8qme_fam10/romstage.c Sat Mar 13 13:54:58 2010 (r5203) @@ -97,7 +97,10 @@ static inline void activate_spd_rom(const struct mem_controller *ctrl) { - /* nothing to do */ +#define SMBUS_SWITCH1 0x70 +#define SMBUS_SWITCH2 0x72 + smbus_send_byte(SMBUS_SWITCH1, 5 & 0x0f); + smbus_send_byte(SMBUS_SWITCH2, (5 >> 4) & 0x0f); } static inline int spd_read_byte(unsigned device, unsigned address) @@ -239,6 +242,46 @@ #include "cpu/amd/microcode/microcode.c" #include "cpu/amd/model_10xxx/update_microcode.c" +#define GPIO1_DEV PNP_DEV(0x2e, W83627HF_GAME_MIDI_GPIO1) +#define GPIO2_DEV PNP_DEV(0x2e, W83627HF_GPIO2) +#define GPIO3_DEV PNP_DEV(0x2e, W83627HF_GPIO3) +void write_GPIO(void) +{ + pnp_enter_ext_func_mode(GPIO1_DEV); + pnp_set_logical_device(GPIO1_DEV); + pnp_write_config(GPIO1_DEV, 0x30, 0x01); + pnp_write_config(GPIO1_DEV, 0x60, 0x00); + pnp_write_config(GPIO1_DEV, 0x61, 0x00); + pnp_write_config(GPIO1_DEV, 0x62, 0x00); + pnp_write_config(GPIO1_DEV, 0x63, 0x00); + pnp_write_config(GPIO1_DEV, 0x70, 0x00); + pnp_write_config(GPIO1_DEV, 0xf0, 0xff); + pnp_write_config(GPIO1_DEV, 0xf1, 0xff); + pnp_write_config(GPIO1_DEV, 0xf2, 0x00); + pnp_exit_ext_func_mode(GPIO1_DEV); + + pnp_enter_ext_func_mode(GPIO2_DEV); + pnp_set_logical_device(GPIO2_DEV); + pnp_write_config(GPIO2_DEV, 0x30, 0x01); + pnp_write_config(GPIO2_DEV, 0xf0, 0xef); + pnp_write_config(GPIO2_DEV, 0xf1, 0xff); + pnp_write_config(GPIO2_DEV, 0xf2, 0x00); + pnp_write_config(GPIO2_DEV, 0xf3, 0x00); + pnp_write_config(GPIO2_DEV, 0xf5, 0x48); + pnp_write_config(GPIO2_DEV, 0xf6, 0x00); + pnp_write_config(GPIO2_DEV, 0xf7, 0xc0); + pnp_exit_ext_func_mode(GPIO2_DEV); + + pnp_enter_ext_func_mode(GPIO3_DEV); + pnp_set_logical_device(GPIO3_DEV); + pnp_write_config(GPIO3_DEV, 0x30, 0x00); + pnp_write_config(GPIO3_DEV, 0xf0, 0xff); + pnp_write_config(GPIO3_DEV, 0xf1, 0xff); + pnp_write_config(GPIO3_DEV, 0xf2, 0xff); + pnp_write_config(GPIO3_DEV, 0xf3, 0x40); + pnp_exit_ext_func_mode(GPIO3_DEV); +} + void real_main(unsigned long bist, unsigned long cpu_init_detectedx) { struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); @@ -261,10 +304,10 @@ w83627hf_enable_dev(SERIAL_DEV, CONFIG_TTYS0_BASE); pnp_exit_ext_func_mode(SERIAL_DEV); - uart_init(); - console_init(); - printk_debug("\n"); - + uart_init(); + console_init(); + write_GPIO(); + printk_debug("\n"); /* Halt if there was a built in self test failure */ report_bist_failure(bist);

1 0

[PATCH] spd_rom FIX H8QME-2+
by Knut Kujat 12 Mar '10

12 Mar '10

Hello, this patch fixes the issue where the board wasn't able to start after getting unplugged. I also added some GPIOs so now the power on led is working. Signed-off-by: Knut Kujat <knuku(a)gap.upv.es> ---

2 2

Supermicro H8QME-2+ mct_d fatal exit.
by Knut Kujat 12 Mar '10

12 Mar '10

Hi, I've got this ugly mct_d fatal exit error again on one of my H8QME-2+ boards. Even every single board is absolutely identical 4 Opterons 16G Ram, etc... there are several boards booting and working without any problem with coreboot and others don't even start and mct_d fatal exit :(. Has someone an idea what the problem could be ? Thanks any comment would be appreciated. Knut Kujat

7 18

Re: [coreboot] Getting started with Coreboot on Intel Core
by Karl-Heinz Nirschl 12 Mar '10

12 Mar '10

Hi, no i use crossgcc which looks fine, but still can't hang with postcode 0x23. if have the following in crt0.disasm: 153 0148 B023E680 post_code(0x23) 154 155 014c E8FCFFFF call stage1_main 155 FF and the following in romstage.inc (both from build dir): stage1_main: subl $24, %esp /APP / 29 "/home/xxx/coreboot/src/cpu/intel/model_6ex/cache_as_ram_disable.c" 1 movb 0xa4, %al outb %al, $0x80 so i suppose i should at least see postcode 0xa4 if the call instruction succeeds. any further hints what i could have done wrong? regards, khn

1 1

SeaBIOS support for high-speed (EHCI) USB
by Kevin O'Connor 11 Mar '10

11 Mar '10

Hi, The latest SeaBIOS git now has support for EHCI USB controllers. This is in addition to the UHCI and OHCI support already in SeaBIOS. To obtain SeaBIOS, see: http://seabios.org/Download I've tested the EHCI support on my epia-cn. Booting from USB drives is now noticeably faster. Currently SeaBIOS supports USB keyboards, USB hubs, and USB drives. Help with testing on a wider range of hardware would be appreciated. -Kevin

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Un-brick a GAM57SLIS4
by tho.wie＠gmx.de 11 Mar '10

11 Mar '10

Hello, [if this is off-topic here, please feel free to ignore/delete this message] I accidently flashed my Gigabyte GA-M57-SLI-S4 Rev. 1 with a corrupted BIOS file. The board does not boot anymore, just a black screen, no beeps, simply dead. I would be glad if I could save the money for a new board so I've got the following question: If I do the hardware-mod as shown in <http://private.vlsi.informatik.tu-darmstadt.de/st/> and can obtain a programmed flash rom with a valid BIOS inside, would it be possible to "reanimate" the board again? Would it be neccessary to remove the original Flash-BIOS or can leave it (permanently switched off) on the board? Thanks Thorsten -- GRATIS für alle GMX-Mitglieder: Die maxdome Movie-FLAT! Jetzt freischalten unter http://portal.gmx.net/de/go/maxdome01

2 1

[PATCH] sb600: don't load verb for codec
by Bao, Zheng 11 Mar '10

11 Mar '10

Don't load verb in BIOS stage. It is not BIOS's responsibility. And we can not have verb for every single codec. Signed-off-by: Zheng Bao <zheng.bao(a)amd.com> Index: src/southbridge/amd/sb600/sb600_hda.c =================================================================== --- src/southbridge/amd/sb600/sb600_hda.c (revision 5184) +++ src/southbridge/amd/sb600/sb600_hda.c (working copy) @@ -90,88 +90,10 @@ return 0; } -static u32 cim_verb_data[] = { - 0x01471c10, - 0x01471d40, - 0x01471e01, - 0x01471f01, -/* 1 */ - 0x01571c12, - 0x01571d10, - 0x01571e01, - 0x01571f01, -/* 2 */ - 0x01671c11, - 0x01671d60, - 0x01671e01, - 0x01671f01, -/* 3 */ - 0x01771c14, - 0x01771d20, - 0x01771e01, - 0x01771f01, -/* 4 */ - 0x01871c30, - 0x01871d90, - 0x01871ea1, - 0x01871f01, -/* 5 */ - 0x01971cf0, - 0x01971d11, - 0x01971e11, - 0x01971f41, -/* 6 */ - 0x01a71c80, - 0x01a71d30, - 0x01a71e81, - 0x01a71f01, -/* 7 */ - 0x01b71cf0, - 0x01b71d11, - 0x01b71e11, - 0x01b71f41, -/* 8 */ - 0x01c71cf0, - 0x01c71d11, - 0x01c71e11, - 0x01c71f41, -/* 9 */ - 0x01d71cf0, - 0x01d71d11, - 0x01d71e11, - 0x01d71f41, -/* 10 */ - 0x01e71c50, - 0x01e71d11, - 0x01e71e44, - 0x01e71f01, -/* 11 */ - 0x01f71c60, - 0x01f71d61, - 0x01f71ec4, - 0x01f71f01, -}; -static u32 find_verb(u32 viddid, u32 ** verb) -{ - device_t azalia_dev = dev_find_slot(0, PCI_DEVFN(0x14, 2)); - struct southbridge_amd_sb600_config *cfg = - (struct southbridge_amd_sb600_config *)azalia_dev->chip_info; - printk_debug("Dev=%s\n", dev_path(azalia_dev)); - printk_debug("Default viddid=%x\n", cfg->hda_viddid); - printk_debug("Reading viddid=%x\n", viddid); - if (!cfg) - return 0; - if (viddid != cfg->hda_viddid) - return 0; - *verb = (u32 *) cim_verb_data; - return sizeof(cim_verb_data) / sizeof(u32); -} - /** * Wait 50usec for for the codec to indicate it is ready * no response would imply that the codec is non-operative */ - static int wait_for_ready(u8 *base) { /* Use a 50 usec timeout - the Linux kernel uses the @@ -194,7 +116,6 @@ * the previous command. No response would imply that the code * is non-operative */ - static int wait_for_valid(u8 *base) { /* Use a 50 usec timeout - the Linux kernel uses the @@ -215,9 +136,6 @@ static void codec_init(u8 * base, int addr) { u32 dword; - u32 *verb; - u32 verb_size; - int i; /* 1 */ if (wait_for_ready(base) == -1) @@ -232,26 +150,7 @@ dword = read32(base + 0x64); /* 2 */ - printk_debug("codec viddid: %08x\n", dword); - verb_size = find_verb(dword, &verb); - - if (!verb_size) { - printk_debug("No verb!\n"); - return; - } - - printk_debug("verb_size: %d\n", verb_size); - /* 3 */ - for (i = 0; i < verb_size; i++) { - if (wait_for_ready(base) == -1) - return; - - write32(base + 0x60, verb[i]); - - if (wait_for_valid(base) == -1) - return; - } - printk_debug("verb loaded!\n"); + printk_debug("%x(th) codec viddid: %08x\n", addr, dword); } static void codecs_init(u8 * base, u32 codec_mask)

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coreboot March 2010