coreboot December 2010

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build service results for r6218
by repository service 27 Dec '10

27 Dec '10

Dear coreboot readers! This is the automatic build system of coreboot. The developer "stepan" checked in revision 6218 to the coreboot repository. This caused the following changes: Change Log: proper printk handling in src/northbridge/intel/i82810/raminit.c and drop some romcc relics in 440bx code too Signed-off-by: Stefan Reinauer <stepan(a)coreboot.org> Acked-by: Stefan Reinauer <stepan(a)coreboot.org> Build Log: Compilation of asus:mew-am is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6218&device=mew-am&vendor=… Compilation of asus:mew-vm is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6218&device=mew-vm&vendor=… Compilation of ecs:p6iwp-fe is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6218&device=p6iwp-fe&vendo… Compilation of hp:e_vectra_p2706t is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6218&device=e_vectra_p2706… Compilation of intel:d810e2cb is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6218&device=d810e2cb&vendo… Compilation of mitac:6513wu is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6218&device=6513wu&vendor=… Compilation of msi:ms6178 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6218&device=ms6178&vendor=… Compilation of nec:powermate2000 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6218&device=powermate2000&… If something broke during this checkin please be a pain in stepan's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

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[commit] r6218 - in trunk/src/northbridge/intel: i440bx i82810
by repository service 27 Dec '10

27 Dec '10

Author: stepan Date: Mon Dec 27 15:31:05 2010 New Revision: 6218 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6218 Log: proper printk handling in src/northbridge/intel/i82810/raminit.c and drop some romcc relics in 440bx code too Signed-off-by: Stefan Reinauer <stepan(a)coreboot.org> Acked-by: Stefan Reinauer <stepan(a)coreboot.org> Modified: trunk/src/northbridge/intel/i440bx/raminit.c trunk/src/northbridge/intel/i82810/raminit.c Modified: trunk/src/northbridge/intel/i440bx/raminit.c ============================================================================== --- trunk/src/northbridge/intel/i440bx/raminit.c Mon Dec 27 14:30:39 2010 (r6217) +++ trunk/src/northbridge/intel/i440bx/raminit.c Mon Dec 27 15:31:05 2010 (r6218) @@ -39,15 +39,9 @@ /* Debugging macros. */ #if CONFIG_DEBUG_RAM_SETUP #define PRINT_DEBUG(x...) printk(BIOS_DEBUG, x) -#define PRINT_DEBUG_HEX8(x) printk(BIOS_DEBUG, "%02x", x) -#define PRINT_DEBUG_HEX16(x) printk(BIOS_DEBUG, "%04x", x) -#define PRINT_DEBUG_HEX32(x) printk(BIOS_DEBUG, "%08x", x) #define DUMPNORTH() dump_pci_device(NB) #else #define PRINT_DEBUG(x...) -#define PRINT_DEBUG_HEX8(x) -#define PRINT_DEBUG_HEX16(x) -#define PRINT_DEBUG_HEX32(x) #define DUMPNORTH() #endif @@ -434,11 +428,8 @@ addr = (dimm_start * 8 * 1024 * 1024) + addr_offset; if (dimm_end > dimm_start) { #if 0 - PRINT_DEBUG(" Sending RAM command 0x"); - PRINT_DEBUG_HEX16(reg16); - PRINT_DEBUG(" to 0x"); - PRINT_DEBUG_HEX32(addr); - PRINT_DEBUG("\n"); + PRINT_DEBUG(" Sending RAM command 0x%04x to 0x%08x\n", + reg16, addr); #endif read32(addr); @@ -648,11 +639,8 @@ reg |= register_values[i + 2] & ~(register_values[i + 1]); pci_write_config8(NB, register_values[i], reg); #if 0 - PRINT_DEBUG(" Set register 0x"); - PRINT_DEBUG_HEX8(register_values[i]); - PRINT_DEBUG(" to 0x"); - PRINT_DEBUG_HEX8(reg); - PRINT_DEBUG("\n"); + PRINT_DEBUG(" Set register 0x%02x to 0x%02x\n", + register_values[i], reg); #endif } } @@ -885,9 +873,7 @@ drb |= (drb + (sz.side2 / 8)) << 8; } else { #if 0 - PRINT_DEBUG("No DIMM found in slot "); - PRINT_DEBUG_HEX8(i); - PRINT_DEBUG("\n"); + PRINT_DEBUG("No DIMM found in slot %d\n", i); #endif /* If there's no DIMM in the slot, set dra to 0x00. */ @@ -900,9 +886,7 @@ pci_write_config16(NB, DRB + (2 * i), drb); #if 0 - PRINT_DEBUG("DRB has been set to 0x"); - PRINT_DEBUG_HEX16(drb); - PRINT_DEBUG("\n"); + PRINT_DEBUG("DRB has been set to 0x%04x\n", drb); #endif /* Brings the upper DRB back down to be base for Modified: trunk/src/northbridge/intel/i82810/raminit.c ============================================================================== --- trunk/src/northbridge/intel/i82810/raminit.c Mon Dec 27 14:30:39 2010 (r6217) +++ trunk/src/northbridge/intel/i82810/raminit.c Mon Dec 27 15:31:05 2010 (r6218) @@ -37,15 +37,9 @@ /* Debugging macros. */ #if CONFIG_DEBUG_RAM_SETUP #define PRINT_DEBUG(x...) printk(BIOS_DEBUG, x) -#define PRINT_DEBUG_HEX8(x) printk(BIOS_DEBUG, "%02x", x) -#define PRINT_DEBUG_HEX16(x) printk(BIOS_DEBUG, "%04x", x) -#define PRINT_DEBUG_HEX32(x) printk(BIOS_DEBUG, "%08x", x) #define DUMPNORTH() dump_pci_device(PCI_DEV(0, 0, 0)) #else -#define PRINT_DEBUG(x) -#define PRINT_DEBUG_HEX8(x) -#define PRINT_DEBUG_HEX16(x) -#define PRINT_DEBUG_HEX32(x) +#define PRINT_DEBUG(x...) #define DUMPNORTH() #endif

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build service results for r6217
by repository service 27 Dec '10

27 Dec '10

Dear coreboot readers! This is the automatic build system of coreboot. The developer "stepan" checked in revision 6217 to the coreboot repository. This caused the following changes: Change Log: __PRE_RAM__ is defined by the makefile Signed-off-by: Stefan Reinauer <stepan(a)coreboot.org> Acked-by: Stefan Reinauer <stepan(a)coreboot.org> Build Log: Compilation of asus:mew-am is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6217&device=mew-am&vendor=… Compilation of asus:mew-vm is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6217&device=mew-vm&vendor=… Compilation of ecs:p6iwp-fe is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6217&device=p6iwp-fe&vendo… Compilation of hp:e_vectra_p2706t is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6217&device=e_vectra_p2706… Compilation of intel:d810e2cb is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6217&device=d810e2cb&vendo… Compilation of mitac:6513wu is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6217&device=6513wu&vendor=… Compilation of msi:ms6178 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6217&device=ms6178&vendor=… Compilation of nec:powermate2000 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6217&device=powermate2000&… If something broke during this checkin please be a pain in stepan's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

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[PATCH 4/6 V2] Geode GX2 cleanup patch
by Nils 27 Dec '10

27 Dec '10

Remove duplicated GX2 processor IIOC mode setting on CS5535 southbridge code and fix CIS mode comments. Signed-off-by: Nils Jacobs <njacobs8(a)hetnet.nl> V2: Add a extra comment. Thanks, Nils.

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Re: [coreboot] [PATCH 4/6] Geode GX2 cleanup patch
by Nils 27 Dec '10

27 Dec '10

Hi Peter. Thanks for the thorough review! As this patches are part from a half year old patch of mine and i did not remember everything in detail i spend a few hours to study these confusing registers again. Peter wrote: >> Remove wrong GX2 processor IIOC mode setting on CS5535 southbridge >> code and fix CIS mode comments. > >Hm, please talk a little about this? > >> +++ src/southbridge/amd/cs5535/early_setup.c (working copy) >> @@ -107,15 +107,11 @@ >.. >> - //Only do this if we are building for 5535 >> - msr.lo = 0x2; >> - msr.hi = 0x0; >> - wrmsr(VIP_GIO_MSR_SEL, msr); > >This code is not added to another place by this patch. Is it simply >completely bogus, but harmless, for 5535? And harmful for GX2? Please >explain a little? I removed this code because it is duplicating code. This register is set in cpureginit and does not have to be set here. This duplication is already removed from the newer CS5536 code in rev2631. > >> +++ src/include/cpu/amd/gx2def.h (working copy) >.. >> +#define FG_GIO_MSR_SEL (MSR_FG + 0x2010) >.. > >> -#define VIP_GIO_MSR_SEL (MSR_VIP + 0x2010) > >(Why remove this?) This is part of a change that i made because i think it is confusing that GLIU1 port 5 has two names in gx2def.h .(VIP and FooGlue FG) The GX2 does not have a VIP Video Input Port. The gx2def.h is clobbered with LX registernames from before it was splitup in a seperate LX tree.(see also AES registers witch the GX2 does not have) The rest of the conversion to one name for the other GLIU1 port 5 registers are in a follow up patch that i didn't send yet. (This splitting up work is a major pain in the ....) > >> +++ src/cpu/amd/model_gx2/cpureginit.c (working copy) >.. >> - msrnum = MSR_FG + 0x10; >.. >> + msrnum = FG_GIO_MSR_SEL; > >This is not the same MSR. Please explain? That is good observed. :) Register MSR_FG + 0x10 (54000010) does not exist according to the datasheet. Register address 54000010 and 54002010 are mapped to the same physical register. So i think it is less confusing to use the documented register address. On top of this confusion the register values in the databook are wrong. This is stated in a OFW comment. I will send an updated patch with this extra comment for future readers. >FG_GIO_MSR_SEL is defined >to MSR_FG + 0x2010 above, so this particular change changes which MSR >is being accessed. Is on purpose? Yes.(see above) Thanks, Nils.

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build service results for r6216
by repository service 27 Dec '10

27 Dec '10

Dear coreboot readers! This is the automatic build system of coreboot. The developer "stepan" checked in revision 6216 to the coreboot repository. This caused the following changes: Change Log: dump_spd_registers() is only defined when ram init debugging is on. Most boards unconditionally call this. Fix it in header file instead of each single romstage.c Signed-off-by: Stefan Reinauer <stepan(a)coreboot.org> Acked-by: Stefan Reinauer <stepan(a)coreboot.org> Build Log: Compilation of a-trend:atc-6220 has been fixed Compilation of a-trend:atc-6240 has been fixed Compilation of abit:be6-ii_v2_0 has been fixed Compilation of asus:mew-am is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6216&device=mew-am&vendor=… Compilation of asus:mew-vm is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6216&device=mew-vm&vendor=… Compilation of asus:p2b has been fixed Compilation of asus:p2b-d has been fixed Compilation of asus:p2b-ds has been fixed Compilation of asus:p2b-f has been fixed Compilation of asus:p2b-ls has been fixed Compilation of asus:p3b-f has been fixed Compilation of azza:pt-6ibd has been fixed Compilation of biostar:m6tba has been fixed Compilation of compaq:deskpro_en_sff_p600 has been fixed Compilation of ecs:p6iwp-fe is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6216&device=p6iwp-fe&vendo… Compilation of gigabyte:ga-6bxc has been fixed Compilation of gigabyte:ga-6bxe has been fixed Compilation of hp:e_vectra_p2706t is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6216&device=e_vectra_p2706… Compilation of intel:d810e2cb is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6216&device=d810e2cb&vendo… Compilation of mitac:6513wu is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6216&device=6513wu&vendor=… Compilation of msi:ms6119 has been fixed Compilation of msi:ms6147 has been fixed Compilation of msi:ms6156 has been fixed Compilation of msi:ms6178 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6216&device=ms6178&vendor=… Compilation of nec:powermate2000 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6216&device=powermate2000&… Compilation of nokia:ip530 has been fixed Compilation of soyo:sy-6ba-plus-iii has been fixed Compilation of tyan:s1846 has been fixed If something broke during this checkin please be a pain in stepan's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

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[commit] r6217 - trunk/src/northbridge/via/vx800/examples
by repository service 27 Dec '10

27 Dec '10

Author: stepan Date: Mon Dec 27 14:30:39 2010 New Revision: 6217 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6217 Log: __PRE_RAM__ is defined by the makefile Signed-off-by: Stefan Reinauer <stepan(a)coreboot.org> Acked-by: Stefan Reinauer <stepan(a)coreboot.org> Modified: trunk/src/northbridge/via/vx800/examples/romstage.c Modified: trunk/src/northbridge/via/vx800/examples/romstage.c ============================================================================== --- trunk/src/northbridge/via/vx800/examples/romstage.c Mon Dec 27 14:29:38 2010 (r6216) +++ trunk/src/northbridge/via/vx800/examples/romstage.c Mon Dec 27 14:30:39 2010 (r6217) @@ -18,8 +18,6 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#define ASSEMBLY 1 -#define __PRE_RAM__ #include <stdint.h> #include <device/pci_def.h>

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[commit] r6216 - trunk/src/northbridge/intel/i440bx
by repository service 27 Dec '10

27 Dec '10

Author: stepan Date: Mon Dec 27 14:29:38 2010 New Revision: 6216 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6216 Log: dump_spd_registers() is only defined when ram init debugging is on. Most boards unconditionally call this. Fix it in header file instead of each single romstage.c Signed-off-by: Stefan Reinauer <stepan(a)coreboot.org> Acked-by: Stefan Reinauer <stepan(a)coreboot.org> Modified: trunk/src/northbridge/intel/i440bx/raminit.h Modified: trunk/src/northbridge/intel/i440bx/raminit.h ============================================================================== --- trunk/src/northbridge/intel/i440bx/raminit.h Mon Dec 27 12:34:57 2010 (r6215) +++ trunk/src/northbridge/intel/i440bx/raminit.h Mon Dec 27 14:29:38 2010 (r6216) @@ -29,8 +29,11 @@ void sdram_set_registers(void); void sdram_set_spd_registers(void); void sdram_enable(void); - /* Debug */ +#if CONFIG_DEBUG_RAM_SETUP void dump_spd_registers(void); void dump_pci_device(unsigned dev); +#else +#define dump_spd_registers() +#endif #endif /* RAMINIT_H */

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[PATCH 3/6 V2] Geode GX2 cleanup patch
by Nils 27 Dec '10

27 Dec '10

Use die() to assure the processor can't wake up from an interrupt. Signed-off-by: Nils Jacobs <njacobs8(a)hetnet.nl> This was suggested by Peter and Stefan. Thanks! I also included the same patch for Geode LX and added a second die() to Geode GX2 at the same place as in the LX code. I boot tested it on my Wyse S50 and it seems to work. Thanks, Nils.

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Re: [coreboot] [PATCH 3/6] Geode GX2 cleanup patch
by Nils 27 Dec '10

27 Dec '10

Stefan wrote: >On 26.12.2010, at 06:19, Peter Stuge <peter at stuge.se> wrote: > >> Nils wrote: >>> - __asm__ __volatile__("hlt\n"); >>> + while(1) { >>> + __asm__ __volatile__("hlt\n"); >>> + } >> >> Why not call die() instead? Is it too early for that? >> >> > >Die() is now extra. It should work early. Thanks for the hint. I will send a new patch. Nils.

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coreboot December 2010