coreboot December 2010

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[commit] r6210 - in trunk/src: cpu/amd/model_gx2 northbridge/amd/gx2
by repository service 26 Dec '10

26 Dec '10

Author: stuge Date: Sun Dec 26 06:21:18 2010 New Revision: 6210 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6210 Log: Remove dead and unused Geode GX2 code Signed-off-by: Nils Jacobs <njacobs8(a)hetnet.nl> Acked-by: Patrick Georgi <patrick(a)georgi-clan.de> Acked-by: Peter Stuge <peter(a)stuge.se> Modified: trunk/src/cpu/amd/model_gx2/cpureginit.c trunk/src/northbridge/amd/gx2/northbridge.c trunk/src/northbridge/amd/gx2/northbridgeinit.c Modified: trunk/src/cpu/amd/model_gx2/cpureginit.c ============================================================================== --- trunk/src/cpu/amd/model_gx2/cpureginit.c Sun Dec 26 06:16:47 2010 (r6209) +++ trunk/src/cpu/amd/model_gx2/cpureginit.c Sun Dec 26 06:21:18 2010 (r6210) @@ -4,8 +4,6 @@ { int msrnum; msr_t msr; - /* Turn on BTM for early debug based on setup. */ - // if (getnvram( TOKEN_BTM_DIAG_MODE) & 3) { /* The following is only for diagnostics mode; do not use for OLPC */ if (0) { /* Set Diagnostic Mode */ @@ -125,37 +123,10 @@ } /* FPU impercise exceptions bit */ - //if (getnvram( TOKEN_FPU_IE_ENABLE) != TVALUE_DISABLE) { { msrnum = CPU_FPU_MSR_MODE; msr = rdmsr(msrnum); msr.lo |= FPU_IE_SET; wrmsr(msrnum, msr); } - -#if 0 - /* Cache Overides */ - /* This code disables the data cache. Don't execute this - * unless you're testing something. - */ - /* Allow NVRam to override DM Setup */ - //if (getnvram( TOKEN_CACHE_DM_MODE) != 1) { - { - msrnum = CPU_DM_CONFIG0; - msr = rdmsr(msrnum); - msr.lo |= DM_CONFIG0_LOWER_DCDIS_SET; - wrmsr(msrnum, msr); - } - /* This code disables the instruction cache. Don't execute - * this unless you're testing something. - */ - /* Allow NVRam to override IM Setup */ - //if (getnvram( TOKEN_CACHE_IM_MODE) ==1) { - { - msrnum = CPU_IM_CONFIG; - msr = rdmsr(msrnum); - msr.lo |= IM_CONFIG_LOWER_ICD_SET; - wrmsr(msrnum, msr); - } -#endif } Modified: trunk/src/northbridge/amd/gx2/northbridge.c ============================================================================== --- trunk/src/northbridge/amd/gx2/northbridge.c Sun Dec 26 06:16:47 2010 (r6209) +++ trunk/src/northbridge/amd/gx2/northbridge.c Sun Dec 26 06:21:18 2010 (r6210) @@ -66,23 +66,9 @@ #define RAM_PROPERTIES (0) #define DEVICE_PROPERTIES (WRITE_SERIALIZE|CACHE_DISABLE) #define ROM_PROPERTIES (WRITE_SERIALIZE|WRITE_PROTECT|CACHE_DISABLE) -#define MSR_WS_CD_DEFAULT (0x21212121) - -/* 1810-1817 give you 8 registers with which to program protection regions */ -/* the are region configuration range registers, or RRCF */ -/* in msr terms, the are a straight base, top address assign, since they are 4k aligned. */ -/* so no left-shift needed for top or base */ -#define RRCF_LOW(base,properties) (base|(1<<8)|properties) -#define RRCF_LOW_CD(base) RRCF_LOW(base, CACHE_DISABLE) - /* build initializer for P2D MSR */ #define P2D_BM(msr, pdid1, bizarro, pbase, pmask) {msr, {.hi=(pdid1<<29)|(bizarro<<28)|(pbase>>24), .lo=(pbase<<8)|pmask}} -#define P2D_BMO(msr, pdid1, bizarro, poffset, pbase, pmask) {msr, {.hi=(pdid1<<29)|(bizarro<<28)|(poffset<<8)|(pbase>>24), .lo=(pbase<<8)|pmask}} -#define P2D_R(msr, pdid1, bizarro, pmax, pmin) {msr, {.hi=(pdid1<<29)|(bizarro<<28)|(pmax>>12), .lo=(pmax<<20)|pmin}} -#define P2D_RO(msr, pdid1, bizarro, poffset, pmax, pmin) {msr, {.hi=(pdid1<<29)|(bizarro<<28)|(poffset<<8)|(pmax>>12), .lo=(pmax<<20)|pmin}} #define P2D_SC(msr, pdid1, bizarro, wen, ren,pscbase) {msr, {.hi=(pdid1<<29)|(bizarro<<28)|(wen), .lo=(ren<<16)|(pscbase>>18)}} -#define IOD_BM(msr, pdid1, bizarro, ibase, imask) {msr, {.hi=(pdid1<<29)|(bizarro<<28)|(ibase>>12), .lo=(ibase<<20)|imask}} -#define IOD_SC(msr, pdid1, bizarro, en, wen, ren, ibase) {msr, {.hi=(pdid1<<29)|(bizarro<<28), .lo=(en<<24)|(wen<<21)|(ren<<20)|(ibase<<3)}} struct msr_defaults { @@ -91,20 +77,6 @@ } msr_defaults [] = { {0x1700, {.hi = 0, .lo = IM_QWAIT}}, {0x1800, {.hi = DMCF_WRITE_SERIALIZE_REQUEST, .lo = DMCF_SERIAL_LOAD_MISSES}}, - /* 1808 will be done down below, so we have to do 180a->1817 (well, 1813 really) */ - /* for 180a, for now, we assume VSM will configure it */ - /* 180b is left at reset value,a0000-bffff is non-cacheable */ - /* 180c, c0000-dffff is set to write serialize and non-cachable */ - /* oops, 180c will be set by cpu bug handling in cpubug.c */ - //{0x180c, {.hi = MSR_WS_CD_DEFAULT, .lo = MSR_WS_CD_DEFAULT}}, - /* 180d is left at default, e0000-fffff is non-cached */ - - /* we will assume 180e, the ssm region configuration, is left at default or set by VSM */ - /* we will not set 0x180f, the DMM,yet */ - //{0x1810, {.hi=0xee7ff000, .lo=RRCF_LOW(0xee000000, WRITE_COMBINE|CACHE_DISABLE)}}, - //{0x1811, {.hi = 0xefffb000, .lo = RRCF_LOW_CD(0xefff8000)}}, - //{0x1812, {.hi = 0xefff7000, .lo = RRCF_LOW_CD(0xefff4000)}}, - //{0x1813, {.hi = 0xefff3000, .lo = RRCF_LOW_CD(0xefff0000)}}, /* now for GLPCI routing */ /* GLIU0 */ P2D_BM(0x10000020, 0x1, 0x0, 0x0, 0xfff80), @@ -196,29 +168,6 @@ * sizeram() directly. */ - /* we need to set 0x10000028 and 0x40000029 */ - - /* These two descriptors cover the range from 1 MB (0x100000) to - * SYSTOP (a.k.a. TOM, or Top of Memory) - */ - -#if 0 - /* This has already been done elsewhere */ - printk(BIOS_DEBUG, "size_kb 0x%x, membytes 0x%x\n", size_kb, membytes); - msr.hi = 0x20000000 | membytes>>24; - msr.lo = 0x100 | ( ((membytes >>12) & 0xfff) << 20); - wrmsr(0x10000028, msr); - msr.hi = 0x20000000 | membytes>>24; - msr.lo = 0x100 | ( ((membytes >>12) & 0xfff) << 20); - wrmsr(0x40000029, msr); -#endif -#if 0 - msr = rdmsr(0x10000028); - printk(BIOS_DEBUG, "MSR 0x%x is now 0x%x:0x%x\n", 0x10000028, msr.hi,msr.lo); - msr = rdmsr(0x40000029); - printk(BIOS_DEBUG, "MSR 0x%x is now 0x%x:0x%x\n", 0x40000029, msr.hi,msr.lo); -#endif -#if 1 /* fixme: SMM MSR 0x10000026 and 0x400000023 */ /* calculate the OFFSET field */ tmp = membytes - SMM_OFFSET; @@ -234,31 +183,6 @@ msr.hi = tmp; msr.lo = tmp2; wrmsr(0x10000026, msr); -#endif -#if 0 - - msr.hi = 0x2cfbc040; - msr.lo = 0x400fffc0; - wrmsr(0x10000026, msr); - msr = rdmsr(0x10000026); - printk(BIOS_DEBUG, "MSR 0x%x is now 0x%x:0x%x\n", 0x10000026, msr.hi, msr.lo); -#endif -#if 0 - msr.hi = 0x22fffc02; - msr.lo = 0x10ffbf00; - wrmsr(0x1808, msr); - msr = rdmsr(0x1808); - printk(BIOS_DEBUG, "MSR 0x%x is now 0x%x:0x%x\n", 0x1808, msr.hi, msr.lo); -#endif -#if 0 /* SDG - don't do this */ - /* now do the default MSR values */ - for(i = 0; msr_defaults[i].msr_no; i++) { - msr_t msr; - wrmsr(msr_defaults[i].msr_no, msr_defaults[i].msr); /* MSR - see table above */ - msr = rdmsr(msr_defaults[i].msr_no); - printk(BIOS_DEBUG, "MSR 0x%08X is now 0x%08X:0x%08X\n", msr_defaults[i].msr_no, msr.hi,msr.lo); - } -#endif } static void enable_shadow(device_t dev) @@ -268,33 +192,17 @@ static void northbridge_init(device_t dev) { - unsigned long m; - struct northbridge_amd_gx2_config *nb = (struct northbridge_amd_gx2_config *)dev->chip_info; printk(BIOS_DEBUG, "northbridge: %s()\n", __func__); enable_shadow(dev); irq_init_steering(dev, nb->irqmap); - - /* HACK HACK HACK HACK */ - /* 0x1000 is where GPIO is being assigned */ - m = inl(0x1038); - m &= ~GPIOL_12_SET; - m |= GPIOL_12_CLEAR; - outl(m, 0x1038); } /* due to vsa interactions, we need not not touch the nb settings ... */ /* this is a test -- we are not sure it will work -- but it ought to */ static void set_resources(struct device *dev) { -#if 0 - struct resource *res; - - for(res = &dev->resource_list; res; res = res->next) { - pci_set_resource(dev, resource); - } -#endif struct bus *bus; for(bus = dev->link_list; bus; bus = bus->next) { @@ -324,9 +232,6 @@ static struct device_operations northbridge_operations = { .read_resources = pci_dev_read_resources, -#if 0 - .set_resources = pci_dev_set_resources, -#endif .set_resources = set_resources, .enable_resources = pci_dev_enable_resources, .init = northbridge_init, @@ -345,52 +250,6 @@ static void pci_domain_set_resources(device_t dev) { -#if 0 - device_t mc_dev; - u32 pci_tolm; - - pci_tolm = find_pci_tolm(dev->link_list); - mc_dev = dev->link_list->children; - if (mc_dev) { - unsigned int tomk, tolmk; - unsigned int ramreg = 0; - int i, idx; - unsigned int *bcdramtop = (unsigned int *)(GX_BASE + BC_DRAM_TOP); - unsigned int *mcgbaseadd = (unsigned int *)(GX_BASE + MC_GBASE_ADD); - - for(i=0; i<0x20; i+= 0x10) { - unsigned int *mcreg = (unsigned int *)(GX_BASE + MC_BANK_CFG); - unsigned int mem_config = *mcreg; - - if (((mem_config & (DIMM_PG_SZ << i)) >> (4 + i)) == 7) - continue; - ramreg += 1 << (((mem_config & (DIMM_SZ << i)) >> (i + 8)) + 2); - } - - tomk = ramreg << 10; - - /* Sort out the framebuffer size */ - tomk -= FRAMEBUFFERK; - *bcdramtop = ((tomk << 10) - 1); - *mcgbaseadd = (tomk >> 9); - - printk(BIOS_DEBUG, "BC_DRAM_TOP = 0x%08x\n", *bcdramtop); - printk(BIOS_DEBUG, "MC_GBASE_ADD = 0x%08x\n", *mcgbaseadd); - - printk(BIOS_DEBUG, "I would set ram size to %d Mbytes\n", (tomk >> 10)); - - /* Compute the top of Low memory */ - tolmk = pci_tolm >> 10; - if (tolmk >= tomk) { - /* The PCI hole does does not overlap the memory. - */ - tolmk = tomk; - } - /* Report the memory regions */ - idx = 10; - ram_resource(dev, idx++, 0, tolmk); - } -#endif assign_resources(dev->link_list); } Modified: trunk/src/northbridge/amd/gx2/northbridgeinit.c ============================================================================== --- trunk/src/northbridge/amd/gx2/northbridgeinit.c Sun Dec 26 06:16:47 2010 (r6209) +++ trunk/src/northbridge/amd/gx2/northbridgeinit.c Sun Dec 26 06:21:18 2010 (r6210) @@ -708,10 +708,6 @@ shadowRom(); - /* GeodeROM ensures that the BIOS waits the required 1 second before */ - /* allowing anything to access PCI */ - // PCIDelay(); - RCONFInit(); /* The cacheInit function in GeodeROM tests cache and, among other things,

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[PATCH 2/6] Geode GX2 cleanup patch
by Nils 26 Dec '10

26 Dec '10

Replace some MSR register numbers with names. Signed-off-by: Nils Jacobs <njacobs8(a)hetnet.nl> Thanks, Nils.

2 1

[commit] r6209 - in trunk/src: cpu/amd/model_gx2 include/cpu/amd northbridge/amd/gx2
by repository service 26 Dec '10

26 Dec '10

Author: stuge Date: Sun Dec 26 06:16:47 2010 New Revision: 6209 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6209 Log: Replace Geode GX2 MSR addresses for GLCP on GLIU1 with names Signed-off-by: Nils Jacobs <njacobs8(a)hetnet.nl> Acked-by: Patrick Georgi <patrick(a)georgi-clan.de> Acked-by: Peter Stuge <peter(a)stuge.se> Modified: trunk/src/cpu/amd/model_gx2/cpureginit.c trunk/src/include/cpu/amd/gx2def.h trunk/src/northbridge/amd/gx2/northbridge.c Modified: trunk/src/cpu/amd/model_gx2/cpureginit.c ============================================================================== --- trunk/src/cpu/amd/model_gx2/cpureginit.c Sun Dec 26 06:12:49 2010 (r6208) +++ trunk/src/cpu/amd/model_gx2/cpureginit.c Sun Dec 26 06:16:47 2010 (r6209) @@ -15,25 +15,25 @@ wrmsr(msrnum, msr); /* Set up GLCP to grab BTM data. */ - msrnum = 0x04C00000C; /* GLCP_DBGOUT MSR */ + msrnum = GLCP_DBGOUT; /* GLCP_DBGOUT MSR */ msr.hi = 0x0; msr.lo = 0x08; /* reset value (SCOPE_SEL = 0) causes FIFO toshift out, */ wrmsr(msrnum, msr); /* exchange it to anything else to prevent this */ /* Turn off debug clock */ - msrnum = 0x04C000016; /* DBG_CLK_CTL */ + msrnum = GLCP_DBGCLKCTL; /* DBG_CLK_CTL */ msr.lo = 0x00; /* No clock */ msr.hi = 0x00; wrmsr(msrnum, msr); /* Set debug clock to CPU */ - msrnum = 0x04C000016; /* DBG_CLK_CTL */ + msrnum = GLCP_DBGCLKCTL; /* DBG_CLK_CTL */ msr.lo = 0x01; /* CPU CLOCK */ msr.hi = 0x00; wrmsr(msrnum, msr); /* Set fifo ctl to BTM bits wide */ - msrnum = 0x04C00005E; /* FIFO_CTL */ + msrnum = GLCP_FIFOCTL; /* FIFO_CTL */ msr.lo = 0x003880000; /* Bit [25:24] are size (11=BTM, 10 = 64 bit, 01= 32 bit, 00 = 16bit) */ wrmsr(msrnum, msr); /* Bit [23:21] are position (100 = CPU downto0) */ /* Bit [19] sets it up in slow data mode. */ @@ -53,7 +53,7 @@ /* Set up delay on data lines, so that the hold time */ /* is 1 ns. */ - msrnum = 0x04C00000D ; /* GLCP IO DELAY CONTROLS */ + msrnum = GLCP_PROCSTAT; /* GLCP IO DELAY CONTROLS */ msr.lo = 0x082b5ad68; msr.hi = 0x080ad6b57; /* RGB delay = 0x07 */ wrmsr(msrnum, msr); @@ -64,7 +64,7 @@ msr.hi = 0; wrmsr(msrnum, msr); - msrnum = 0x04C00000C ; /* GLCP_DBGOUT MSR */ + msrnum = GLCP_DBGOUT; /* GLCP_DBGOUT MSR */ msr.hi = 0x0; msr.lo = 0x0; /* reset value (SCOPE_SEL = 0) causes FIFO to shift out, */ wrmsr(msrnum, msr); @@ -85,7 +85,7 @@ wrmsr(msrnum, msr); /* Setup throttling to proper mode if it is ever enabled. */ - msrnum = 0x04C00001E; + msrnum = GLCP_TH_OD; msr.hi = 0x000000000; msr.lo = 0x00000603C; wrmsr(msrnum, msr); @@ -108,14 +108,14 @@ wrmsr(msrnum, msr); /* Enable RSDC */ - msrnum = 0x1301 ; + msrnum = CPU_AC_SMM_CTL; msr = rdmsr(msrnum); msr.lo |= 0x08; wrmsr(msrnum, msr); /* Enable BTB */ /* I hate to put this check here but it doesn't really work in cpubug.asm */ - msrnum = MSR_GLCP+0x17; + msrnum = GLCP_CHIP_REVID; msr = rdmsr(msrnum); if (msr.lo >= CPU_REV_2_1){ msrnum = CPU_PF_BTB_CONF; Modified: trunk/src/include/cpu/amd/gx2def.h ============================================================================== --- trunk/src/include/cpu/amd/gx2def.h Sun Dec 26 06:12:49 2010 (r6208) +++ trunk/src/include/cpu/amd/gx2def.h Sun Dec 26 06:16:47 2010 (r6209) @@ -15,10 +15,15 @@ #define CPU_REV_2_2 0x022 #define CPU_REV_3_0 0x030 -/* GeodeLink Control Processor Registers, GLIU1, Port 3 */ -#define GLCP_CLK_DIS_DELAY 0x4c000008 -#define GLCP_PMCLKDISABLE 0x4c000009 -#define GLCP_CHIP_REVID 0x4c000017 +/* GeodeLink Control Processor Registers, GLIU1, Port 3 ; MSR_GLCP = 4c00xxxx */ +#define GLCP_CLK_DIS_DELAY (MSR_GLCP + 0x08) +#define GLCP_PMCLKDISABLE (MSR_GLCP + 0x09) +#define GLCP_DBGOUT (MSR_GLCP + 0x0C) +#define GLCP_PROCSTAT (MSR_GLCP + 0x0D) +#define GLCP_DBGCLKCTL (MSR_GLCP + 0x16) +#define GLCP_CHIP_REVID (MSR_GLCP + 0x17) +#define GLCP_TH_OD (MSR_GLCP + 0x1E) +#define GLCP_FIFOCTL (MSR_GLCP + 0x5E) /* GLCP_SYS_RSTPLL, Upper 32 bits */ #define GLCP_SYS_RSTPLL_MDIV_SHIFT 9 Modified: trunk/src/northbridge/amd/gx2/northbridge.c ============================================================================== --- trunk/src/northbridge/amd/gx2/northbridge.c Sun Dec 26 06:12:49 2010 (r6208) +++ trunk/src/northbridge/amd/gx2/northbridge.c Sun Dec 26 06:16:47 2010 (r6209) @@ -29,8 +29,8 @@ unsigned short dimm; /* Get the RAM size from the memory controller as calculated and set by auto_size_dimm() */ - msr = rdmsr(0x20000018); - printk(BIOS_DEBUG, "sizeram: %08x:%08x\n", msr.hi, msr.lo); + msr = rdmsr(MC_CF07_DATA); + printk(BIOS_DEBUG, "sizeram: _MSR MC_CF07_DATA: %08x:%08x\n", msr.hi, msr.lo); /* dimm 0 */ dimm = msr.hi;

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[PATCH 1/6] Geode GX2 cleanup patch
by Nils 26 Dec '10

26 Dec '10

-Clean up some comments. -Remove some white spaces. -Some coding style fixes. Signed-off-by: Nils Jacobs <njacobs8(a)hetnet.nl> Thanks, Nils.

2 1

[commit] r6208 - in trunk/src: cpu/amd/model_gx2 include/cpu/amd northbridge/amd/gx2
by repository service 26 Dec '10

26 Dec '10

Author: stuge Date: Sun Dec 26 06:12:49 2010 New Revision: 6208 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6208 Log: Clean up Geode GX2 comments, whitespace and coding style. Trivial. Signed-off-by: Nils Jacobs <njacobs8(a)hetnet.nl> Acked-by: Patrick Georgi <patrick(a)georgi-clan.de> Acked-by: Peter Stuge <peter(a)stuge.se> Modified: trunk/src/cpu/amd/model_gx2/cpubug.c trunk/src/cpu/amd/model_gx2/cpureginit.c trunk/src/cpu/amd/model_gx2/syspreinit.c trunk/src/include/cpu/amd/gx2def.h trunk/src/northbridge/amd/gx2/grphinit.c trunk/src/northbridge/amd/gx2/northbridge.c trunk/src/northbridge/amd/gx2/northbridgeinit.c Modified: trunk/src/cpu/amd/model_gx2/cpubug.c ============================================================================== --- trunk/src/cpu/amd/model_gx2/cpubug.c Sat Dec 25 23:54:41 2010 (r6207) +++ trunk/src/cpu/amd/model_gx2/cpubug.c Sun Dec 26 06:12:49 2010 (r6208) @@ -11,49 +11,38 @@ #include <cpu/x86/msr.h> #include <cpu/x86/cache.h> - #if 0 -void -bug645(void){ +void bug645(void) +{ msr_t msr; rdmsr(CPU_ID_CONFIG); msr.whatever |= ID_CONFIG_SERIAL_SET; wrmsr(msr); } -void -bug573(void){ +void bug573(void) +{ msr_t msr; - msr = rdmsr(MC_GLD_MSR_PM); msr.eax &= 0xfff3; wrmsr(MC_GLD_MSR_PM); } #endif -/************************************************************************** - * - * pcideadlock - * - * Bugtool #465 and #609 - * PCI cache deadlock - * There is also fix code in cache and PCI functions. This bug is very is pervasive. +/* pcideadlock * - * Entry: - * Exit: - * Modified: - * - **************************************************************************/ -static void -pcideadlock(void) + * Bugtool #465 and #609 + * PCI cache deadlock + * There is also fix code in cache and PCI functions. This bug is very is pervasive. + */ +static void pcideadlock(void) { msr_t msr; - /* - * forces serialization of all load misses. Setting this bit prevents the + /* forces serialization of all load misses. Setting this bit prevents the * DM pipe from backing up if a read request has to be held up waiting * for PCI writes to complete. - */ + */ msr = rdmsr(CPU_DM_CONFIG0); msr.hi &= ~(7<<DM_CONFIG0_UPPER_WSREQ_SHIFT); msr.hi |= (2<<DM_CONFIG0_UPPER_WSREQ_SHIFT); @@ -78,20 +67,12 @@ wrmsr( CPU_RCONF_E0_FF, msr); } -/**************************************************************************** - * - * CPUbug784 - * - * Bugtool #784 + #792 - * - * Fix CPUID instructions for < 3.0 CPUs +/* CPUbug784 * - * Entry: - * Exit: - * Modified: + * Bugtool #784 + #792 * - ****************************************************************************/ - + * Fix CPUID instructions for < 3.0 CPUs + */ static void bug784(void) { msr_t msr; @@ -120,19 +101,14 @@ } /* cpubug 1398: enable MC if we KNOW we have DDR*/ -/************************************************************************** - * - * CPUbugIAENG1398 - * - * ClearQuest #IAENG1398 - * The MC can not be enabled with SDR memory but can for DDR. Enable for - * DDR here if the setup token is "Default" - * Add this back to core by default once 2.0 CPUs are not supported. - * Entry: - * Exit: - * Modified: + +/* CPUbugIAENG1398 * - **************************************************************************/ + * ClearQuest #IAENG1398 + * The MC can not be enabled with SDR memory but can for DDR. Enable for + * DDR here if the setup token is "Default" + * Add this back to core by default once 2.0 CPUs are not supported. + */ static void eng1398(void) { msr_t msr; @@ -150,22 +126,14 @@ wrmsr(MC_GLD_MSR_PM, msr); } -/*************************************************************************** - * - * CPUbugIAENG2900 - * - * Clear Quest IAENG00002900, VSS 118.150 +/* CPUbugIAENG2900 * - * BTB issue causes blue screen in windows, but the fix is required - * for all operating systems. + * Clear Quest IAENG00002900, VSS 118.150 * - * Entry: - * Exit: - * Modified: - * - **************************************************************************/ -static void -eng2900(void) + * BTB issue causes blue screen in windows, but the fix is required + * for all operating systems. + */ +static void eng2900(void) { msr_t msr; @@ -267,38 +235,38 @@ /* Disable enable_actions in DIAGCTL while setting up GLCP */ wrmsr(MSR_GLCP + 0x005f, msr); - /* SET2M fires if VG pri is odd (3, not 2) and Ystate=0 */ + /* SET2M fires if VG pri is odd (3, not 2) and Ystate=0 */ msrnum = MSR_GLCP + 0x042; /* msr.hi = 2d6b8000h */; msr.hi = 0x596b8000; msr.lo = 0x00000a00; wrmsr(msrnum, msr); - /* SET3M fires if MBUS changed and VG pri is odd */ + /* SET3M fires if MBUS changed and VG pri is odd */ msrnum = MSR_GLCP + 0x043; msr.hi = 0x596b8040; msr.lo = 0; wrmsr(msrnum, msr); - /* Put VG request data on lower diag bus */ + /* Put VG request data on lower diag bus */ msrnum = MSR_GLIU0 + 0x2005; msr.hi = 0; msr.lo = 0x80338041; wrmsr(msrnum, msr); - /* Increment Y state if SET3M if true */ + /* Increment Y state if SET3M if true */ msrnum = MSR_GLCP + 0x074; msr.hi = 0; msr.lo = 0x0000c000; wrmsr(msrnum, msr); - /* Set up MBUS action to PRI=3 read of MBIU */ + /* Set up MBUS action to PRI=3 read of MBIU */ msrnum = MSR_GLCP + 0x020; msr.hi = 0x0000d863; msr.lo = 0x20002000; wrmsr(msrnum, msr); - /* Trigger MBUS action if VG=pri3 and Y=0, this blocks most PCI */ + /* Trigger MBUS action if VG=pri3 and Y=0, this blocks most PCI */ msrnum = MSR_GLCP + 0x071; msr.hi = 0; msr.lo = 0x00000c00; @@ -310,10 +278,11 @@ msr.lo = 0x80004000; wrmsr(msrnum, msr); - /* Code to enable FS2 even when BTB and VGTEAR SWAPSiFs are enabled */ - /* As per Todd Roberts in PBz1094 and PBz1095 */ - /* Moved from CPUREG to CPUBUG per Tom Sylla */ - msrnum = 0x04C000042; /* GLCP SETMCTL Register */; + /* Code to enable FS2 even when BTB and VGTEAR SWAPSiFs are enabled + * As per Todd Roberts in PBz1094 and PBz1095 + * Moved from CPUREG to CPUBUG per Tom Sylla + */ + msrnum = 0x04C000042; /* GLCP SETMCTL Register */ msr = rdmsr(msrnum); msr.hi |= 8; /* Bit 35 = MCP_IN */ wrmsr(msrnum, msr); @@ -321,33 +290,24 @@ -/****************************************************************************/ -/***/ -/** DisableMemoryReorder*/ -/***/ -/** PBZ 3659:*/ -/** The MC reordered transactions incorrectly and breaks coherency.*/ -/** Disable reording and take a potential performance hit.*/ -/** This is safe to do here and not in MC init since there is nothing*/ -/** to maintain coherency with and the cache is not enabled yet.*/ -/***/ -/***/ -/** Entry:*/ -/** Exit:*/ -/** Modified:*/ -/***/ -/****************************************************************************/ +/* DisableMemoryReorder + * + * PBZ 3659: + * The MC reordered transactions incorrectly and breaks coherency. + * Disable reording and take a potential performance hit. + * This is safe to do here and not in MC init since there is nothing + * to maintain coherency with and the cache is not enabled yet. + */ static void disablememoryreadorder(void) { msr_t msr; - msr = rdmsr(MC_CF8F_DATA); + msr = rdmsr(MC_CF8F_DATA); msr.hi |= CF8F_UPPER_REORDER_DIS_SET; wrmsr(MC_CF8F_DATA, msr); } -void -cpubug(void) +void cpubug(void) { msr_t msr; int rev; Modified: trunk/src/cpu/amd/model_gx2/cpureginit.c ============================================================================== --- trunk/src/cpu/amd/model_gx2/cpureginit.c Sat Dec 25 23:54:41 2010 (r6207) +++ trunk/src/cpu/amd/model_gx2/cpureginit.c Sun Dec 26 06:12:49 2010 (r6208) @@ -5,7 +5,7 @@ int msrnum; msr_t msr; /* Turn on BTM for early debug based on setup. */ - /* if (getnvram( TOKEN_BTM_DIAG_MODE) & 3) { */ + // if (getnvram( TOKEN_BTM_DIAG_MODE) & 3) { /* The following is only for diagnostics mode; do not use for OLPC */ if (0) { /* Set Diagnostic Mode */ @@ -21,8 +21,8 @@ wrmsr(msrnum, msr); /* exchange it to anything else to prevent this */ /* Turn off debug clock */ - msrnum = 0x04C000016; /* DBG_CLK_CTL*/ - msr.lo = 0x00; /* No clock*/ + msrnum = 0x04C000016; /* DBG_CLK_CTL */ + msr.lo = 0x00; /* No clock */ msr.hi = 0x00; wrmsr(msrnum, msr); @@ -64,7 +64,7 @@ msr.hi = 0; wrmsr(msrnum, msr); - msrnum = 0x04C00000C ; /* GLCP_DBGOUT MSR */ + msrnum = 0x04C00000C ; /* GLCP_DBGOUT MSR */ msr.hi = 0x0; msr.lo = 0x0; /* reset value (SCOPE_SEL = 0) causes FIFO to shift out, */ wrmsr(msrnum, msr); @@ -97,7 +97,7 @@ msrnum = MSR_FG + 0x10; msr = rdmsr(msrnum); msr.lo &= ~3; - msr.lo |= 2; /* ModeB */ + msr.lo |= 2; /* ModeB */ wrmsr(msrnum, msr); #endif @@ -125,7 +125,7 @@ } /* FPU impercise exceptions bit */ - /* if (getnvram( TOKEN_FPU_IE_ENABLE) != TVALUE_DISABLE) { */ + //if (getnvram( TOKEN_FPU_IE_ENABLE) != TVALUE_DISABLE) { { msrnum = CPU_FPU_MSR_MODE; msr = rdmsr(msrnum); @@ -139,7 +139,7 @@ * unless you're testing something. */ /* Allow NVRam to override DM Setup */ - /* if (getnvram( TOKEN_CACHE_DM_MODE) != 1) { */ + //if (getnvram( TOKEN_CACHE_DM_MODE) != 1) { { msrnum = CPU_DM_CONFIG0; msr = rdmsr(msrnum); @@ -150,7 +150,7 @@ * this unless you're testing something. */ /* Allow NVRam to override IM Setup */ - /* if (getnvram( TOKEN_CACHE_IM_MODE) ==1) { */ + //if (getnvram( TOKEN_CACHE_IM_MODE) ==1) { { msrnum = CPU_IM_CONFIG; msr = rdmsr(msrnum); Modified: trunk/src/cpu/amd/model_gx2/syspreinit.c ============================================================================== --- trunk/src/cpu/amd/model_gx2/syspreinit.c Sat Dec 25 23:54:41 2010 (r6207) +++ trunk/src/cpu/amd/model_gx2/syspreinit.c Sun Dec 26 06:12:49 2010 (r6208) @@ -1,12 +1,9 @@ -/* ***************************************************************************/ -/* **/ -/* * StartTimer1*/ -/* **/ -/* * Entry: none*/ -/* * Exit: Starts Timer 1 for port 61 use*/ -/* * Destroys: Al,*/ -/* **/ -/* ***************************************************************************/ +/* StartTimer1 + * + * Entry: none + * Exit: Starts Timer 1 for port 61 use + * Destroys: Al, + */ static void StartTimer1(void) { outb(0x56, 0x43); Modified: trunk/src/include/cpu/amd/gx2def.h ============================================================================== --- trunk/src/include/cpu/amd/gx2def.h Sat Dec 25 23:54:41 2010 (r6207) +++ trunk/src/include/cpu/amd/gx2def.h Sun Dec 26 06:12:49 2010 (r6208) @@ -1,19 +1,19 @@ #ifndef CPU_AMD_GX2DEF_H #define CPU_AMD_GX2DEF_H -#define CPU_ID_1_X 0x540 /* Stepping ID 1.x*/ -#define CPU_ID_2_0 0x551 /* Stepping ID 2.0*/ -#define CPU_ID_2_1 0x552 /* Stepping ID 2.1*/ -#define CPU_ID_2_2 0x553 /* Stepping ID 2.2*/ - -#define CPU_REV_1_0 0x011 -#define CPU_REV_1_1 0x012 -#define CPU_REV_1_2 0x013 -#define CPU_REV_1_3 0x014 -#define CPU_REV_2_0 0x020 -#define CPU_REV_2_1 0x021 -#define CPU_REV_2_2 0x022 -#define CPU_REV_3_0 0x030 +#define CPU_ID_1_X 0x540 /* Stepping ID 1.x*/ +#define CPU_ID_2_0 0x551 /* Stepping ID 2.0*/ +#define CPU_ID_2_1 0x552 /* Stepping ID 2.1*/ +#define CPU_ID_2_2 0x553 /* Stepping ID 2.2*/ + +#define CPU_REV_1_0 0x011 +#define CPU_REV_1_1 0x012 +#define CPU_REV_1_2 0x013 +#define CPU_REV_1_3 0x014 +#define CPU_REV_2_0 0x020 +#define CPU_REV_2_1 0x021 +#define CPU_REV_2_2 0x022 +#define CPU_REV_3_0 0x030 /* GeodeLink Control Processor Registers, GLIU1, Port 3 */ #define GLCP_CLK_DIS_DELAY 0x4c000008 @@ -21,23 +21,22 @@ #define GLCP_CHIP_REVID 0x4c000017 /* GLCP_SYS_RSTPLL, Upper 32 bits */ -#define GLCP_SYS_RSTPLL_MDIV_SHIFT 9 -#define GLCP_SYS_RSTPLL_VDIV_SHIFT 6 -#define GLCP_SYS_RSTPLL_FBDIV_SHIFT 0 +#define GLCP_SYS_RSTPLL_MDIV_SHIFT 9 +#define GLCP_SYS_RSTPLL_VDIV_SHIFT 6 +#define GLCP_SYS_RSTPLL_FBDIV_SHIFT 0 /* GLCP_SYS_RSTPLL, Lower 32 bits */ -#define GLCP_SYS_RSTPLL_SWFLAGS_SHIFT 26 -#define GLCP_SYS_RSTPLL_SWFLAGS_MASK (0x3f << 26) - -#define GLCP_SYS_RSTPLL_LOCKWAIT 24 -#define GLCP_SYS_RSTPLL_HOLDCOUNT 16 -#define GLCP_SYS_RSTPLL_BYPASS 15 -#define GLCP_SYS_RSTPLL_PD 14 -#define GLCP_SYS_RSTPLL_RESETPLL 13 -#define GLCP_SYS_RSTPLL_DDRMODE 10 -#define GLCP_SYS_RSTPLL_VA_SEMI_SYNC_MODE 9 -#define GLCP_SYS_RSTPLL_PCI_SEMI_SYNC_MODE 8 -#define GLCP_SYS_RSTPLL_CHIP_RESET 0 +#define GLCP_SYS_RSTPLL_SWFLAGS_SHIFT 26 +#define GLCP_SYS_RSTPLL_SWFLAGS_MASK (0x3f << 26) +#define GLCP_SYS_RSTPLL_LOCKWAIT 24 +#define GLCP_SYS_RSTPLL_HOLDCOUNT 16 +#define GLCP_SYS_RSTPLL_BYPASS 15 +#define GLCP_SYS_RSTPLL_PD 14 +#define GLCP_SYS_RSTPLL_RESETPLL 13 +#define GLCP_SYS_RSTPLL_DDRMODE 10 +#define GLCP_SYS_RSTPLL_VA_SEMI_SYNC_MODE 9 +#define GLCP_SYS_RSTPLL_PCI_SEMI_SYNC_MODE 8 +#define GLCP_SYS_RSTPLL_CHIP_RESET 0 /* MSR routing as follows */ /* MSB = 1 means not for CPU */ @@ -61,344 +60,328 @@ /* port4 - PCI */ /* port5 - FG */ -#define GL0_GLIU0 0 -#define GL0_MC 1 -#define GL0_GLIU1 2 -#define GL0_CPU 3 -#define GL0_VG 4 -#define GL0_GP 5 -#define GL0_DF 6 - -#define GL1_GLIU0 1 -#define GL1_GLCP 3 -#define GL1_PCI 4 -#define GL1_FG 5 -#define GL1_VIP 5 -#define GL1_AES 6 - -#define MSR_GLIU0 (GL0_GLIU0 << 29) + (1 << 28) /* 1000xxxx - To get on GeodeLink one bit has to be set */ -#define MSR_MC (GL0_MC << 29) /* 2000xxxx */ -#define MSR_GLIU1 (GL0_GLIU1 << 29) /* 4000xxxx */ -#define MSR_CPU (GL0_CPU << 29) /* 6000xxxx - this is not used for BIOS since code executing on CPU doesn't need to be routed */ -#define MSR_VG (GL0_VG << 29) /* 8000xxxx */ -#define MSR_GP (GL0_GP << 29) /* A000xxxx */ -#define MSR_DF (GL0_DF << 29) /* C000xxxx */ - -#define MSR_GLCP (GL1_GLCP << 26) + MSR_GLIU1 /* 4C00xxxx */ -#define MSR_PCI (GL1_PCI << 26) + MSR_GLIU1 /* 5000xxxx */ -#define MSR_FG (GL1_FG << 26) + MSR_GLIU1 /* 5400xxxx */ -#define MSR_VIP ((GL1_VIP << 26) + MSR_GLIU1) /* 5400xxxx */ -#define MSR_AES ((GL1_AES << 26) + MSR_GLIU1) /* 5800xxxx */ +#define GL0_GLIU0 0 +#define GL0_MC 1 +#define GL0_GLIU1 2 +#define GL0_CPU 3 +#define GL0_VG 4 +#define GL0_GP 5 +#define GL0_DF 6 + +#define GL1_GLIU0 1 +#define GL1_GLCP 3 +#define GL1_PCI 4 +#define GL1_FG 5 +#define GL1_VIP 5 +#define GL1_AES 6 + +#define MSR_GLIU0 (GL0_GLIU0 << 29) + (1 << 28) /* 1000xxxx - To get on GeodeLink one bit has to be set */ +#define MSR_MC (GL0_MC << 29) /* 2000xxxx */ +#define MSR_GLIU1 (GL0_GLIU1 << 29) /* 4000xxxx */ +#define MSR_CPU (GL0_CPU << 29) /* 6000xxxx - this is not used for BIOS since code executing on CPU doesn't need to be routed */ +#define MSR_VG (GL0_VG << 29) /* 8000xxxx */ +#define MSR_GP (GL0_GP << 29) /* A000xxxx */ +#define MSR_DF (GL0_DF << 29) /* C000xxxx */ + +#define MSR_GLCP (GL1_GLCP << 26) + MSR_GLIU1 /* 4C00xxxx */ +#define MSR_PCI (GL1_PCI << 26) + MSR_GLIU1 /* 5000xxxx */ +#define MSR_FG (GL1_FG << 26) + MSR_GLIU1 /* 5400xxxx */ +#define MSR_VIP ((GL1_VIP << 26) + MSR_GLIU1) /* 5400xxxx */ +#define MSR_AES ((GL1_AES << 26) + MSR_GLIU1) /* 5800xxxx */ /* South Bridge */ #define SB_PORT 2 /* port of the SouthBridge */ /* GeodeLink Interface Unit 0 (GLIU0) port0 */ -#define GLIU0_GLD_MSR_CAP (MSR_GLIU0 + 0x2000) -#define GLIU0_GLD_MSR_PM (MSR_GLIU0 + 0x2004) +#define GLIU0_GLD_MSR_CAP (MSR_GLIU0 + 0x2000) +#define GLIU0_GLD_MSR_PM (MSR_GLIU0 + 0x2004) -#define GLIU0_DESC_BASE (MSR_GLIU0 + 0x20) -#define GLIU0_CAP (MSR_GLIU0 + 0x86) -#define GLIU0_GLD_MSR_COH (MSR_GLIU0 + 0x80) +#define GLIU0_DESC_BASE (MSR_GLIU0 + 0x20) +#define GLIU0_CAP (MSR_GLIU0 + 0x86) +#define GLIU0_GLD_MSR_COH (MSR_GLIU0 + 0x80) /* Memory Controller GLIU0 port 1 */ #define MC_GLD_MSR_CAP (MSR_MC + 0x2000) #define MC_GLD_MSR_PM (MSR_MC + 0x2004) -#define MC_CF07_DATA (MSR_MC + 0x18) - -#define CF07_UPPER_D1_SZ_SHIFT 28 -#define CF07_UPPER_D1_MB_SHIFT 24 -#define CF07_UPPER_D1_CB_SHIFT 20 -#define CF07_UPPER_D1_PSZ_SHIFT 16 -#define CF07_UPPER_D0_SZ_SHIFT 12 -#define CF07_UPPER_D0_MB_SHIFT 8 -#define CF07_UPPER_D0_CB_SHIFT 4 -#define CF07_UPPER_D0_PSZ_SHIFT 0 - -#define CF07_LOWER_REF_INT_SHIFT 8 -#define CF07_LOWER_LOAD_MODE_DDR_SET (1 << 28) -#define CF07_LOWER_LOAD_MODE_DLL_RESET (1 << 27) -#define CF07_LOWER_EMR_QFC_SET (1 << 26) -#define CF07_LOWER_EMR_DRV_SET (1 << 25) -#define CF07_LOWER_REF_TEST_SET (1 << 3) -#define CF07_LOWER_PROG_DRAM_SET (1 << 0) - -#define MC_CF8F_DATA (MSR_MC + 0x19) - -#define CF8F_UPPER_XOR_BS_SHIFT 19 -#define CF8F_UPPER_XOR_MB0_SHIFT 18 -#define CF8F_UPPER_XOR_BA1_SHIFT 17 -#define CF8F_UPPER_XOR_BA0_SHIFT 16 -#define CF8F_UPPER_REORDER_DIS_SET (1 << 8) -#define CF8F_UPPER_REG_DIMM_SHIFT 4 -#define CF8F_LOWER_CAS_LAT_SHIFT 28 -#define CF8F_LOWER_REF2ACT_SHIFT 24 -#define CF8F_LOWER_ACT2PRE_SHIFT 20 -#define CF8F_LOWER_PRE2ACT_SHIFT 16 -#define CF8F_LOWER_ACT2CMD_SHIFT 12 -#define CF8F_LOWER_ACT2ACT_SHIFT 8 -#define CF8F_UPPER_32BIT_SET (1 << 5) -#define CF8F_UPPER_HOI_LOI_SET (1 << 1) - -#define MC_CF1017_DATA (MSR_MC + 0x1A) - -#define CF1017_LOWER_PM1_UP_DLY_SET (1 << 8) -#define CF1017_LOWER_WR2DAT_SHIFT 0 - -#define MC_CFCLK_DBUG (MSR_MC + 0x1D) - -#define CFCLK_UPPER_MTST_B2B_DIS_SET (1 << 2) -#define CFCLK_UPPER_MTST_DQS_EN_SET (1 << 1) -#define CFCLK_UPPER_MTEST_EN_SET (1 << 0) - -#define CFCLK_LOWER_MASK_CKE_SET1 (1 << 9) -#define CFCLK_LOWER_MASK_CKE_SET0 (1 << 8) -#define CFCLK_LOWER_SDCLK_SET (0x0F << 0) +#define MC_CF07_DATA (MSR_MC + 0x18) +#define CF07_UPPER_D1_SZ_SHIFT 28 +#define CF07_UPPER_D1_MB_SHIFT 24 +#define CF07_UPPER_D1_CB_SHIFT 20 +#define CF07_UPPER_D1_PSZ_SHIFT 16 +#define CF07_UPPER_D0_SZ_SHIFT 12 +#define CF07_UPPER_D0_MB_SHIFT 8 +#define CF07_UPPER_D0_CB_SHIFT 4 +#define CF07_UPPER_D0_PSZ_SHIFT 0 +#define CF07_LOWER_REF_INT_SHIFT 8 +#define CF07_LOWER_LOAD_MODE_DDR_SET (1 << 28) +#define CF07_LOWER_LOAD_MODE_DLL_RESET (1 << 27) +#define CF07_LOWER_EMR_QFC_SET (1 << 26) +#define CF07_LOWER_EMR_DRV_SET (1 << 25) +#define CF07_LOWER_REF_TEST_SET (1 << 3) +#define CF07_LOWER_PROG_DRAM_SET (1 << 0) + +#define MC_CF8F_DATA (MSR_MC + 0x19) +#define CF8F_UPPER_XOR_BS_SHIFT 19 +#define CF8F_UPPER_XOR_MB0_SHIFT 18 +#define CF8F_UPPER_XOR_BA1_SHIFT 17 +#define CF8F_UPPER_XOR_BA0_SHIFT 16 +#define CF8F_UPPER_REORDER_DIS_SET (1 << 8) +#define CF8F_UPPER_REG_DIMM_SHIFT 4 +#define CF8F_LOWER_CAS_LAT_SHIFT 28 +#define CF8F_LOWER_REF2ACT_SHIFT 24 +#define CF8F_LOWER_ACT2PRE_SHIFT 20 +#define CF8F_LOWER_PRE2ACT_SHIFT 16 +#define CF8F_LOWER_ACT2CMD_SHIFT 12 +#define CF8F_LOWER_ACT2ACT_SHIFT 8 +#define CF8F_UPPER_32BIT_SET (1 << 5) +#define CF8F_UPPER_HOI_LOI_SET (1 << 1) + +#define MC_CF1017_DATA (MSR_MC + 0x1A) +#define CF1017_LOWER_PM1_UP_DLY_SET (1 << 8) +#define CF1017_LOWER_WR2DAT_SHIFT 0 + +#define MC_CFCLK_DBUG (MSR_MC + 0x1D) +#define CFCLK_UPPER_MTST_B2B_DIS_SET (1 << 2) +#define CFCLK_UPPER_MTST_DQS_EN_SET (1 << 1) +#define CFCLK_UPPER_MTEST_EN_SET (1 << 0) +#define CFCLK_LOWER_MASK_CKE_SET1 (1 << 9) +#define CFCLK_LOWER_MASK_CKE_SET0 (1 << 8) +#define CFCLK_LOWER_SDCLK_SET (0x0F << 0) -#define MC_CF_RDSYNC (MSR_MC + 0x1F) +#define MC_CF_RDSYNC (MSR_MC + 0x1F) /* GLIU1 GLIU0 port2 */ #define GLIU1_GLD_MSR_CAP (MSR_GLIU1 + 0x2000) #define GLIU1_GLD_MSR_PM (MSR_GLIU1 + 0x2004) - #define GLIU1_GLD_MSR_COH (MSR_GLIU1 + 0x80) /* CPU ; does not need routing instructions since we are executing there. */ -#define CPU_GLD_MSR_CAP 0x2000 -#define CPU_GLD_MSR_CONFIG 0x2001 -#define CPU_GLD_MSR_PM 0x2004 - -#define CPU_GLD_MSR_DIAG 0x2005 -#define DIAG_SEL1_MODE_SHIFT 16 -#define DIAG_SEL1_SET (1 << 31) -#define DIAG_SEL0__MODE_SHIFT 0 -#define DIAG_SET0_SET (1 << 15) - -#define CPU_PF_BTB_CONF 0x1100 -#define BTB_ENABLE_SET (1 << 0) -#define RETURN_STACK_ENABLE_SET (1 << 4) -#define CPU_PF_BTBRMA_BIST 0x110C - -#define CPU_XC_CONFIG 0x1210 -#define XC_CONFIG_SUSP_ON_HLT (1 << 0) -#define CPU_ID_CONFIG 0x1250 -#define ID_CONFIG_SERIAL_SET (1 << 0) - -#define CPU_AC_MSR 0x1301 -#define CPU_EX_BIST 0x1428 +#define CPU_GLD_MSR_CAP 0x2000 +#define CPU_GLD_MSR_CONFIG 0x2001 +#define CPU_GLD_MSR_PM 0x2004 +#define CPU_GLD_MSR_DIAG 0x2005 +#define DIAG_SEL1_MODE_SHIFT 16 +#define DIAG_SEL1_SET (1 << 31) +#define DIAG_SEL0__MODE_SHIFT 0 +#define DIAG_SET0_SET (1 << 15) +#define CPU_PF_BTB_CONF 0x1100 +#define BTB_ENABLE_SET (1 << 0) +#define RETURN_STACK_ENABLE_SET (1 << 4) +#define CPU_PF_BTBRMA_BIST 0x110C +#define CPU_XC_CONFIG 0x1210 +#define XC_CONFIG_SUSP_ON_HLT (1 << 0) +#define CPU_ID_CONFIG 0x1250 +#define ID_CONFIG_SERIAL_SET (1 << 0) +#define CPU_AC_MSR 0x1301 +#define CPU_EX_BIST 0x1428 /* IM */ -#define CPU_IM_CONFIG 0x1700 -#define IM_CONFIG_LOWER_ICD_SET (1 << 8) -#define IM_CONFIG_LOWER_QWT_SET (1 << 20) -#define CPU_IC_INDEX 0x1710 -#define CPU_IC_DATA 0x1711 -#define CPU_IC_TAG 0x1712 -#define CPU_IC_TAG_I 0x1713 -#define CPU_ITB_INDEX 0x1720 -#define CPU_ITB_LRU 0x1721 -#define CPU_ITB_ENTRY 0x1722 -#define CPU_ITB_ENTRY_I 0x1723 -#define CPU_IM_BIST_TAG 0x1730 -#define CPU_IM_BIST_DATA 0x1731 +#define CPU_IM_CONFIG 0x1700 +#define IM_CONFIG_LOWER_ICD_SET (1 << 8) +#define IM_CONFIG_LOWER_QWT_SET (1 << 20) +#define CPU_IC_INDEX 0x1710 +#define CPU_IC_DATA 0x1711 +#define CPU_IC_TAG 0x1712 +#define CPU_IC_TAG_I 0x1713 +#define CPU_ITB_INDEX 0x1720 +#define CPU_ITB_LRU 0x1721 +#define CPU_ITB_ENTRY 0x1722 +#define CPU_ITB_ENTRY_I 0x1723 +#define CPU_IM_BIST_TAG 0x1730 +#define CPU_IM_BIST_DATA 0x1731 /* various CPU MSRs */ -#define CPU_DM_CONFIG0 0x1800 -#define DM_CONFIG0_UPPER_WSREQ_SHIFT 12 -#define DM_CONFIG0_LOWER_DCDIS_SET (1<<8) -#define DM_CONFIG0_LOWER_WBINVD_SET (1<<5) -#define DM_CONFIG0_LOWER_MISSER_SET (1<<1) +#define CPU_DM_CONFIG0 0x1800 +#define DM_CONFIG0_UPPER_WSREQ_SHIFT 12 +#define DM_CONFIG0_LOWER_DCDIS_SET (1<<8) +#define DM_CONFIG0_LOWER_WBINVD_SET (1<<5) +#define DM_CONFIG0_LOWER_MISSER_SET (1<<1) /* configuration MSRs */ -#define CPU_RCONF_DEFAULT 0x1808 -#define RCONF_DEFAULT_UPPER_ROMRC_SHIFT 24 -#define RCONF_DEFAULT_UPPER_ROMBASE_SHIFT 4 -#define RCONF_DEFAULT_UPPER_DEVRC_HI_SHIFT 0 -#define RCONF_DEFAULT_LOWER_DEVRC_LOW_SHIFT 28 -#define RCONF_DEFAULT_LOWER_SYSTOP_SHIFT 8 -#define RCONF_DEFAULT_LOWER_SYSRC_SHIFT 0 - -#define CPU_RCONF_BYPASS 0x180A -#define CPU_RCONF_A0_BF 0x180B -#define CPU_RCONF_C0_DF 0x180C -#define CPU_RCONF_E0_FF 0x180D - -#define CPU_RCONF_SMM 0x180E -#define RCONF_SMM_UPPER_SMMTOP_SHIFT 12 -#define RCONF_SMM_UPPER_RCSMM_SHIFT 0 -#define RCONF_SMM_LOWER_SMMBASE_SHIFT 12 -#define RCONF_SMM_LOWER_RCNORM_SHIFT 0 -#define RCONF_SMM_LOWER_EN_SET (1<<8) - -#define CPU_RCONF_DMM 0x180F -#define RCONF_DMM_UPPER_DMMTOP_SHIFT 12 -#define RCONF_DMM_UPPER_RCDMM_SHIFT 0 -#define RCONF_DMM_LOWER_DMMBASE_SHIFT 12 -#define RCONF_DMM_LOWER_RCNORM_SHIFT 0 -#define RCONF_DMM_LOWER_EN_SET (1<<8) - -#define CPU_RCONF0 0x1810 -#define CPU_RCONF1 0x1811 -#define CPU_RCONF2 0x1812 -#define CPU_RCONF3 0x1813 -#define CPU_RCONF4 0x1814 -#define CPU_RCONF5 0x1815 -#define CPU_RCONF6 0x1816 -#define CPU_RCONF7 0x1817 -#define CPU_CR1_MSR 0x1881 -#define CPU_CR2_MSR 0x1882 -#define CPU_CR3_MSR 0x1883 -#define CPU_CR4_MSR 0x1884 -#define CPU_DC_INDEX 0x1890 -#define CPU_DC_DATA 0x1891 -#define CPU_DC_TAG 0x1892 -#define CPU_DC_TAG_I 0x1893 -#define CPU_SNOOP 0x1894 -#define CPU_DTB_INDEX 0x1898 -#define CPU_DTB_LRU 0x1899 -#define CPU_DTB_ENTRY 0x189A -#define CPU_DTB_ENTRY_I 0x189B -#define CPU_L2TB_INDEX 0x189C -#define CPU_L2TB_LRU 0x189D -#define CPU_L2TB_ENTRY 0x189E -#define CPU_L2TB_ENTRY_I 0x189F -#define CPU_DM_BIST 0x18C0 - /* SMM */ -#define CPU_AC_SMM_CTL 0x1301 -#define SMM_NMI_EN_SET (1<<0) -#define SMM_SUSP_EN_SET (1<<1) -#define NEST_SMI_EN_SET (1<<2) -#define SMM_INST_EN_SET (1<<3) -#define INTL_SMI_EN_SET (1<<4) -#define EXTL_SMI_EN_SET (1<<5) - -#define CPU_FPU_MSR_MODE 0x1A00 -#define FPU_IE_SET (1<<0) - -#define CPU_FP_UROM_BIST 0x1A03 - -#define CPU_BC_CONF_0 0x1900 -#define TSC_SUSP_SET (1<<5) -#define SUSP_EN_SET (1<<12) +#define CPU_RCONF_DEFAULT 0x1808 +#define RCONF_DEFAULT_UPPER_ROMRC_SHIFT 24 +#define RCONF_DEFAULT_UPPER_ROMBASE_SHIFT 4 +#define RCONF_DEFAULT_UPPER_DEVRC_HI_SHIFT 0 +#define RCONF_DEFAULT_LOWER_DEVRC_LOW_SHIFT 28 +#define RCONF_DEFAULT_LOWER_SYSTOP_SHIFT 8 +#define RCONF_DEFAULT_LOWER_SYSRC_SHIFT 0 +#define CPU_RCONF_BYPASS 0x180A +#define CPU_RCONF_A0_BF 0x180B +#define CPU_RCONF_C0_DF 0x180C +#define CPU_RCONF_E0_FF 0x180D +#define CPU_RCONF_SMM 0x180E +#define RCONF_SMM_UPPER_SMMTOP_SHIFT 12 +#define RCONF_SMM_UPPER_RCSMM_SHIFT 0 +#define RCONF_SMM_LOWER_SMMBASE_SHIFT 12 +#define RCONF_SMM_LOWER_RCNORM_SHIFT 0 +#define RCONF_SMM_LOWER_EN_SET (1<<8) +#define CPU_RCONF_DMM 0x180F +#define RCONF_DMM_UPPER_DMMTOP_SHIFT 12 +#define RCONF_DMM_UPPER_RCDMM_SHIFT 0 +#define RCONF_DMM_LOWER_DMMBASE_SHIFT 12 +#define RCONF_DMM_LOWER_RCNORM_SHIFT 0 +#define RCONF_DMM_LOWER_EN_SET (1<<8) + +#define CPU_RCONF0 0x1810 +#define CPU_RCONF1 0x1811 +#define CPU_RCONF2 0x1812 +#define CPU_RCONF3 0x1813 +#define CPU_RCONF4 0x1814 +#define CPU_RCONF5 0x1815 +#define CPU_RCONF6 0x1816 +#define CPU_RCONF7 0x1817 +#define CPU_CR1_MSR 0x1881 +#define CPU_CR2_MSR 0x1882 +#define CPU_CR3_MSR 0x1883 +#define CPU_CR4_MSR 0x1884 +#define CPU_DC_INDEX 0x1890 +#define CPU_DC_DATA 0x1891 +#define CPU_DC_TAG 0x1892 +#define CPU_DC_TAG_I 0x1893 +#define CPU_SNOOP 0x1894 +#define CPU_DTB_INDEX 0x1898 +#define CPU_DTB_LRU 0x1899 +#define CPU_DTB_ENTRY 0x189A +#define CPU_DTB_ENTRY_I 0x189B +#define CPU_L2TB_INDEX 0x189C +#define CPU_L2TB_LRU 0x189D +#define CPU_L2TB_ENTRY 0x189E +#define CPU_L2TB_ENTRY_I 0x189F +#define CPU_DM_BIST 0x18C0 + +/* SMM */ +#define CPU_AC_SMM_CTL 0x1301 +#define SMM_NMI_EN_SET (1<<0) +#define SMM_SUSP_EN_SET (1<<1) +#define NEST_SMI_EN_SET (1<<2) +#define SMM_INST_EN_SET (1<<3) +#define INTL_SMI_EN_SET (1<<4) +#define EXTL_SMI_EN_SET (1<<5) + +#define CPU_FPU_MSR_MODE 0x1A00 +#define FPU_IE_SET (1<<0) + +#define CPU_FP_UROM_BIST 0x1A03 + +#define CPU_BC_CONF_0 0x1900 +#define TSC_SUSP_SET (1<<5) +#define SUSP_EN_SET (1<<12) /* VG GLIU0 port4 */ -#define VG_GLD_MSR_CAP (MSR_VG + 0x2000) -#define VG_GLD_MSR_CONFIG (MSR_VG + 0x2001) -#define VG_GLD_MSR_PM (MSR_VG + 0x2004) - -#define GP_GLD_MSR_CAP (MSR_GP + 0x2000) -#define GP_GLD_MSR_CONFIG (MSR_GP + 0x2001) -#define GP_GLD_MSR_PM (MSR_GP + 0x2004) +#define VG_GLD_MSR_CAP (MSR_VG + 0x2000) +#define VG_GLD_MSR_CONFIG (MSR_VG + 0x2001) +#define VG_GLD_MSR_PM (MSR_VG + 0x2004) + +#define GP_GLD_MSR_CAP (MSR_GP + 0x2000) +#define GP_GLD_MSR_CONFIG (MSR_GP + 0x2001) +#define GP_GLD_MSR_PM (MSR_GP + 0x2004) /* DF GLIU0 port6 */ -#define DF_GLD_MSR_CAP (MSR_DF + 0x2000) -#define DF_GLD_MSR_MASTER_CONF (MSR_DF + 0x2001) -#define DF_LOWER_LCD_SHIFT 6 -#define DF_GLD_MSR_PM (MSR_DF + 0x2004) +#define DF_GLD_MSR_CAP (MSR_DF + 0x2000) +#define DF_GLD_MSR_MASTER_CONF (MSR_DF + 0x2001) +#define DF_LOWER_LCD_SHIFT 6 +#define DF_GLD_MSR_PM (MSR_DF + 0x2004) /* GeodeLink Control Processor GLIU1 port3 */ -#define GLCP_GLD_MSR_CAP (MSR_GLCP + 0x2000) -#define GLCP_GLD_MSR_CONF (MSR_GLCP + 0x2001) -#define GLCP_GLD_MSR_PM (MSR_GLCP + 0x2004) +#define GLCP_GLD_MSR_CAP (MSR_GLCP + 0x2000) +#define GLCP_GLD_MSR_CONF (MSR_GLCP + 0x2001) +#define GLCP_GLD_MSR_PM (MSR_GLCP + 0x2004) -#define GLCP_DELAY_CONTROLS (MSR_GLCP + 0x0F) +#define GLCP_DELAY_CONTROLS (MSR_GLCP + 0x0F) #define GLCP_SYS_RSTPLL (MSR_GLCP +0x14 /* R/W */) -#define RSTPLL_UPPER_MDIV_SHIFT 9 -#define RSTPLL_UPPER_VDIV_SHIFT 6 -#define RSTPLL_UPPER_FBDIV_SHIFT 0 - -#define RSTPLL_LOWER_SWFLAGS_SHIFT 26 -#define RSTPLL_LOWER_SWFLAGS_MASK (0x3F<<RSTPLL_LOWER_SWFLAGS_SHIFT) - -#define RSTPPL_LOWER_HOLD_COUNT_SHIFT 16 -#define RSTPPL_LOWER_BYPASS_SHIFT 15 -#define RSTPPL_LOWER_TST_SHIFT 11 -#define RSTPPL_LOWER_SDRMODE_SHIFT 10 -#define RSTPPL_LOWER_BOOTSTRAP_SHIFT 4 - -#define RSTPPL_LOWER_LOCK_SET (1<<25) -#define RSTPPL_LOWER_LOCKWAIT_SET (1<<24) -#define RSTPPL_LOWER_BYPASS_SET (1<<15) -#define RSTPPL_LOWER_PD_SET (1<<14) -#define RSTPPL_LOWER_PLL_RESET_SET (1<<13) -#define RSTPPL_LOWER_SDRMODE_SET (1<<10) -#define RSTPPL_LOWER_CPU_SEMI_SYNC_SET (1<<9) -#define RSTPPL_LOWER_PCI_SEMI_SYNC_SET (1<<8) -#define RSTPPL_LOWER_CHIP_RESET_SET (1<<0) +#define RSTPLL_UPPER_MDIV_SHIFT 9 +#define RSTPLL_UPPER_VDIV_SHIFT 6 +#define RSTPLL_UPPER_FBDIV_SHIFT 0 +#define RSTPLL_LOWER_SWFLAGS_SHIFT 26 +#define RSTPLL_LOWER_SWFLAGS_MASK (0x3F<<RSTPLL_LOWER_SWFLAGS_SHIFT) +#define RSTPPL_LOWER_HOLD_COUNT_SHIFT 16 +#define RSTPPL_LOWER_BYPASS_SHIFT 15 +#define RSTPPL_LOWER_TST_SHIFT 11 +#define RSTPPL_LOWER_SDRMODE_SHIFT 10 +#define RSTPPL_LOWER_BOOTSTRAP_SHIFT 4 +#define RSTPPL_LOWER_LOCK_SET (1<<25) +#define RSTPPL_LOWER_LOCKWAIT_SET (1<<24) +#define RSTPPL_LOWER_BYPASS_SET (1<<15) +#define RSTPPL_LOWER_PD_SET (1<<14) +#define RSTPPL_LOWER_PLL_RESET_SET (1<<13) +#define RSTPPL_LOWER_SDRMODE_SET (1<<10) +#define RSTPPL_LOWER_CPU_SEMI_SYNC_SET (1<<9) +#define RSTPPL_LOWER_PCI_SEMI_SYNC_SET (1<<8) +#define RSTPPL_LOWER_CHIP_RESET_SET (1<<0) -#define GLCP_DOTPLL (MSR_GLCP + 0x15 /* R/W */) -#define DOTPPL_LOWER_PD_SET (1<<14) +#define GLCP_DOTPLL (MSR_GLCP + 0x15 /* R/W */) +#define DOTPPL_LOWER_PD_SET (1<<14) /* GLIU1 port 4 */ -#define GLPCI_GLD_MSR_CAP (MSR_PCI + 0x2000) -#define GLPCI_GLD_MSR_CONFIG (MSR_PCI + 0x2001) -#define GLPCI_GLD_MSR_PM (MSR_PCI + 0x2004) - -#define GLPCI_CTRL (MSR_PCI + 0x2010) -#define GLPCI_CTRL_UPPER_FTH_SHIFT 28 -#define GLPCI_CTRL_UPPER_RTH_SHIFT 24 -#define GLPCI_CTRL_UPPER_SBRTH_SHIFT 20 -#define GLPCI_CTRL_UPPER_DTL_SHIFT 14 -#define GLPCI_CTRL_UPPER_WTO_SHIFT 11 -#define GLPCI_CTRL_UPPER_LAT_SHIFT 3 -#define GLPCI_CTRL_UPPER_ILTO_SHIFT 8 -#define GLPCI_CTRL_LOWER_IRFT_SHIFT 18 -#define GLPCI_CTRL_LOWER_IRFC_SHIFT 16 -#define GLPCI_CTRL_LOWER_ER_SET (1<<11) -#define GLPCI_CTRL_LOWER_LDE_SET (1<<9) -#define GLPCI_CTRL_LOWER_OWC_SET (1<<4) -#define GLPCI_CTRL_LOWER_IWC_SET (1<<3) -#define GLPCI_CTRL_LOWER_PCD_SET (1<<2) -#define GLPCI_CTRL_LOWER_ME_SET (1<<0) - -#define GLPCI_ARB (MSR_PCI + 0x2011) -#define GLPCI_ARB_UPPER_BM1_SET (1<<17) -#define GLPCI_ARB_UPPER_BM0_SET (1<<16) -#define GLPCI_ARB_UPPER_CPRE_SET (1<<15) -#define GLPCI_ARB_UPPER_PRE2_SET (1<<10) -#define GLPCI_ARB_UPPER_PRE1_SET (1<<9) -#define GLPCI_ARB_UPPER_PRE0_SET (1<<8) -#define GLPCI_ARB_UPPER_CRME_SET (1<<7) -#define GLPCI_ARB_UPPER_RME2_SET (1<<2) -#define GLPCI_ARB_UPPER_RME1_SET (1<<1) -#define GLPCI_ARB_UPPER_RME0_SET (1<<0) -#define GLPCI_ARB_LOWER_PRCM_SHIFT 24 -#define GLPCI_ARB_LOWER_FPVEC_SHIFT 16 -#define GLPCI_ARB_LOWER_RMT_SHIFT 6 -#define GLPCI_ARB_LOWER_IIE_SET (1<<8) -#define GLPCI_ARB_LOWER_PARK_SET (1<<0) - -#define GLPCI_REN (MSR_PCI + 0x2014) -#define GLPCI_A0_BF (MSR_PCI + 0x2015) -#define GLPCI_C0_DF (MSR_PCI + 0x2016) -#define GLPCI_E0_FF (MSR_PCI + 0x2017) -#define GLPCI_RC0 (MSR_PCI + 0x2018) -#define GLPCI_RC1 (MSR_PCI + 0x2019) -#define GLPCI_RC2 (MSR_PCI + 0x201A) -#define GLPCI_RC3 (MSR_PCI + 0x201B) -#define GLPCI_RC4 (MSR_PCI + 0x201C) -#define GLPCI_RC_UPPER_TOP_SHIFT 12 -#define GLPCI_RC_LOWER_BASE_SHIFT 12 -#define GLPCI_RC_LOWER_EN_SET (1<<8) -#define GLPCI_RC_LOWER_PF_SET (1<<5) -#define GLPCI_RC_LOWER_WC_SET (1<<4) -#define GLPCI_RC_LOWER_WP_SET (1<<2) -#define GLPCI_RC_LOWER_CD_SET (1<<0) -#define GLPCI_ExtMSR (MSR_PCI + 0x201E) -#define GLPCI_SPARE (MSR_PCI + 0x201F) -#define GLPCI_SPARE_LOWER_AILTO_SET (1<<6) -#define GLPCI_SPARE_LOWER_PPD_SET (1<<5) -#define GLPCI_SPARE_LOWER_PPC_SET (1<<4) -#define GLPCI_SPARE_LOWER_MPC_SET (1<<3) -#define GLPCI_SPARE_LOWER_MME_SET (1<<2) -#define GLPCI_SPARE_LOWER_NSE_SET (1<<1) -#define GLPCI_SPARE_LOWER_SUPO_SET (1<<0) +#define GLPCI_GLD_MSR_CAP (MSR_PCI + 0x2000) +#define GLPCI_GLD_MSR_CONFIG (MSR_PCI + 0x2001) +#define GLPCI_GLD_MSR_PM (MSR_PCI + 0x2004) + +#define GLPCI_CTRL (MSR_PCI + 0x2010) +#define GLPCI_CTRL_UPPER_FTH_SHIFT 28 +#define GLPCI_CTRL_UPPER_RTH_SHIFT 24 +#define GLPCI_CTRL_UPPER_SBRTH_SHIFT 20 +#define GLPCI_CTRL_UPPER_DTL_SHIFT 14 +#define GLPCI_CTRL_UPPER_WTO_SHIFT 11 +#define GLPCI_CTRL_UPPER_LAT_SHIFT 3 +#define GLPCI_CTRL_UPPER_ILTO_SHIFT 8 +#define GLPCI_CTRL_LOWER_IRFT_SHIFT 18 +#define GLPCI_CTRL_LOWER_IRFC_SHIFT 16 +#define GLPCI_CTRL_LOWER_ER_SET (1<<11) +#define GLPCI_CTRL_LOWER_LDE_SET (1<<9) +#define GLPCI_CTRL_LOWER_OWC_SET (1<<4) +#define GLPCI_CTRL_LOWER_IWC_SET (1<<3) +#define GLPCI_CTRL_LOWER_PCD_SET (1<<2) +#define GLPCI_CTRL_LOWER_ME_SET (1<<0) + +#define GLPCI_ARB (MSR_PCI + 0x2011) +#define GLPCI_ARB_UPPER_BM1_SET (1<<17) +#define GLPCI_ARB_UPPER_BM0_SET (1<<16) +#define GLPCI_ARB_UPPER_CPRE_SET (1<<15) +#define GLPCI_ARB_UPPER_PRE2_SET (1<<10) +#define GLPCI_ARB_UPPER_PRE1_SET (1<<9) +#define GLPCI_ARB_UPPER_PRE0_SET (1<<8) +#define GLPCI_ARB_UPPER_CRME_SET (1<<7) +#define GLPCI_ARB_UPPER_RME2_SET (1<<2) +#define GLPCI_ARB_UPPER_RME1_SET (1<<1) +#define GLPCI_ARB_UPPER_RME0_SET (1<<0) +#define GLPCI_ARB_LOWER_PRCM_SHIFT 24 +#define GLPCI_ARB_LOWER_FPVEC_SHIFT 16 +#define GLPCI_ARB_LOWER_RMT_SHIFT 6 +#define GLPCI_ARB_LOWER_IIE_SET (1<<8) +#define GLPCI_ARB_LOWER_PARK_SET (1<<0) + +#define GLPCI_REN (MSR_PCI + 0x2014) +#define GLPCI_A0_BF (MSR_PCI + 0x2015) +#define GLPCI_C0_DF (MSR_PCI + 0x2016) +#define GLPCI_E0_FF (MSR_PCI + 0x2017) +#define GLPCI_RC0 (MSR_PCI + 0x2018) +#define GLPCI_RC1 (MSR_PCI + 0x2019) +#define GLPCI_RC2 (MSR_PCI + 0x201A) +#define GLPCI_RC3 (MSR_PCI + 0x201B) +#define GLPCI_RC4 (MSR_PCI + 0x201C) +#define GLPCI_RC_UPPER_TOP_SHIFT 12 +#define GLPCI_RC_LOWER_BASE_SHIFT 12 +#define GLPCI_RC_LOWER_EN_SET (1<<8) +#define GLPCI_RC_LOWER_PF_SET (1<<5) +#define GLPCI_RC_LOWER_WC_SET (1<<4) +#define GLPCI_RC_LOWER_WP_SET (1<<2) +#define GLPCI_RC_LOWER_CD_SET (1<<0) +#define GLPCI_ExtMSR (MSR_PCI + 0x201E) +#define GLPCI_SPARE (MSR_PCI + 0x201F) +#define GLPCI_SPARE_LOWER_AILTO_SET (1<<6) +#define GLPCI_SPARE_LOWER_PPD_SET (1<<5) +#define GLPCI_SPARE_LOWER_PPC_SET (1<<4) +#define GLPCI_SPARE_LOWER_MPC_SET (1<<3) +#define GLPCI_SPARE_LOWER_MME_SET (1<<2) +#define GLPCI_SPARE_LOWER_NSE_SET (1<<1) +#define GLPCI_SPARE_LOWER_SUPO_SET (1<<0) /* FooGlue GLIU1 port 5 */ -#define FG_GLD_MSR_CAP (MSR_FG + 0x2000) -#define FG_GLD_MSR_PM (MSR_FG + 0x2004) +#define FG_GLD_MSR_CAP (MSR_FG + 0x2000) +#define FG_GLD_MSR_PM (MSR_FG + 0x2004) /* VIP GLIU1 port 5 */ #define VIP_GLD_MSR_CAP (MSR_VIP + 0x2000) @@ -423,68 +406,68 @@ /* more fun stuff */ #define BM 1 /* Base Mask - map power of 2 size aligned region */ #define BMO 2 /* BM with an offset */ -#define R 3 /* Range - 4k range minimum */ +#define R 3 /* Range - 4k range minimum */ #define RO 4 /* R with offset */ #define SC 5 /* Swiss 0xCeese - maps a 256K region in to 16K 0xcunks. Set W/R */ #define BMIO 6 /* Base Mask IO */ #define SCIO 7 /* Swiss 0xCeese IO */ -#define SC_SHADOW 8 /* Special marker for Shadow SC descriptors so setShadow proc is independant of CPU */ +#define SC_SHADOW 8 /* Special marker for Shadow SC descriptors so setShadow proc is independant of CPU */ #define R_SYSMEM 9 /* Special marker for SYSMEM R descriptors so GLIUInit proc is independant of CPU */ -#define BMO_SMM 10 /* Specail marker for SMM */ -#define BM_SMM 11 /* Specail marker for SMM */ -#define BMO_DMM 12 /* Specail marker for DMM */ -#define BM_DMM 13 /* Specail marker for DMM */ +#define BMO_SMM 10 /* Specail marker for SMM */ +#define BM_SMM 11 /* Specail marker for SMM */ +#define BMO_DMM 12 /* Specail marker for DMM */ +#define BM_DMM 13 /* Specail marker for DMM */ #define RO_FB 14 /* special for Frame buffer. */ #define R_FB 15 /* special for FB. */ -#define OTHER 0x0FE /* Special marker for other */ -#define GL_END 0x0FF /* end */ +#define OTHER 0x0FE /* Special marker for other */ +#define GL_END 0x0FF /* end */ #define MSR_GL0 (GL1_GLIU0 << 29) /* Set up desc addresses from 20 - 3f */ /* This is chip specific! */ -#define MSR_GLIU0_BASE1 (MSR_GLIU0 + 0x20) /* BM */ -#define MSR_GLIU0_BASE2 (MSR_GLIU0 + 0x21) /* BM */ -#define MSR_GLIU0_SHADOW (MSR_GLIU0 + 0x2C) /* SCO should only be SC */ -#define MSR_GLIU0_SYSMEM (MSR_GLIU0 + 0x28) /* RO should only be R */ -#define MSR_GLIU0_SMM (MSR_GLIU0 + 0x26) /* BMO */ -#define MSR_GLIU0_DMM (MSR_GLIU0 + 0x27) /* BMO */ - -#define MSR_GLIU1_BASE1 (MSR_GLIU1 + 0x20) /* BM */ -#define MSR_GLIU1_BASE2 (MSR_GLIU1 + 0x21) /* BM */ -#define MSR_GLIU1_SHADOW (MSR_GLIU1 + 0x2D) /* SCO should only be SC */ -#define MSR_GLIU1_SYSMEM (MSR_GLIU1 + 0x29) /* RO should only be R */ -#define MSR_GLIU1_SMM (MSR_GLIU1 + 0x23) /* BM */ -#define MSR_GLIU1_DMM (MSR_GLIU1 + 0x24) /* BM */ -#define MSR_GLIU1_FPU_TRAP (MSR_GLIU1 + 0x0E3) /* FooGlue F0 for FPU */ +#define MSR_GLIU0_BASE1 (MSR_GLIU0 + 0x20) /* BM */ +#define MSR_GLIU0_BASE2 (MSR_GLIU0 + 0x21) /* BM */ +#define MSR_GLIU0_SHADOW (MSR_GLIU0 + 0x2C) /* SCO should only be SC */ +#define MSR_GLIU0_SYSMEM (MSR_GLIU0 + 0x28) /* RO should only be R */ +#define MSR_GLIU0_SMM (MSR_GLIU0 + 0x26) /* BMO */ +#define MSR_GLIU0_DMM (MSR_GLIU0 + 0x27) /* BMO */ + +#define MSR_GLIU1_BASE1 (MSR_GLIU1 + 0x20) /* BM */ +#define MSR_GLIU1_BASE2 (MSR_GLIU1 + 0x21) /* BM */ +#define MSR_GLIU1_SHADOW (MSR_GLIU1 + 0x2D) /* SCO should only be SC */ +#define MSR_GLIU1_SYSMEM (MSR_GLIU1 + 0x29) /* RO should only be R */ +#define MSR_GLIU1_SMM (MSR_GLIU1 + 0x23) /* BM */ +#define MSR_GLIU1_DMM (MSR_GLIU1 + 0x24) /* BM */ +#define MSR_GLIU1_FPU_TRAP (MSR_GLIU1 + 0x0E3) /* FooGlue F0 for FPU */ /* definitions that are "once you are mostly up, start VSA" type things */ -#define SMM_OFFSET 0x40400000 -#define SMM_SIZE 128 /* changed SMM_SIZE from 256 KB to 128 KB */ -#define DMM_OFFSET 0x0C0000000 +#define SMM_OFFSET 0x40400000 +#define SMM_SIZE 128 /* changed SMM_SIZE from 256 KB to 128 KB */ +#define DMM_OFFSET 0x0C0000000 #define DMM_SIZE 128 #define FB_OFFSET 0x41000000 -#define PCI_MEM_TOP 0x0EFFFFFFF // Top of PCI mem allocation region -#define PCI_IO_TOP 0x0EFFF // Top of PCI I/O allocation region -#define END_OPTIONROM_SPACE 0x0DFFF // E0000 is reserved for SystemROMs. - -#define MDD_SMBUS 0x06000 // SMBUS IO location -#define MDD_GPIO 0x06100 // GPIO & ICF IO location -#define MDD_MFGPT 0x06200 // General Purpose Timers IO location -#define MDD_IRQ_MAPPER 0x06300 // IRQ Mapper -#define ACPI_BASE 0x09C00 // ACPI Base -#define MDD_PM 0x09D00 // Power Management Logic - placed at the end of ACPI - -#define CS5535_IDSEL 0x02000000 // IDSEL = AD25, device #15 -#define CHIPSET_DEV_NUM 15 -#define IDSEL_BASE 11 // bit 11 = device 1 +#define PCI_MEM_TOP 0x0EFFFFFFF /* Top of PCI mem allocation region */ +#define PCI_IO_TOP 0x0EFFF /* Top of PCI I/O allocation region */ +#define END_OPTIONROM_SPACE 0x0DFFF /* E0000 is reserved for SystemROMs */ + +#define MDD_SMBUS 0x06000 /* SMBUS IO location */ +#define MDD_GPIO 0x06100 /* GPIO & ICF IO location */ +#define MDD_MFGPT 0x06200 /* General Purpose Timers IO location */ +#define MDD_IRQ_MAPPER 0x06300 /* IRQ Mapper */ +#define ACPI_BASE 0x09C00 /* ACPI Base */ +#define MDD_PM 0x09D00 /* Power Management Logic - placed at the end of ACPI */ + +#define CS5535_IDSEL 0x02000000 /* IDSEL = AD25, device #15 */ +#define CHIPSET_DEV_NUM 15 +#define IDSEL_BASE 11 /* bit 11 = device 1 */ /* SB LBAR IO + MEMORY MAP */ -#define SMBUS_BASE ( 0x6000) -#define GPIO_BASE ( 0x6100) -#define MFGPT_BASE ( 0x6200) -#define IRQMAP_BASE ( 0x6300) -#define PMLogic_BASE ( 0x9D00) +#define SMBUS_BASE (0x6000) +#define GPIO_BASE (0x6100) +#define MFGPT_BASE (0x6200) +#define IRQMAP_BASE (0x6300) +#define PMLogic_BASE (0x9D00) #if !defined(__ROMCC__) && !defined(ASSEMBLY) Modified: trunk/src/northbridge/amd/gx2/grphinit.c ============================================================================== --- trunk/src/northbridge/amd/gx2/grphinit.c Sat Dec 25 23:54:41 2010 (r6207) +++ trunk/src/northbridge/amd/gx2/grphinit.c Sun Dec 26 06:12:49 2010 (r6208) @@ -5,13 +5,10 @@ #include "chip.h" #include "northbridge.h" -// FIXME handle UMA properly. -#define VIDEO_MB 8 // MB of video memory +/* FIXME handle UMA properly. */ +#define VIDEO_MB 8 /* MB of video memory */ - - /* - * This function mirrors the Graphics_Init routine in GeodeROM. - */ +/* This function mirrors the Graphics_Init routine in GeodeROM. */ void graphics_init(void) { /* SoftVG initialization */ Modified: trunk/src/northbridge/amd/gx2/northbridge.c ============================================================================== --- trunk/src/northbridge/amd/gx2/northbridge.c Sat Dec 25 23:54:41 2010 (r6207) +++ trunk/src/northbridge/amd/gx2/northbridge.c Sun Dec 26 06:12:49 2010 (r6208) @@ -20,15 +20,15 @@ #define NORTHBRIDGE_FILE "northbridge.c" /* todo: add a resource record. We don't do this here because this may be called when - * very little of the platform is actually working. - */ -int -sizeram(void) + * very little of the platform is actually working. + */ +int sizeram(void) { msr_t msr; int sizem = 0; unsigned short dimm; + /* Get the RAM size from the memory controller as calculated and set by auto_size_dimm() */ msr = rdmsr(0x20000018); printk(BIOS_DEBUG, "sizeram: %08x:%08x\n", msr.hi, msr.lo); @@ -38,8 +38,7 @@ if ((dimm & 7) != 7) sizem = (1 << ((dimm >> 12)-1)) * 8; - - /* dimm 1*/ + /* dimm 1 */ dimm = msr.hi >> 16; /* installed? */ if ((dimm & 7) != 7) @@ -49,8 +48,7 @@ return sizem; } - -/* here is programming for the various MSRs.*/ +/* here is programming for the various MSRs. */ #define IM_QWAIT 0x100000 #define DMCF_WRITE_SERIALIZE_REQUEST (2<<12) /* 2 outstanding */ /* in high */ @@ -86,9 +84,8 @@ #define IOD_BM(msr, pdid1, bizarro, ibase, imask) {msr, {.hi=(pdid1<<29)|(bizarro<<28)|(ibase>>12), .lo=(ibase<<20)|imask}} #define IOD_SC(msr, pdid1, bizarro, en, wen, ren, ibase) {msr, {.hi=(pdid1<<29)|(bizarro<<28), .lo=(en<<24)|(wen<<21)|(ren<<20)|(ibase<<3)}} - - -struct msr_defaults { +struct msr_defaults +{ int msr_no; msr_t msr; } msr_defaults [] = { @@ -121,7 +118,8 @@ }; /* note that dev is NOT used -- yet */ -static void irq_init_steering(struct device *dev, u16 irq_map) { +static void irq_init_steering(struct device *dev, u16 irq_map) +{ /* Set up IRQ steering */ u32 pciAddr = 0x80000000 | (CHIPSET_DEV_NUM << 11) | 0x5C; @@ -142,16 +140,12 @@ outl(irq_map, 0xCFC); } - -/* - * setup_gx2_cache +/* setup_gx2_cache * * Returns the amount of memory (in KB) available to the system. This is the * total amount of memory less the amount of memory reserved for SMM use. - * */ -static int -setup_gx2_cache(void) +static int setup_gx2_cache(void) { msr_t msr; unsigned long long val; @@ -164,7 +158,7 @@ /* set romrp */ val = ((unsigned long long) ROM_PROPERTIES) << 56; /* make rom base useful for 1M roms */ - /* Flash base address -- sized for 1M for now*/ + /* Flash base address -- sized for 1M for now */ val |= ((unsigned long long) 0xfff00)<<36; /* set the devrp properties */ val |= ((unsigned long long) DEVICE_PROPERTIES) << 28; @@ -172,7 +166,7 @@ /* yank off memory for the SMM handler */ sizekbytes -= SMM_SIZE; sizereg = sizekbytes; - sizereg *= 1024; // convert to bytes + sizereg *= 1024; /* convert to bytes */ sizereg >>= 12; sizereg <<= 8; val |= sizereg; @@ -188,10 +182,8 @@ } /* we have to do this here. We have not found a nicer way to do it */ -static void -setup_gx2(void) +static void setup_gx2(void) { - unsigned long tmp, tmp2; msr_t msr; unsigned long size_kb, membytes; @@ -200,13 +192,13 @@ membytes = size_kb * 1024; /* NOTE! setup_gx2_cache returns the SIZE OF RAM - RAMADJUST! - * so it is safe to use. You should NOT at this point call - * sizeram() directly. - */ + * so it is safe to use. You should NOT at this point call + * sizeram() directly. + */ /* we need to set 0x10000028 and 0x40000029 */ - /* - * These two descriptors cover the range from 1 MB (0x100000) to + + /* These two descriptors cover the range from 1 MB (0x100000) to * SYSTOP (a.k.a. TOM, or Top of Memory) */ @@ -258,11 +250,11 @@ msr = rdmsr(0x1808); printk(BIOS_DEBUG, "MSR 0x%x is now 0x%x:0x%x\n", 0x1808, msr.hi, msr.lo); #endif -#if 0 // SDG - don't do this +#if 0 /* SDG - don't do this */ /* now do the default MSR values */ for(i = 0; msr_defaults[i].msr_no; i++) { msr_t msr; - wrmsr(msr_defaults[i].msr_no, msr_defaults[i].msr); // MSR - see table above + wrmsr(msr_defaults[i].msr_no, msr_defaults[i].msr); /* MSR - see table above */ msr = rdmsr(msr_defaults[i].msr_no); printk(BIOS_DEBUG, "MSR 0x%08X is now 0x%08X:0x%08X\n", msr_defaults[i].msr_no, msr.hi,msr.lo); } @@ -297,51 +289,49 @@ static void set_resources(struct device *dev) { #if 0 - struct resource *res; + struct resource *res; - for(res = &dev->resource_list; res; res = res->next) { - pci_set_resource(dev, resource); - } + for(res = &dev->resource_list; res; res = res->next) { + pci_set_resource(dev, resource); + } #endif struct bus *bus; for(bus = dev->link_list; bus; bus = bus->next) { - if (bus->children) { - assign_resources(bus); - } - } + if (bus->children) { + assign_resources(bus); + } + } #if 0 - /* set a default latency timer */ - pci_write_config8(dev, PCI_LATENCY_TIMER, 0x40); + /* set a default latency timer */ + pci_write_config8(dev, PCI_LATENCY_TIMER, 0x40); + + /* set a default secondary latency timer */ + if ((dev->hdr_type & 0x7f) == PCI_HEADER_TYPE_BRIDGE) { + pci_write_config8(dev, PCI_SEC_LATENCY_TIMER, 0x40); + } - /* set a default secondary latency timer */ - if ((dev->hdr_type & 0x7f) == PCI_HEADER_TYPE_BRIDGE) { - pci_write_config8(dev, PCI_SEC_LATENCY_TIMER, 0x40); - } - - /* zero the irq settings */ - u8 line = pci_read_config8(dev, PCI_INTERRUPT_PIN); - if (line) { - pci_write_config8(dev, PCI_INTERRUPT_LINE, 0); - } - /* set the cache line size, so far 64 bytes is good for everyone */ - pci_write_config8(dev, PCI_CACHE_LINE_SIZE, 64 >> 2); + /* zero the irq settings */ + u8 line = pci_read_config8(dev, PCI_INTERRUPT_PIN); + if (line) { + pci_write_config8(dev, PCI_INTERRUPT_LINE, 0); + } + /* set the cache line size, so far 64 bytes is good for everyone */ + pci_write_config8(dev, PCI_CACHE_LINE_SIZE, 64 >> 2); #endif } - - static struct device_operations northbridge_operations = { - .read_resources = pci_dev_read_resources, + .read_resources = pci_dev_read_resources, #if 0 - .set_resources = pci_dev_set_resources, + .set_resources = pci_dev_set_resources, #endif - .set_resources = set_resources, + .set_resources = set_resources, .enable_resources = pci_dev_enable_resources, - .init = northbridge_init, - .enable = 0, - .ops_pci = 0, + .init = northbridge_init, + .enable = 0, + .ops_pci = 0, }; static const struct pci_driver northbridge_driver __pci_driver = { @@ -350,16 +340,16 @@ .device = PCI_DEVICE_ID_NS_GX2, }; -// FIXME handle UMA correctly. +/* FIXME handle UMA correctly. */ #define FRAMEBUFFERK 4096 static void pci_domain_set_resources(device_t dev) { #if 0 device_t mc_dev; - u32 pci_tolm; + u32 pci_tolm; - pci_tolm = find_pci_tolm(dev->link_list); + pci_tolm = find_pci_tolm(dev->link_list); mc_dev = dev->link_list->children; if (mc_dev) { unsigned int tomk, tolmk; @@ -405,16 +395,16 @@ } static struct device_operations pci_domain_ops = { - .read_resources = pci_domain_read_resources, - .set_resources = pci_domain_set_resources, - .enable_resources = NULL, - .init = NULL, - .scan_bus = pci_domain_scan_bus, + .read_resources = pci_domain_read_resources, + .set_resources = pci_domain_set_resources, + .enable_resources = NULL, + .init = NULL, + .scan_bus = pci_domain_scan_bus, }; static void cpu_bus_init(device_t dev) { - initialize_cpus(dev->link_list); + initialize_cpus(dev->link_list); } static void cpu_bus_noop(device_t dev) @@ -422,11 +412,11 @@ } static struct device_operations cpu_bus_ops = { - .read_resources = cpu_bus_noop, - .set_resources = cpu_bus_noop, - .enable_resources = cpu_bus_noop, - .init = cpu_bus_init, - .scan_bus = 0, + .read_resources = cpu_bus_noop, + .set_resources = cpu_bus_noop, + .enable_resources = cpu_bus_noop, + .init = cpu_bus_init, + .scan_bus = 0, }; void chipsetInit (void); @@ -440,8 +430,8 @@ printk(BIOS_DEBUG, "gx2 north: enable_dev\n"); void do_vsmbios(void); - /* Set the operations if it is a special bus type */ - if (dev->path.type == DEVICE_PATH_PCI_DOMAIN) { + /* Set the operations if it is a special bus type */ + if (dev->path.type == DEVICE_PATH_PCI_DOMAIN) { u32 tomk; printk(BIOS_DEBUG, "DEVICE_PATH_PCI_DOMAIN\n"); /* cpubug MUST be called before setup_gx2(), so we force the issue here */ @@ -460,10 +450,10 @@ high_tables_size = HIGH_MEMORY_SIZE; #endif ram_resource(dev, 0, 0, tomk); - } else if (dev->path.type == DEVICE_PATH_APIC_CLUSTER) { + } else if (dev->path.type == DEVICE_PATH_APIC_CLUSTER) { printk(BIOS_DEBUG, "DEVICE_PATH_APIC_CLUSTER\n"); - dev->ops = &cpu_bus_ops; - } + dev->ops = &cpu_bus_ops; + } printk(BIOS_DEBUG, "gx2 north: end enable_dev\n"); } Modified: trunk/src/northbridge/amd/gx2/northbridgeinit.c ============================================================================== --- trunk/src/northbridge/amd/gx2/northbridgeinit.c Sat Dec 25 23:54:41 2010 (r6207) +++ trunk/src/northbridge/amd/gx2/northbridgeinit.c Sun Dec 26 06:12:49 2010 (r6208) @@ -15,38 +15,40 @@ /* put this here for now, we are not sure where it belongs */ -struct gliutable { +struct gliutable +{ unsigned long desc_name; unsigned short desc_type; unsigned long hi, lo; }; struct gliutable gliu0table[] = { - {.desc_name=MSR_GLIU0_BASE1, .desc_type= BM,.hi= MSR_MC + 0x0,.lo= 0x0FFF80}, /* 0-7FFFF to MC */ + {.desc_name=MSR_GLIU0_BASE1, .desc_type= BM,.hi= MSR_MC + 0x0,.lo= 0x0FFF80}, /* 0-7FFFF to MC */ {.desc_name=MSR_GLIU0_BASE2, .desc_type= BM,.hi= MSR_MC + 0x0,.lo=(0x80 << 20) + 0x0FFFE0}, /* 80000-9ffff to Mc */ - {.desc_name=MSR_GLIU0_SHADOW, .desc_type= SC_SHADOW,.hi= MSR_MC + 0x0,.lo= 0x03}, /* C0000-Fffff split to MC and PCI (sub decode) A0000-Bffff handled by SoftVideo */ - {.desc_name=MSR_GLIU0_SYSMEM, .desc_type= R_SYSMEM,.hi= MSR_MC,.lo= 0x0}, /* Catch and fix dynamicly. */ - {.desc_name=MSR_GLIU0_DMM, .desc_type= BMO_DMM,.hi= MSR_MC,.lo= 0x0}, /* Catch and fix dynamicly. */ - {.desc_name=MSR_GLIU0_SMM, .desc_type= BMO_SMM,.hi= MSR_MC,.lo= 0x0}, /* Catch and fix dynamicly. */ + {.desc_name=MSR_GLIU0_SHADOW, .desc_type= SC_SHADOW,.hi= MSR_MC + 0x0,.lo= 0x03}, /* C0000-Fffff split to MC and PCI (sub decode) A0000-Bffff handled by SoftVideo */ + {.desc_name=MSR_GLIU0_SYSMEM, .desc_type= R_SYSMEM,.hi= MSR_MC,.lo= 0x0}, /* Catch and fix dynamicly. */ + {.desc_name=MSR_GLIU0_DMM, .desc_type= BMO_DMM,.hi= MSR_MC,.lo= 0x0}, /* Catch and fix dynamicly. */ + {.desc_name=MSR_GLIU0_SMM, .desc_type= BMO_SMM,.hi= MSR_MC,.lo= 0x0}, /* Catch and fix dynamicly. */ {.desc_name=GLIU0_GLD_MSR_COH,.desc_type= OTHER,.hi= 0x0,.lo= GL0_CPU}, {.desc_name=GL_END, .desc_type= GL_END,.hi= 0x0,.lo= 0x0}, }; struct gliutable gliu1table[] = { - {.desc_name=MSR_GLIU1_BASE1,.desc_type= BM,.hi= MSR_GL0 + 0x0,.lo= 0x0FFF80}, /* 0-7FFFF to MC */ + {.desc_name=MSR_GLIU1_BASE1,.desc_type= BM,.hi= MSR_GL0 + 0x0,.lo= 0x0FFF80}, /* 0-7FFFF to MC */ {.desc_name=MSR_GLIU1_BASE2,.desc_type= BM,.hi= MSR_GL0 + 0x0,.lo= (0x80 << 20) +0x0FFFE0}, /* 80000-9ffff to Mc */ - {.desc_name=MSR_GLIU1_SHADOW,.desc_type= SC_SHADOW,.hi= MSR_GL0 + 0x0,.lo= 0x03}, /* C0000-Fffff split to MC and PCI (sub decode) */ - {.desc_name=MSR_GLIU1_SYSMEM,.desc_type= R_SYSMEM,.hi= MSR_GL0,.lo= 0x0}, /* Catch and fix dynamicly. */ - {.desc_name=MSR_GLIU1_DMM,.desc_type= BM_DMM,.hi= MSR_GL0,.lo= 0x0}, /* Catch and fix dynamicly. */ - {.desc_name=MSR_GLIU1_SMM,.desc_type= BM_SMM,.hi= MSR_GL0,.lo= 0x0}, /* Catch and fix dynamicly. */ + {.desc_name=MSR_GLIU1_SHADOW,.desc_type= SC_SHADOW,.hi= MSR_GL0 + 0x0,.lo= 0x03}, /* C0000-Fffff split to MC and PCI (sub decode) */ + {.desc_name=MSR_GLIU1_SYSMEM,.desc_type= R_SYSMEM,.hi= MSR_GL0,.lo= 0x0}, /* Catch and fix dynamicly. */ + {.desc_name=MSR_GLIU1_DMM,.desc_type= BM_DMM,.hi= MSR_GL0,.lo= 0x0}, /* Catch and fix dynamicly. */ + {.desc_name=MSR_GLIU1_SMM,.desc_type= BM_SMM,.hi= MSR_GL0,.lo= 0x0}, /* Catch and fix dynamicly. */ {.desc_name=GLIU1_GLD_MSR_COH,.desc_type= OTHER,.hi= 0x0,.lo= GL1_GLIU0}, - {.desc_name=MSR_GLIU1_FPU_TRAP,.desc_type= SCIO,.hi= (GL1_GLCP << 29) + 0x0,.lo= 0x033000F0}, /* FooGlue FPU 0xF0 */ + {.desc_name=MSR_GLIU1_FPU_TRAP,.desc_type= SCIO,.hi= (GL1_GLCP << 29) + 0x0,.lo= 0x033000F0}, /* FooGlue FPU 0xF0 */ {.desc_name=GL_END,.desc_type= GL_END,.hi= 0x0,.lo= 0x0}, }; struct gliutable *gliutables[] = {gliu0table, gliu1table, 0}; -struct msrinit { +struct msrinit +{ unsigned long msrnum; msr_t msr; }; @@ -56,15 +58,16 @@ /* MC must stay off in SDR mode. It is turned on in CPUBug??? lotus #77.142 */ {MC_GLD_MSR_PM, {.hi=0x00,.lo=0x0000}}, {GLIU1_GLD_MSR_PM, {.hi=0x00,.lo=0x0005}}, - {VG_GLD_MSR_PM, {.hi=0x00,.lo=0x0000}}, /* lotus #77.163 */ + {VG_GLD_MSR_PM, {.hi=0x00,.lo=0x0000}}, /* lotus #77.163 */ {GP_GLD_MSR_PM, {.hi=0x00,.lo=0x0001}}, {DF_GLD_MSR_PM, {.hi=0x00,.lo=0x0155}}, {GLCP_GLD_MSR_PM, {.hi=0x00,.lo=0x0015}}, {GLPCI_GLD_MSR_PM, {.hi=0x00,.lo=0x0015}}, - {FG_GLD_MSR_PM, {.hi=0x00,.lo=0x0000}}, /* Always on */ + {FG_GLD_MSR_PM, {.hi=0x00,.lo=0x0000}}, /* Always on */ {0xffffffff, {0xffffffff, 0xffffffff}}, }; - /* All On */ + +/* All On */ struct msrinit ClockGatingAllOn[] = { {GLIU0_GLD_MSR_PM, {.hi=0x00,.lo=0x0FFFFFFFF}}, {MC_GLD_MSR_PM, {.hi=0x00,.lo=0x0FFFFFFFF}}, @@ -78,16 +81,16 @@ {0xffffffff, {0xffffffff, 0xffffffff}}, }; - /* Performance */ +/* Performance */ struct msrinit ClockGatingPerformance[] = { - {VG_GLD_MSR_PM, {.hi=0x00,.lo=0x0000}}, /* lotus #77.163*/ + {VG_GLD_MSR_PM, {.hi=0x00,.lo=0x0000}}, /* lotus #77.163 */ {GP_GLD_MSR_PM, {.hi=0x00,.lo=0x0001}}, {DF_GLD_MSR_PM, {.hi=0x00,.lo=0x0155}}, {GLCP_GLD_MSR_PM, {.hi=0x00,.lo=0x0015}}, {0xffffffff, {0xffffffff, 0xffffffff}}, }; - /* SET GeodeLink PRIORITY */ +/* SET GeodeLink PRIORITY */ struct msrinit GeodeLinkPriorityTable [] = { {CPU_GLD_MSR_CONFIG, {.hi=0x00,.lo=0x0220}}, /* CPU Priority. */ {DF_GLD_MSR_MASTER_CONF, {.hi=0x00,.lo=0x0000}}, /* DF Priority. */ @@ -103,8 +106,8 @@ /* do we have dmi or not? assume NO per AMD */ int havedmi = 0; -static void -writeglmsr(struct gliutable *gl){ +static void writeglmsr(struct gliutable *gl) +{ msr_t msr; msr.lo = gl->lo; @@ -116,8 +119,7 @@ printk(BIOS_DEBUG, "%s: AFTER write msr 0x%08lx, val 0x%08x:0x%08x\n", __func__, gl->desc_name, msr.hi, msr.lo); } -static void -ShadowInit(struct gliutable *gl) +static void ShadowInit(struct gliutable *gl) { msr_t msr; @@ -132,14 +134,12 @@ * CLEAN ME UP */ /* yes, this duplicates later code, but it seems that is how they want it done. */ -static void -SysmemInit(struct gliutable *gl) +static void SysmemInit(struct gliutable *gl) { msr_t msr; int sizembytes, sizebytes; - /* - * Figure out how much RAM is in the machine and alocate all to the + /* Figure out how much RAM is in the machine and alocate all to the * system. We will adjust for SMM and DMM now and Frame Buffer later. */ sizembytes = sizeram(); @@ -164,8 +164,8 @@ gl->desc_name, msr.hi, msr.lo); } -static void -DMMGL0Init(struct gliutable *gl) { +static void DMMGL0Init(struct gliutable *gl) +{ msr_t msr; int sizebytes = sizeram()<<20; long offset; @@ -191,8 +191,8 @@ printk(BIOS_DEBUG, "%s: AFTER write msr 0x%08lx, val 0x%08x:0x%08x\n", __func__, gl->desc_name, msr.hi, msr.lo); } -static void -DMMGL1Init(struct gliutable *gl) { +static void DMMGL1Init(struct gliutable *gl) +{ msr_t msr; if (! havedmi) @@ -214,8 +214,8 @@ printk(BIOS_DEBUG, "%s: AFTER write msr 0x%08lx, val 0x%08x:0x%08x\n", __func__, gl->desc_name, msr.hi, msr.lo); } -static void -SMMGL0Init(struct gliutable *gl) { +static void SMMGL0Init(struct gliutable *gl) +{ msr_t msr; int sizebytes = sizeram()<<20; long offset; @@ -242,8 +242,8 @@ printk(BIOS_DEBUG, "%s: AFTER write msr 0x%08lx, val 0x%08x:0x%08x\n", __func__, gl->desc_name, msr.hi, msr.lo); } -static void -SMMGL1Init(struct gliutable *gl) { +static void SMMGL1Init(struct gliutable *gl) +{ msr_t msr; printk(BIOS_DEBUG, "%s:\n", __func__ ); @@ -259,9 +259,8 @@ printk(BIOS_DEBUG, "%s: AFTER write msr 0x%08lx, val 0x%08x:0x%08x\n", __func__, gl->desc_name, msr.hi, msr.lo); } -static void -GLIUInit(struct gliutable *gl){ - +static void GLIUInit(struct gliutable *gl) +{ while (gl->desc_type != GL_END){ switch(gl->desc_type){ default: @@ -295,8 +294,7 @@ } } -/* - * Set up GLPCI settings for reads/write into memory. +/* Set up GLPCI settings for reads/write into memory. * * R0: 0-640KB, * R1: 1MB - Top of System Memory @@ -304,7 +302,8 @@ * R3: Framebuffer? - not set up yet * R4: ?? */ -static void GLPCIInit(void){ +static void GLPCIInit(void) +{ struct gliutable *gl = 0; int i; msr_t msr; @@ -334,7 +333,7 @@ * base of 1M and top of around 256M */ /* we have to create a page-aligned (4KB page) address for base and top - * So we need a high page aligned addresss (pah) and low page aligned address (pal) + * so we need a high page aligned addresss (pah) and low page aligned address (pal) * pah is from msr.hi << 12 | msr.low >> 20. pal is msr.lo << 12 */ printk(BIOS_DEBUG, "GLPCI r1: system msr.lo 0x%08x msr.hi 0x%08x\n", msr.lo, msr.hi); @@ -504,8 +503,7 @@ } } -/* - * Get the GLIU0 shadow register settings. +/* Get the GLIU0 shadow register settings. * * If the setShadow function is used then all shadow descriptors * will stay sync'ed. @@ -517,8 +515,7 @@ return ( ( (uint64_t) msr.hi ) << 32 ) | msr.lo; } -/* - * Set the cache RConf registers for the memory hole. +/* Set the cache RConf registers for the memory hole. * * Keeps all cache shadow descriptors sync'ed. * This is part of the PCI lockup solution. @@ -536,17 +533,17 @@ /* load up D000 settings in edx. */ for (bit = 8; (bit > 4); bit--) { msr.hi <<= 8; - msr.hi |= 1; /* cache disable PCI/Shadow memory */ + msr.hi |= 1; /* cache disable PCI/Shadow memory */ if (shadowByte && (1 << bit)) - msr.hi |= 0x20; /* write serialize PCI memory */ + msr.hi |= 0x20; /* write serialize PCI memory */ } /* load up C000 settings in eax. */ for ( ; bit; bit--) { msr.lo <<= 8; - msr.lo |= 1; /* cache disable PCI/Shadow memory */ + msr.lo |= 1; /* cache disable PCI/Shadow memory */ if (shadowByte && (1 << bit)) - msr.lo |= 0x20; /* write serialize PCI memory */ + msr.lo |= 0x20; /* write serialize PCI memory */ } wrmsr(CPU_RCONF_C0_DF, msr); @@ -556,24 +553,23 @@ /* load up F000 settings in edx. */ for (bit = 8; (bit > 4); bit--) { msr.hi <<= 8; - msr.hi |= 1; /* cache disable PCI/Shadow memory */ + msr.hi |= 1; /* cache disable PCI/Shadow memory */ if (shadowByte && (1 << bit)) - msr.hi |= 0x20; /* write serialize PCI memory */ + msr.hi |= 0x20; /* write serialize PCI memory */ } /* load up E000 settings in eax. */ for ( ; bit; bit--) { msr.lo <<= 8; - msr.lo |= 1; /* cache disable PCI/Shadow memory */ + msr.lo |= 1; /* cache disable PCI/Shadow memory */ if (shadowByte && (1 << bit)) - msr.lo |= 0x20; /* write serialize PCI memory */ + msr.lo |= 0x20; /* write serialize PCI memory */ } wrmsr(CPU_RCONF_E0_FF, msr); } -/* - * Set the GLPCI registers for the memory hole. +/* Set the GLPCI registers for the memory hole. * Keeps all cache shadow descriptors sync'ed. * Entry: EDX:EAX is the shadow settings */ @@ -588,8 +584,7 @@ wrmsr(GLPCI_REN, msr); } -/* - * Set the GLIU SC register settings. Scans descriptor tables for SC_SHADOW. +/* Set the GLIU SC register settings. Scans descriptor tables for SC_SHADOW. * Keeps all shadow descriptors sync'ed. * Entry: EDX:EAX is the shadow settings */ @@ -630,8 +625,7 @@ setShadow(shadowSettings); } -/* - * Set up RCONF_DEFAULT and any other RCONF registers needed. +/* Set up RCONF_DEFAULT and any other RCONF registers needed. * * DEVRC_RCONF_DEFAULT: * ROMRC(63:56) = 04h ; write protect ROMBASE @@ -645,8 +639,7 @@ #define ROMBASE_RCONF_DEFAULT 0xFFFC0000 #define ROMRC_RCONF_DEFAULT 0x25 -static void -RCONFInit(void) +static void RCONFInit(void) { struct gliutable *gl = 0; int i;

1 0

[PATCH 4/6] Geode GX2 cleanup patch
by Nils 26 Dec '10

26 Dec '10

Remove wrong GX2 processor IIOC mode setting on CS5535 southbridge code and fix CIS mode comments. Signed-off-by: Nils Jacobs <njacobs8(a)hetnet.nl> Thanks, Nils.

2 1

Restarting the Nokia-IP530 project with I440BX, failed to start
by Marc Bertens 25 Dec '10

25 Dec '10

hi all, i restarted the my project with the nokia IP530, and checked out the newest release of coreboot and i got only to the initstage of the i440bx. I changed my Kconfig and added SDRAMPWR_4DIMM for safety, but not change in the startup it stays the same. Anyone any ideas ? >> First boot with 4 DIMMs, not the same models, but the SAME size. coreboot-4.0-r6206M-ip530 Sat Dec 25 10:54:12 CET 2010 starting... DIMM 0: 50 00: 80 08 04 0c 0a 02 40 00 01 75 54 00 80 08 00 01 10: 8f 04 06 01 01 00 0e a0 60 00 00 14 0f 14 2d 20 20: 15 08 15 08 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 12 b0 40: 10 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 64 ff 80: 53 45 4d 49 43 4f 4e 00 00 00 00 00 00 00 ff ff 90: 44 45 56 49 43 45 53 ff ff ff ff ff ff ff ff ff a0: 53 49 4e 47 41 50 4f 52 45 ff ff ff ff ff ff ff b0: 36 35 2d 32 38 31 33 37 35 30 ff ff ff ff ff ff c0: 30 31 30 39 ff ff ff 54 54 ff ff ff ff ff ff ff d0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff e0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff f0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff DIMM 1: 51 00: 80 08 04 0c 0a 02 40 00 01 75 54 00 80 08 00 01 10: 8f 04 04 01 01 00 0e 00 00 00 00 14 0f 14 2d 20 20: 15 08 15 08 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 12 ae 40: 7f 4f 00 00 00 00 00 00 00 00 00 00 00 00 00 00 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 64 fd 80: 41 48 50 44 36 30 39 38 41 20 20 20 20 18 18 73 90: 29 4e 53 44 20 42 00 b6 00 00 f6 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 DIMM 2: 52 00: 80 08 04 0c 0a 02 40 00 01 75 54 00 80 08 00 01 10: 8f 04 06 01 01 00 0e 75 54 00 00 0f 0f 0f 2d 20 20: 15 08 15 08 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 12 6f 40: ad ff ff ff ff ff ff ff 02 37 31 56 33 32 36 33 50: 35 48 43 54 38 50 2d 4b 20 20 20 41 41 32 66 80 60: 85 01 ea 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 64 ff 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 DIMM 3: 53 00: 80 08 04 0c 0a 02 40 00 01 75 54 00 80 08 00 01 10: 8f 04 06 01 01 00 0e 75 54 00 00 0f 0f 0f 2d 20 20: 15 08 15 08 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 12 6f 40: ad ff ff ff ff ff ff ff 02 37 31 56 33 32 36 33 50: 35 48 43 54 38 50 2d 4b 20 20 20 41 41 32 66 80 60: 85 01 bd 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 64 ff 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 Northbridge prior to SDRAM init: PCI: 00:00.00 00: 86 80 90 71 06 00 10 22 03 00 00 06 00 00 00 00 10: 08 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 a0 00 00 00 00 00 00 00 00 00 00 00 40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 50: 04 00 00 00 00 00 00 00 03 00 00 00 00 00 00 00 60: 01 01 01 01 01 01 01 01 00 00 00 00 00 00 00 00 70: 00 1f 02 38 00 00 00 00 00 00 00 38 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 80 00 00 00 04 61 00 00 00 05 00 00 00 00 00 00 a0: 02 00 10 00 03 02 00 1f 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 18 0c 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 0c 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 f8 00 00 20 0f 00 00 00 00 00 00 Found DIMM in slot 0 Found DIMM in slot 1 Found DIMM in slot 2 Found DIMM in slot 3 PGPOL[BPR] has been set to 0xff RPS has been set to 0xaaaa NBXECC[31:24] has been set to 0xff DRAMC has been set to 0x08 RAM Enable 1: Apply NOP RAM Enable 2: Precharge all RAM Enable 3: CBR RAM Enable 4: Mode register set RAM Enable 5: Normal operation RAM Enable 6: Enable refresh Enabling refresh (DRAMC = 0x09) for DIMM 00 Enabling refresh (DRAMC = 0x09) for DIMM 01 Enabling refresh (DRAMC = 0x09) for DIMM 02 Enabling refresh (DRAMC = 0x09) for DIMM 03 Northbridge following SDRAM init: PCI: 00:00.00 00: 86 80 90 71 06 00 10 22 03 00 00 06 00 00 00 00 10: 08 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 a0 00 00 00 00 00 00 00 00 00 00 00 40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 50: 0c 80 00 ff 00 00 00 09 03 30 33 33 33 33 33 33 60: 10 20 30 40 50 60 70 80 00 b0 2a 00 a0 aa 00 00 70: 00 1f 02 38 aa aa 00 00 00 ff 10 38 10 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 80 00 00 00 04 61 00 00 00 05 00 00 00 00 00 00 a0: 02 00 10 00 03 02 00 1f 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 18 0c fe ff 7f 00 00 00 d0: 00 00 00 00 00 00 00 00 0c 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 f8 00 00 20 0f 00 00 00 00 00 00 >> Second boot sequence, with all the same type of DIMMs, but single sided so only one side is used by coreboot (128MB) coreboot-4.0-r6206M-ip530 Sat Dec 25 10:54:12 CET 2010 starting... DIMM 0: 50 00: 80 08 04 0d 0a 01 40 00 01 75 54 00 82 08 00 01 10: 8f 04 06 01 01 00 0e a0 60 00 00 14 0f 14 2d 40 20: 15 08 15 08 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 12 d2 40: 7f 98 00 00 00 00 00 00 04 20 33 32 4d 58 36 34 50: 50 43 31 33 33 43 4c 33 31 36 38 50 20 03 1d 0a 60: 48 49 5f ff ff ff ff ff ff ff ff ff ff ff ff ff 70: ff ff ff ff ff ff ff ff ff ff ff ff ff ff 64 a7 80: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff 90: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff a0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff b0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff c0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff d0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff e0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff f0: 39 39 30 35 31 32 31 2d 30 30 37 2e 41 30 32 00 DIMM 1: 51 00: 80 08 04 0d 0a 01 40 00 01 75 54 00 82 08 00 01 10: 8f 04 06 01 01 00 0e a0 60 00 00 14 0f 14 2d 40 20: 15 08 15 08 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 12 d2 40: 7f 98 00 00 00 00 00 00 04 20 33 32 4d 58 36 34 50: 50 43 31 33 33 43 4c 33 31 36 38 50 20 03 1d 0a 60: 48 aa 9d ff ff ff ff ff ff ff ff ff ff ff ff ff 70: ff ff ff ff ff ff ff ff ff ff ff ff ff ff 64 a7 80: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff 90: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff a0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff b0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff c0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff d0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff e0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff f0: 39 39 30 35 31 32 31 2d 30 30 37 2e 41 30 32 00 DIMM 2: 52 00: 80 08 04 0d 0a 01 40 00 01 75 54 00 82 08 00 01 10: 8f 04 06 01 01 00 0e a0 60 00 00 14 0f 14 2d 40 20: 15 08 15 08 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 12 d2 40: 7f 98 00 00 00 00 00 00 04 20 33 32 4d 58 36 34 50: 50 43 31 33 33 43 4c 33 31 36 38 50 20 03 1d 04 60: 48 8b 5f ff ff ff ff ff ff ff ff ff ff ff ff ff 70: ff ff ff ff ff ff ff ff ff ff ff ff ff ff 64 a7 80: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff 90: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff a0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff b0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff c0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff d0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff e0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff f0: 39 39 30 35 31 32 31 2d 30 30 37 2e 41 30 32 00 DIMM 3: 53 00: 80 08 04 0d 0a 01 40 00 01 75 54 00 82 08 00 01 10: 8f 04 06 01 01 00 0e a0 60 00 00 14 0f 14 2d 40 20: 15 08 15 08 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 12 d2 40: 7f 98 00 00 00 00 00 00 04 20 33 32 4d 58 36 34 50: 50 43 31 33 33 43 4c 33 31 36 38 50 20 03 1d 17 60: 48 30 5f ff ff ff ff ff ff ff ff ff ff ff ff ff 70: ff ff ff ff ff ff ff ff ff ff ff ff ff ff 64 a7 80: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff 90: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff a0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff b0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff c0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff d0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff e0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff f0: 39 39 30 35 31 32 31 2d 30 30 37 2e 41 30 32 00 Northbridge prior to SDRAM init: PCI: 00:00.00 00: 86 80 90 71 06 00 10 22 03 00 00 06 00 00 00 00 10: 08 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 a0 00 00 00 00 00 00 00 00 00 00 00 40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 50: 04 00 00 00 00 00 00 00 03 00 00 00 00 00 00 00 60: 01 01 01 01 01 01 01 01 00 00 00 00 00 00 00 00 70: 00 1f 02 38 00 00 00 00 00 00 00 38 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 80 00 00 00 04 61 00 00 00 05 00 00 00 00 00 00 a0: 02 00 10 00 03 02 00 1f 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 18 0c 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 0c 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 f8 00 00 20 0f 00 00 00 00 00 00 Found DIMM in slot 0 Side1 was 256MB but only 128MB will be used. Found DIMM in slot 1 Side1 was 256MB but only 128MB will be used. Found DIMM in slot 2 Side1 was 256MB but only 128MB will be used. Found DIMM in slot 3 Side1 was 256MB but only 128MB will be used. PGPOL[BPR] has been set to 0x55 RPS has been set to 0x2222 NBXECC[31:24] has been set to 0xff DRAMC has been set to 0x08 RAM Enable 1: Apply NOP RAM Enable 2: Precharge all RAM Enable 3: CBR RAM Enable 4: Mode register set RAM Enable 5: Normal operation RAM Enable 6: Enable refresh Enabling refresh (DRAMC = 0x0d) for DIMM 00 Enabling refresh (DRAMC = 0x0d) for DIMM 01 Enabling refresh (DRAMC = 0x0d) for DIMM 02 Enabling refresh (DRAMC = 0x0d) for DIMM 03 Northbridge following SDRAM init: PCI: 00:00.00 00: 86 80 90 71 06 00 10 22 03 00 00 06 00 00 00 00 10: 08 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 a0 00 00 00 00 00 00 00 00 00 00 00 40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 50: 0c 80 00 ff 00 00 00 0d 03 30 33 33 33 33 33 33 60: 10 10 20 20 30 30 40 40 00 ec 3f 00 a0 fa 00 00 70: 00 1f 02 38 22 22 00 00 00 55 10 38 10 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 80 00 00 00 04 61 00 00 00 05 00 00 00 00 00 00 a0: 02 00 10 00 03 02 00 1f 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 18 0c 84 ff 1f 00 00 00 d0: 00 00 00 00 00 00 00 00 0c 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 f8 00 00 20 0f 00 00 00 00 00 00

2 1

[commit] r6207 - trunk/src/mainboard/nokia/ip530
by repository service 25 Dec '10

25 Dec '10

Author: uwe Date: Sat Dec 25 23:54:41 2010 New Revision: 6207 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6207 Log: Nokia IP530: Add missing "select SDRAMPWR_4DIMM". This is needed for all Intel 440BX boards with 4 DIMM slots (such as this one). Thanks Marc Bertens <mbertens(a)xs4all.nl> for bringing up the issue and for the success report for this fix on IRC. Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Modified: trunk/src/mainboard/nokia/ip530/Kconfig Modified: trunk/src/mainboard/nokia/ip530/Kconfig ============================================================================== --- trunk/src/mainboard/nokia/ip530/Kconfig Thu Dec 23 18:12:03 2010 (r6206) +++ trunk/src/mainboard/nokia/ip530/Kconfig Sat Dec 25 23:54:41 2010 (r6207) @@ -31,6 +31,7 @@ select PIRQ_ROUTE select HAVE_PIRQ_TABLE select UDELAY_TSC + select SDRAMPWR_4DIMM config MAINBOARD_DIR string

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CONFIG_DEBUG_RAM_SETUP breaks build on i82810, i440bx and maybe more
by Keith Hui 23 Dec '10

23 Dec '10

As title. Log from a locally modified abuild attached. I think this is something we did some time ago with simplifying debugging facility - trying to use printk() everywhere. I have seen i440bx build break similarly. You don't see it in this log because I am developing a fix for it. (Working mainly on a P2B-LS, I'm directly affected :-) ) i440lx uses a similar debugging facility and theoretically is also broken, but apparently there is no 440LX mainboards in the tree. abuild is modified as below, just to get CONFIG_DEBUG_RAM_SETUP set when doing all-targets abuild: --8<------ Index: util/abuild/abuild =================================================================== --- util/abuild/abuild (revision 6204) +++ util/abuild/abuild (working copy) @@ -58,6 +58,9 @@ # use ccache ccache=false +# RAM debug messages +debugramsetup=true + # stackprotect mode enabled by -ns option. stackprotect=false @@ -197,6 +200,11 @@ echo "CONFIG_CCACHE=y" >> ${build_dir}/config.build fi + if [ "$debugramsetup" = "true" ]; then + printf "(debugramsetup enabled) " + echo "CONFIG_DEBUG_RAM_SETUP=y" >> ${build_dir}/config.build + fi + if [ "$scanbuild" = "true" ]; then printf "(scan-build enabled) " echo "CONFIG_SCANBUILD_ENABLE=y" >> ${build_dir}/config.build --8<------ Above is not meant to be committed, but just in case, it is Signed-off-by: Keith Hui <buurin(a)gmail.com>

4 6

[commit] r6206 - trunk/src/northbridge/intel/i440bx
by repository service 23 Dec '10

23 Dec '10

Author: uwe Date: Thu Dec 23 18:12:03 2010 New Revision: 6206 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6206 Log: Fix build with CONFIG_DEBUG_RAM_SETUP on Intel 440BX, use printk(). It's a good thing to use printk() instead of print_*() anyway on 440BX (and other chipsets which have been converted to CAR). Build tested and boot-tested on ASUS P2B-LS. Signed-off-by: Keith Hui <buurin(a)gmail.com> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Modified: trunk/src/northbridge/intel/i440bx/debug.c trunk/src/northbridge/intel/i440bx/raminit.c Modified: trunk/src/northbridge/intel/i440bx/debug.c ============================================================================== --- trunk/src/northbridge/intel/i440bx/debug.c Tue Dec 21 00:40:23 2010 (r6205) +++ trunk/src/northbridge/intel/i440bx/debug.c Thu Dec 23 18:12:03 2010 (r6206) @@ -1,66 +1,34 @@ #include "raminit.h" +#include <spd.h> +#include <console/console.h> void dump_spd_registers(void) { #if CONFIG_DEBUG_RAM_SETUP int i; - print_debug("\n"); + printk(BIOS_DEBUG, "\n"); for(i = 0; i < DIMM_SOCKETS; i++) { unsigned device; device = DIMM0 + i; if (device) { int j; - print_debug("dimm: "); - print_debug_hex8(i); - print_debug(".0: "); - print_debug_hex8(device); + printk(BIOS_DEBUG, "DIMM %d: %02x", i, device); for(j = 0; j < 256; j++) { int status; unsigned char byte; if ((j & 0xf) == 0) { - print_debug("\n"); - print_debug_hex8(j); - print_debug(": "); + printk(BIOS_DEBUG, "\n%02x: ", j); } status = spd_read_byte(device, j); if (status < 0) { - print_debug("bad device\n"); + printk(BIOS_DEBUG, "bad device\n"); break; } byte = status & 0xff; - print_debug_hex8(byte); - print_debug_char(' '); + printk(BIOS_DEBUG, "%02x ", byte); } - print_debug("\n"); + printk(BIOS_DEBUG, "\n"); } } #endif } - -#if 0 -void dump_spd_registers(void) -{ - unsigned device; - device = SMBUS_MEM_DEVICE_START; - printk(BIOS_DEBUG, "\n"); - while(device <= SMBUS_MEM_DEVICE_END) { - int status = 0; - int i; - printk(BIOS_DEBUG, "dimm %02x", device); - for(i = 0; (i < 256) && (status == 0); i++) { - unsigned char byte; - if ((i % 20) == 0) { - printk(BIOS_DEBUG, "\n%3d: ", i); - } - status = smbus_read_byte(device, i, &byte); - if (status != 0) { - printk(BIOS_DEBUG, "bad device\n"); - continue; - } - printk(BIOS_DEBUG, "%02x ", byte); - } - device += SMBUS_MEM_DEVICE_INC; - printk(BIOS_DEBUG, "\n"); - } -} -#endif Modified: trunk/src/northbridge/intel/i440bx/raminit.c ============================================================================== --- trunk/src/northbridge/intel/i440bx/raminit.c Tue Dec 21 00:40:23 2010 (r6205) +++ trunk/src/northbridge/intel/i440bx/raminit.c Thu Dec 23 18:12:03 2010 (r6206) @@ -38,13 +38,14 @@ /* Debugging macros. */ #if CONFIG_DEBUG_RAM_SETUP -#define PRINT_DEBUG(x) print_debug(x) -#define PRINT_DEBUG_HEX8(x) print_debug_hex8(x) -#define PRINT_DEBUG_HEX16(x) print_debug_hex16(x) -#define PRINT_DEBUG_HEX32(x) print_debug_hex32(x) +#include "lib/debug.c" +#define PRINT_DEBUG(x...) printk(BIOS_DEBUG, x) +#define PRINT_DEBUG_HEX8(x) PRINT_DEBUG("%02x", x) +#define PRINT_DEBUG_HEX16(x) PRINT_DEBUG("%04x", x) +#define PRINT_DEBUG_HEX32(x) PRINT_DEBUG("%08x", x) #define DUMPNORTH() dump_pci_device(NB) #else -#define PRINT_DEBUG(x) +#define PRINT_DEBUG(x...) #define PRINT_DEBUG_HEX8(x) #define PRINT_DEBUG_HEX16(x) #define PRINT_DEBUG_HEX32(x) @@ -621,11 +622,7 @@ continue; reg = (reg & 0xf8) | refresh_rate_map[(value & 0x7f)]; - PRINT_DEBUG(" Enabling refresh (DRAMC = 0x"); - PRINT_DEBUG_HEX8(reg); - PRINT_DEBUG(") for DIMM "); - PRINT_DEBUG_HEX8(i); - PRINT_DEBUG("\n"); + PRINT_DEBUG(" Enabling refresh (DRAMC = 0x%02x) for DIMM %02x\n", reg, i); } pci_write_config8(NB, DRAMC, reg); @@ -662,8 +659,8 @@ } struct dimm_size { - unsigned long side1; - unsigned long side2; + u32 side1; + u32 side2; }; static struct dimm_size spd_get_dimm_size(unsigned int device) @@ -718,15 +715,13 @@ * modules by setting them to a supported size. */ if(sz.side1 > 128) { - PRINT_DEBUG("Side1 was 0x"); - PRINT_DEBUG_HEX16(sz.side1); - PRINT_DEBUG(" but only 128MB will be used.\n"); + PRINT_DEBUG("Side1 was %dMB but only 128MB will be used.\n", + sz.side1); sz.side1 = 128; if(sz.side2 > 128) { - PRINT_DEBUG("Side2 was 0x"); - PRINT_DEBUG_HEX16(sz.side2); - PRINT_DEBUG(" but only 128MB will be used.\n"); + PRINT_DEBUG("Side2 was %dMB but only 128MB will be used.\n", + sz.side2); sz.side2 = 128; } } @@ -759,15 +754,12 @@ if (value == SPD_MEMORY_TYPE_EDO || value == SPD_MEMORY_TYPE_SDRAM) { - PRINT_DEBUG("Found "); if (value == SPD_MEMORY_TYPE_EDO) { edosd |= 0x02; } else if (value == SPD_MEMORY_TYPE_SDRAM) { edosd |= 0x04; } - PRINT_DEBUG("DIMM in slot "); - PRINT_DEBUG_HEX8(i); - PRINT_DEBUG("\n"); + PRINT_DEBUG("Found DIMM in slot %d\n", i); if (edosd == 0x06) { print_err("Mixing EDO/SDRAM unsupported!\n"); @@ -925,21 +917,15 @@ /* Set paging policy register. */ pci_write_config8(NB, PGPOL + 1, bpr); - PRINT_DEBUG("PGPOL[BPR] has been set to 0x"); - PRINT_DEBUG_HEX8(bpr); - PRINT_DEBUG("\n"); + PRINT_DEBUG("PGPOL[BPR] has been set to 0x%02x\n", bpr); /* Set DRAM row page size register. */ pci_write_config16(NB, RPS, rps); - PRINT_DEBUG("RPS has been set to 0x"); - PRINT_DEBUG_HEX16(rps); - PRINT_DEBUG("\n"); + PRINT_DEBUG("RPS has been set to 0x%04x\n", rps); /* ### ECC */ pci_write_config8(NB, NBXCFG + 3, nbxecc); - PRINT_DEBUG("NBXECC[31:24] has been set to 0x"); - PRINT_DEBUG_HEX8(nbxecc); - PRINT_DEBUG("\n"); + PRINT_DEBUG("NBXECC[31:24] has been set to 0x%02x\n", nbxecc); /* Set DRAMC[4:3] to proper memory type (EDO/SDRAM). * TODO: Registered SDRAM support. @@ -956,9 +942,7 @@ value = pci_read_config8(NB, DRAMC) & 0xe7; value |= edosd; pci_write_config8(NB, DRAMC, value); - PRINT_DEBUG("DRAMC has been set to 0x"); - PRINT_DEBUG_HEX8(value); - PRINT_DEBUG("\n"); + PRINT_DEBUG("DRAMC has been set to 0x%02x\n", value); } void sdram_set_spd_registers(void)

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coreboot December 2010