coreboot December 2010

coreboot@coreboot.org

52 participants
262 discussions

build service results for r6215
by repository service 27 Dec '10

27 Dec '10

Dear coreboot readers! This is the automatic build system of coreboot. The developer "stepan" checked in revision 6215 to the coreboot repository. This caused the following changes: Change Log: Fix most CONFIG_DEBUG_RAM_SETUP issues. The intel/xe7501devkit is still broken, I think the (romcc) image is too big to fit in the bootblock if CONFIG_DEBUG_RAM_SETUP is enabled. It would make sense to convert all CPU_INTEL_SOCKET_MPGA604 to CAR, but I have no hardware to test. Signed-off-by: Stefan Reinauer <stepan(a)coreboot.org> Acked-by: Stefan Reinauer <stepan(a)coreboot.org> Build Log: Compilation of a-trend:atc-6220 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6215&device=atc-6220&vendo… Compilation of a-trend:atc-6240 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6215&device=atc-6240&vendo… Compilation of abit:be6-ii_v2_0 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6215&device=be6-ii_v2_0&ve… Compilation of asus:mew-am has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6215&device=mew-am&vendor=… Compilation of asus:mew-vm has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6215&device=mew-vm&vendor=… Compilation of asus:p2b has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6215&device=p2b&vendor=asu… Compilation of asus:p2b-d has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6215&device=p2b-d&vendor=a… Compilation of asus:p2b-ds has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6215&device=p2b-ds&vendor=… Compilation of asus:p2b-f has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6215&device=p2b-f&vendor=a… Compilation of asus:p2b-ls has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6215&device=p2b-ls&vendor=… Compilation of asus:p3b-f has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6215&device=p3b-f&vendor=a… Compilation of azza:pt-6ibd has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6215&device=pt-6ibd&vendor… Compilation of biostar:m6tba has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6215&device=m6tba&vendor=b… Compilation of compaq:deskpro_en_sff_p600 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6215&device=deskpro_en_sff… Compilation of ecs:p6iwp-fe has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6215&device=p6iwp-fe&vendo… Compilation of gigabyte:ga-6bxc has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6215&device=ga-6bxc&vendor… Compilation of gigabyte:ga-6bxe has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6215&device=ga-6bxe&vendor… Compilation of hp:e_vectra_p2706t has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6215&device=e_vectra_p2706… Compilation of intel:d810e2cb has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6215&device=d810e2cb&vendo… Compilation of mitac:6513wu has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6215&device=6513wu&vendor=… Compilation of msi:ms6119 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6215&device=ms6119&vendor=… Compilation of msi:ms6147 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6215&device=ms6147&vendor=… Compilation of msi:ms6156 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6215&device=ms6156&vendor=… Compilation of msi:ms6178 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6215&device=ms6178&vendor=… Compilation of nec:powermate2000 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6215&device=powermate2000&… Compilation of nokia:ip530 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6215&device=ip530&vendor=n… Compilation of soyo:sy-6ba-plus-iii has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6215&device=sy-6ba-plus-ii… Compilation of tyan:s1846 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6215&device=s1846&vendor=t… If something broke during this checkin please be a pain in stepan's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

1 0

[commit] r6215 - in trunk/src: mainboard/asus/p2b-d mainboard/asus/p2b-ls mainboard/gigabyte/ga-6bxe northbridge/intel/e7501 northbridge/intel/i440bx northbridge/intel/i82810 northbridge/intel/i945...
by repository service 27 Dec '10

27 Dec '10

Author: stepan Date: Mon Dec 27 12:34:57 2010 New Revision: 6215 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6215 Log: Fix most CONFIG_DEBUG_RAM_SETUP issues. The intel/xe7501devkit is still broken, I think the (romcc) image is too big to fit in the bootblock if CONFIG_DEBUG_RAM_SETUP is enabled. It would make sense to convert all CPU_INTEL_SOCKET_MPGA604 to CAR, but I have no hardware to test. Signed-off-by: Stefan Reinauer <stepan(a)coreboot.org> Acked-by: Stefan Reinauer <stepan(a)coreboot.org> Modified: trunk/src/mainboard/asus/p2b-d/romstage.c trunk/src/mainboard/asus/p2b-ls/romstage.c trunk/src/mainboard/gigabyte/ga-6bxe/romstage.c trunk/src/northbridge/intel/e7501/raminit.c trunk/src/northbridge/intel/i440bx/debug.c trunk/src/northbridge/intel/i440bx/raminit.c trunk/src/northbridge/intel/i440bx/raminit.h trunk/src/northbridge/intel/i82810/debug.c trunk/src/northbridge/intel/i82810/raminit.c trunk/src/northbridge/intel/i82810/raminit.h trunk/src/northbridge/intel/i945/raminit.c trunk/src/northbridge/intel/i945/raminit.h trunk/src/northbridge/via/vx800/dram_util.c Modified: trunk/src/mainboard/asus/p2b-d/romstage.c ============================================================================== --- trunk/src/mainboard/asus/p2b-d/romstage.c Mon Dec 27 09:21:23 2010 (r6214) +++ trunk/src/mainboard/asus/p2b-d/romstage.c Mon Dec 27 12:34:57 2010 (r6215) @@ -28,7 +28,6 @@ #include <console/console.h> #include "southbridge/intel/i82371eb/i82371eb.h" #include "northbridge/intel/i440bx/raminit.h" -#include "lib/debug.c" #include "pc80/udelay_io.c" #include "lib/delay.c" #include "cpu/x86/bist.h" Modified: trunk/src/mainboard/asus/p2b-ls/romstage.c ============================================================================== --- trunk/src/mainboard/asus/p2b-ls/romstage.c Mon Dec 27 09:21:23 2010 (r6214) +++ trunk/src/mainboard/asus/p2b-ls/romstage.c Mon Dec 27 12:34:57 2010 (r6215) @@ -28,7 +28,6 @@ #include <console/console.h> #include "southbridge/intel/i82371eb/i82371eb.h" #include "northbridge/intel/i440bx/raminit.h" -#include "lib/debug.c" #include "pc80/udelay_io.c" #include "lib/delay.c" #include "cpu/x86/bist.h" Modified: trunk/src/mainboard/gigabyte/ga-6bxe/romstage.c ============================================================================== --- trunk/src/mainboard/gigabyte/ga-6bxe/romstage.c Mon Dec 27 09:21:23 2010 (r6214) +++ trunk/src/mainboard/gigabyte/ga-6bxe/romstage.c Mon Dec 27 12:34:57 2010 (r6215) @@ -28,7 +28,6 @@ #include <console/console.h> #include "southbridge/intel/i82371eb/i82371eb.h" #include "northbridge/intel/i440bx/raminit.h" -#include "lib/debug.c" #include "pc80/udelay_io.c" #include "lib/delay.c" #include "cpu/x86/bist.h" Modified: trunk/src/northbridge/intel/e7501/raminit.c ============================================================================== --- trunk/src/northbridge/intel/e7501/raminit.c Mon Dec 27 09:21:23 2010 (r6214) +++ trunk/src/northbridge/intel/e7501/raminit.c Mon Dec 27 12:34:57 2010 (r6215) @@ -1044,9 +1044,9 @@ sz = spd_get_dimm_size(dimm_socket_address); RAM_DEBUG_MESSAGE("dimm size ="); - RAM_DEBUG_HEX32(sz.side1); + RAM_DEBUG_HEX32((u32)sz.side1); RAM_DEBUG_MESSAGE(" "); - RAM_DEBUG_HEX32(sz.side2); + RAM_DEBUG_HEX32((u32)sz.side2); RAM_DEBUG_MESSAGE("\n"); if (sz.side1 == 0) Modified: trunk/src/northbridge/intel/i440bx/debug.c ============================================================================== --- trunk/src/northbridge/intel/i440bx/debug.c Mon Dec 27 09:21:23 2010 (r6214) +++ trunk/src/northbridge/intel/i440bx/debug.c Mon Dec 27 12:34:57 2010 (r6215) @@ -1,10 +1,14 @@ +#include <console/console.h> +#include <arch/io.h> +#include <arch/romcc_io.h> +#include <spd.h> #include "raminit.h" #include <spd.h> #include <console/console.h> +#if CONFIG_DEBUG_RAM_SETUP void dump_spd_registers(void) { -#if CONFIG_DEBUG_RAM_SETUP int i; printk(BIOS_DEBUG, "\n"); for(i = 0; i < DIMM_SOCKETS; i++) { @@ -30,5 +34,36 @@ printk(BIOS_DEBUG, "\n"); } } -#endif } + +static void print_debug_pci_dev(unsigned dev) +{ + print_debug("PCI: "); + print_debug_hex8((dev >> 16) & 0xff); + print_debug_char(':'); + print_debug_hex8((dev >> 11) & 0x1f); + print_debug_char('.'); + print_debug_hex8((dev >> 8) & 7); +} + +void dump_pci_device(unsigned dev) +{ + int i; + print_debug_pci_dev(dev); + print_debug("\n"); + + for (i = 0; i <= 255; i++) { + unsigned char val; + if ((i & 0x0f) == 0) { + print_debug_hex8(i); + print_debug_char(':'); + } + val = pci_read_config8(dev, i); + print_debug_char(' '); + print_debug_hex8(val); + if ((i & 0x0f) == 0x0f) { + print_debug("\n"); + } + } +} +#endif Modified: trunk/src/northbridge/intel/i440bx/raminit.c ============================================================================== --- trunk/src/northbridge/intel/i440bx/raminit.c Mon Dec 27 09:21:23 2010 (r6214) +++ trunk/src/northbridge/intel/i440bx/raminit.c Mon Dec 27 12:34:57 2010 (r6215) @@ -38,11 +38,10 @@ /* Debugging macros. */ #if CONFIG_DEBUG_RAM_SETUP -#include "lib/debug.c" #define PRINT_DEBUG(x...) printk(BIOS_DEBUG, x) -#define PRINT_DEBUG_HEX8(x) PRINT_DEBUG("%02x", x) -#define PRINT_DEBUG_HEX16(x) PRINT_DEBUG("%04x", x) -#define PRINT_DEBUG_HEX32(x) PRINT_DEBUG("%08x", x) +#define PRINT_DEBUG_HEX8(x) printk(BIOS_DEBUG, "%02x", x) +#define PRINT_DEBUG_HEX16(x) printk(BIOS_DEBUG, "%04x", x) +#define PRINT_DEBUG_HEX32(x) printk(BIOS_DEBUG, "%08x", x) #define DUMPNORTH() dump_pci_device(NB) #else #define PRINT_DEBUG(x...) Modified: trunk/src/northbridge/intel/i440bx/raminit.h ============================================================================== --- trunk/src/northbridge/intel/i440bx/raminit.h Mon Dec 27 09:21:23 2010 (r6214) +++ trunk/src/northbridge/intel/i440bx/raminit.h Mon Dec 27 12:34:57 2010 (r6215) @@ -29,6 +29,8 @@ void sdram_set_registers(void); void sdram_set_spd_registers(void); void sdram_enable(void); -void dump_spd_registers(void); +/* Debug */ +void dump_spd_registers(void); +void dump_pci_device(unsigned dev); #endif /* RAMINIT_H */ Modified: trunk/src/northbridge/intel/i82810/debug.c ============================================================================== --- trunk/src/northbridge/intel/i82810/debug.c Mon Dec 27 09:21:23 2010 (r6214) +++ trunk/src/northbridge/intel/i82810/debug.c Mon Dec 27 12:34:57 2010 (r6215) @@ -1,8 +1,13 @@ +#include <console/console.h> +#include <arch/io.h> +#include <arch/romcc_io.h> +#include <spd.h> +#include "i82810.h" #include "raminit.h" +#if CONFIG_DEBUG_RAM_SETUP void dump_spd_registers(void) { -#if CONFIG_DEBUG_RAM_SETUP int i; print_debug("\n"); for(i = 0; i < DIMM_SOCKETS; i++) { @@ -34,5 +39,36 @@ print_debug("\n"); } } -#endif } + +static void print_debug_pci_dev(unsigned dev) +{ + print_debug("PCI: "); + print_debug_hex8((dev >> 16) & 0xff); + print_debug_char(':'); + print_debug_hex8((dev >> 11) & 0x1f); + print_debug_char('.'); + print_debug_hex8((dev >> 8) & 7); +} + +void dump_pci_device(unsigned dev) +{ + int i; + print_debug_pci_dev(dev); + print_debug("\n"); + + for (i = 0; i <= 255; i++) { + unsigned char val; + if ((i & 0x0f) == 0) { + print_debug_hex8(i); + print_debug_char(':'); + } + val = pci_read_config8(dev, i); + print_debug_char(' '); + print_debug_hex8(val); + if ((i & 0x0f) == 0x0f) { + print_debug("\n"); + } + } +} +#endif Modified: trunk/src/northbridge/intel/i82810/raminit.c ============================================================================== --- trunk/src/northbridge/intel/i82810/raminit.c Mon Dec 27 09:21:23 2010 (r6214) +++ trunk/src/northbridge/intel/i82810/raminit.c Mon Dec 27 12:34:57 2010 (r6215) @@ -35,17 +35,12 @@ -----------------------------------------------------------------------------*/ /* Debugging macros. */ -#define HAVE_ENOUGH_REGISTERS 0 /* Don't have enough registers to compile all - * debugging code with ROMCC - */ #if CONFIG_DEBUG_RAM_SETUP -#define PRINT_DEBUG(x) print_debug(x) -#define PRINT_DEBUG_HEX8(x) print_debug_hex8(x) -#define PRINT_DEBUG_HEX16(x) print_debug_hex16(x) -#define PRINT_DEBUG_HEX32(x) print_debug_hex32(x) -// no dump_pci_device in src/northbridge/intel/i82810/ -// #define DUMPNORTH() dump_pci_device(PCI_DEV(0, 0, 0)) -#define DUMPNORTH() +#define PRINT_DEBUG(x...) printk(BIOS_DEBUG, x) +#define PRINT_DEBUG_HEX8(x) printk(BIOS_DEBUG, "%02x", x) +#define PRINT_DEBUG_HEX16(x) printk(BIOS_DEBUG, "%04x", x) +#define PRINT_DEBUG_HEX32(x) printk(BIOS_DEBUG, "%08x", x) +#define DUMPNORTH() dump_pci_device(PCI_DEV(0, 0, 0)) #else #define PRINT_DEBUG(x) #define PRINT_DEBUG_HEX8(x) @@ -209,27 +204,14 @@ dimm_size = translate_i82810_to_mb[drp]; if (dimm_size) { addr = (dimm_start * 1024 * 1024) + addr_offset; -#if HAVE_ENOUGH_REGISTERS - PRINT_DEBUG(" Sending RAM command 0x"); - PRINT_DEBUG_HEX8(reg8); - PRINT_DEBUG(" to 0x"); - PRINT_DEBUG_HEX32(addr); - PRINT_DEBUG("\n"); -#endif - + PRINT_DEBUG(" Sending RAM command 0x%02x to 0x%08x\n", reg8, addr); read32(addr); } dimm_bank = translate_i82810_to_bank[drp]; if (dimm_bank) { addr = ((dimm_start + dimm_bank) * 1024 * 1024) + addr_offset; -#if HAVE_ENOUGH_REGISTERS - PRINT_DEBUG(" Sending RAM command 0x"); - PRINT_DEBUG_HEX8(reg8); - PRINT_DEBUG(" to 0x"); - PRINT_DEBUG_HEX32(addr); - PRINT_DEBUG("\n"); -#endif + PRINT_DEBUG(" Sending RAM command 0x%02x to 0x%08x\n", reg8, addr); read32(addr); } @@ -256,16 +238,11 @@ for (i = 0; i < DIMM_SOCKETS; i++) { /* First check if a DIMM is actually present. */ if (smbus_read_byte(DIMM0 + i, 2) == 4) { - print_debug("Found DIMM in slot "); - print_debug_hex8(i); - print_debug("\n"); + printk(BIOS_DEBUG, "Found DIMM in slot %d\n", i); dimm_size = smbus_read_byte(DIMM0 + i, 31); - /* WISHLIST: would be nice to display it as decimal? */ - print_debug("DIMM is 0x"); - print_debug_hex8(dimm_size * 4); - print_debug("MB\n"); + printk(BIOS_DEBUG, "DIMM is %dMB\n", dimm_size * 4); /* The i810 can't handle DIMMs larger than 128MB per * side. This will fail if the DIMM uses a @@ -274,10 +251,10 @@ * Note: the factory BIOS just dies if it spots this :D */ if (dimm_size > 32) { - print_err("DIMM row sizes larger than 128MB not" + printk(BIOS_ERR, "DIMM row sizes larger than 128MB not" "supported on i810\n"); - print_err - ("Attempting to treat as 128MB DIMM\n"); + printk + (BIOS_ERR, "Attempting to treat as 128MB DIMM\n"); dimm_size = 32; } @@ -287,21 +264,17 @@ */ dimm_size = translate_spd_to_i82810[dimm_size]; - print_debug("After translation, dimm_size is 0x"); - print_debug_hex8(dimm_size); - print_debug("\n"); + printk(BIOS_DEBUG, "After translation, dimm_size is %d\n", dimm_size); /* If the DIMM is dual-sided, the DRP value is +2 */ /* TODO: Figure out asymetrical configurations. */ if ((smbus_read_byte(DIMM0 + i, 127) | 0xf) == 0xff) { - print_debug("DIMM is dual-sided\n"); + printk(BIOS_DEBUG, "DIMM is dual-sided\n"); dimm_size += 2; } } else { - print_debug("No DIMM found in slot "); - print_debug_hex8(i); - print_debug("\n"); + printk(BIOS_DEBUG, "No DIMM found in slot %d\n", i); /* If there's no DIMM in the slot, set value to 0. */ dimm_size = 0x00; @@ -311,9 +284,7 @@ drp |= dimm_size << (i * 4); } - print_debug("DRP calculated to 0x"); - print_debug_hex8(drp); - print_debug("\n"); + printk(BIOS_DEBUG, "DRP calculated to 0x%02x\n", drp); pci_write_config8(PCI_DEV(0, 0, 0), DRP, drp); } @@ -414,9 +385,7 @@ if (!d0.size && d1.size) buff_sc |= 1 << 15; - print_debug("BUFF_SC calculated to 0x"); - print_debug_hex16(buff_sc); - print_debug("\n"); + printk(BIOS_DEBUG, "BUFF_SC calculated to 0x%04x\n", buff_sc); pci_write_config16(PCI_DEV(0, 0, 0), BUFF_SC, buff_sc); } Modified: trunk/src/northbridge/intel/i82810/raminit.h ============================================================================== --- trunk/src/northbridge/intel/i82810/raminit.h Mon Dec 27 09:21:23 2010 (r6214) +++ trunk/src/northbridge/intel/i82810/raminit.h Mon Dec 27 12:34:57 2010 (r6215) @@ -28,6 +28,8 @@ void sdram_set_registers(void); void sdram_set_spd_registers(void); void sdram_enable(void); -void dump_spd_registers(void); +/* Debug */ +void dump_spd_registers(void); +void dump_pci_device(unsigned dev); #endif Modified: trunk/src/northbridge/intel/i945/raminit.c ============================================================================== --- trunk/src/northbridge/intel/i945/raminit.c Mon Dec 27 09:21:23 2010 (r6214) +++ trunk/src/northbridge/intel/i945/raminit.c Mon Dec 27 12:34:57 2010 (r6215) @@ -88,7 +88,7 @@ } #if CONFIG_DEBUG_RAM_SETUP -static void sdram_dump_mchbar_registers(void) +void sdram_dump_mchbar_registers(void) { int i; printk(BIOS_DEBUG, "Dumping MCHBAR Registers\n"); Modified: trunk/src/northbridge/intel/i945/raminit.h ============================================================================== --- trunk/src/northbridge/intel/i945/raminit.h Mon Dec 27 09:21:23 2010 (r6214) +++ trunk/src/northbridge/intel/i945/raminit.h Mon Dec 27 12:34:57 2010 (r6215) @@ -71,4 +71,8 @@ unsigned long get_top_of_ram(void); int fixup_i945_errata(void); void udelay(u32 us); + +#if CONFIG_DEBUG_RAM_SETUP +void sdram_dump_mchbar_registers(void); +#endif #endif /* RAMINIT_H */ Modified: trunk/src/northbridge/via/vx800/dram_util.c ============================================================================== --- trunk/src/northbridge/via/vx800/dram_util.c Mon Dec 27 09:21:23 2010 (r6214) +++ trunk/src/northbridge/via/vx800/dram_util.c Mon Dec 27 12:34:57 2010 (r6215) @@ -193,7 +193,7 @@ PRINT_DEBUG_MEM ("---------------------------------------------------\r"); for (i = 0; i < 0x10; i++) { - PRINT_DEBUG_MEM_HEX32(i); + PRINT_DEBUG_MEM_HEX32((u32)i); for (j = 0; j < 0x10; j++) { ByteVal = pci_read_config8(PCI_DEV(0, DevNum, FuncNum),

1 0

[commit] r6214 - trunk/src/southbridge/intel/sch
by repository service 27 Dec '10

27 Dec '10

Author: stepan Date: Mon Dec 27 09:21:23 2010 New Revision: 6214 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6214 Log: Intel SCH: make state machine binary selection available in Kconfig for now. Signed-off-by: Stefan Reinauer <stepan(a)coreboot.org> Acked-by: Stefan Reinauer <stepan(a)coreboot.org> Modified: trunk/src/southbridge/intel/sch/Kconfig trunk/src/southbridge/intel/sch/Makefile.inc Modified: trunk/src/southbridge/intel/sch/Kconfig ============================================================================== --- trunk/src/southbridge/intel/sch/Kconfig Sun Dec 26 17:49:57 2010 (r6213) +++ trunk/src/southbridge/intel/sch/Kconfig Mon Dec 27 09:21:23 2010 (r6214) @@ -22,11 +22,31 @@ select TINY_BOOTBLOCK select HAVE_USBDEBUG +if SOUTHBRIDGE_INTEL_SCH + config EHCI_BAR hex - default 0xfef00000 if SOUTHBRIDGE_INTEL_SCH + default 0xfef00000 config EHCI_DEBUG_OFFSET hex - default 0xa0 if SOUTHBRIDGE_INTEL_SCH + default 0xa0 + +config HAVE_CMC + bool "Add a CMC state machine binary" + help + Select this option to add a CMC state machine binary to + the resulting coreboot image. + + Note: Without this binary coreboot will not work + +config CMC_FILE + string "Intel CMC path and filename" + depends on HAVE_CMC + default "cmc.bin" + help + The path and filename of the file to use as CMC state machine + binary. + +endif Modified: trunk/src/southbridge/intel/sch/Makefile.inc ============================================================================== --- trunk/src/southbridge/intel/sch/Makefile.inc Sun Dec 26 17:49:57 2010 (r6213) +++ trunk/src/southbridge/intel/sch/Makefile.inc Mon Dec 27 09:21:23 2010 (r6214) @@ -36,7 +36,7 @@ romstage-$(CONFIG_USBDEBUG) += usb_debug.c # We don't ship that, but booting without it is bound to fail -#cbfs-files-y += cmc.bin -#cmc.bin-name := cmc.bin -#cmc.bin-type := 0xaa -#cmc.bin-position := 0xfffd0000 +cbfs-files-$(CONFIG_HAVE_CMC) += cmc.bin +cmc.bin-name := $(CONFIG_CMC_FILE) +cmc.bin-type := 0xaa +cmc.bin-position := 0xfffd0000

1 0

[commit] r6213 - in trunk/src: drivers/dec/21143 mainboard/nokia/ip530
by repository service 26 Dec '10

26 Dec '10

Author: stepan Date: Sun Dec 26 17:49:57 2010 New Revision: 6213 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6213 Log: All the values should stay untouched or be set automatically by the resource allocator. If that does not work out, they should be set in the code. Setting them in Kconfig is the worst possible thing to do. Signed-off-by: Stefan Reinauer <stepan(a)coreboot.org> Acked-by: Stefan Reinauer <stepan(a)coreboot.org> Modified: trunk/src/drivers/dec/21143/21143.c trunk/src/mainboard/nokia/ip530/Kconfig Modified: trunk/src/drivers/dec/21143/21143.c ============================================================================== --- trunk/src/drivers/dec/21143/21143.c Sun Dec 26 15:12:38 2010 (r6212) +++ trunk/src/drivers/dec/21143/21143.c Sun Dec 26 17:49:57 2010 (r6213) @@ -24,42 +24,23 @@ #include <device/pci_ids.h> #include <console/console.h> -/** - * The following should be set in the mainboard-specific Kconfig file. - */ -#if (!defined(CONFIG_DEC21143_CACHE_LINE_SIZE) || \ - !defined(CONFIG_DEC21143_EXPANSION_ROM_BASE_ADDRESS) || \ - !defined(CONFIG_DEC21143_COMMAND_AND_STATUS_CONFIGURATION)) -#error "you must supply these values in your mainboard-specific Kconfig file" -#endif - -/* CONFIG_DEC21143_CACHE_LINE_SIZE try 0x00000000 if unsure */ -/* CONFIG_DEC21143_EXPANSION_ROM_BASE_ADDRESS try 0x00000000 if unsure */ -/* CONFIG_DEC21143_COMMAND_AND_STATUS_CONFIGURATION try 0x02800107 or 0x02800007 if unsure */ - -/** - * This driver takes the values from Kconfig and loads them in the registers. - */ static void dec_21143_enable(device_t dev) { printk(BIOS_DEBUG, "Initializing DECchip 21143\n"); + // The resource allocator should do this. If not, it needs to be fixed + // differently. +#if 0 /* Command and status configuration (offset 0x04) */ - pci_write_config32(dev, 0x04, - CONFIG_DEC21143_COMMAND_AND_STATUS_CONFIGURATION); + pci_write_config32(dev, 0x04, 0x02800107); printk(BIOS_DEBUG, "0x04 = %08x (07 01 80 02)\n", pci_read_config32(dev, 0x04)); /* Cache line size (offset 0x0C) */ - pci_write_config8(dev, 0x0C, CONFIG_DEC21143_CACHE_LINE_SIZE); - printk(BIOS_DEBUG, "0x0c = %08x (00 80 00 00)\n", - pci_read_config32(dev, 0x0C)); - - /* Expansion ROM base address (offset 0x30) */ - pci_write_config32(dev, 0x30, - CONFIG_DEC21143_EXPANSION_ROM_BASE_ADDRESS); - printk(BIOS_DEBUG, "0x30 = %08x (0x00000000)\n", - pci_read_config32(dev, 0x30)); + pci_write_config8(dev, 0x0C, 0x00); + printk(BIOS_DEBUG, "0x0c = %08x (00)\n", + pci_read_config8(dev, 0x0C)); +#endif } static struct device_operations dec_21143_ops = { @@ -73,5 +54,5 @@ static const struct pci_driver dec_21143_driver __pci_driver = { .ops = &dec_21143_ops, .vendor = PCI_VENDOR_ID_DEC, - .device = PCI_DEVICE_ID_DEC_21142, + .device = PCI_DEVICE_ID_DEC_21142, // FIXME wrong ID? }; Modified: trunk/src/mainboard/nokia/ip530/Kconfig ============================================================================== --- trunk/src/mainboard/nokia/ip530/Kconfig Sun Dec 26 15:12:38 2010 (r6212) +++ trunk/src/mainboard/nokia/ip530/Kconfig Sun Dec 26 17:49:57 2010 (r6213) @@ -45,19 +45,6 @@ int default 22 -## Configuration items for the ethernet adaptors -config DEC21143_CACHE_LINE_SIZE - hex - default 0x00000000 - -config DEC21143_EXPANSION_ROM_BASE_ADDRESS - hex - default 0x00000000 - -config DEC21143_COMMAND_AND_STATUS_CONFIGURATION - hex - default 0x02800107 - ## Configuration for the PCMCIA-Cardbus controller. config TI_PCMCIA_CARDBUS_CMDR hex

1 0

[commit] r6212 - in trunk/src: drivers/dec/21143 mainboard/hp/dl145_g1 mainboard/hp/dl145_g3 mainboard/hp/dl165_g6_fam10 mainboard/nokia/ip530 southbridge/ti/pci1x2x
by repository service 26 Dec '10

26 Dec '10

Author: uwe Date: Sun Dec 26 15:12:38 2010 New Revision: 6212 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6212 Log: Random fixes for TI pci1x2x / Nokia IP530 / others. - nokia/ip530/devicetree.cb, southbridge/ti/pci1x2x/pci1x2x.c: - Fix SMSC FDC37B787 name (was a typo). - Disable PS/2 keyboard/mouse LDN, the IP530 doesn't have either. - Fix typo: s/PCI_DEVICE_ID_TI_1420/PCI_DEVICE_ID_TI_1520/. - All of these are confirmed by Marc Bertens on IRC. - Fix a few CHIP_NAME HP board names. - Random whitespace and coding-style fixes. Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Modified: trunk/src/drivers/dec/21143/21143.c trunk/src/mainboard/hp/dl145_g1/mainboard.c trunk/src/mainboard/hp/dl145_g3/mainboard.c trunk/src/mainboard/hp/dl165_g6_fam10/mainboard.c trunk/src/mainboard/nokia/ip530/devicetree.cb trunk/src/southbridge/ti/pci1x2x/pci1x2x.c Modified: trunk/src/drivers/dec/21143/21143.c ============================================================================== --- trunk/src/drivers/dec/21143/21143.c Sun Dec 26 06:24:50 2010 (r6211) +++ trunk/src/drivers/dec/21143/21143.c Sun Dec 26 15:12:38 2010 (r6212) @@ -38,33 +38,40 @@ /* CONFIG_DEC21143_COMMAND_AND_STATUS_CONFIGURATION try 0x02800107 or 0x02800007 if unsure */ /** - * This driver take the values from Kconfig and load them in the registers + * This driver takes the values from Kconfig and loads them in the registers. */ -static void dec_21143_enable( device_t dev ) +static void dec_21143_enable(device_t dev) { - printk( BIOS_DEBUG, "Init of DECchip 21143 Kconfig style\n"); - // Command and Status Configuration Register (Offset 0x04) - pci_write_config32( dev, 0x04, CONFIG_DEC21143_COMMAND_AND_STATUS_CONFIGURATION ); - printk( BIOS_DEBUG, "0x04 = %08x (07 01 80 02)\n", pci_read_config32(dev, 0x04) ); - // Cache Line Size Register (Offset 0x0C) - pci_write_config8( dev, 0x0C, CONFIG_DEC21143_CACHE_LINE_SIZE ); - printk( BIOS_DEBUG, "0x0c = %08x (00 80 00 00)\n", pci_read_config32(dev, 0x0C) ); - // Expansion ROM Base Address Register (Offset 0x30) - pci_write_config32( dev, 0x30, CONFIG_DEC21143_EXPANSION_ROM_BASE_ADDRESS ); - printk( BIOS_DEBUG, "0x30 = %08x (0x00000000)\n", pci_read_config32(dev, 0x30) ); - return; + printk(BIOS_DEBUG, "Initializing DECchip 21143\n"); + + /* Command and status configuration (offset 0x04) */ + pci_write_config32(dev, 0x04, + CONFIG_DEC21143_COMMAND_AND_STATUS_CONFIGURATION); + printk(BIOS_DEBUG, "0x04 = %08x (07 01 80 02)\n", + pci_read_config32(dev, 0x04)); + + /* Cache line size (offset 0x0C) */ + pci_write_config8(dev, 0x0C, CONFIG_DEC21143_CACHE_LINE_SIZE); + printk(BIOS_DEBUG, "0x0c = %08x (00 80 00 00)\n", + pci_read_config32(dev, 0x0C)); + + /* Expansion ROM base address (offset 0x30) */ + pci_write_config32(dev, 0x30, + CONFIG_DEC21143_EXPANSION_ROM_BASE_ADDRESS); + printk(BIOS_DEBUG, "0x30 = %08x (0x00000000)\n", + pci_read_config32(dev, 0x30)); } -static struct device_operations dec_21143_ops = { - .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = dec_21143_enable, - .scan_bus = 0, +static struct device_operations dec_21143_ops = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = dec_21143_enable, + .scan_bus = 0, }; static const struct pci_driver dec_21143_driver __pci_driver = { - .ops = &dec_21143_ops, - .vendor = PCI_VENDOR_ID_DEC, - .device = PCI_DEVICE_ID_DEC_21142, + .ops = &dec_21143_ops, + .vendor = PCI_VENDOR_ID_DEC, + .device = PCI_DEVICE_ID_DEC_21142, }; Modified: trunk/src/mainboard/hp/dl145_g1/mainboard.c ============================================================================== --- trunk/src/mainboard/hp/dl145_g1/mainboard.c Sun Dec 26 06:24:50 2010 (r6211) +++ trunk/src/mainboard/hp/dl145_g1/mainboard.c Sun Dec 26 15:12:38 2010 (r6212) @@ -25,5 +25,5 @@ #include "chip.h" struct chip_operations mainboard_ops = { - CHIP_NAME("HP DL145G1 Mainboard") + CHIP_NAME("HP ProLiant DL145 G1 Mainboard") }; Modified: trunk/src/mainboard/hp/dl145_g3/mainboard.c ============================================================================== --- trunk/src/mainboard/hp/dl145_g3/mainboard.c Sun Dec 26 06:24:50 2010 (r6211) +++ trunk/src/mainboard/hp/dl145_g3/mainboard.c Sun Dec 26 15:12:38 2010 (r6212) @@ -30,5 +30,5 @@ #include "chip.h" struct chip_operations mainboard_ops = { - CHIP_NAME("HP DL145 G3 Mainboard") + CHIP_NAME("HP ProLiant DL145 G3 Mainboard") }; Modified: trunk/src/mainboard/hp/dl165_g6_fam10/mainboard.c ============================================================================== --- trunk/src/mainboard/hp/dl165_g6_fam10/mainboard.c Sun Dec 26 06:24:50 2010 (r6211) +++ trunk/src/mainboard/hp/dl165_g6_fam10/mainboard.c Sun Dec 26 15:12:38 2010 (r6212) @@ -30,5 +30,5 @@ #include "chip.h" struct chip_operations mainboard_ops = { - CHIP_NAME("HP DL165 G6 Mainboard (Family 10)") + CHIP_NAME("HP ProLiant DL165 G6 Mainboard (Fam10h)") }; Modified: trunk/src/mainboard/nokia/ip530/devicetree.cb ============================================================================== --- trunk/src/mainboard/nokia/ip530/devicetree.cb Sun Dec 26 06:24:50 2010 (r6211) +++ trunk/src/mainboard/nokia/ip530/devicetree.cb Sun Dec 26 15:12:38 2010 (r6212) @@ -19,9 +19,9 @@ ## chip northbridge/intel/i440bx # Northbridge - device lapic_cluster 0 on # APIC cluster - chip cpu/intel/socket_PGA370 # CPU - device lapic 0 on end # APIC + device lapic_cluster 0 on # (L)APIC cluster + chip cpu/intel/socket_PGA370 # CPU socket + device lapic 0 on end # Local APIC of the CPU end end device pci_domain 0 on # PCI domain @@ -29,7 +29,7 @@ device pci 1.0 on end # PCI/AGP bridge chip southbridge/intel/i82371eb # Southbridge device pci 7.0 on # ISA bridge - chip superio/smsc/smscsuperio # Super I/O (SMSC FDC37C878) + chip superio/smsc/smscsuperio # Super I/O (SMSC FDC37B787) device pnp 3f0.0 off end # Floppy (No connector) device pnp 3f0.3 off end # Parallel port (No connector) device pnp 3f0.4 on # COM1 @@ -40,10 +40,10 @@ io 0x60 = 0x2f8 irq 0x70 = 3 end - device pnp 3f0.7 on end # PS/2 keyboard / mouse device pnp 3f0.6 on end # RTC + device pnp 3f0.7 off end # PS/2 keyboard / mouse (No connector) device pnp 3f0.8 on end # AUX I/O - device pnp 3f0.A off end # ACPI (No support yet) + device pnp 3f0.a off end # ACPI (No support yet) end end device pci 7.1 on end # IDE Modified: trunk/src/southbridge/ti/pci1x2x/pci1x2x.c ============================================================================== --- trunk/src/southbridge/ti/pci1x2x/pci1x2x.c Sun Dec 26 06:24:50 2010 (r6211) +++ trunk/src/southbridge/ti/pci1x2x/pci1x2x.c Sun Dec 26 15:12:38 2010 (r6212) @@ -24,41 +24,43 @@ #include <device/pci_ops.h> #include <console/console.h> -#if ( !defined( CONFIG_TI_PCMCIA_CARDBUS_CMDR ) || \ - !defined( CONFIG_TI_PCMCIA_CARDBUS_CLSR ) || \ - !defined( CONFIG_TI_PCMCIA_CARDBUS_CLTR ) || \ - !defined( CONFIG_TI_PCMCIA_CARDBUS_BCR ) || \ - !defined( CONFIG_TI_PCMCIA_CARDBUS_SCR ) || \ - !defined( CONFIG_TI_PCMCIA_CARDBUS_MRR ) ) +#if (!defined(CONFIG_TI_PCMCIA_CARDBUS_CMDR) || \ + !defined(CONFIG_TI_PCMCIA_CARDBUS_CLSR) || \ + !defined(CONFIG_TI_PCMCIA_CARDBUS_CLTR) || \ + !defined(CONFIG_TI_PCMCIA_CARDBUS_BCR) || \ + !defined(CONFIG_TI_PCMCIA_CARDBUS_SCR) || \ + !defined(CONFIG_TI_PCMCIA_CARDBUS_MRR)) #error "you must supply these values in your mainboard-specific Kconfig file" #endif static void ti_pci1x2y_init(struct device *dev) { printk(BIOS_INFO, "Init of Texas Instruments PCI1x2x PCMCIA/CardBus controller\n"); - // Command register (offset 04) - pci_write_config16( dev, 0x04, CONFIG_TI_PCMCIA_CARDBUS_CMDR ); - // Cache Line Size Register (offset 0x0C) - pci_write_config8( dev, 0x0C, CONFIG_TI_PCMCIA_CARDBUS_CLSR ); - // CardBus latency timer register (offset 1B) - pci_write_config8( dev, 0x1B, CONFIG_TI_PCMCIA_CARDBUS_CLTR ); - // Bridge control register (offset 3E) - pci_write_config16( dev, 0x3E, CONFIG_TI_PCMCIA_CARDBUS_BCR ); - /** Enable change sub-vendor id - * Clear the bit 5 to enable to write to the sub-vendor/device ids at 40 and 42 */ - pci_write_config32( dev, 0x80, 0x10 ); - pci_write_config32( dev, 0x40, PCI_VENDOR_ID_NOKIA ); - // Now write the correct value for SCR - // System Control Register (offset 0x80) - pci_write_config32( dev, 0x80, CONFIG_TI_PCMCIA_CARDBUS_SCR ); - // Multifunction routing register - pci_write_config32( dev, 0x8C, CONFIG_TI_PCMCIA_CARDBUS_MRR ); - // Set Device Control Register (0x92) accordingly - pci_write_config8( dev, 0x92, pci_read_config8( dev, 0x92 ) | 0x02 ); - return; + + /* Command (offset 04) */ + pci_write_config16(dev, 0x04, CONFIG_TI_PCMCIA_CARDBUS_CMDR); + /* Cache Line Size (offset 0x0C) */ + pci_write_config8(dev, 0x0C, CONFIG_TI_PCMCIA_CARDBUS_CLSR); + /* CardBus latency timer (offset 0x1B) */ + pci_write_config8(dev, 0x1B, CONFIG_TI_PCMCIA_CARDBUS_CLTR); + /* Bridge control (offset 0x3E) */ + pci_write_config16(dev, 0x3E, CONFIG_TI_PCMCIA_CARDBUS_BCR); + /* + * Enable change sub-vendor ID. Clear the bit 5 to enable to write + * to the sub-vendor/device ids at 40 and 42. + */ + pci_write_config32(dev, 0x80, 0x10); + pci_write_config32(dev, 0x40, PCI_VENDOR_ID_NOKIA); + /* Now write the correct value for SCR. */ + /* System control (offset 0x80) */ + pci_write_config32(dev, 0x80, CONFIG_TI_PCMCIA_CARDBUS_SCR); + /* Multifunction routing */ + pci_write_config32(dev, 0x8C, CONFIG_TI_PCMCIA_CARDBUS_MRR); + /* Set the device control register (0x92) accordingly. */ + pci_write_config8(dev, 0x92, pci_read_config8(dev, 0x92) | 0x02); } -static struct device_operations ti_pci1x2y_ops = { +static struct device_operations ti_pci1x2y_ops = { .read_resources = NULL, //pci_dev_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, @@ -67,19 +69,19 @@ }; static const struct pci_driver ti_pci1225_driver __pci_driver = { - .ops = &ti_pci1x2y_ops, - .vendor = PCI_VENDOR_ID_TI, - .device = PCI_DEVICE_ID_TI_1225, + .ops = &ti_pci1x2y_ops, + .vendor = PCI_VENDOR_ID_TI, + .device = PCI_DEVICE_ID_TI_1225, }; static const struct pci_driver ti_pci1420_driver __pci_driver = { - .ops = &ti_pci1x2y_ops, - .vendor = PCI_VENDOR_ID_TI, - .device = PCI_DEVICE_ID_TI_1420, + .ops = &ti_pci1x2y_ops, + .vendor = PCI_VENDOR_ID_TI, + .device = PCI_DEVICE_ID_TI_1420, }; static const struct pci_driver ti_pci1520_driver __pci_driver = { - .ops = &ti_pci1x2y_ops, - .vendor = PCI_VENDOR_ID_TI, - .device = PCI_DEVICE_ID_TI_1420, + .ops = &ti_pci1x2y_ops, + .vendor = PCI_VENDOR_ID_TI, + .device = PCI_DEVICE_ID_TI_1520, };

2 1

[PATCH 3/6] Geode GX2 cleanup patch
by Nils 26 Dec '10

26 Dec '10

Add a "while (1)" function around the hlt instruction to assure the processor can't wake up from an interrupt. Signed-off-by: Nils Jacobs <njacobs8(a)hetnet.nl> This was suggested by Uwe Hermann. Thanks! I also included the same patch for Geode LX. Nils.

3 2

Re: [coreboot] [PATCH 0/6] Geode GX2 cleanup patch
by Nils 26 Dec '10

26 Dec '10

Patrick: Thanks for the quick ack. All: It would be nice if someone with SVN access would be able to commit these patches. Thanks, Nils.

2 1

[PATCH 6/6] Geode GX2 cleanup patch
by Nils 26 Dec '10

26 Dec '10

Move VIDEO_MB to Kconfig. Signed-off-by: Nils Jacobs <njacobs8(a)hetnet.nl> Thanks, Nils.

2 1

[commit] r6211 - trunk/src/northbridge/amd/gx2
by repository service 26 Dec '10

26 Dec '10

Author: stuge Date: Sun Dec 26 06:24:50 2010 New Revision: 6211 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6211 Log: Move Geode GX2 UMA video memory size to Kconfig Signed-off-by: Nils Jacobs <njacobs8(a)hetnet.nl> Acked-by: Patrick Georgi <patrick(a)georgi-clan.de> Acked-by: Peter Stuge <peter(a)stuge.se> Modified: trunk/src/northbridge/amd/gx2/Kconfig trunk/src/northbridge/amd/gx2/grphinit.c trunk/src/northbridge/amd/gx2/northbridge.c Modified: trunk/src/northbridge/amd/gx2/Kconfig ============================================================================== --- trunk/src/northbridge/amd/gx2/Kconfig Sun Dec 26 06:21:18 2010 (r6210) +++ trunk/src/northbridge/amd/gx2/Kconfig Sun Dec 26 06:24:50 2010 (r6211) @@ -21,6 +21,11 @@ bool select GEODE_VSA +config VIDEO_MB + int + default 8 + depends on NORTHBRIDGE_AMD_GX2 + # The GX2_PROCESSOR_MHZ options let you chose the correct GX2 processor # speed in the mainboard's Kconfig file. config GX2_PROCESSOR_MHZ_300 Modified: trunk/src/northbridge/amd/gx2/grphinit.c ============================================================================== --- trunk/src/northbridge/amd/gx2/grphinit.c Sun Dec 26 06:21:18 2010 (r6210) +++ trunk/src/northbridge/amd/gx2/grphinit.c Sun Dec 26 06:24:50 2010 (r6211) @@ -5,9 +5,6 @@ #include "chip.h" #include "northbridge.h" -/* FIXME handle UMA properly. */ -#define VIDEO_MB 8 /* MB of video memory */ - /* This function mirrors the Graphics_Init routine in GeodeROM. */ void graphics_init(void) { @@ -15,7 +12,7 @@ /* Call SoftVG with the main configuration parameters. */ /* NOTE: SoftVG expects the memory size to be given in 512 KB pages */ - vrWrite((VRC_VG << 8) + VG_MEM_SIZE, 0x0100 | (VIDEO_MB * 2)); + vrWrite((VRC_VG << 8) + VG_MEM_SIZE, 0x0100 | (CONFIG_VIDEO_MB * 2)); } Modified: trunk/src/northbridge/amd/gx2/northbridge.c ============================================================================== --- trunk/src/northbridge/amd/gx2/northbridge.c Sun Dec 26 06:21:18 2010 (r6210) +++ trunk/src/northbridge/amd/gx2/northbridge.c Sun Dec 26 06:24:50 2010 (r6211) @@ -15,7 +15,6 @@ #include <cpu/amd/vr.h> #include <cpu/cpu.h> #include "../../../southbridge/amd/cs5536/cs5536.h" -#define VIDEO_MB 8 #define NORTHBRIDGE_FILE "northbridge.c" @@ -302,7 +301,7 @@ graphics_init(); dev->ops = &pci_domain_ops; pci_set_method(dev); - tomk = ((sizeram() - VIDEO_MB) * 1024) - SMM_SIZE; + tomk = ((sizeram() - CONFIG_VIDEO_MB) * 1024) - SMM_SIZE; #if CONFIG_WRITE_HIGH_TABLES==1 /* Leave some space for ACPI, PIRQ and MP tables */ high_tables_base = (tomk * 1024) - HIGH_MEMORY_SIZE;

1 0

[PATCH 5/6] Geode GX2 cleanup patch
by Nils 26 Dec '10

26 Dec '10

Delete some unused code. Signed-off-by: Nils Jacobs <njacobs8(a)hetnet.nl> Thanks, Nils.

2 1

← Newer
1
...
6
7
8
9
10
11
12
...
27
Older →

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

2012

2011

2010

2009

2008

2007

2006

2005

2004

2003

2002

coreboot December 2010