coreboot December 2010

coreboot@coreboot.org

52 participants
262 discussions

build service results for r6223
by repository service 30 Dec '10

30 Dec '10

Dear coreboot readers! This is the automatic build system of coreboot. The developer "stepan" checked in revision 6223 to the coreboot repository. This caused the following changes: Change Log: Per default, use SeaBIOS payload instead of no payload. Add choice to use stable or master version of seabios repository Signed-off-by: Stefan Reinauer <stepan(a)coreboot.org> Acked-by: Stefan Reinauer <stepan(a)coreboot.org> Build Log: Compilation of lippert:frontrunner is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6223&device=frontrunner&ve… If something broke during this checkin please be a pain in stepan's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

1 0

[PATCH] Add easy SeaBIOS as payload option
by Stefan Reinauer 30 Dec '10

30 Dec '10

See patch

5 6

[commit] r6223 - in trunk: . payloads/external/SeaBIOS src src/arch/x86 util/abuild
by repository service 30 Dec '10

30 Dec '10

Author: stepan Date: Thu Dec 30 18:39:50 2010 New Revision: 6223 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6223 Log: Per default, use SeaBIOS payload instead of no payload. Add choice to use stable or master version of seabios repository Signed-off-by: Stefan Reinauer <stepan(a)coreboot.org> Acked-by: Stefan Reinauer <stepan(a)coreboot.org> Added: trunk/payloads/external/SeaBIOS/ trunk/payloads/external/SeaBIOS/Makefile.inc Modified: trunk/Makefile trunk/src/Kconfig trunk/src/arch/x86/Makefile.inc trunk/util/abuild/abuild Modified: trunk/Makefile ============================================================================== --- trunk/Makefile Thu Dec 30 17:57:58 2010 (r6222) +++ trunk/Makefile Thu Dec 30 18:39:50 2010 (r6223) @@ -363,6 +363,7 @@ rm -f $(obj)/mainboard/$(MAINBOARDDIR)/bootblock.* $(obj)/mainboard/$(MAINBOARDDIR)/dsdt.* rm -f $(obj)/cpu/x86/smm/smm_bin.c $(obj)/cpu/x86/smm/smm.* $(obj)/cpu/x86/smm/smm rmdir -p $(alldirs) 2>/dev/null >/dev/null || true + make -C payloads/external/SeaBIOS clean clean: clean-for-update rm -f $(obj)/coreboot* .ccwrap Added: trunk/payloads/external/SeaBIOS/Makefile.inc ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/payloads/external/SeaBIOS/Makefile.inc Thu Dec 30 18:39:50 2010 (r6223) @@ -0,0 +1,31 @@ + + +TAG-$(CONFIG_SEABIOS_MASTER)=master +TAG-$(CONFIG_SEABIOS_STABLE)=0.6.1-stable + +all: seabios + +seabios: patch + cd seabios; $(MAKE) CC="$(CC)" LD="$(LD)" + +patch: checkout + test -r seabios/.patched || \ + perl -pi -e "s,#define CONFIG_COREBOOT 0,#define CONFIG_COREBOOT 1,;" \ + -e "s,#define CONFIG_DEBUG_SERIAL 0,#define CONFIG_DEBUG_SERIAL 1,;" \ + -e "s,#define CONFIG_VGAHOOKS 0,#define CONFIG_VGAHOOKS 1,;" \ + seabios/src/config.h + touch seabios/.patched + +checkout: + echo "Checking out SeaBIOS $(TAG-y)" + test -d seabios && ( cd seabios; git pull ) || \ + git clone git://git.linuxtogo.org/home/kevin/seabios.git seabios + cd seabios; git checkout $(TAG-y) + +clean: + test -d seabios && (cd seabios; $(MAKE) CC="$(CC)" LD="$(LD)" clean) || exit 0 + +distclean: + rm -rf seabios + +.PHONY: seabios Modified: trunk/src/Kconfig ============================================================================== --- trunk/src/Kconfig Thu Dec 30 17:57:58 2010 (r6222) +++ trunk/src/Kconfig Thu Dec 30 18:39:50 2010 (r6223) @@ -333,7 +333,8 @@ choice prompt "Add a payload" - default PAYLOAD_NONE + default PAYLOAD_NONE if !ARCH_X86 + default PAYLOAD_SEABIOS if ARCH_X86 config PAYLOAD_NONE bool "None" @@ -355,6 +356,31 @@ You will be able to specify the location and file name of the payload image later. +config PAYLOAD_SEABIOS + bool "SeaBIOS" + depends on ARCH_X86 + help + Select this option if you want to build a coreboot image + with a SeaBIOS payload. If you don't know what this is + about, just leave it enabled. + + See http://coreboot.org/Payloads for more information. + +endchoice + +choice + prompt "SeaBIOS version" + default SEABIOS_STABLE + depends on PAYLOAD_SEABIOS + +config SEABIOS_STABLE + bool "stable" + help + Stable SeaBIOS version +config SEABIOS_MASTER + bool "master" + help + Newest SeaBIOS version endchoice config PAYLOAD_FILE @@ -364,11 +390,15 @@ help The path and filename of the ELF executable file to use as payload. +config PAYLOAD_FILE + depends on PAYLOAD_SEABIOS + default "payloads/external/SeaBIOS/seabios/out/bios.bin.elf" + # TODO: Defined if no payload? Breaks build? config COMPRESSED_PAYLOAD_LZMA bool "Use LZMA compression for payloads" default y - depends on PAYLOAD_ELF + depends on PAYLOAD_ELF || PAYLOAD_SEABIOS help In order to reduce the size payloads take up in the ROM chip coreboot can compress them using the LZMA algorithm. Modified: trunk/src/arch/x86/Makefile.inc ============================================================================== --- trunk/src/arch/x86/Makefile.inc Thu Dec 30 17:57:58 2010 (r6222) +++ trunk/src/arch/x86/Makefile.inc Thu Dec 30 18:39:50 2010 (r6223) @@ -34,9 +34,12 @@ ####################################################################### # Build the final rom image COREBOOT_ROM_DEPENDENCIES:= -ifneq ($(CONFIG_PAYLOAD_NONE),y) +ifeq ($(CONFIG_PAYLOAD_ELF),y) COREBOOT_ROM_DEPENDENCIES+=$(CONFIG_PAYLOAD_FILE) endif +ifeq ($(CONFIG_PAYLOAD_SEABIOS),y) +COREBOOT_ROM_DEPENDENCIES+=seabios +endif ifeq ($(CONFIG_VGA_BIOS),y) COREBOOT_ROM_DEPENDENCIES+=$(CONFIG_VGA_BIOS_FILE) endif @@ -80,10 +83,15 @@ $(CBFSTOOL) $@.tmp add-stage $(obj)/coreboot_ram $(CONFIG_CBFS_PREFIX)/coreboot_ram $(CBFS_COMPRESS_FLAG) ifeq ($(CONFIG_PAYLOAD_NONE),y) @printf " PAYLOAD \e[1;31mnone (as specified by user)\e[0m\n" -else +endif +ifeq ($(CONFIG_PAYLOAD_ELF),y) @printf " PAYLOAD $(CONFIG_PAYLOAD_FILE) (compression: $(CBFS_PAYLOAD_COMPRESS_NAME))\n" $(CBFSTOOL) $@.tmp add-payload $(CONFIG_PAYLOAD_FILE) $(CONFIG_CBFS_PREFIX)/payload $(CBFS_PAYLOAD_COMPRESS_FLAG) endif +ifeq ($(CONFIG_PAYLOAD_SEABIOS),y) + @printf " PAYLOAD SeaBIOS (internal, compression: $(CBFS_PAYLOAD_COMPRESS_NAME))\n" + $(CBFSTOOL) $@.tmp add-payload $(CONFIG_PAYLOAD_FILE) $(CONFIG_CBFS_PREFIX)/payload $(CBFS_PAYLOAD_COMPRESS_FLAG) +endif ifeq ($(CONFIG_VGA_BIOS),y) @printf " VGABIOS $(CONFIG_VGA_BIOS_FILE) $(CONFIG_VGA_BIOS_ID)\n" $(CBFSTOOL) $@.tmp add $(CONFIG_VGA_BIOS_FILE) "pci$(CONFIG_VGA_BIOS_ID).rom" optionrom @@ -272,3 +280,10 @@ else include $(src)/arch/x86/Makefile.bigbootblock.inc endif + +seabios: + $(MAKE) -C payloads/external/SeaBIOS -f Makefile.inc \ + CC="$(CC)" LD="$(LD)" \ + CONFIG_SEABIOS_MASTER=$(CONFIG_SEABIOS_MASTER) \ + CONFIG_SEABIOS_STABLE=$(CONFIG_SEABIOS_STABLE) + Modified: trunk/util/abuild/abuild ============================================================================== --- trunk/util/abuild/abuild Thu Dec 30 17:57:58 2010 (r6222) +++ trunk/util/abuild/abuild Thu Dec 30 18:39:50 2010 (r6223) @@ -175,6 +175,7 @@ echo "CONFIG_CBFS_PREFIX=\"$cbfs_prefix\"" >> ${build_dir}/config.build if [ "$PAYLOAD" != "/dev/null" ]; then echo "# CONFIG_PAYLOAD_NONE is not set" >> ${build_dir}/config.build + echo "# CONFIG_PAYLOAD_SEABIOS is not set" >> ${build_dir}/config.build echo "CONFIG_PAYLOAD_ELF=y" >> ${build_dir}/config.build echo "CONFIG_PAYLOAD_FILE=\"$PAYLOAD\"" >> ${build_dir}/config.build fi

1 0

build service results for r6222
by repository service 30 Dec '10

30 Dec '10

Dear coreboot readers! This is the automatic build system of coreboot. The developer "stepan" checked in revision 6222 to the coreboot repository. This caused the following changes: Change Log: superiotool: Don't skip probing on a port if a a chip was detected on another port. Only skip probing if chip was found on the same port already to avoid duplicates. Signed-off-by: Stefan Reinauer <stepan(a)coreboot.org> Acked-by: Stefan Reinauer <stepan(a)coreboot.org> Build Log: Compilation of lippert:frontrunner is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6222&device=frontrunner&ve… If something broke during this checkin please be a pain in stepan's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

1 0

[commit] r6222 - trunk/util/superiotool
by repository service 30 Dec '10

30 Dec '10

Author: stepan Date: Thu Dec 30 17:57:58 2010 New Revision: 6222 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6222 Log: superiotool: Don't skip probing on a port if a a chip was detected on another port. Only skip probing if chip was found on the same port already to avoid duplicates. Signed-off-by: Stefan Reinauer <stepan(a)coreboot.org> Acked-by: Stefan Reinauer <stepan(a)coreboot.org> Modified: trunk/util/superiotool/ite.c trunk/util/superiotool/winbond.c Modified: trunk/util/superiotool/ite.c ============================================================================== --- trunk/util/superiotool/ite.c Wed Dec 29 22:12:10 2010 (r6221) +++ trunk/util/superiotool/ite.c Thu Dec 30 17:57:58 2010 (r6222) @@ -798,6 +798,8 @@ regwrite(port, 0x02, 0x02); } +static int chip_found_at_port; + static void probe_idregs_ite_helper(const char *init, uint16_t port) { uint16_t id, chipver, ecport; @@ -817,6 +819,7 @@ printf("Found ITE %s (id=0x%04x, rev=0x%01x) at 0x%x\n", get_superio_name(reg_table, id), id, chipver, port); chip_found = 1; + chip_found_at_port = 1; dump_superio("ITE", reg_table, port, id, LDN_SEL); @@ -837,41 +840,43 @@ void probe_idregs_ite(uint16_t port) { + chip_found_at_port = 0; + if (port == 0x3f0 || port == 0x3bd || port == 0x370) { enter_conf_mode_ite_legacy(port, initkey_it8661f); probe_idregs_ite_helper("(init=legacy/it8661f) ", port); exit_conf_mode_ite(port); - if (chip_found) return; + if (chip_found_at_port) return; enter_conf_mode_ite_legacy(port, initkey_it8671f); probe_idregs_ite_helper("(init=legacy/it8671f) ", port); exit_conf_mode_ite(port); - if (chip_found) return; + if (chip_found_at_port) return; } else { enter_conf_mode_ite(port); probe_idregs_ite_helper("(init=standard) ", port); exit_conf_mode_ite(port); - if (chip_found) return; + if (chip_found_at_port) return; enter_conf_mode_ite_it8502e(port); probe_idregs_ite_helper("(init=it8502e) ", port); exit_conf_mode_ite(port); - if (chip_found) return; + if (chip_found_at_port) return; enter_conf_mode_ite_it8761e(port); probe_idregs_ite_helper("(init=it8761e) ", port); exit_conf_mode_ite(port); - if (chip_found) return; + if (chip_found_at_port) return; enter_conf_mode_ite_it8228e(port); probe_idregs_ite_helper("(init=it8228e) ", port); exit_conf_mode_ite(port); - if (chip_found) return; + if (chip_found_at_port) return; enter_conf_mode_winbond_fintek_ite_8787(port); probe_idregs_ite_helper("(init=0x87,0x87) ", port); exit_conf_mode_winbond_fintek_ite_8787(port); - if (chip_found) return; + if (chip_found_at_port) return; } } Modified: trunk/util/superiotool/winbond.c ============================================================================== --- trunk/util/superiotool/winbond.c Wed Dec 29 22:12:10 2010 (r6221) +++ trunk/util/superiotool/winbond.c Thu Dec 30 17:57:58 2010 (r6222) @@ -625,6 +625,8 @@ OUTB(0x86, port); } +static int chip_found_at_port; + static void probe_idregs_winbond_helper(const char *init, uint16_t port) { uint16_t id, hwmport; @@ -662,6 +664,7 @@ printf("Found Winbond %s (id=0x%02x, rev=0x%02x) at 0x%x\n", get_superio_name(reg_table, id), devid, rev, port); chip_found = 1; + chip_found_at_port = 1; dump_superio("Winbond", reg_table, port, id, LDN_SEL); @@ -688,25 +691,27 @@ void probe_idregs_winbond(uint16_t port) { + chip_found_at_port = 0; + enter_conf_mode_winbond_88(port); probe_idregs_winbond_helper("(init=0x88) ", port); exit_conf_mode_winbond_fintek_ite_8787(port); - if (chip_found) return; + if (chip_found_at_port) return; enter_conf_mode_winbond_89(port); probe_idregs_winbond_helper("(init=0x89) ", port); exit_conf_mode_winbond_fintek_ite_8787(port); - if (chip_found) return; + if (chip_found_at_port) return; enter_conf_mode_winbond_86(port); probe_idregs_winbond_helper("(init=0x86,0x86) ", port); exit_conf_mode_winbond_fintek_ite_8787(port); - if (chip_found) return; + if (chip_found_at_port) return; enter_conf_mode_winbond_fintek_ite_8787(port); probe_idregs_winbond_helper("(init=0x87,0x87) ", port); exit_conf_mode_winbond_fintek_ite_8787(port); - if (chip_found) return; + if (chip_found_at_port) return; } void print_winbond_chips(void)

1 0

[PATCH 2/7] Geode GX2 cleanup next round
by Nils 30 Dec '10

30 Dec '10

Add a MSR printing function to northbridge.c like in the Geode LX code. Signed-off-by: Nils Jacobs <njacobs8(a)hetnet.nl> Thanks, Nils.

2 5

[PATCH 2/3] add amd sb800 support
by She, Kerry 30 Dec '10

30 Dec '10

sb800 southbridge CIMx code Signed-off-by: Kerry She <Kerry.she(a)amd.com> Regards, Kerry She < kerry.she(a)amd.com> Tel: 86-10-6280-1415 Mobile: 86 - 152 1018 2083

2 1

[PATCH 1/3] add amd bimini mainboard support
by She, Kerry 30 Dec '10

30 Dec '10

add amd bimini mainboard support Signed-off-by: Kerry She <Kerry.she(a)amd.com> Regards, Kerry She < kerry.she(a)amd.com> Tel: 86-10-6280-1415 Mobile: 86 - 152 1018 2083

2 1

[patch] Add RS785(RS880) support
by Bao, Zheng 30 Dec '10

30 Dec '10

Add RS785(RS880) support. Just few pci_ids. Signed-off-by: Zheng Bao <zheng.bao(a)amd.com> Index: src/southbridge/amd/rs780/gfx.c =================================================================== --- src/southbridge/amd/rs780/gfx.c (revision 6204) +++ src/southbridge/amd/rs780/gfx.c (working copy) @@ -26,6 +26,10 @@ * RS780MC:0x9613 * RS780E: 0x9615 * RS785G: 0x9710 - just works, not much tested + * RS785C: 0x9711 + * RS785M: 0x9712 + * RS785MC:0x9713 + * RS785D: 0x9714 */ #include <console/console.h> #include <device/device.h> @@ -912,6 +916,26 @@ .vendor = PCI_VENDOR_ID_ATI, .device = PCI_DEVICE_ID_ATI_RS785G_INT_GFX, }; +static const struct pci_driver pcie_driver_785c __pci_driver = { + .ops = &pcie_ops, + .vendor = PCI_VENDOR_ID_ATI, + .device = PCI_DEVICE_ID_ATI_RS785C_INT_GFX, +}; +static const struct pci_driver pcie_driver_785m __pci_driver = { + .ops = &pcie_ops, + .vendor = PCI_VENDOR_ID_ATI, + .device = PCI_DEVICE_ID_ATI_RS785M_INT_GFX, +}; +static const struct pci_driver pcie_driver_785mc __pci_driver = { + .ops = &pcie_ops, + .vendor = PCI_VENDOR_ID_ATI, + .device = PCI_DEVICE_ID_ATI_RS785MC_INT_GFX, +}; +static const struct pci_driver pcie_driver_785d __pci_driver = { + .ops = &pcie_ops, + .vendor = PCI_VENDOR_ID_ATI, + .device = PCI_DEVICE_ID_ATI_RS785D_INT_GFX, +}; /* step 12 ~ step 14 from rpr */ static void single_port_configuration(device_t nb_dev, device_t dev) Index: src/include/device/pci_ids.h =================================================================== --- src/include/device/pci_ids.h (revision 6221) +++ src/include/device/pci_ids.h (working copy) @@ -341,6 +341,10 @@ #define PCI_DEVICE_ID_ATI_RS780MC_INT_GFX 0x9613 #define PCI_DEVICE_ID_ATI_RS780E_INT_GFX 0x9615 #define PCI_DEVICE_ID_ATI_RS785G_INT_GFX 0x9710 +#define PCI_DEVICE_ID_ATI_RS785C_INT_GFX 0x9711 +#define PCI_DEVICE_ID_ATI_RS785M_INT_GFX 0x9712 +#define PCI_DEVICE_ID_ATI_RS785MC_INT_GFX 0x9713 +#define PCI_DEVICE_ID_ATI_RS785D_INT_GFX 0x9714 #define PCI_VENDOR_ID_VLSI 0x1004 #define PCI_DEVICE_ID_VLSI_82C592 0x0005

3 2

[patch][superiotool] Add detection of Nuvoton WPCM450
by Bao, Zheng 30 Dec '10

30 Dec '10

Add detection of Nuvoton WPCM450. Signed-off-by: Zheng Bao <zheng.bao(a)amd.com> Index: util/superiotool/nuvoton.c =================================================================== --- util/superiotool/nuvoton.c (revision 6221) +++ util/superiotool/nuvoton.c (working copy) @@ -64,6 +64,8 @@ {0x30,0x60,0x61,0x70,0x71,0x74,0x75,0xf0,EOT}, {0x00,0x02,0xf8,0x03,0x03,0x04,0x04,0x02,EOT}}, {EOT}}}, + {0x1a, "WPCM450", { + {EOT}}}, {EOT} };

2 1

← Newer
1
2
3
4
5
6
7
8
...
27
Older →

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

2012

2011

2010

2009

2008

2007

2006

2005

2004

2003

2002

coreboot December 2010