coreboot December 2010

coreboot@coreboot.org

52 participants
262 discussions

by Marc Bertens

Signed-off: Marc Bertens <mbertens(a)xs4all.nl> Tested: Marc Bertens <mbertens(a)xs4all.nl> I added superio registers for mainly the AUX device, to get it as the orginal bios. With its the LEDs in the front panel can be controlled and the JP900 and JP901 can be read. I changed the flash ROM size 512Kb this was from the beginning a typo. I removed the board_enable code due that all is in the devicetree.cb file now. Changed the irq_tables.c to avoid IRQ9. At the moment eth0 and eth3 work properly. The Cardbus interface the inserting en eject works correct and is seen by the OS (Linux 2.6.35 (ubuntu distro) Hard disk and CDROM work correct on IDE0. TODO: - eth1 and eth2 those still work no completely (they are buggy) - IDE1 needs to be tested - USB connections need to be found on the board and enabled - the HACK in the /arch/x86/boot/pirq_tables.c still needs to be fixed. Marc

10 years, 1 month

[PATCH 1/2] Geode GX2 cleanup again

by Nils

For gx2/northbridgeinit.c -some white space fixes -some codingstyle fixes -some comment fixes. Signed-off-by: Nils Jacobs <njacobs8(a)hetnet.nl> Thanks, Nils.

10 years, 1 month

superiotool sometimes skips further SuperIO chips in the system - suggested remedy included

by Frantisek Rysanek

Dear maintainers of the superiotool, I have the following "feature request" (maybe not a bug report): I have this idea that superiotool should be able to detect more than one SuperIO chip in the system. Such detection of multiple chips may work in some cases, but may fail in others. The primary cause seems to be that winbond.c :: probe_idregs_winbond() and ite.c :: probe_idregs_ite() call if (chip_found) return; // this is a global variable! after every "init sequence" tried. Therefore, after the first chip detected (of any kind), only the first init sequence is ever tried, in any subsequent calls to the aforementioned probe_* functions. My immediate hack was to comment out all occurrences of if (chip_found) return; in those probe functions. Makes me wonder if this has some adverse effects, such as repeatedly scanning some EFER bases / init sequences by probes belonging to different chip families. And my conclusion for the moment is that this repeated probing should be harmless, and that the current behavior (stop after the first init sequence tried) is flawed anyway :-) My motivation is simple: right now I'm working with an embedded PC that has two SuperIO chips on the inside: W83627 + W83977. But I've seen other models in the past as well. Your SuperIOtool is quite useful for a quick overview of the SuperIO chips in the system, including a thorough dump of their registers. In the past I myself have written and reused some simple snippet of code / a tiny library (in DOS) to help me debug/tweak SuperIO stuff, but I never got as far as making it truly universal and extensible. As for SuperIOtool, I could fancy a writing capability, and maybe an external configuration file, potentially allowing for extensions without coding in C, maybe human-readable interpretations / annotations of the register dump etc - but I admit that's too much work to be worth the bother, certainly for me at the moment :-) Keep up the excellent work that you're doing... Frank Rysanek

10 years, 2 months

[PATCH 3/3] add amd sb800 support

by She, Kerry

add amd sb800 southbridge support Signed-off-by: Kerry She <Kerry.she(a)amd.com> Regards, Kerry She < kerry.she(a)amd.com> Tel: 86-10-6280-1415 Mobile: 86 - 152 1018 2083

10 years, 2 months

Seabios - VGA & Boot From First Hard Drive Issues

by Roger

1) If I use coreboot's "Run VGA Option ROMs", I can get VGA up and the first thing displayed is one text line of something like "SeaBIOS Version...". And then I usually get some of my other PCI devices option roms executing as well on the VGA display. But when I turn "Run VGA & other Option ROMs" off in Coreboot and then modify SeaBIOS config.h with any of these options: // Support finding and running option roms during post. #define CONFIG_OPTIONROMS 1 // Set if option roms are already copied to 0xc0000-0xf0000 #define CONFIG_OPTIONROMS_DEPLOYED 0 // When option roms are not pre-deployed, SeaBIOS can copy an optionrom // from flash for up to 2 devices. #define OPTIONROM_VENDEV_1 0x00000000 #define OPTIONROM_MEM_1 0xf9000000 #define OPTIONROM_VENDEV_2 0x00000000 #define OPTIONROM_MEM_2 0x00000000 I get no VGA display. I even tried specifying the address of PCI VGA 01:00, but I don't know if I have the correct address of the nvidia option rom. I had better success with letting coreboot copy the vga pci option rom into 0x0c000 (or 0xc000) and then letting SeaBIOS to try simply executing it. I would get the one line "Seabios Version ..." and then nothing else on the VGA console. 2) SeaBIOS seems to find a lot of things, but still tries to boot from floppy device (or image), for which I have neither. I thought SeaBIOS was able to boot from the first hard drive partition (ie. grub)? This is what I see on serial console along with the quick f12 boot pause. But pressing f12 only pauses longer with nothing else displayed via serial console. But, I can press ESC and have it reboot, or the wonderful Windows Key will print it's scancode on screen, but no other keys. (See very last lines in log.) Attaching log with max debug on. -- Roger http://rogerx.freeshell.org/

10 years, 2 months

[commit] r6228 - trunk

by repository service

Author: jakllsch Date: Fri Dec 31 20:20:23 2010 New Revision: 6228 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6228 Log: Use $(MAKE) instead of make when cleaning for SeaBIOS. Signed-off-by: Jonathan Kollasch <jakllsch(a)kollasch.net> Acked-by: Jonathan Kollasch <jakllsch(a)kollasch.net> Modified: trunk/Makefile Modified: trunk/Makefile ============================================================================== --- trunk/Makefile Fri Dec 31 02:46:12 2010 (r6227) +++ trunk/Makefile Fri Dec 31 20:20:23 2010 (r6228) @@ -363,7 +363,7 @@ rm -f $(obj)/mainboard/$(MAINBOARDDIR)/bootblock.* $(obj)/mainboard/$(MAINBOARDDIR)/dsdt.* rm -f $(obj)/cpu/x86/smm/smm_bin.c $(obj)/cpu/x86/smm/smm.* $(obj)/cpu/x86/smm/smm rmdir -p $(alldirs) 2>/dev/null >/dev/null || true - make -C payloads/external/SeaBIOS clean + $(MAKE) -C payloads/external/SeaBIOS clean clean: clean-for-update rm -f $(obj)/coreboot* .ccwrap

10 years, 2 months

Will coreboot work on my Acer Travelmate?

by Saku Sammakko

Hello Will coreboot work with the following hardware? Acer Travelmate 8100 main board (dmidecode): Acer Kingfisher cpu: Intel M 730 1,6GHz, 533MHz fsb, 2MB L2 cache northbridge (lspci): Intel Corporation Mobile 915GM/PM/GMS/910GML Express Processor to DRAM Controller (rev 03) southbridge (lspci): Intel Corporation 82801FB/FBM/FR/FW/FRW (ICH6 Family) memory: 2x512MB DDR2 SO-DIMM SDRAM vga: ATI Mobility Radeon X700 (PCIE) best regards, Saku Sammakko

10 years, 2 months

[commit] r6227 - in trunk/src: include/device southbridge/amd/rs780

by repository service

Author: zbao Date: Fri Dec 31 02:46:12 2010 New Revision: 6227 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6227 Log: Add RS785(RS880) support. Just few pci_ids. Signed-off-by: Zheng Bao <zheng.bao(a)amd.com> Acked-by: Stefan Reinauer <stepan(a)coreboot.org> Modified: trunk/src/include/device/pci_ids.h trunk/src/southbridge/amd/rs780/gfx.c Modified: trunk/src/include/device/pci_ids.h ============================================================================== --- trunk/src/include/device/pci_ids.h Fri Dec 31 02:38:45 2010 (r6226) +++ trunk/src/include/device/pci_ids.h Fri Dec 31 02:46:12 2010 (r6227) @@ -341,6 +341,10 @@ #define PCI_DEVICE_ID_ATI_RS780MC_INT_GFX 0x9613 #define PCI_DEVICE_ID_ATI_RS780E_INT_GFX 0x9615 #define PCI_DEVICE_ID_ATI_RS785G_INT_GFX 0x9710 +#define PCI_DEVICE_ID_ATI_RS785C_INT_GFX 0x9711 +#define PCI_DEVICE_ID_ATI_RS785M_INT_GFX 0x9712 +#define PCI_DEVICE_ID_ATI_RS785MC_INT_GFX 0x9713 +#define PCI_DEVICE_ID_ATI_RS785D_INT_GFX 0x9714 #define PCI_VENDOR_ID_VLSI 0x1004 #define PCI_DEVICE_ID_VLSI_82C592 0x0005 Modified: trunk/src/southbridge/amd/rs780/gfx.c ============================================================================== --- trunk/src/southbridge/amd/rs780/gfx.c Fri Dec 31 02:38:45 2010 (r6226) +++ trunk/src/southbridge/amd/rs780/gfx.c Fri Dec 31 02:46:12 2010 (r6227) @@ -26,6 +26,10 @@ * RS780MC:0x9613 * RS780E: 0x9615 * RS785G: 0x9710 - just works, not much tested + * RS785C: 0x9711 + * RS785M: 0x9712 + * RS785MC:0x9713 + * RS785D: 0x9714 */ #include <console/console.h> #include <device/device.h> @@ -912,6 +916,26 @@ .vendor = PCI_VENDOR_ID_ATI, .device = PCI_DEVICE_ID_ATI_RS785G_INT_GFX, }; +static const struct pci_driver pcie_driver_785c __pci_driver = { + .ops = &pcie_ops, + .vendor = PCI_VENDOR_ID_ATI, + .device = PCI_DEVICE_ID_ATI_RS785C_INT_GFX, +}; +static const struct pci_driver pcie_driver_785m __pci_driver = { + .ops = &pcie_ops, + .vendor = PCI_VENDOR_ID_ATI, + .device = PCI_DEVICE_ID_ATI_RS785M_INT_GFX, +}; +static const struct pci_driver pcie_driver_785mc __pci_driver = { + .ops = &pcie_ops, + .vendor = PCI_VENDOR_ID_ATI, + .device = PCI_DEVICE_ID_ATI_RS785MC_INT_GFX, +}; +static const struct pci_driver pcie_driver_785d __pci_driver = { + .ops = &pcie_ops, + .vendor = PCI_VENDOR_ID_ATI, + .device = PCI_DEVICE_ID_ATI_RS785D_INT_GFX, +}; /* step 12 ~ step 14 from rpr */ static void single_port_configuration(device_t nb_dev, device_t dev)

10 years, 2 months

[commit] r6226 - trunk/util/superiotool

by repository service

Author: zbao Date: Fri Dec 31 02:38:45 2010 New Revision: 6226 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6226 Log: Add detection of Nuvoton WPCM450. Signed-off-by: Zheng Bao <zheng.bao(a)amd.com> Acked-by: Stefan Reinauer <stepan(a)coreboot.org> Modified: trunk/util/superiotool/nuvoton.c Modified: trunk/util/superiotool/nuvoton.c ============================================================================== --- trunk/util/superiotool/nuvoton.c Thu Dec 30 20:23:29 2010 (r6225) +++ trunk/util/superiotool/nuvoton.c Fri Dec 31 02:38:45 2010 (r6226) @@ -64,6 +64,8 @@ {0x30,0x60,0x61,0x70,0x71,0x74,0x75,0xf0,EOT}, {0x00,0x02,0xf8,0x03,0x03,0x04,0x04,0x02,EOT}}, {EOT}}}, + {0x1a, "WPCM450", { + {EOT}}}, {EOT} };

10 years, 2 months

[PATCH 2/2] Geode GX2 cleanup again

by Nils

-update gx2/northbridgeinit.c to lx standards -remove not longer needed code from gx2/northbridge.c Signed-off-by: Nils Jacobs <njacobs8(a)hetnet.nl> Thanks, Nils.

10 years, 2 months

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coreboot December 2010