coreboot December 2010

coreboot@coreboot.org

52 participants
262 discussions

Re: [coreboot] DL145 G1 with dual dualcore CPU using coreboot ?
by Oskar Enoksson 28 Sep '11

28 Sep '11

Oskar Enoksson wrote: > Myles Watson wrote: > >>> I think Myles was right, there is a i2c mux in this server that somehow >>> multiplexes DIMM devices on the i2c bus. I was able to guess which i2c >>> ports contain the DIMM info, and which port is the mux, then added the >>> mux to devicetree.cb and the DIMM ports under it. Now I'm able to use >>> memory from both CPU's, at least for the combination of DIMM's I have >>> (2x2x1GB and 2x2x512MB). >>> >>> >> I'm glad it worked out! >> >> >>> So I'm basically able to use these servers now. I would love to have >>> ACPI and Cool'nQuiet of course, perhaps I'll try to do that later. >>> >>> Thanks very much for all help! If you want me to commit the new >>> mainboard to your svn repository let me know. >>> >>> >> Yes, please. If you'll send your latest patch with a Signed-off-by: line, >> I'll take it from there. >> >> Thanks, >> Myles >> >> > I hope this file is the way you want it. I did "svn cp > src/mainboard/tyan/s2881 src/mainboard/hp/dl145_g1" and then modified > the files, then "svn diff src/mainboard" so I assume you should do the > same svn cp operation, then apply my patch, then commit to retain the > original files' history. > I have fixed several problems and now it boots reliably for both and older dual Opteron 248 server and an upgraded dual Opteron 280 server. memtest86+ doesn't work, but according to another mailinglist thread memtest cannot handle tables in high memory, so that seems to be a memtest issue. Attached is a cleaned-up patch. Thanks to Myles and others for excellent help and support. I hope someone finds the result useful.

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[PATCH] More explicite and straight way to set seed
by Bao, Zheng 03 Jun '11

03 Jun '11

More explicite and straight way to set seed. Signed-off-by: Zheng Bao <zheng.bao(a)amd.com> Index: src/northbridge/amd/amdmct/mct/mctsrc.c =================================================================== --- src/northbridge/amd/amdmct/mct/mctsrc.c (revision 6135) +++ src/northbridge/amd/amdmct/mct/mctsrc.c (working copy) @@ -1023,13 +1023,9 @@ dev = pDCTstat->dev_dct; for (index = 0x50; index <= 0x52; index ++) { - val = Get_NB32_index_wait(dev, index_reg, index); - val |= (FenceTrnFinDlySeed & 0x1F); + val = (FenceTrnFinDlySeed & 0x1F); if (index != 0x52) { - val &= ~(0xFF << 8); - val |= (val & 0xFF) << 8; - val &= 0xFFFF; - val |= val << 16; + val |= val << 8 | val << 16 | val << 24; } Set_NB32_index_wait(dev, index_reg, index, val); } Index: src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c =================================================================== --- src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c (revision 6135) +++ src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c (working copy) @@ -972,13 +972,9 @@ */ dev = pDCTstat->dev_dct; for (index = 0x50; index <= 0x52; index ++) { - val = Get_NB32_index_wait(dev, index_reg, index) & ~0xFF; - val |= (FenceTrnFinDlySeed & 0x1F); + val = (FenceTrnFinDlySeed & 0x1F); if (index != 0x52) { - val &= ~(0xFF << 8); - val |= (val & 0xFF) << 8; - val &= 0xFFFF; - val |= val << 16; + val |= val << 8 | val << 16 | val << 24; } Set_NB32_index_wait(dev, index_reg, index, val); }

3 2

[patch] fix Windows 7 checked build assert caused by FADT length/revision inconsistency
by Scott Duplichan 18 Apr '11

18 Apr '11

Running a checked build of Windows is needed for understanding its various BIOS related BSODs. Win7 checked build complains when running coreboot+seabios: FADT revision inconsistent with length. Revision: 0x1 Length: 0xf4 Expected Length: 0x74 The following patch solves the problem. Tested on Mahogany_fam10 only. Signed-off-by: Scott Duplichan <scott(a)notabs.org> Index: src/southbridge/nvidia/ck804/ck804_fadt.c =================================================================== --- src/southbridge/nvidia/ck804/ck804_fadt.c (revision 5978) +++ src/southbridge/nvidia/ck804/ck804_fadt.c (working copy) @@ -20,10 +20,11 @@ memcpy(header->signature, "FACP", 4); #ifdef LONG_FADT header->length = 244; + header->revision = 3; #else header->length = 0x74; + header->revision = 1; #endif - header->revision = 1; memcpy(header->oem_id, "CORE ", 6); memcpy(header->oem_table_id, "CB-FADT ", 8); memcpy(header->asl_compiler_id, "IASL", 4); Index: src/mainboard/iwill/dk8_htx/fadt.c =================================================================== --- src/mainboard/iwill/dk8_htx/fadt.c (revision 5978) +++ src/mainboard/iwill/dk8_htx/fadt.c (working copy) @@ -19,7 +19,7 @@ memset((void *)fadt,0,sizeof(acpi_fadt_t)); memcpy(header->signature,"FACP",4); header->length = 244; - header->revision = 1; + header->revision = 3; memcpy(header->oem_id,OEM_ID,6); memcpy(header->oem_table_id,"COREBOOT",8); memcpy(header->asl_compiler_id,ASLC,4); Index: src/mainboard/asrock/939a785gmh/fadt.c =================================================================== --- src/mainboard/asrock/939a785gmh/fadt.c (revision 5978) +++ src/mainboard/asrock/939a785gmh/fadt.c (working copy) @@ -52,7 +52,7 @@ memset((void *)fadt, 0, sizeof(acpi_fadt_t)); memcpy(header->signature, "FACP", 4); header->length = 244; - header->revision = 1; + header->revision = 3; memcpy(header->oem_id, OEM_ID, 6); memcpy(header->oem_table_id, "COREBOOT", 8); memcpy(header->asl_compiler_id, ASLC, 4); Index: src/mainboard/kontron/kt690/fadt.c =================================================================== --- src/mainboard/kontron/kt690/fadt.c (revision 5978) +++ src/mainboard/kontron/kt690/fadt.c (working copy) @@ -52,7 +52,7 @@ memset((void *)fadt, 0, sizeof(acpi_fadt_t)); memcpy(header->signature, "FACP", 4); header->length = 244; - header->revision = 1; + header->revision = 3; memcpy(header->oem_id, OEM_ID, 6); memcpy(header->oem_table_id, "COREBOOT", 8); memcpy(header->asl_compiler_id, ASLC, 4); Index: src/mainboard/gigabyte/ma78gm/fadt.c =================================================================== --- src/mainboard/gigabyte/ma78gm/fadt.c (revision 5978) +++ src/mainboard/gigabyte/ma78gm/fadt.c (working copy) @@ -52,7 +52,7 @@ memset((void *)fadt, 0, sizeof(acpi_fadt_t)); memcpy(header->signature, "FACP", 4); header->length = 244; - header->revision = 1; + header->revision = 3; memcpy(header->oem_id, OEM_ID, 6); memcpy(header->oem_table_id, "COREBOOT", 8); memcpy(header->asl_compiler_id, ASLC, 4); Index: src/mainboard/gigabyte/ma785gmt/fadt.c =================================================================== --- src/mainboard/gigabyte/ma785gmt/fadt.c (revision 5978) +++ src/mainboard/gigabyte/ma785gmt/fadt.c (working copy) @@ -52,7 +52,7 @@ memset((void *)fadt, 0, sizeof(acpi_fadt_t)); memcpy(header->signature, "FACP", 4); header->length = 244; - header->revision = 1; + header->revision = 3; memcpy(header->oem_id, OEM_ID, 6); memcpy(header->oem_table_id, "COREBOOT", 8); memcpy(header->asl_compiler_id, ASLC, 4); Index: src/mainboard/amd/mahogany/fadt.c =================================================================== --- src/mainboard/amd/mahogany/fadt.c (revision 5978) +++ src/mainboard/amd/mahogany/fadt.c (working copy) @@ -52,7 +52,7 @@ memset((void *)fadt, 0, sizeof(acpi_fadt_t)); memcpy(header->signature, "FACP", 4); header->length = 244; - header->revision = 1; + header->revision = 3; memcpy(header->oem_id, OEM_ID, 6); memcpy(header->oem_table_id, "COREBOOT", 8); memcpy(header->asl_compiler_id, ASLC, 4); Index: src/mainboard/amd/pistachio/fadt.c =================================================================== --- src/mainboard/amd/pistachio/fadt.c (revision 5978) +++ src/mainboard/amd/pistachio/fadt.c (working copy) @@ -52,7 +52,7 @@ memset((void *)fadt, 0, sizeof(acpi_fadt_t)); memcpy(header->signature, "FACP", 4); header->length = 244; - header->revision = 1; + header->revision = 3; memcpy(header->oem_id, OEM_ID, 6); memcpy(header->oem_table_id, "COREBOOT", 8); memcpy(header->asl_compiler_id, ASLC, 4); Index: src/mainboard/amd/dbm690t/fadt.c =================================================================== --- src/mainboard/amd/dbm690t/fadt.c (revision 5978) +++ src/mainboard/amd/dbm690t/fadt.c (working copy) @@ -52,7 +52,7 @@ memset((void *)fadt, 0, sizeof(acpi_fadt_t)); memcpy(header->signature, "FACP", 4); header->length = 244; - header->revision = 1; + header->revision = 3; memcpy(header->oem_id, OEM_ID, 6); memcpy(header->oem_table_id, "COREBOOT", 8); memcpy(header->asl_compiler_id, ASLC, 4); Index: src/mainboard/amd/serengeti_cheetah/fadt.c =================================================================== --- src/mainboard/amd/serengeti_cheetah/fadt.c (revision 5978) +++ src/mainboard/amd/serengeti_cheetah/fadt.c (working copy) @@ -19,7 +19,7 @@ memset((void *)fadt,0,sizeof(acpi_fadt_t)); memcpy(header->signature,"FACP",4); header->length = 244; - header->revision = 1; + header->revision = 3; memcpy(header->oem_id,OEM_ID,6); memcpy(header->oem_table_id,"COREBOOT",8); memcpy(header->asl_compiler_id,ASLC,4); Index: src/mainboard/amd/mahogany_fam10/fadt.c =================================================================== --- src/mainboard/amd/mahogany_fam10/fadt.c (revision 5978) +++ src/mainboard/amd/mahogany_fam10/fadt.c (working copy) @@ -52,7 +52,7 @@ memset((void *)fadt, 0, sizeof(acpi_fadt_t)); memcpy(header->signature, "FACP", 4); header->length = 244; - header->revision = 1; + header->revision = 3; memcpy(header->oem_id, OEM_ID, 6); memcpy(header->oem_table_id, "COREBOOT", 8); memcpy(header->asl_compiler_id, ASLC, 4); Index: src/mainboard/amd/tilapia_fam10/fadt.c =================================================================== --- src/mainboard/amd/tilapia_fam10/fadt.c (revision 5978) +++ src/mainboard/amd/tilapia_fam10/fadt.c (working copy) @@ -52,7 +52,7 @@ memset((void *)fadt, 0, sizeof(acpi_fadt_t)); memcpy(header->signature, "FACP", 4); header->length = 244; - header->revision = 1; + header->revision = 3; memcpy(header->oem_id, OEM_ID, 6); memcpy(header->oem_table_id, "COREBOOT", 8); memcpy(header->asl_compiler_id, ASLC, 4); Index: src/mainboard/amd/serengeti_cheetah_fam10/fadt.c =================================================================== --- src/mainboard/amd/serengeti_cheetah_fam10/fadt.c (revision 5978) +++ src/mainboard/amd/serengeti_cheetah_fam10/fadt.c (working copy) @@ -40,7 +40,7 @@ memset((void *)fadt,0,sizeof(acpi_fadt_t)); memcpy(header->signature,"FACP",4); header->length = 244; - header->revision = 1; + header->revision = 3; memcpy(header->oem_id,OEM_ID,6); memcpy(header->oem_table_id,"COREBOOT",8); memcpy(header->asl_compiler_id,ASLC,4); Index: src/mainboard/iei/kino-780am2-fam10/fadt.c =================================================================== --- src/mainboard/iei/kino-780am2-fam10/fadt.c (revision 5978) +++ src/mainboard/iei/kino-780am2-fam10/fadt.c (working copy) @@ -52,7 +52,7 @@ memset((void *)fadt, 0, sizeof(acpi_fadt_t)); memcpy(header->signature, "FACP", 4); header->length = 244; - header->revision = 1; + header->revision = 3; memcpy(header->oem_id, OEM_ID, 6); memcpy(header->oem_table_id, "COREBOOT", 8); memcpy(header->asl_compiler_id, ASLC, 4); Index: src/mainboard/via/epia-m700/fadt.c =================================================================== --- src/mainboard/via/epia-m700/fadt.c (revision 5978) +++ src/mainboard/via/epia-m700/fadt.c (working copy) @@ -30,7 +30,7 @@ memset((void *)fadt, 0, sizeof(acpi_fadt_t)); memcpy(header->signature, "FACP", 4); header->length = 244; - header->revision = 1; + header->revision = 3; memcpy(header->oem_id, "VX800 ", 6); memcpy(header->oem_table_id, "LNXBACPI", 8); memcpy(header->asl_compiler_id, "LXB", 8); Index: src/mainboard/via/vt8454c/fadt.c =================================================================== --- src/mainboard/via/vt8454c/fadt.c (revision 5978) +++ src/mainboard/via/vt8454c/fadt.c (working copy) @@ -29,7 +29,7 @@ memset((void *) fadt, 0, sizeof(acpi_fadt_t)); memcpy(header->signature, "FACP", 4); header->length = 244; - header->revision = 1; + header->revision = 3; memcpy(header->oem_id, "CX700 ", 6); memcpy(header->oem_table_id, "COREBOOT", 8); memcpy(header->asl_compiler_id, "CORE", 4); Index: src/mainboard/via/epia-m/fadt.c =================================================================== --- src/mainboard/via/epia-m/fadt.c (revision 5978) +++ src/mainboard/via/epia-m/fadt.c (working copy) @@ -31,7 +31,7 @@ memset((void *)fadt,0,sizeof(acpi_fadt_t)); memcpy(header->signature,"FACP",4); header->length = 244; - header->revision = 1; + header->revision = 3; memcpy(header->oem_id,OEM_ID,6); memcpy(header->oem_table_id,"COREBOOT",8); memcpy(header->asl_compiler_id,ASLC,4); Index: src/mainboard/via/epia-n/fadt.c =================================================================== --- src/mainboard/via/epia-n/fadt.c (revision 5978) +++ src/mainboard/via/epia-n/fadt.c (working copy) @@ -33,7 +33,7 @@ memset((void *)fadt,0,sizeof(acpi_fadt_t)); memcpy(header->signature,"FACP",4); header->length = 244; - header->revision = 1; + header->revision = 3; memcpy(header->oem_id,OEM_ID,6); memcpy(header->oem_table_id,"COREBOOT",8); memcpy(header->asl_compiler_id,ASLC,4); Index: src/mainboard/jetway/pa78vm5/fadt.c =================================================================== --- src/mainboard/jetway/pa78vm5/fadt.c (revision 5978) +++ src/mainboard/jetway/pa78vm5/fadt.c (working copy) @@ -52,7 +52,7 @@ memset((void *)fadt, 0, sizeof(acpi_fadt_t)); memcpy(header->signature, "FACP", 4); header->length = 244; - header->revision = 1; + header->revision = 3; memcpy(header->oem_id, OEM_ID, 6); memcpy(header->oem_table_id, "COREBOOT", 8); memcpy(header->asl_compiler_id, ASLC, 4); Index: src/mainboard/technexion/tim8690/fadt.c =================================================================== --- src/mainboard/technexion/tim8690/fadt.c (revision 5978) +++ src/mainboard/technexion/tim8690/fadt.c (working copy) @@ -52,7 +52,7 @@ memset((void *)fadt, 0, sizeof(acpi_fadt_t)); memcpy(header->signature, "FACP", 4); header->length = 244; - header->revision = 1; + header->revision = 3; memcpy(header->oem_id, OEM_ID, 6); memcpy(header->oem_table_id, "COREBOOT", 8); memcpy(header->asl_compiler_id, ASLC, 4); Index: src/mainboard/technexion/tim5690/fadt.c =================================================================== --- src/mainboard/technexion/tim5690/fadt.c (revision 5978) +++ src/mainboard/technexion/tim5690/fadt.c (working copy) @@ -52,7 +52,7 @@ memset((void *)fadt, 0, sizeof(acpi_fadt_t)); memcpy(header->signature, "FACP", 4); header->length = 244; - header->revision = 1; + header->revision = 3; memcpy(header->oem_id, OEM_ID, 6); memcpy(header->oem_table_id, "COREBOOT", 8); memcpy(header->asl_compiler_id, ASLC, 4); Index: src/mainboard/intel/eagleheights/fadt.c =================================================================== --- src/mainboard/intel/eagleheights/fadt.c (revision 5978) +++ src/mainboard/intel/eagleheights/fadt.c (working copy) @@ -56,7 +56,7 @@ memset((void *) fadt, 0, sizeof(acpi_fadt_t)); memcpy(header->signature, "FACP", 4); header->length = 244; - header->revision = 1; + header->revision = 3; memcpy(header->oem_id, "CORE ", 6); memcpy(header->oem_table_id, "COREBOOT", 8); memcpy(header->asl_compiler_id, "CORE", 4); Index: src/mainboard/asus/m4a785-m/fadt.c =================================================================== --- src/mainboard/asus/m4a785-m/fadt.c (revision 5978) +++ src/mainboard/asus/m4a785-m/fadt.c (working copy) @@ -52,7 +52,7 @@ memset((void *)fadt, 0, sizeof(acpi_fadt_t)); memcpy(header->signature, "FACP", 4); header->length = 244; - header->revision = 1; + header->revision = 3; memcpy(header->oem_id, OEM_ID, 6); memcpy(header->oem_table_id, "COREBOOT", 8); memcpy(header->asl_compiler_id, ASLC, 4);

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Re: [coreboot] [PATCH] SECC Pentium 2/3 users are gonna love this
by Keith Hui 02 Mar '11

02 Mar '11

> > Please don't gzip patches, it lowers the chance of someone reviewing > them to zero ;-) I figured if we're coding at this level, gzip won't be a hurdle. I announced it up front, didn't I? :p > > There is 65x microcode in the model_67x directory, and it's not split up > into single files as for the other CPUs. > The microcodes are static and are not supposed to change, our CPU drivers are grouped by family, and the microcodes are going to be included one after another in one place anyway even when made separate, so why have 5 files for 5 microcodes in the 67x family for example when one will do? Of course I retained the comments therein that marks the microcodes and the processors they're intended for. To put things in perspective, the microcode data we get from Intel has hundreds of them all in one file. > + if (cpuid_res.ebx != 0x756e6547 || cpuid_res.edx != 0x49656e69 || > cpuid_res.ecx != 0x6c65746e) { > + printk(BIOS_INFO, "Not 'GenuineIntel' Processor"); > + return 0; > + } > > This is not necessary. When model_6**_init() is executed, it's clear > already that this is an intel cpu. I'm not sure if the check for choosing the CPU driver to execute is on these CPUID signatures, or through some other fields. This check is carried from v1. I agree we can take a chance and take it out; we'll revisit when something breaks. :D > > +/* if (signature & 0x1000) { > + printk(BIOS_DEBUG,"Overdrive chip no L2 cache configuration\n"); > + return 0; > + } > + > + if (signature < 0x630 || signature >= 0x680) { > + printk(BIOS_DEBUG,"L2 cache on CPUID %x does not require > configuration\n", signature); > + return 0; > + }*/ > > I think this code should just be dropped That may change when (IF) we manage to get coreboot on a socket 8 board on which a Pentium II OverDrive processor sits. Again this piece is from the original code from v1. I agree the second signature check is not needed. > > Is it generally possible to move p6_configure_l2_cache to a generic > place, maybe to cpu/x86/cache ? > > +/*--- End L2 init code from corebbot v1 ---*/ > > I think this kind of comment is not needed. > That's a marker to help preserve my sanity. :-p > +static inline void strcpy(char *dst, char *src) > +{ > + while (*src) *dst++ = *src++; > +} > > I know I am the idiot who introduced this in a model_xxx_init.c file, > but maybe we should move it to lib/strcpy.c ? Well, 63x and 67x don't even need this; they don't support the processor brand string that 6bx do. Same with the fill_processor_name() function. I'll just take them out entirely. > > +static struct cpu_device_id cpu_table[] = { > + { X86_VENDOR_INTEL, 0x0650 }, > + { X86_VENDOR_INTEL, 0x0651 }, > + { X86_VENDOR_INTEL, 0x0652 }, > + { X86_VENDOR_INTEL, 0x0653 }, > + { X86_VENDOR_INTEL, 0x0671 }, > + { X86_VENDOR_INTEL, 0x0672 }, > + { X86_VENDOR_INTEL, 0x0673 }, > + { 0, 0 }, > +}; > > Instead of using a common driver, can two drivers use a common set of > shared functions instead? > It's already partially done. src/cpu/intel/model_67x/l2_cache.c (new in this patch) is linked in by model_65x driver too. Next prime suspect: fill_processor_name() in 6bx and a few other CPU models I'm no expert of. But 65x and 67x really are so similar that one driver can do both. Now is our end goal here to spin off model_63x/65x/66x/67x/68x/6ax/6bx all into their own CPU drivers when most of what's being done is duplicating code from model_6xx which is what they collectively once were? What's the rationale behind this need for split? I think a split should only be done when different initialization sequence are needed, eg. the special L2 initialization sequence for these SECC P6s. Same with motherboard models. When P2B-LS support matures I'd probably use the same directory for P2B-L and P2B-S support. They share the same circuit board anyway, and a -LS can emulate both by moving two jumpers. > +ifeq ($(CONFIG_USE_DCACHE_RAM),y) > +cpu_incs += $(src)/cpu/intel/car/cache_as_ram.inc > +endif > > This will break all targets except the ones you worked on. > I read this and thought, "I gotta run abuild." So I did. The errors I saw all seems to be k8/k10 targets and/or ACPI related. Even the entire P2B family that is in the tree passed abuild with this patch applied. Oh they haven't been migrated to CAR yet. Thanks Keith

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coreboot certified hardware
by Carl-Daniel Hailfinger 02 Mar '11

02 Mar '11

Hi, I wonder if we want to establish something like the "Designed for Windows XP" or "Yes it runs with Netware" certificates? It would certainly be a nice marketing aid for vendors, and at the same time it would promote coreboot visibility. If there is interest in such an idea, we will have to decide which criteria have to be fulfilled to get such a certificate, and if the certificate has an expiry date and/or is bound to a specific svn revision. Off the top of my head, I can think of the following criteria: - coreboot+SeaBIOS works well enough to boot $ENTERPRISE_LINUX, $ENDUSER_LINUX and Windows 7 (Vista and XP as well?) - Nvidia and ATI graphics drivers (both free and closed) work if booted with a coreboot+SeaBIOS image? - Frequency scaling and the various suspend methods work - Soft poweroff works - IRQ routing and all PCI/PCIe/AGP/whatever slots work - Legacy ports (if present) work - Fans work well enough (temperature-based scaling if present in the "normal" BIOS) - Source for a working coreboot image (including the Kconfig settings for the board, and possibly NVRAM settings?) is available for free without NDA - Board port merged into coreboot svn - SeaBIOS source code is available - SeaBIOS code is merged into SeaBIOS git - flashrom works on the board (no lockdown) or there is a way to boot unlocked and run flashrom for your image of choice - At least some serial output (coreboot version) if a serial port (header) is present, otherwise... USB Debug? Floppy? LPC bus? POST card on port 82h? Did I forget something? Are some criteria useless? What would Jane User expect from a normal mainboard if she didn't know coreboot was running? Regards, Carl-Daniel -- http://www.hailfinger.org/

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[PATCH] RFC AMD powernow generation for pre fam 0fh
by Rudolf Marek 24 Feb '11

24 Feb '11

Hi all, This is RFC patch. It adds support for automatic PSS object generation for AMD pre fam Fh CPU. Those CPUs require a hardcoded table, which I managed to rewrite during one particularly boring flight. Too pity it is only for Opteron CPUs. Someone needs to finish the second PDF for All others Athlons and Semprons. It just adds the table to same place where is the fam0fh generator. To make the powernow work on my Asrock 939 board I had to enable undocumented bit1 in PM_Misc 67h of SB710. It looks like this bit is documented in SB600 and it is doing LDT_STOP toggle for C states (and for FID/VID). I remember I had to fix this toggle for VIA chipset too. It took me some time to figure it out. It helped that it started to work if the orig bios was booted and halted to S5. All search was to find out what register was not updated by coreboot). Whom to ask to fix the AMD documentation? It is unknown if the bit is necessary for fam 0fh or fam10h, question is if the second bit CC_en which says: "C State enable. This bit must be set in order to exercise the C state" should be enabled (it is for me with orig BIOS). Thanks, Rudolf

3 3

Test SeaBIOS AHCI support
by Kevin O'Connor 30 Jan '11

30 Jan '11

Hi, One of the qemu developers added AHCI support to SeaBIOS. This support has been tested on qemu, but not on real hardware. It would be great if folks with coreboot supported hardware could also test it. (Unfortunately, my coreboot board doesn't have AHCI.) To test, grab the latest seabios git (see: http://seabios.org/Download ), edit src/config.h and enable CONFIG_AHCI. (Be sure to also set the other coreboot settings - see: http://www.coreboot.org/SeaBIOS .) Thanks, -Kevin

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[patch][superiotool] Add w83527hg support
by Bao, Zheng 26 Jan '11

26 Jan '11

The datasheet is available on nuvoton's website. http://www.nuvoton.com/NuvotonMOSS/Community/ProductInfo.aspx?tp_GUID=cf 73485c-9e0a-4218-9bee-89dfe9a7bb87 Signed-off-by: Zheng Bao <zheng.bao(a)amd.com> Index: util/superiotool/winbond.c =================================================================== --- util/superiotool/winbond.c (revision 6169) +++ util/superiotool/winbond.c (working copy) @@ -345,6 +345,30 @@ {EOT}}}, {0xb07, "W83527HG", { /* TODO: Not yet in sensors-detect */ + {NOLDN, NULL, + {0x02,0x20,0x21,0x22,0x23,0x24,0x25,0x26,0x28,0x29, + 0x2a,0x2c,0x2d,0x2e,0x2f,EOT}, + {0x00,0xB0,0x73,0xff,0x00,MISC,0x00,0x00,0x50,0x00, + 0x00,0xe2,0x21,0x00,0x00,EOT}}, + {0x5, "Keyboard", + {0x30,0x60,0x61,0x62,0x63,0x70,0x72,0xf0,EOT}, + {0x01,0x00,0x60,0x00,0x64,0x01,0x0c,0x83,EOT}}, + {0x8, "Watchdog timer", + {0x30,0xf5,0xf6,0xf7,EOT}, + {0x00,0x00,0x00,0x00,EOT}}, + {0x9, "GPIO 2, GPIO3, GPIO5", + {0x30,0xe0,0xe1,0xe2,0xe3,0xe4,0xe5,0xe6,0xe7,0xe9, + 0xf0,0xf1,0xf2,0xf3,0xf8,0xf9,0xfa,0xfe,EOT}, + {0x00,0xff,0x00,0x00,0xff,0x00,0x00,0x00,0x00,0x00, + 0xff,0x00,0x00,0x00,0x00,0x00,0x00,0x00,EOT}}, + {0xa, "ACPI", + {0x30,0x70,0xe0,0xe1,0xe2,0xe3,0xe4,0xe5,0xe6,0xe7, + 0xf2,0xf3,0xf4,0xf6,0xf7,0xfe,EOT}, + {0x00,0x00,0x00,0x00,NANA,NANA,0x00,0x00,0x1c,0x00, + 0x7c,0x00,0x00,0x00,0x00,0x00,EOT}}, + {0xb, "Hardware monitor", + {0x30,0x60,0x61,0x70,0xf0,0xf2,EOT}, + {0x00,0x00,0x00,0x00,0x81,0x00,EOT}}, {EOT}}}, /* ID only */ {0x52, "W83627HF/F/HG/G", {

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Licensing question
by Vibrans, Frank 18 Jan '11

18 Jan '11

Hi All, The Open Source Review Board of AMD has decided the upcoming release of Agesa and the chipset CIM modules for our Family14h CPU will be under a dual license: GPLv2 and BSD. As the coreboot community, do you have any issue with this? If not, are there any specific coreboot requirements that must be met because of the dual license scheme? Thanks for your help. Frank Vibrans

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[commit] r5902 - in trunk/src: cpu/amd/car cpu/intel/car cpu/intel/model_106cx cpu/intel/model_6ex cpu/intel/model_6fx cpu/via/car include/cpu/x86
by repository service 17 Jan '11

17 Jan '11

Author: uwe Date: Fri Oct 1 23:46:04 2010 New Revision: 5902 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5902 Log: Factor out common CAR asm snippets. This makes the CAR implementations a lot more readable, shorter and easier to follow, and also reduces the amount of uselessly duplicated code. For example there are more than 12 open-coded "enable cache" instances spread all over the place (and 12 "disable cache" ones), multiple "enable mtrr", "save BIST", "restore BIST", etc. etc. Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Peter Stuge <peter(a)stuge.se> Added: trunk/src/include/cpu/x86/car.h Modified: trunk/src/cpu/amd/car/cache_as_ram.inc trunk/src/cpu/intel/car/cache_as_ram.inc trunk/src/cpu/intel/model_106cx/cache_as_ram.inc trunk/src/cpu/intel/model_6ex/cache_as_ram.inc trunk/src/cpu/intel/model_6fx/cache_as_ram.inc trunk/src/cpu/via/car/cache_as_ram.inc Modified: trunk/src/cpu/amd/car/cache_as_ram.inc ============================================================================== --- trunk/src/cpu/amd/car/cache_as_ram.inc Fri Oct 1 19:37:45 2010 (r5901) +++ trunk/src/cpu/amd/car/cache_as_ram.inc Fri Oct 1 23:46:04 2010 (r5902) @@ -18,6 +18,7 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#include <cpu/x86/car.h> #include <cpu/x86/mtrr.h> #include <cpu/amd/mtrr.h> @@ -45,8 +46,7 @@ * xmm3: Backup EBX */ - /* Save the BIST result. */ - movl %eax, %ebp + save_bist_result() /* * For normal part %ebx already contain cpu_init_detected @@ -56,10 +56,7 @@ cache_as_ram_setup: post_code(0xa0) - /* Enable SSE. */ - movl %cr4, %eax - orl $(3 << 9), %eax - movl %eax, %cr4 + enable_sse() /* Figure out the CPU family. */ cvtsi2sd %ebx, %xmm3 @@ -299,10 +296,7 @@ post_code(0xa1) - /* Enable cache. */ - movl %cr0, %eax - andl $(~((1 << 30) | (1 << 29))), %eax - movl %eax, %cr0 + enable_cache() jmp_if_k8(fam10_end_part1) @@ -384,13 +378,9 @@ post_code(0xa5) - /* Disable SSE. */ - movl %cr4, %eax - andl $~(3 << 9), %eax - movl %eax, %cr4 + disable_sse() - /* Restore the BIST result. */ - movl %ebp, %eax + restore_bist_result() /* We need to set EBP? No need. */ movl %esp, %ebp Modified: trunk/src/cpu/intel/car/cache_as_ram.inc ============================================================================== --- trunk/src/cpu/intel/car/cache_as_ram.inc Fri Oct 1 19:37:45 2010 (r5901) +++ trunk/src/cpu/intel/car/cache_as_ram.inc Fri Oct 1 23:46:04 2010 (r5902) @@ -21,6 +21,7 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#include <cpu/x86/car.h> #include <cpu/x86/stack.h> #include <cpu/x86/mtrr.h> #include <cpu/x86/lapic_def.h> @@ -28,8 +29,7 @@ #define CacheSize CONFIG_DCACHE_RAM_SIZE #define CacheBase (0xd0000 - CacheSize) - /* Save the BIST result. */ - movl %eax, %ebp + save_bist_result() CacheAsRam: /* Check whether the processor has HT capability. */ @@ -231,10 +231,7 @@ wrmsr #endif /* CONFIG_XIP_ROM_SIZE && CONFIG_XIP_ROM_BASE */ - /* Enable cache. */ - movl %cr0, %eax - andl $(~((1 << 30) | (1 << 29))), %eax - movl %eax, %cr0 + enable_cache() /* Read the range with lodsl. */ movl $CacheBase, %esi @@ -295,8 +292,7 @@ movl $(CacheBase + CacheSize - 4), %eax movl %eax, %esp lout: - /* Restore the BIST result. */ - movl %ebp, %eax + restore_bist_result() /* We need to set EBP? No need. */ movl %esp, %ebp @@ -305,10 +301,7 @@ /* We don't need CAR from now on. */ - /* Disable cache. */ - movl %cr0, %eax - orl $(1 << 30), %eax - movl %eax, %cr0 + disable_cache() /* Clear sth. */ movl $MTRRfix4K_C8000_MSR, %ecx @@ -330,10 +323,7 @@ movl $0x00000800, %eax /* Enable variable and disable fixed MTRRs. */ wrmsr - /* Enable cache. */ - movl %cr0, %eax - andl $(~((1 << 30) | (1 << 29))), %eax - movl %eax, %cr0 + enable_cache(); /* Clear boot_complete flag. */ xorl %ebp, %ebp Modified: trunk/src/cpu/intel/model_106cx/cache_as_ram.inc ============================================================================== --- trunk/src/cpu/intel/model_106cx/cache_as_ram.inc Fri Oct 1 19:37:45 2010 (r5901) +++ trunk/src/cpu/intel/model_106cx/cache_as_ram.inc Fri Oct 1 23:46:04 2010 (r5902) @@ -18,14 +18,14 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#include <cpu/x86/car.h> #include <cpu/x86/stack.h> #include <cpu/x86/mtrr.h> #define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE #define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE - /* Save the BIST result. */ - movl %eax, %ebp + save_bist_result() cache_as_ram: post_code(0x20) @@ -66,19 +66,12 @@ xorl %edx, %edx wrmsr - /* Enable MTRR. */ - movl $MTRRdefType_MSR, %ecx - rdmsr - orl $(1 << 11), %eax - wrmsr + enable_mtrr() - /* Enable L2 cache. */ - movl $0x11e, %ecx - rdmsr - orl $(1 << 8), %eax - wrmsr + enable_l2_cache() /* Enable cache (CR0.CD = 0, CR0.NW = 0). */ + /* TODO: enable_cache()? But that doesn't have "invd". */ movl %cr0, %eax andl $(~((1 << 30) | (1 << 29))), %eax invd @@ -93,9 +86,7 @@ rep stosl /* Enable Cache-as-RAM mode by disabling cache. */ - movl %cr0, %eax - orl $(1 << 30), %eax - movl %eax, %cr0 + disable_cache() #if defined(CONFIG_XIP_ROM_SIZE) && defined(CONFIG_XIP_ROM_BASE) /* Enable cache for our code in Flash because we do XIP here */ @@ -116,10 +107,7 @@ wrmsr #endif /* CONFIG_XIP_ROM_SIZE && CONFIG_XIP_ROM_BASE */ - /* Enable cache. */ - movl %cr0, %eax - andl $(~((1 << 30) | (1 << 29))), %eax - movl %eax, %cr0 + enable_cache() /* Set up the stack pointer. */ #if defined(CONFIG_USBDEBUG) && (CONFIG_USBDEBUG == 1) @@ -130,8 +118,8 @@ #endif movl %eax, %esp - /* Restore the BIST result. */ - movl %ebp, %eax + restore_bist_result() + movl %esp, %ebp pushl %eax @@ -144,18 +132,11 @@ post_code(0x30) - /* Disable cache. */ - movl %cr0, %eax - orl $(1 << 30), %eax - movl %eax, %cr0 + disable_cache() post_code(0x31) - /* Disable MTRR. */ - movl $MTRRdefType_MSR, %ecx - rdmsr - andl $(~(1 << 11)), %eax - wrmsr + disable_mtrr() post_code(0x31) @@ -175,17 +156,11 @@ post_code(0x33) - /* Enable cache. */ - movl %cr0, %eax - andl $~((1 << 30) | (1 << 29)), %eax - movl %eax, %cr0 + enable_cache() post_code(0x36) - /* Disable cache. */ - movl %cr0, %eax - orl $(1 << 30), %eax - movl %eax, %cr0 + disable_cache() post_code(0x38) @@ -202,17 +177,11 @@ post_code(0x39) /* And enable cache again after setting MTRRs. */ - movl %cr0, %eax - andl $~((1 << 30) | (1 << 29)), %eax - movl %eax, %cr0 + enable_cache() post_code(0x3a) - /* Enable MTRR. */ - movl $MTRRdefType_MSR, %ecx - rdmsr - orl $(1 << 11), %eax - wrmsr + enable_mtrr() post_code(0x3b) Modified: trunk/src/cpu/intel/model_6ex/cache_as_ram.inc ============================================================================== --- trunk/src/cpu/intel/model_6ex/cache_as_ram.inc Fri Oct 1 19:37:45 2010 (r5901) +++ trunk/src/cpu/intel/model_6ex/cache_as_ram.inc Fri Oct 1 23:46:04 2010 (r5902) @@ -18,14 +18,14 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#include <cpu/x86/car.h> #include <cpu/x86/stack.h> #include <cpu/x86/mtrr.h> #define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE #define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE - /* Save the BIST result. */ - movl %eax, %ebp + save_bist_result() cache_as_ram: post_code(0x20) @@ -66,19 +66,12 @@ movl $0x0000000f, %edx wrmsr - /* Enable MTRR. */ - movl $MTRRdefType_MSR, %ecx - rdmsr - orl $(1 << 11), %eax - wrmsr + enable_mtrr() - /* Enable L2 cache. */ - movl $0x11e, %ecx - rdmsr - orl $(1 << 8), %eax - wrmsr + enable_l2_cache() /* Enable cache (CR0.CD = 0, CR0.NW = 0). */ + /* TODO: enable_cache()? But that doesn't have "invd". */ movl %cr0, %eax andl $(~((1 << 30) | (1 << 29))), %eax invd @@ -93,9 +86,7 @@ rep stosl /* Enable Cache-as-RAM mode by disabling cache. */ - movl %cr0, %eax - orl $(1 << 30), %eax - movl %eax, %cr0 + disable_cache() #if defined(CONFIG_XIP_ROM_SIZE) && defined(CONFIG_XIP_ROM_BASE) /* Enable cache for our code in Flash because we do XIP here */ @@ -116,10 +107,7 @@ wrmsr #endif /* CONFIG_XIP_ROM_SIZE && CONFIG_XIP_ROM_BASE */ - /* Enable cache. */ - movl %cr0, %eax - andl $(~((1 << 30) | (1 << 29))), %eax - movl %eax, %cr0 + enable_cache() /* Set up the stack pointer. */ #if defined(CONFIG_USBDEBUG) && (CONFIG_USBDEBUG == 1) @@ -130,8 +118,8 @@ #endif movl %eax, %esp - /* Restore the BIST result. */ - movl %ebp, %eax + restore_bist_result() + movl %esp, %ebp pushl %eax @@ -144,18 +132,11 @@ post_code(0x30) - /* Disable cache. */ - movl %cr0, %eax - orl $(1 << 30), %eax - movl %eax, %cr0 + disable_cache() post_code(0x31) - /* Disable MTRR. */ - movl $MTRRdefType_MSR, %ecx - rdmsr - andl $(~(1 << 11)), %eax - wrmsr + disable_mtrr() post_code(0x31) @@ -175,17 +156,11 @@ post_code(0x33) - /* Enable cache. */ - movl %cr0, %eax - andl $~((1 << 30) | (1 << 29)), %eax - movl %eax, %cr0 + enable_cache() post_code(0x36) - /* Disable cache. */ - movl %cr0, %eax - orl $(1 << 30), %eax - movl %eax, %cr0 + disable_cache() post_code(0x38) @@ -202,17 +177,11 @@ post_code(0x39) /* And enable cache again after setting MTRRs. */ - movl %cr0, %eax - andl $~((1 << 30) | (1 << 29)), %eax - movl %eax, %cr0 + enable_cache() post_code(0x3a) - /* Enable MTRR. */ - movl $MTRRdefType_MSR, %ecx - rdmsr - orl $(1 << 11), %eax - wrmsr + enable_mtrr() post_code(0x3b) Modified: trunk/src/cpu/intel/model_6fx/cache_as_ram.inc ============================================================================== --- trunk/src/cpu/intel/model_6fx/cache_as_ram.inc Fri Oct 1 19:37:45 2010 (r5901) +++ trunk/src/cpu/intel/model_6fx/cache_as_ram.inc Fri Oct 1 23:46:04 2010 (r5902) @@ -18,14 +18,14 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#include <cpu/x86/car.h> #include <cpu/x86/stack.h> #include <cpu/x86/mtrr.h> #define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE #define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE - /* Save the BIST result. */ - movl %eax, %ebp + save_bist_result() cache_as_ram: post_code(0x20) @@ -73,19 +73,12 @@ movl $0x0000000f, %edx wrmsr - /* Enable MTRR. */ - movl $MTRRdefType_MSR, %ecx - rdmsr - orl $(1 << 11), %eax - wrmsr + enable_mtrr() - /* Enable L2 cache. */ - movl $0x11e, %ecx - rdmsr - orl $(1 << 8), %eax - wrmsr + enable_l2_cache() /* Enable cache (CR0.CD = 0, CR0.NW = 0). */ + /* TODO: enable_cache()? But that doesn't have "invd". */ movl %cr0, %eax andl $(~((1 << 30) | (1 << 29))), %eax invd @@ -100,9 +93,7 @@ rep stosl /* Enable Cache-as-RAM mode by disabling cache. */ - movl %cr0, %eax - orl $(1 << 30), %eax - movl %eax, %cr0 + disable_cache() #if defined(CONFIG_XIP_ROM_SIZE) && defined(CONFIG_XIP_ROM_BASE) /* Enable cache for our code in Flash because we do XIP here */ @@ -123,10 +114,7 @@ wrmsr #endif /* CONFIG_XIP_ROM_SIZE && CONFIG_XIP_ROM_BASE */ - /* Enable cache. */ - movl %cr0, %eax - andl $(~((1 << 30) | (1 << 29))), %eax - movl %eax, %cr0 + enable_cache() /* Set up the stack pointer. */ #if defined(CONFIG_USBDEBUG) && (CONFIG_USBDEBUG == 1) @@ -137,8 +125,8 @@ #endif movl %eax, %esp - /* Restore the BIST result. */ - movl %ebp, %eax + restore_bist_result() + movl %esp, %ebp pushl %eax @@ -151,18 +139,11 @@ post_code(0x30) - /* Disable cache. */ - movl %cr0, %eax - orl $(1 << 30), %eax - movl %eax, %cr0 + disable_cache() post_code(0x31) - /* Disable MTRR. */ - movl $MTRRdefType_MSR, %ecx - rdmsr - andl $(~(1 << 11)), %eax - wrmsr + disable_mtrr() post_code(0x31) @@ -182,17 +163,11 @@ post_code(0x33) - /* Enable cache. */ - movl %cr0, %eax - andl $~((1 << 30) | (1 << 29)), %eax - movl %eax, %cr0 + enable_cache() post_code(0x36) - /* Disable cache. */ - movl %cr0, %eax - orl $(1 << 30), %eax - movl %eax, %cr0 + disable_cache() post_code(0x38) @@ -209,17 +184,11 @@ post_code(0x39) /* And enable cache again after setting MTRRs. */ - movl %cr0, %eax - andl $~((1 << 30) | (1 << 29)), %eax - movl %eax, %cr0 + enable_cache() post_code(0x3a) - /* Enable MTRR. */ - movl $MTRRdefType_MSR, %ecx - rdmsr - orl $(1 << 11), %eax - wrmsr + enable_mtrr() post_code(0x3b) Modified: trunk/src/cpu/via/car/cache_as_ram.inc ============================================================================== --- trunk/src/cpu/via/car/cache_as_ram.inc Fri Oct 1 19:37:45 2010 (r5901) +++ trunk/src/cpu/via/car/cache_as_ram.inc Fri Oct 1 23:46:04 2010 (r5902) @@ -25,21 +25,18 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#include <cpu/x86/car.h> #include <cpu/x86/stack.h> #include <cpu/x86/mtrr.h> #define CacheSize CONFIG_DCACHE_RAM_SIZE #define CacheBase CONFIG_DCACHE_RAM_BASE - /* Save the BIST result. */ - movl %eax, %ebp + save_bist_result() CacheAsRam: - /* Disable cache. */ - movl %cr0, %eax - orl $(1 << 30), %eax - movl %eax, %cr0 + disable_cache() invd /* Set the default memory type and enable fixed and variable MTRRs. */ @@ -116,10 +113,7 @@ movl $(MTRRdefTypeEn), %eax wrmsr - /* Enable cache. */ - movl %cr0, %eax - andl $(~((1 << 30) | (1 << 29))), %eax - movl %eax, %cr0 + enable_cache() /* Read the range with lodsl. */ cld @@ -175,8 +169,7 @@ jne stackerr #endif - /* Restore the BIST result. */ - movl %ebp, %eax + restore_bist_result() /* We need to set EBP? No need. */ movl %esp, %ebp @@ -191,10 +184,7 @@ /* We don't need CAR from now on. */ - /* Disable cache. */ - movl %cr0, %eax - orl $(1 << 30), %eax - movl %eax, %cr0 + disable_cache() /* Set the default memory type and enable variable MTRRs. */ /* TODO: Or also enable fixed MTRRs? Bug in the code? */ @@ -253,10 +243,7 @@ movl $(~(CONFIG_XIP_ROM_SIZE - 1) | 0x800), %eax wrmsr - /* Enable cache. */ - movl %cr0, %eax - andl $(~((1 << 30) | (1 << 29))), %eax - movl %eax, %cr0 + enable_cache() invd /* Clear boot_complete flag. */ Added: trunk/src/include/cpu/x86/car.h ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/include/cpu/x86/car.h Fri Oct 1 23:46:04 2010 (r5902) @@ -0,0 +1,75 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2000,2007 Ronald G. Minnich <rminnich(a)gmail.com> + * Copyright (C) 2007-2008 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <cpu/x86/mtrr.h> + +/* Save the BIST result. */ +#define save_bist_result() \ + movl %eax, %ebp + +/* Restore the BIST result. */ +#define restore_bist_result() \ + movl %ebp, %eax + +/* Enable cache. */ +#define enable_cache() \ + movl %cr0, %eax; \ + andl $(~((1 << 30) | (1 << 29))), %eax; \ + movl %eax, %cr0 + +/* Disable cache. */ +#define disable_cache() \ + movl %cr0, %eax; \ + orl $(1 << 30), %eax; \ + movl %eax, %cr0 + +/* Enable MTRR. */ +#define enable_mtrr() \ + movl $MTRRdefType_MSR, %ecx; \ + rdmsr; \ + orl $(1 << 11), %eax; \ + wrmsr + +/* Disable MTRR. */ +#define disable_mtrr() \ + movl $MTRRdefType_MSR, %ecx; \ + rdmsr; \ + andl $(~(1 << 11)), %eax; \ + wrmsr + +/* Enable L2 cache. */ +#define enable_l2_cache() \ + movl $0x11e, %ecx; \ + rdmsr; \ + orl $(1 << 8), %eax; \ + wrmsr + +/* Enable SSE. */ +#define enable_sse() \ + movl %cr4, %eax; \ + orl $(3 << 9), %eax; \ + movl %eax, %cr4 + +/* Disable SSE. */ +#define disable_sse() \ + movl %cr4, %eax; \ + andl $~(3 << 9), %eax; \ + movl %eax, %cr4 +

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coreboot December 2010