2010/12/25 Rudolf Marek <r.marek(a)assembler.cz>cz>:
This is RFC patch. It adds support for automatic PSS object generation for
AMD pre fam Fh CPU. Those CPUs require a hardcoded table, which I managed to
rewrite during one particularly boring flight. Too pity it is only for
Opteron CPUs. Someone needs to finish the second PDF for All others Athlons
It just adds the table to same place where is the fam0fh generator. To make
the powernow work on my Asrock 939 board I had to enable undocumented bit1
in PM_Misc 67h of SB710. It looks like this bit is documented in SB600 and
it is doing LDT_STOP toggle for C states (and for FID/VID). I remember I had
to fix this toggle for VIA chipset too. It took me some time to figure it
out. It helped that it started to work if the orig bios was booted and
halted to S5.
All search was to find out what register was not updated by coreboot).
Whom to ask to fix the AMD documentation?
I don't know if this is the case for this bit, but some registers are
only documented in the register programming requirements document
(rpr) and not in the register reference guide (rrg). This is
intentional by AMD and they probably won't be changed.
Frank Vibrans is on this list and should be able to relay the request
back to the document gatekeepers next week, when they get back from
the holiday shutdown.