coreboot September 2009

coreboot@coreboot.org

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305 discussions

[BuildROM] r272 - buildrom-devel/packages/grub2
by svn＠coreboot.org 04 Sep '09

04 Sep '09

Author: myles Date: 2009-09-04 15:06:59 +0200 (Fri, 04 Sep 2009) New Revision: 272 Modified: buildrom-devel/packages/grub2/grub2.mk Log: Force symlink creation so grub2 builds when the symlink already exists. Signed-off-by: Nathan Williams <nathan(a)traverse.com.au> Acked-by: Myles Watson <mylesgw(a)gmail.com> Modified: buildrom-devel/packages/grub2/grub2.mk =================================================================== --- buildrom-devel/packages/grub2/grub2.mk 2009-09-02 21:41:13 UTC (rev 271) +++ buildrom-devel/packages/grub2/grub2.mk 2009-09-04 13:06:59 UTC (rev 272) @@ -48,7 +48,7 @@ @ echo "Using custom config $(GRUB2_CONFIG)" endif @ echo "Building grub2..." - @ ln -s $(GRUB2_SRC_DIR)/config.log $(GRUB2_LOG_DIR) + @ ln -sf $(GRUB2_SRC_DIR)/config.log $(GRUB2_LOG_DIR) @ (cd $(GRUB2_SRC_DIR) ; sh ./autogen.sh >> $(GRUB2_BUILD_LOG) 2>&1) @ (cd $(GRUB2_SRC_DIR) ; export LIBS= CC= LDFLAGS= CFLAGS=; ./configure --with-platform=coreboot --prefix=$(STAGING_DIR) >> $(GRUB2_BUILD_LOG) 2>&1) @ make -C $(GRUB2_SRC_DIR) >> $(GRUB2_BUILD_LOG) 2>&1

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K8 machine with (a lot of) ram from 2 vendors keeps resetting
by Ward Vandewege 03 Sep '09

03 Sep '09

Hi all, I'm having some problems with a supermicro h8dme board with 2 K8 processors and 64 GB of ram. Sadly, the ram is of two types (that was not my decision :/). We have 8x 4GB Samsung M393T5160QZA-CE6 and 8x 4GB Kingston KVR667D2D4P5/4G. Both of these types of ram are dual rank DDR2, 667 MHz, CL5, 1.8 V, registered, ECC. The memory is installed like this: BANK CPU1 CPU2 1B KING KING 1A KING KING 2B KING KING 2A KING KING 3B SAMS SAMS 3A SAMS SAMS 4B SAMS SAMS 4A SAMS SAMS With the proprietary BIOS, this setup works perfectly. That said, the manual for the board does say it's not recommended to mix memory types. Our system integrator mentions that when 16 banks are used, the memory runs at maximum 533MHz. I should mention that this particular coreboot port has one oddity - the memory on each CPU must be matched because we don't know how to do the SPD address switch to detect ram on the second CPU. As you can see in the diagram above, that condition is met. There are two problems. First, with the above (64GB) configuration coreboot just keeps resetting itself after printing "Clearing initial memory region:". I've attached a log with RAM_TIMING_DEBUG enabled, see minicom-20090902-with-64G.cap. Perhaps this is related to coreboot not dropping down to 533MHz with 16 DIMMs installed? Dropping the installed ram down to 48GB like this: BANK CPU1 CPU2 1B KING KING 1A KING KING 2B KING KING 2A KING KING 3B SAMS SAMS 3A SAMS SAMS 4B -- -- 4A -- -- Makes the boot get all the way to seabios, but the board still resets itself just before booting the linux kernel. See attached minicom-20090902-with-48G.cap. Any thoughts on what might be happening here, or how I could debug further? Thanks, Ward. -- Ward Vandewege <ward(a)fsf.org> Free Software Foundation - Senior Systems Administrator

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Re: [coreboot] SeaBIOS WinXP install
by Arnaud Maye 03 Sep '09

03 Sep '09

Hello Myles, Kevin and others I've been implementing the ACPI for the ep80579 and so far it is not going very well. Linux refuses to boot unless I use acpi=off or acpi=ht as boot parameters. acpi=ht seems to display my ACPI ioports in proc/ioports as expected ( the ioports addresses are all mapped to the ACPI BAR ). Without to disable acpi the kernel complains that the 0xE0000000 range is not a reserved range and the MMCONF is not supported and then hangs. Using acpi=noirq still hangs so I believe the problem is not related to the acpi irqoverride. The DSDT been dumped from the legacy BIOS using acpidump and this is what I am including in the build process to test. Actually I've based my code on the mainboard\intel\eagleheigths. I wanted to discard the linux problem so far and concentrate on Windows XP install. I've been disabling the ACPI ( pressing F7 in early install ) and it goes well until "Starting windows..." then I get a BSOD : STOP: 0x0000007B (0xF8980524, 0xc0000034, 0x0000000, 0x00000000). This error indeed point to "Inaccessible Boot Device" and the second argument 0xc0000043 points to "Status Object Name Not Found" This post is quite old and nothing have been answered to it since July 2008. You probably been able to fix that issue. What is related to missing floppy disk controller or something else? Thank you. Arnaud reference email : >/ -----Original Message----- />/ From: Kevin O'Connor [mailto:kevin at koconnor.net <http://www.coreboot.org/mailman/listinfo/coreboot>] />/ Sent: Friday, July 25, 2008 9:49 PM />/ To: Myles Watson />/ Cc: Coreboot />/ Subject: Re: SeaBIOS WinXP install />/ />/ Hi Myles, />/ />/ On Fri, Jul 25, 2008 at 03:58:05PM -0600, Myles Watson wrote: />/ > Just for the fun of it I tried installing XP with the old Bochs BIOS and />/ > then booting it with SeaBIOS. It installs fine, then can't boot with />/ either />/ > BIOS. With SeaBIOS, it blue screens with the same message as the />/ install />/ > CD. Here's the log: />/ />/ The log looks like a CD boot log - was it the same for the hd boot? / After an install, you have to reboot with the CD. >/ A couple of notes: />/ />/ A "STOP: 0x0000007B" message is an INACCESSIBLE_BOOT_DEVICE error />/ according to: />/ />/ http://blogs.technet.com/asksbs/archive/2008/03/30/how-to-troubleshoot- />/ the-stop-error-0x0000007b.aspx />/ />/ I did notice that the last log message always seems to be: />/ />/ > fail floppy_13XX:709(00000001): />/ > a=00001507 b=00000003 c=0000000f d=00065000 si=00005026 di=00000000 />/ > ds=00001a49 es=0000504a ip=000055be cs=00001000 f=00000212 r=00000c02 />/ />/ you could try enabling the CONFIG_FLOPPY_SUPPORT on your machine. If />/ that doesn't work, you could try just enabling a floppy_1315() handler />/ that always sets regs->ah=0 and calls set_success(). / I'll try it. >/ Another thing to try would be to set DEBUG_HDL_13 and DEBUG_HDL_40 to />/ 1 so that you see every call into the bios disk handlers. />/ />/ BTW, what are you using to log the output from serial? If something />/ is sending backspaces - is there a way to capture that? / I'm using HyperTerminal. Thanks for pointing this out. It shoots my theory about backspaces, because HyperTerminal logs those. Any thoughts on where the disappearing output might go? >/ />/ Also, you reported that Bochs 1.186 is working with ADLO. Does a more />/ recent version of Bochs also work? The seabios code is basically in />/ synch with the latest bochs (v1.211). / I can try it. >/ I wish there was more help I could give; unfortunately I'm seeing a />/ totally different set of failures here. :-( / Hopefully we'll get to a common case eventually so we can help each other better. Thanks, Myles * *

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PATCH: do not rely on "tempfile" being available
by Bernie Innocenti 02 Sep '09

02 Sep '09

Signed-off-by: Bernie Innocenti <bernie(a)codewiz.org> Build fix: add a fallback for systems where tempfile is missing Index: bin/show-instructions.sh =================================================================== --- bin/show-instructions.sh (revision 261) +++ bin/show-instructions.sh (working copy) @@ -1,6 +1,6 @@ #!/bin/sh -tmp=`tempfile` +tmp=`tempfile 2>/dev/null || echo /tmp/show-instructions.$$` cat $1 | sed -e "s:%DESTFILE%:$2:" > $tmp if [ -x `dirname $0`/../scripts/kconfig/lxdialog/lxdialog ]; then -- // Bernie Innocenti - http://codewiz.org/ \X/ Sugar Labs - http://sugarlabs.org/

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[BuildROM] r271 - buildrom-devel/bin
by svn＠coreboot.org 02 Sep '09

02 Sep '09

Author: ward Date: 2009-09-02 23:41:13 +0200 (Wed, 02 Sep 2009) New Revision: 271 Modified: buildrom-devel/bin/show-instructions.sh Log: Build fix: add a fallback for systems where tempfile is missing Signed-off-by: Bernie Innocenti <bernie(a)codewiz.org> Acked-by: Ward Vandewege <ward(a)gnu.org> Modified: buildrom-devel/bin/show-instructions.sh =================================================================== --- buildrom-devel/bin/show-instructions.sh 2009-08-24 16:10:31 UTC (rev 270) +++ buildrom-devel/bin/show-instructions.sh 2009-09-02 21:41:13 UTC (rev 271) @@ -1,6 +1,6 @@ #!/bin/sh -tmp=`tempfile` +tmp=`tempfile 2>/dev/null || echo /tmp/show-instructions.$$` cat $1 | sed -e "s:%DESTFILE%:$2:" > $tmp if [ -x `dirname $0`/../scripts/kconfig/lxdialog/lxdialog ]; then

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Re: [coreboot] AMD Geode LX 800 and the CS5536
by Myles Watson 02 Sep '09

02 Sep '09

> To: Myles Watson If you send your questions to the list you'll generally get better answers. > I'm comment out line > > option CONFIG_FALLBACK_SIZE = CONFIG_ROM_SIZE > > and get a successfull build. > > Also i'am turn on debug with level 8 as recommended and make correct > setup for FALLBACK_IMAGE_SIZE > > But after i'am flash rom image on the chip with hardware programmer > and attach my minicom terminal via COM port i can't see anything debug > output. > > Seems to be the code from IEI pci-isa-lx800 can't properly initialize > my SuperIO chip or something else. I have no idea what do next. >> I have a motherboard from unknown manufacturer based on the AMD Geode >> LX 800 and the CS5536 with Winbond W83627HG The iei/pci-isa-lx800 has a Winbond W83627HF. It looks like the cs5536 has a few board-specific settings. Suggestions from anyone? I've never played with a geode board. Thanks, Myles

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[PATCH] V-link optimization on K8M890/VT8237S
by Rudolf Marek 01 Sep '09

01 Sep '09

-----BEGIN PGP SIGNED MESSAGE----- Hash: SHA1 Hi all, As more users of Asus M2V-MX SE emerged. Here is long pending patch I wanted to write. It boots the SB/NB V-link performance to full duplex 533MB/s. (in fact x2 for FDX) The default was 266MB/s but half duplex only. If you encourage any stability issues we need to look into fine tuning the bus. The values are VIA recommended. Rudolf -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.9 (GNU/Linux) Comment: Using GnuPG with Mozilla - http://enigmail.mozdev.org iEYEARECAAYFAkqam/gACgkQ3J9wPJqZRNUsEQCfVF/cTtN/6/+vhnYyPQFK/JLg C9gAoKFg4TWH8O8aWI5EgxX8zG249Q5Y =6Zot -----END PGP SIGNATURE-----

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[v2] r4625 - trunk/coreboot-v2/src/southbridge/via/vt8237r
by svn＠coreboot.org 01 Sep '09

01 Sep '09

Author: ruik Date: 2009-09-01 17:29:12 +0200 (Tue, 01 Sep 2009) New Revision: 4625 Modified: trunk/coreboot-v2/src/southbridge/via/vt8237r/vt8237_ctrl.c Log: As more users of Asus M2V-MX SE emerged. Here is long pending patch I wanted to write. It boots the SB/NB V-link performance to full duplex 533MB/s. (in fact x2 for FDX) The default was 266MB/s but half duplex only. If you encourage any stability issues we need to look into fine tuning the bus. The values are VIA recommended. Signed-off-by: Rudolf Marek <r.marek(a)assembler.cz> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/coreboot-v2/src/southbridge/via/vt8237r/vt8237_ctrl.c =================================================================== --- trunk/coreboot-v2/src/southbridge/via/vt8237r/vt8237_ctrl.c 2009-09-01 10:03:01 UTC (rev 4624) +++ trunk/coreboot-v2/src/southbridge/via/vt8237r/vt8237_ctrl.c 2009-09-01 15:29:12 UTC (rev 4625) @@ -94,6 +94,9 @@ * V-Link CKG Control 0xb0 0x05 0x05 0x06 0x03 * V-Link CKG Control 0xb1 0x05 0x05 0x01 0x03 */ + +/* we setup 533MB/s mode full duplex */ + static void vt8237s_vlink_init(struct device *dev) { u8 reg; @@ -114,24 +117,47 @@ * and VT8251) a different init code is required. */ + /* disable auto disconnect */ + reg = pci_read_config8(devfun7, 0x42); + reg &= ~0x4; + pci_write_config8(devfun7, 0x42, reg); + + /* NB part setup */ pci_write_config8(devfun7, 0xb5, 0x66); pci_write_config8(devfun7, 0xb6, 0x66); - pci_write_config8(devfun7, 0xb7, 0x65); + pci_write_config8(devfun7, 0xb7, 0x64); reg = pci_read_config8(devfun7, 0xb4); reg |= 0x1; + reg &= ~0x10; pci_write_config8(devfun7, 0xb4, reg); - pci_write_config8(dev, 0xb9, 0x68); + pci_write_config8(devfun7, 0xb0, 0x6); + pci_write_config8(devfun7, 0xb1, 0x1); + + /* SB part setup */ + pci_write_config8(dev, 0xb7, 0x60); + pci_write_config8(dev, 0xb9, 0x88); pci_write_config8(dev, 0xba, 0x88); pci_write_config8(dev, 0xbb, 0x89); reg = pci_read_config8(dev, 0xbd); reg |= 0x3; + reg &= ~0x4; pci_write_config8(dev, 0xbd, reg); - /* Program V-link 8X 8bit full duplex, parity disabled. FIXME. */ - pci_write_config8(dev, 0x48, 0x13); + reg = pci_read_config8(dev, 0xbc); + reg &= ~0x7; + pci_write_config8(dev, 0xbc, reg); + + /* Program V-link 8X 8bit full duplex, parity enabled. */ + pci_write_config8(dev, 0x48, 0x23 | 0x80); + + /* enable auto disconnect, for STPGNT and HALT */ + reg = pci_read_config8(devfun7, 0x42); + reg |= 0x7; + pci_write_config8(devfun7, 0x42, reg); + } static void ctrl_enable(struct device *dev) @@ -158,8 +184,7 @@ device_t devsb = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT8237S_LPC, 0); if (devsb) { - /* FIXME: Skip v-link setup for now. */ -// vt8237s_vlink_init(dev); + vt8237s_vlink_init(dev); } /* Configure PCI1 and copy mirror registers from D0F3. */

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[PATCH] misc coreboot utility patches
by Stefan Reinauer 01 Sep '09

01 Sep '09

See attachments -- coresystems GmbH • Brahmsstr. 16 • D-79104 Freiburg i. Br. Tel.: +49 761 7668825 • Fax: +49 761 7664613 Email: info(a)coresystems.de • http://www.coresystems.de/ Registergericht: Amtsgericht Freiburg • HRB 7656 Geschäftsführer: Stefan Reinauer • Ust-IdNr.: DE245674866

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coreboot utilities on MacOSX
by Stefan Reinauer 01 Sep '09

01 Sep '09

Hi, As a weekend project I had been porting coreboot utilities to Mac OS X. I put up a new set of installer images, source code and patches to http://www.coresystems.de/~stepan/OSX/ The order of installation should be: - DirectIO 1.1 - pciutils 3.1.4 - coreboot-utils 1.0 All packages are both 32bit and 64bit and they have been tested on Mac OS X 10.6. Feedback is welcome! Stefan

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coreboot September 2009