coreboot September 2009

coreboot@coreboot.org

62 participants
305 discussions

AMD 780 support
by Daniel Toussaint 08 Sep '09

08 Sep '09

Dear Coreboot , Is there any sign of the AMD 780 code yet ? I have a board just waiting to be flashed with it ... :) Greetings, Daniel Toussaint

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I just stumbled across this
by ron minnich 06 Sep '09

06 Sep '09

http://blogs.sun.com/makia/entry/building_a_mini_cluster Short writeup on building a onesis minicluster. Makia is no relation to me, as you can tell 'cause he spells his last name wrong. But he's very smart and acccomplished in supercomputing, and always worth paying attention to :-) ron

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possible bug, reported on irc
by Maciej Pijanka 06 Sep '09

06 Sep '09

Hello, < Guest836553> Hello I noticed that OpenBIOS' disk-label package doesn't allow raw disk access unless it has an apple partition map. In particular I noticed that only modules/mac-parts.c honours the specs (ftp://playground.sun.com/pub/1275/bindings/postscript/CHRP.ps, section 11.1.2), which state the partition number 0 indicates the whole disk. In pc-parts.c (MSDOS partition table format) partiton 0 is the first primary partiton (it should be partition 1, I suppose) and in sun-parts.c (I didn't try it) I don't see any special-handling code for partition 0, so I suppose it's affected by the bug too. I asked reporting person to post mail to list, so at least after moderation it could reach ML. But mail don't appear so i am posting this now. best regards Maciej -- Maciej Pijanka, PLD-Linux Developer, Reg Linux user #133161 POE/Perl user

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DOS booting using V3
by Gregg C Levine 06 Sep '09

06 Sep '09

Hello! Can it boot what I am calling original DOS? I have access to DOS 6.22 and of course DOS 3.3. And also the thing promoted by General Software. Which is also called DOS and is largely code and binary- level compatible. This is from an iPod Touch.

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[PATCH] Some K8 revF RAM SPD refactoring
by Carl-Daniel Hailfinger 05 Sep '09

05 Sep '09

Hi Ward, I wanted to calculate the optimal timing for any setup with mixed DIMMs where the timing parameters may be compatible but not identical. This patch is a step in the right direction (hopefully). I think Marc already reviewed parts of it last year, but I couldn't find the conversation anymore. Warning: The spec is horribly backwards in some places, and the code sort of inherits this. I spent a few days figuring out why the old code even worked, and then I noticed it wasn't as bad as it originally looked. Feel free to comment, fix, apply, rip to shreds. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: LinuxBIOSv2-asus_m2a-vm/src/northbridge/amd/amdk8/raminit_f.c =================================================================== --- LinuxBIOSv2-asus_m2a-vm/src/northbridge/amd/amdk8/raminit_f.c (Revision 4614) +++ LinuxBIOSv2-asus_m2a-vm/src/northbridge/amd/amdk8/raminit_f.c (Arbeitskopie) @@ -39,7 +39,7 @@ #error This file needs CONFIG_USE_PRINTK_IN_CAR #endif -#define RAM_TIMING_DEBUG 0 +#define RAM_TIMING_DEBUG 1 #if RAM_TIMING_DEBUG == 1 #define printk_raminit printk_debug @@ -1499,7 +1499,8 @@ } if (value0 != value1) { printk_raminit("SPD values differ between channel 0/1 for byte %i\n", addr); - goto single_channel; + printk_raminit("Ignoring the differences for now!\n", addr); + //goto single_channel; } } } @@ -1786,6 +1787,51 @@ return 0; } +int check_spd_latency_available(u32 spd_device, unsigned min_cycle_time, unsigned min_latency) +{ + int latencies; + int latency; + int index; + int value; + + latencies = spd_read_byte(spd_device, SPD_CAS_LAT); + if (latencies < 0) + return -1; + if (latencies == 0) + return 1; + + /* Compute the lowest cas latency supported */ + latency = log2(latencies) -2; + + /* Walk through searching for the selected latency */ + for (index = 0; index < 3; index++, latency++) { + if (!(latencies & (1 << latency))) { + continue; + } + if (latency == min_latency) + break; + } + /* If I can't find the latency or my index is bad error */ + if ((latency != min_latency) || (index >= 3)) { + return -2; + } + + /* Read the min_cycle_time for this latency */ + value = spd_read_byte(spd_device, latency_indicies[index]); + if (value < 0) + return -1; + + value = convert_to_linear(value); + /* All is good if the selected clock speed + * is what I need or slower. + */ + if (value <= min_cycle_time) + return 1; + + /* That didn't work out... */ + return -2; +} + static struct spd_set_memclk_result spd_set_memclk(const struct mem_controller *ctrl, struct mem_info *meminfo) { /* Compute the minimum cycle time for these dimms */ @@ -1856,10 +1902,6 @@ printk_raminit("3 min_latency: %08x\n", min_latency); for (i = 0; (i < DIMM_SOCKETS); i++) { - int latencies; - int latency; - int index; - int value; u32 spd_device = ctrl->channel0[i]; if (!(meminfo->dimm_mask & (1 << i))) { @@ -1870,42 +1912,17 @@ } } - latencies = spd_read_byte(spd_device, SPD_CAS_LAT); - if (latencies < 0) goto hw_error; - if (latencies == 0) { + switch (check_spd_latency_available(spd_device, min_cycle_time, min_latency)) { + case -2: + /* We have an error, disable the dimm */ + meminfo->dimm_mask = disable_dimm(ctrl, i, meminfo); + break; + case -1: + goto hw_error; + break; + case 1: continue; } - - /* Compute the lowest cas latency supported */ - latency = log2(latencies) -2; - - /* Walk through searching for the selected latency */ - for (index = 0; index < 3; index++, latency++) { - if (!(latencies & (1 << latency))) { - continue; - } - if (latency == min_latency) - break; - } - /* If I can't find the latency or my index is bad error */ - if ((latency != min_latency) || (index >= 3)) { - goto dimm_err; - } - - /* Read the min_cycle_time for this latency */ - value = spd_read_byte(spd_device, latency_indicies[index]); - if (value < 0) goto hw_error; - - value = convert_to_linear(value); - /* All is good if the selected clock speed - * is what I need or slower. - */ - if (value <= min_cycle_time) { - continue; - } - /* Otherwise I have an error, disable the dimm */ - dimm_err: - meminfo->dimm_mask = disable_dimm(ctrl, i, meminfo); } printk_raminit("4 min_cycle_time: %08x\n", min_cycle_time); -- http://www.hailfinger.org/

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[v2] r4628 - trunk/coreboot-v2/documentation
by svn＠coreboot.org 04 Sep '09

04 Sep '09

Author: uwe Date: 2009-09-04 21:34:43 +0200 (Fri, 04 Sep 2009) New Revision: 4628 Modified: trunk/coreboot-v2/documentation/Makefile Log: Fix clean rules for the tex files. Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Modified: trunk/coreboot-v2/documentation/Makefile =================================================================== --- trunk/coreboot-v2/documentation/Makefile 2009-09-04 19:25:51 UTC (rev 4627) +++ trunk/coreboot-v2/documentation/Makefile 2009-09-04 19:34:43 UTC (rev 4628) @@ -63,10 +63,9 @@ grep '^config' $< | awk '{print $2}' >>$@ cat endverbatim.tex >> $@ - clean: - rm -f *.aux *.idx *.log *.toc *.out $(FIGS) mainboardkconfig.tex skconfig.tex cpukconfig.tex socketkconfig.tex + rm -f *.aux *.idx *.log *.toc *.out $(FIGS) mainboardkconfig.tex skconfig.tex cpukconfig.tex socketfkconfig.tex distclean: clean - rm -f LinuxBIOS-AMD64.pdf - + rm -f LinuxBIOS-AMD64.pdf Kconfig.pdf +

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[v2] r4627 - trunk/coreboot-v2/documentation
by svn＠coreboot.org 04 Sep '09

04 Sep '09

Author: uwe Date: 2009-09-04 21:25:51 +0200 (Fri, 04 Sep 2009) New Revision: 4627 Modified: trunk/coreboot-v2/documentation/LinuxBIOS-AMD64.tex Log: Fix various build issues and errors in LinuxBIOS-AMD64.tex. Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Modified: trunk/coreboot-v2/documentation/LinuxBIOS-AMD64.tex =================================================================== --- trunk/coreboot-v2/documentation/LinuxBIOS-AMD64.tex 2009-09-04 16:30:31 UTC (rev 4626) +++ trunk/coreboot-v2/documentation/LinuxBIOS-AMD64.tex 2009-09-04 19:25:51 UTC (rev 4627) @@ -1234,7 +1234,7 @@ coreboot has to either assert an LDTSTOP or a reset to make the changes become active. Additionally Linux can do a firmware reset, if coreboot provides the needed infrastructure. To use this capability, define the -option \texttt{HAVE\_HARD\CONFIG_RESET} and add an object file specifying the +option \texttt{CONFIG\_HAVE\_HARD\_RESET} and add an object file specifying the reset code in your mainboard specific configuration file \texttt{coreboot-v2/src/mainboard/$<$vendor$>$/$<$mainboard$>$/Config.lb}: @@ -1552,7 +1552,7 @@ ROMCC images are so-called because C code for the ROM part is compiled with romcc. romcc is an optimizing C compiler which compiles one, and only one file; to get more than one file, one must include the C code via include statements. The main ROM code .c file is usually called auto.c. \subsubsection{How it is built} -Romcc compiles auto.c to produce auto.inc. auto.inc is included in the main crt0.S, which is then preprocessed to produce crt0.s. The inclusion of files into crt0.S is controlled by the CONFIG_CRT0\_INCLUDES variable. crt0.s is then assembled. +Romcc compiles auto.c to produce auto.inc. auto.inc is included in the main crt0.S, which is then preprocessed to produce crt0.s. The inclusion of files into crt0.S is controlled by the CONFIG\_CRT0\_INCLUDES variable. crt0.s is then assembled. File for the ram part are compiled in a conventional manner. @@ -1574,17 +1574,17 @@ As we mentioned, the ROM file consists of multiple images. In the basic file, there are two full coreboot rom images. The build sequence for each is the same, and in fact the ldscript.ld files are almost identical. The only difference is in a few makefile variables, generated by the config tool. \begin{itemize} -\item PAYLOAD\_SIZE. Each image may have a different payload size. -\item \CONFIG_ROMBASE Each image must have a different base in rom. -\item \CONFIG_RESET Unclear what this is used for. -\item \_EXCEPTION\_VECTORS where an optional IDT might go. -\item USE\_OPTION\_TABLE if set, an option table section will be linked in. +\item CONFIG\_PAYLOAD\_SIZE. Each image may have a different payload size. +\item CONFIG\_ROMBASE Each image must have a different base in rom. +\item CONFIG\_RESET Unclear what this is used for. +\item CONFIG\_EXCEPTION\_VECTORS where an optional IDT might go. +\item CONFIG\_USE\_OPTION\_TABLE if set, an option table section will be linked in. \item CONFIG\_ROM\_PAYLOAD\_START This is the soon-to-be-deprecated way of locating a payload. cbfs eliminates this. -\item USE\_FALLBACK\_IMAGE Whether this is a fallback or normal image -\item ROM\_SECTION\_SIZE Essentially, the payload size. Soon to be deprecated. -\item ROM\_IMAGE\_SIZE Size of this image (i.e. fallback or normal image) -\item ROM\_SIZE Total size of the ROM -\item XIP\_RAM\_BASE The start of eXecute In Place code. XIP allows for not copying code to ram, but just running it from ROM. +\item CONFIG\_USE\_FALLBACK\_IMAGE Whether this is a fallback or normal image +\item CONFIG\_ROM\_SECTION\_SIZE Essentially, the payload size. Soon to be deprecated. +\item CONFIG\_ROM\_IMAGE\_SIZE Size of this image (i.e. fallback or normal image) +\item CONFIG\_ROM\_SIZE Total size of the ROM +\item CONFIG\_XIP\_RAM\_BASE The start of eXecute In Place code. XIP allows for not copying code to ram, but just running it from ROM. \end{itemize} Each image (normal or fallback) is built completely independently and does not get linked to the other. They are assembled into one ROM image by the (soon to be deprecated) buildrom tool, or by the cbfs tool.

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[PATCH] Use driver-y instead of obj-y for model_6xx_init.o
by Uwe Hermann 04 Sep '09

04 Sep '09

See patch. Uwe. -- http://www.hermann-uwe.de | http://www.holsham-traders.de http://www.crazy-hacks.org | http://www.unmaintained-free-software.org

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[v2] r4626 - trunk/coreboot-v2/src/cpu/intel/model_6xx
by svn＠coreboot.org 04 Sep '09

04 Sep '09

Author: uwe Date: 2009-09-04 18:30:31 +0200 (Fri, 04 Sep 2009) New Revision: 4626 Modified: trunk/coreboot-v2/src/cpu/intel/model_6xx/Makefile.inc Log: Use driver-y instead of obj-y for model_6xx_init.o. Otherwise booting (but not building) fails: Initializing CPU #0 CPU: vendor Intel device 665 CPU: family 06, model 06, stepping 05 Unknown cpu This patch was tested to fix the issue on MSI MS-6178. Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Myles Watson <mylesgw(a)gmail.com> Modified: trunk/coreboot-v2/src/cpu/intel/model_6xx/Makefile.inc =================================================================== --- trunk/coreboot-v2/src/cpu/intel/model_6xx/Makefile.inc 2009-09-01 15:29:12 UTC (rev 4625) +++ trunk/coreboot-v2/src/cpu/intel/model_6xx/Makefile.inc 2009-09-04 16:30:31 UTC (rev 4626) @@ -18,5 +18,5 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -obj-y += model_6xx_init.o +driver-y += model_6xx_init.o

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[PATCH] buildrom: Force creation of symlink
by Nathan Williams 04 Sep '09

04 Sep '09

Building grub2 was failing if the symlink already exists. Signed-off-by: Nathan Williams <nathan(a)traverse.com.au> Index: buildrom-devel/packages/grub2/grub2.mk =================================================================== --- buildrom-devel/packages/grub2/grub2.mk (revision 271) +++ buildrom-devel/packages/grub2/grub2.mk (working copy) @@ -48,7 +48,7 @@ @ echo "Using custom config $(GRUB2_CONFIG)" endif @ echo "Building grub2..." - @ ln -s $(GRUB2_SRC_DIR)/config.log $(GRUB2_LOG_DIR) + @ ln -sf $(GRUB2_SRC_DIR)/config.log $(GRUB2_LOG_DIR) @ (cd $(GRUB2_SRC_DIR) ; sh ./autogen.sh >> $(GRUB2_BUILD_LOG) 2>&1) @ (cd $(GRUB2_SRC_DIR) ; export LIBS= CC= LDFLAGS= CFLAGS=; ./configure --with-platform=coreboot --prefix=$(STAGING_DIR) >> $(GRUB2_BUILD_LOG) 2>&1) @ make -C $(GRUB2_SRC_DIR) >> $(GRUB2_BUILD_LOG) 2>&1

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coreboot September 2009