coreboot September 2009

coreboot@coreboot.org

62 participants
305 discussions

cbfstool2 0.9.9
by Patrick Georgi 13 Sep '09

13 Sep '09

Hi, I got my TODO covered: the current cbfstool2 works (as cbfstool, that "2" suffix is purely internal) as a drop-in replacement in the coreboot tree, incl. makefiles to build it both for newconfig and kconfig style builds. The code should match the codingstyle and license headers are added, so I think this is ready to go in. You can find the tarball at http://www.coresystems.de/~patrick/cbfstool2-0.9.9.tar.bz2 My change would also include a trivial change to newconfig, to only create a $(obj)/cbfs directory, instead of $(obj)/cbfs/tools/lzma, as this isn't necessary anymore. The "svn diff" is quite messy, as I reused files that are sufficiently similar using svn mv, and those changes aren't well expressed in diff output. That code is Signed-off-by: Patrick Georgi <patrick.georgi(a)coresystems.de> Regards, Patrick

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hello coreboot
by eran shemi 13 Sep '09

13 Sep '09

Hi coreboot my name is eran and i want to now what is road map for supporting the Intel atom core and what version of coreboot bios will support Intel® 945GM + Intel® ICH7R Chipset with Winbond W83627HF Thanks, Eran Shemi

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QEMU BIOS question
by Jen-Cheng(Tommy) Huang 13 Sep '09

13 Sep '09

Hi, 1. What is the difference between QEMU BIOS and the other coreboot BIOS which can be flashed to ROM? I mean what functionalities QEMU lack or incomplete compared to the others? 2. What is the major difference between QEMU coreboot BIOS and the original QEMU BIOS? High-level answers would be very helpful. I just want to know some basics. Any response is very appreciated. Thanks. Regards, Tommy

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SMP Linux on QEMU
by Jen-Cheng(Tommy) Huang 11 Sep '09

11 Sep '09

Hi, I am using coreboot v3 with FILO. I specify "qemu -L . vd.img -smp 4". But I always see one cpu in /proc/cpuinfo. Then I tried if SMP works in v2. However, when I tried to boot, qemu showed the following error messages: (v3 works fine here) Uncompressing coreboot to RAM. Jumping to image. Check CBFS header at fffeffe0 magic is 4f524243 Found CBFS header at fffeffe0 Check fallback/payload CBFS: follow chain: fff80000 + 38 + 14efa + align -> fff94f40 Check fallback/coreboot_ram CBFS: follow chain: fff94f40 + 38 + 687f + align -> fff9b800 Check CBFS: follow chain: fff9b800 + 28 + 547d8 + align -> ffff0000 CBFS: Could not find file normal/coreboot_ram Jumping to image. qemu: fatal: Trying to execute code outside RAM or ROM at 0x000a0000 Does anyone know how to boot up SMP kernel on qemu? Any hint is very appreciated. Thanks in advance. Regards, Tommy

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cbfstool2 0.9
by Patrick Georgi 11 Sep '09

11 Sep '09

Hi, at http://www.coresystems.de/~patrick/cbfstool2-0.9.tar.bz2 you can find a copy of my current work on improving the CBFS toolchain. It's a drop-in replacement for cbfstool as provided in the coreboot tree, with the following differences: - no more mmap, nor fork/exec, improving portability - locking a file to a specific location in the flash image works - bootblock size is determined from the file size, the command line argument is ignored (but expected for compatibility purposes) Some parts of the code are clean rewrites, from the cbfstool README, with tests using cbfstool, the cbfs_file handling (creation, splitting, iterating) in particular. Other parts of the code are mostly unchanged, like the ELF parsers that handle stages and payloads. I figured that it's more work to get rid of mmap and fork/exec and implement working fixed-address files in the existing code base without introducing lots of hacks then re-implementing parts of it. I also tried to document a couple of the finer points, I hope I caught all the important things. There are a couple of things left to do: 1. The CodingStyle must be followed, right now it follows my own (with >160 characters per lines, for example) 2. Licensing information is missing in lots of source files. Given that some of them contain GPLv2 references, and the nature of that license, all of the tarball is distributed under GPLv2. Still, I'll have to clean it up. 3. There's no integration into the coreboot build system yet. 4. Some commands aren't implemented yet. This is not really a problem, given that they touch functionality that is rather fragile in cbfstool. Deleting files comes to mind. It's supposed to be a drop-in replacement, meaning that I re-implemented the behaviour of the CLI. It's hand-threaded spaghetti code now, and I'd love to replace the command line format with something more getopt compatible eventually. I also didn't bother to free() all malloc()ed memory regions given that the code survives a couple of milliseconds, before it ends itself. One battle at a time. Still, I think it's good enough to get some public exposure, maybe some watchful eyes at code and behaviour. The big new feature of this code is the capability to lock files to fixed locations, which we'll need for a variety of things: I'm currently working on moving the ROM stage (that does CAR and raminit) into CBFS, and this project came into existence because I needed some way to put code at defined places without cbfstool blowing up. Certain EC roms, romstraps, and other auxilliary data of devices also must be located at pre-defined places to make hardware happy. Regards, Patrick

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LNXI eVelocity 2 BIOS reburn
by Sebastian Lara 11 Sep '09

11 Sep '09

Hi, I'm trying to revive a Linux Netwox eVelocity 2 Cluster with LinuxBIOS-1.1.7.8 and Etherboot 5.2 on compute nodes. After some trouble, I have access to a shell after node system installation over network. My problem now is that I can't get localboot to work. I need to know if I can re-burn the BIOS with a newer version of coreboot or something else, so I can use PXE and use GRUB for booting from local. Here is my lspci output. Thanks in advance for any help lspci -tv -+-[0000:01]-+-01.0-[0000:02]--+-03.0 Broadcom Corporation NetXtreme BCM5702X Gigabit Ethernet | | \-04.0 Broadcom Corporation NetXtreme BCM5702X Gigabit Ethernet | +-01.1 Advanced Micro Devices [AMD] AMD-8131 PCI-X IOAPIC | +-02.0-[0000:03-04]----01.0-[0000:04]----00.0 Mellanox Technologies MT23108 InfiniHost | +-02.1 Advanced Micro Devices [AMD] AMD-8131 PCI-X IOAPIC | +-03.0-[0000:05]--+-00.0 Advanced Micro Devices [AMD] AMD-8111 USB | | +-00.1 Advanced Micro Devices [AMD] AMD-8111 USB | | \-06.0 ATI Technologies Inc Rage XL | +-04.0 Advanced Micro Devices [AMD] AMD-8111 LPC | +-04.1 Advanced Micro Devices [AMD] AMD-8111 IDE | +-04.2 Advanced Micro Devices [AMD] AMD-8111 SMBus 2.0 | +-04.3 Advanced Micro Devices [AMD] AMD-8111 ACPI | \-04.6 Advanced Micro Devices [AMD] AMD-8111 MC97 Modem \-[0000:00]-+-18.0 Advanced Micro Devices [AMD] K8 [Athlon64/Opteron] HyperTransport Technology Configuration +-18.1 Advanced Micro Devices [AMD] K8 [Athlon64/Opteron] Address Map +-18.2 Advanced Micro Devices [AMD] K8 [Athlon64/Opteron] DRAM Controller +-18.3 Advanced Micro Devices [AMD] K8 [Athlon64/Opteron] Miscellaneous Control +-19.0 Advanced Micro Devices [AMD] K8 [Athlon64/Opteron] HyperTransport Technology Configuration +-19.1 Advanced Micro Devices [AMD] K8 [Athlon64/Opteron] Address Map +-19.2 Advanced Micro Devices [AMD] K8 [Athlon64/Opteron] DRAM Controller \-19.3 Advanced Micro Devices [AMD] K8 [Athlon64/Opteron] Miscellaneous Control sh-3.2# lspci -tvnn -+-[0000:01]-+-01.0-[0000:02]--+-03.0 14e4:16a6 | | \-04.0 14e4:16a6 | +-01.1 1022:7451 | +-02.0-[0000:03-04]----01.0-[0000:04]----00.0 15b3:5a44 | +-02.1 1022:7451 | +-03.0-[0000:05]--+-00.0 1022:7464 | | +-00.1 1022:7464 | | \-06.0 1002:4752 | +-04.0 1022:7468 | +-04.1 1022:7469 | +-04.2 1022:746a | +-04.3 1022:746b | \-04.6 1022:746e \-[0000:00]-+-18.0 1022:1100 +-18.1 1022:1101 +-18.2 1022:1102 +-18.3 1022:1103 +-19.0 1022:1100 +-19.1 1022:1101 +-19.2 1022:1102 \-19.3 1022:1103 -- Sebastián Lara Menares Ingeniería Civil Electrónica Universidad de Concepción

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USB debug port in ICH5?
by ron minnich 11 Sep '09

11 Sep '09

I'm looking but don't see info yet on a USB debug port in ICH5, anyone know? The issue is that the Dell Server 1850 node I'm trying to get working doesn't give direct COM1 access to the P4; it goes through a (ack! Ptui!) baseboard maintenance controller. So to talk to COM1 you have to know how to talk to the BMC. This may just be another non-standard IPMI interface or something else, not sure, but in any case I figure the USB debug port might be easier. ron

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Control Transfer from coreboot to payload
by Jen-Cheng(Tommy) Huang 10 Sep '09

10 Sep '09

Hey there, I read the documents on the website. But those documents cover the internal stages of coreboot. I am more curious about how coreboot transfers control to the payload, where the payload is loaded and the processor state, paging enabled or not. Please give me some clues about how coreboot achieve those things or where I can find such information. Thanks in advance. Regards, Tommy

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Geode GX1 with VGA-enabled payload?
by Jonathan Sturges 10 Sep '09

10 Sep '09

Hi, I am trying to remind myself what I need (or if it's even possible) to use a payload that makes use of VGA on a Geode GX1/CS5530 system. I'd like to have a bootloader payload that uses VGA instead of serial, if possible. Now, I've got VGA enabled in the coreboot image I'm currently using, and I get the coreboot logo splash screen, but I'm still using a payload configured for COM1. Aside from changing payloads to one that uses VGA and PS/2 devices, what else is required? Am I required to have a VGA BIOS? I'm guessing that I am. Can someone confirm that that's what I need? If so, I remember seeing the tutorial somewhere on extracting the VGA BIOS and incorporating it in coreboot. Though, if someone has an up-to-date recipe for this, that'd be even better! thanks, Jonathan

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[v2] r4629 - trunk/util/getpir
by svn＠coreboot.org 10 Sep '09

10 Sep '09

Author: stepan Date: 2009-09-10 13:21:48 +0200 (Thu, 10 Sep 2009) New Revision: 4629 Modified: trunk/util/getpir/code_gen.c trunk/util/getpir/pirq_routing.h Log: fix compilation issues for pirq checker tool (trivial) Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/util/getpir/code_gen.c =================================================================== --- trunk/util/getpir/code_gen.c 2009-09-04 19:34:43 UTC (rev 4628) +++ trunk/util/getpir/code_gen.c 2009-09-10 11:21:48 UTC (rev 4629) @@ -50,7 +50,7 @@ fprintf(fpir, "%s", *code++); fprintf(fpir, "\t32 + 16 * %d, /* Max. number of devices on the bus */\n", - ts, ts); + ts); fprintf(fpir, "\t0x%02x, /* Interrupt router bus */\n", rt->rtr_bus); fprintf(fpir, "\t(0x%02x << 3) | 0x%01x, /* Interrupt router dev */\n", Modified: trunk/util/getpir/pirq_routing.h =================================================================== --- trunk/util/getpir/pirq_routing.h 2009-09-04 19:34:43 UTC (rev 4628) +++ trunk/util/getpir/pirq_routing.h 2009-09-10 11:21:48 UTC (rev 4629) @@ -39,6 +39,10 @@ extern const struct irq_routing_table intel_irq_routing_table; +#ifdef GETPIR +#define copy_pirq_routing_table(start) (start) +unsigned long write_pirq_routing_table(unsigned long start); +#else #if CONFIG_HAVE_PIRQ_TABLE==1 unsigned long copy_pirq_routing_table(unsigned long start); unsigned long write_pirq_routing_table(unsigned long start); @@ -46,5 +50,6 @@ #define copy_pirq_routing_table(start) (start) #define write_pirq_routing_table(start) (start) #endif +#endif #endif /* ARCH_PIRQ_ROUTING_H */

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coreboot September 2009