coreboot August 2009

coreboot@coreboot.org

61 participants
356 discussions

Re: [coreboot] coreboot Digest, Vol 54, Issue 61
by Harrison, Jon (SELEX GALILEO, UK) 19 Aug '09

19 Aug '09

Just a couple of questions. How does the ACPI/MP/PIR Table support in SeaBIOS relate to what I already have in Coreboot ? I note the comment text says that these options are for emulators (or Win32 ??) Can I safely disable these options for linux only support ? > ------------------------------ > > Message: 6 > Date: Wed, 19 Aug 2009 16:21:54 +0100 > From: "Harrison, Jon (SELEX GALILEO, UK)" > <jon.harrison(a)selexgalileo.com> > To: "Myles Watson" <mylesgw(a)gmail.com> > Cc: coreboot(a)coreboot.org > Subject: Re: [coreboot] Patches for CN400 CBFS Compatibility > Message-ID: > > <8E520A5E7FB8D647BFDA039F6031C1C605C34C72(a)desmdswms201.des.grplnk.net> > Content-Type: text/plain; charset="us-ascii" > > Yes, I've seen quite a bit of traffic on SeaBIOS, and it does > look like > it might answer a number of questions at once. > > Looks like it's worth a go. > > SELEX Sensors and Airborne Systems Limited Registered Office: Sigma House, Christopher Martin Road, Basildon, Essex SS14 3EL A company registered in England & Wales. Company no. 02426132 ******************************************************************** This email and any attachments are confidential to the intended recipient and may also be privileged. If you are not the intended recipient please delete it from your system and notify the sender. You should not copy it or use it for any purpose nor disclose or distribute its contents to any other person. ********************************************************************

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[RFC] flashrom 0.9.1
by Carl-Daniel Hailfinger 19 Aug '09

19 Aug '09

Hi, there are no more pending flashrom patches for 0.9.1 and I would like to release it today or tomorrow. Draft 0.9.1 announcement is at http://www.coreboot.org/Flashrom/0.9.1 . Please test! Regards, Carl-Daniel -- http://www.hailfinger.org/

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Re: [coreboot] Patches for CN400 CBFS Compatibility
by Myles Watson 19 Aug '09

19 Aug '09

> Features Tested as Working using FILO 0.6.0 Payload launching Fedora > Core 9 (2.6.25 kernel):: > VGA Console / X > SATA (As Boot device) > PATA CDROM (Autodetect/Mount/Eject all seem to work) > USB (keyboard, mouse and USB Flash Disk) > Networking > ACPI (S0/S5 Soft-off Works OK, Linux PM Seems to be working, PCI IRQ > Routing) > IOAPIC/LAPIC > > Legacy Keyboard/Mouse have NOT been tested, but should work based on > existing VT8237R work. > > Boots to FILO in ~1 second. FILO USB Keyboard/Mouse Support tested as > working. Good work. > I've also attached a log of the boot console output. > > cn400-src-v9.patch should be applied at src level > cn400-targets-v9.patch should be applied at targets level > Signed-off-by: Jon Harrison <bothlyn(a)blueyonder.co.uk> > > PS > The change itself is a bit of a hack to get things up and running again. > Discussions with Patrick suggest that the way that I'm doing the VGA > Init, based on the rather elderly epia-m build, is > obsolete/anachronistic as there is stuff in the core functionality to > the same job perhaps a bit more cleanly. I don't really have the time at > the moment to sort this out, perhaps someone else will have a look if a > working build is out there ? If you stopped here and used SeaBIOS, it would solve multiple issues at once. SeaBIOS is the Bochs BIOS converted to C, understands VGA ROMs in CBFS, and can have multiple payloads (I saw that in the other thread.) Now might be the right time for you to try it. Thanks, Myles

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Re: [coreboot] Patches for CN400 CBFS Compatibility
by ron minnich 19 Aug '09

19 Aug '09

Acked-by; Ronald G. Minnich <rminnich(a)gmail.com>

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alix1d_lab_question
by Oliver Niesner 19 Aug '09

19 Aug '09

Hi! I slowly understand how all this stuff works, but now i need the help from the list. I build a coreboot.rom with the latest buidrom-devel tool and coreboot-v3. i choosed Linux as bootloader and the build process ended sucessfully with a pcenginesalix1c.rom (2048KB) After flashing, the board seems initialized, but hangs at a certain point. I found a message (see the attached log) saying: "Unknown bootloader class", maybe that's the reason it hangs? Any help is appreciated Oliver LAR: Compression algorithm #0 (none) used LAR: Attempting to open 'normal/payload/segment5'. LAR: Start 0xffe00000 len 0x200000 LAR: seen member normal/option_table LAR: seen member normal/initram/segment0 LAR: seen member normal/stage2/segment0 LAR: seen member normal/stage2/segment1 LAR: seen member normal/stage2/segment2 LAR: seen member normal/payload/segment0 LAR: seen member normal/payload/segment1 LAR: seen member normal/payload/segment2 LAR: seen member normal/payload/segment3 LAR: seen member normal/payload/segment4 LAR: seen member blob/vsa LAR: seen member zerofill LAR: seen member bootblock LAR: File not found! LAR: load_file: No such file 'normal/payload/segment5' LAR: load_file_segments: All loaded, entry 0x00010000 ========== mainboard_pre_payload: done ========================================= Unknown bootloader class! type=00010000 data=00010000 param=ffffcd46 Firmware type: LinuxBIOS [ 0.000000] Linux version 2.6.20.2 (root(a)localhost.localdomain) (gcc-Version 4.1.2 20080704 (Red Hat 4.1.2-44)) #1 Wed Aug 19 14:19:15 CEST 2009 [ 0.000000] BIOS-provided physical RAM map: [ 0.000000] sanitize start [ 0.000000] sanitize end [ 0.000000] copy_e820_map() start: 0000000000000000 size: 0000000000000b9c en d: 0000000000000b9c type: 2 [ 0.000000] copy_e820_map() start: 0000000000000b9c size: 000000000009f464 en d: 00000000000a0000 type: 1 [ 0.000000] copy_e820_map() type is E820_RAM [ 0.000000] copy_e820_map() start: 00000000000f0000 size: 0000000000000400 en d: 00000000000f0400 type: 2 [ 0.000000] copy_e820_map() start: 0000000000100000 size: 000000000f6e0000 en d: 000000000f7e0000 type: 1 [ 0.000000] copy_e820_map() type is E820_RAM [ 0.000000] BIOS-e820: 0000000000000000 - 0000000000000b9c (reserved) [ 0.000000] BIOS-e820: 0000000000000b9c - 00000000000a0000 (usable) [ 0.000000] BIOS-e820: 00000000000f0000 - 00000000000f0400 (reserved) [ 0.000000] BIOS-e820: 0000000000100000 - 000000000f7e0000 (usable) [ 0.000000] 0MB HIGHMEM available. [ 0.000000] 247MB LOWMEM available. [ 0.000000] Zone PFN ranges: [ 0.000000] DMA 0 -> 4096 [ 0.000000] Normal 4096 -> 63456 [ 0.000000] HighMem 63456 -> 63456 [ 0.000000] early_node_map[1] active PFN ranges [ 0.000000] 0: 0 -> 63456 [ 0.000000] DMI not present or invalid. [ 0.000000] ACPI: PM-Timer IO Port: 0x9c10 [ 0.000000] Allocating PCI resources starting at 10000000 (gap: 0f7e0000:f082 0000) [ 0.000000] Detected 498.075 MHz processor. [ 13.720474] Built 1 zonelists. Total pages: 62961 [ 13.720489] Kernel command line: console=tty0 console=ttyS0,115200 rdinit=/li nuxrc [ 13.721508] Initializing CPU#0 [ 13.721580] PID hash table entries: 1024 (order: 10, 4096 bytes) [ 13.722216] Console: colour dummy device 80x25 [ 13.893697] Dentry cache hash table entries: 32768 (order: 5, 131072 bytes) [ 13.901308] Inode-cache hash table entries: 16384 (order: 4, 65536 bytes) [ 13.946560] Memory: 247824k/253824k available (2094k kernel code, 5504k reser ved, 696k data, 180k init, 0k highmem) [ 13.957074] virtual kernel memory layout: [ 13.957082] fixmap : 0xfffec000 - 0xfffff000 ( 76 kB) [ 13.957092] pkmap : 0xff800000 - 0xffc00000 (4096 kB) [ 13.957102] vmalloc : 0xd0000000 - 0xff7fe000 ( 759 MB) [ 13.957112] lowmem : 0xc0000000 - 0xcf7e0000 ( 247 MB) [ 13.957122] .init : 0xc03bc000 - 0xc03e9000 ( 180 kB) [ 13.957132] .data : 0xc030bb7d - 0xc03b9be4 ( 696 kB) [ 13.957142] .text : 0xc0100000 - 0xc030bb7d (2094 kB) [ 14.001442] Checking if this processor honours the WP bit even in supervisor mode... Ok. [ 14.151381] Calibrating delay using timer specific routine.. 997.13 BogoMIPS (lpj=4985680) [ 14.159852] Mount-cache hash table entries: 512 [ 14.164713] CPU: L1 I Cache: 64K (32 bytes/line), D cache 64K (32 bytes/line) [ 14.171878] CPU: L2 Cache: 128K (32 bytes/line) [ 14.176472] CPU: AMD Geode(TM) Integrated Processor by AMD PCS stepping 02 [ 14.183457] Checking 'hlt' instruction... OK. [ 14.221871] ACPI: Core revision 20060707 [ 14.226767] ACPI Error (tbget-0154): Could not map memory at 000000000F7B3040 for table header [20060707] [ 14.236431] ACPI Exception (tbrsdt-0259): AE_NO_MEMORY, Could not get the RSD T/XSDT [20060707] [ 14.245133] ACPI Exception (tbxface-0094): AE_NO_MEMORY, Could not load RSDT [20060707] [ 14.253229] ACPI Exception (tbxface-0120): AE_NO_MEMORY, Could not load table s [20060707] [ 14.261492] ACPI: Unable to load the System Description Tables [ 14.268201] NET: Registered protocol family 16 [ 14.272971] PCI: Using configuration type 1 [ 14.277171] Setting up standard PCI resources [ 14.291227] ACPI: Interpreter disabled. [ 14.295107] Linux Plug and Play Support v0.97 (c) Adam Belay [ 14.300808] pnp: PnP ACPI: disabled [ 14.304786] SCSI subsystem initialized [ 14.308716] usbcore: registered new interface driver usbfs [ 14.314329] usbcore: registered new interface driver hub [ 14.319774] usbcore: registered new device driver usb [ 14.325081] PCI: Probing PCI hardware [ 14.337251] PCI: Using IRQ router default [1022/2090] at 0000:00:0f.0 [ 14.345216] PCI: Ignore bogus resource 6 [0:0] of 0000:00:01.1 [ 14.351155] NET: Registered protocol family 2 [ 14.441390] IP route cache hash table entries: 2048 (order: 1, 8192 bytes) [ 14.448495] TCP established hash table entries: 8192 (order: 3, 32768 bytes) [ 14.455743] TCP bind hash table entries: 4096 (order: 2, 16384 bytes) [ 14.462284] TCP: Hash tables configured (established 8192 bind 4096) [ 14.468657] TCP reno registered [ 14.501692] checking if image is initramfs... it is [ 14.575516] Freeing initrd memory: 137k freed [ 14.581569] Installing knfsd (copyright (C) 1996 okir(a)monad.swb.de). [ 14.588367] io scheduler noop registered [ 14.592348] io scheduler anticipatory registered (default) [ 14.597907] io scheduler deadline registered [ 14.602256] io scheduler cfq registered [ 14.768105] Real Time Clock Driver v1.12ac [ 14.772330] AMD Geode RNG detected [ 14.775893] Serial: 8250/16550 driver $Revision: 1.90 $ 4 ports, IRQ sharing disabled [ 14.784058] serial8250: ttyS0 at I/O 0x3f8 (irq = 4) is a 16550A [ 14.790469] serial8250: ttyS1 at I/O 0x2f8 (irq = 3) is a 16550A [ 14.815001] FDC 0 is a post-1991 82077 [ 14.821337] RAMDISK driver initialized: 16 RAM disks of 4096K size 1024 block size [ 14.829653] loop: loaded (max 8 devices) [ 14.833803] nbd: registered device at major 43 [ 14.840595] Uniform Multi-Platform E-IDE driver Revision: 7.00alpha2 [ 14.847028] ide: Assuming 33MHz system bus speed for PIO modes; override with idebus=xx [ 14.855150] AMD5536: IDE controller at PCI slot 0000:00:0f.2 [ 14.860965] AMD5536: chipset revision 1 [ 14.864837] AMD5536: not 100% native mode: will probe irqs later [ 14.870987] AMD5536: 0000:00:0f.2 (rev 01) UDMA100 controller [ 14.876906] ide0: BM-DMA at 0x1ca0-0x1ca7, BIOS settings: hda:pio, hdb:pi o [ 15.191126] hda: CF CARD, ATA DISK drive [ 15.911115] ide0 at 0x1f0-0x1f7,0x3f6 on irq 14 [ 16.510370] hda: max request size: 128KiB [ 16.514409] hda: 31326208 sectors (16039 MB) w/1KiB Cache, CHS=33149/15/63 [ 16.521496] hda: hda1 hda2 hda3 [ 16.527653] PCI: Guessed IRQ 9 for device 0000:00:0f.5 [ 16.532997] PCI: Sharing IRQ 9 with 0000:00:0f.4 [ 16.537774] ehci_hcd 0000:00:0f.5: EHCI Host Controller [ 16.543168] ehci_hcd 0000:00:0f.5: new USB bus registered, assigned bus numbe r 1 [ 16.580236] ehci_hcd 0000:00:0f.5: irq 9, io mem 0xfe019000 [ 16.585842] ehci_hcd 0000:00:0f.5: USB 2.0 started, EHCI 1.00, driver 10 Dec 2004 [ 16.593735] usb usb1: configuration #1 chosen from 1 choice [ 16.599448] hub 1-0:1.0: USB hub found [ 16.603248] hub 1-0:1.0: 4 ports detected [ 16.710719] PCI: Guessed IRQ 9 for device 0000:00:0f.4 [ 16.716062] PCI: Sharing IRQ 9 with 0000:00:0f.5 [ 16.720831] ohci_hcd 0000:00:0f.4: OHCI Host Controller [ 16.726182] ohci_hcd 0000:00:0f.4: new USB bus registered, assigned bus numbe r 2 [ 16.733636] ohci_hcd 0000:00:0f.4: irq 9, io mem 0xfe018000 [ 16.822498] usb usb2: configuration #1 chosen from 1 choice [ 16.828202] hub 2-0:1.0: USB hub found [ 16.832000] hub 2-0:1.0: 4 ports detected [ 16.940282] Initializing USB Mass Storage driver... [ 16.945274] usbcore: registered new interface driver usb-storage [ 16.951312] USB Mass Storage support registered. [ 16.956015] usbcore: registered new interface driver usbhid [ 16.961621] drivers/usb/input/hid-core.c: v2.6:USB HID core driver [ 16.968110] PNP: No PS/2 controller found. Probing ports directly. [ 17.491697] i8042.c: Can't read CTR while initializing i8042. [ 17.497467] i8042: probe of i8042 failed with error -5 [ 17.502927] mice: PS/2 mouse device common for all mice [ 17.508354] i2c /dev entries driver [ 17.512095] **WARNING** I2C adapter driver [CS5536 ACB0] forgot to specify ph ysical device; fix it! [ 17.568991] PM-Timer had no reasonable result: 0x0xffffff - aborting. [ 17.575472] TCP cubic registered [ 17.578754] NET: Registered protocol family 1 [ 17.583151] NET: Registered protocol family 17 [ 17.587726] Using IPI Shortcut mode [ 17.591548] Freeing unused kernel memory: 180k freed [ 17.599728] Time: tsc clocksource has been installed.

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build service results for r4555
by coreboot information 19 Aug '09

19 Aug '09

Dear coreboot readers! This is the automatic build system of coreboot. The developer "oxygene" checked in revision 4555 to the coreboot repository. This caused the following changes: Change Log: Config-abuild.lb doesn't need to override ROM_IMAGE_SIZE. Trivial change Signed-off-by: Patrick Georgi <patrick.georgi(a)coresystems.de> Acked-by: Patrick Georgi <patrick.georgi(a)coresystems.de> Build Log: Compilation of embeddedplanet:ep405pc is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4555&device=ep405pc&vendor… Compilation of motorola:sandpointx3_altimus_mpc7410 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4555&device=sandpointx3_al… Compilation of totalimpact:briq is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4555&device=briq&vendor=to… Compilation of via:epia-m has been fixed If something broke during this checkin please be a pain in oxygene's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

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Re: [coreboot] [filo] How to boot secondary payload from flash using FILO ?
by Kevin O'Connor 19 Aug '09

19 Aug '09

On Wed, Aug 19, 2009 at 01:33:39PM +0100, Harrison, Jon (SELEX GALILEO, UK) wrote: > Hi Guys, > > What I'd like to do now is to use filo to boot either Linux for SATA > (Working already) or a second Payload/ElfImage from Flash. > > Ideally, for maximum efficiency, I'd like to be able to pull the second > payload into the CBFS image that is programmed and have FILO load the > elfImage from CBFS. > > I'm happy to do some work on this, if it's not there right now, and > someone can give me an inital steer into the code. > > Any alterantive suggestions ? As far as I know, SeaBIOS is the only payload that supports launching other CBFS payloads right now. There was some talk on adding CBFS support to libpayload. If this were done, then filo should be able to pull that support in. -Kevin

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[v2] r4555 - trunk/coreboot-v2/targets/via/epia-m
by svn＠coreboot.org 19 Aug '09

19 Aug '09

Author: oxygene Date: 2009-08-19 16:08:42 +0200 (Wed, 19 Aug 2009) New Revision: 4555 Modified: trunk/coreboot-v2/targets/via/epia-m/Config-abuild.lb Log: Config-abuild.lb doesn't need to override ROM_IMAGE_SIZE. Trivial change Signed-off-by: Patrick Georgi <patrick.georgi(a)coresystems.de> Acked-by: Patrick Georgi <patrick.georgi(a)coresystems.de> Modified: trunk/coreboot-v2/targets/via/epia-m/Config-abuild.lb =================================================================== --- trunk/coreboot-v2/targets/via/epia-m/Config-abuild.lb 2009-08-19 13:40:20 UTC (rev 4554) +++ trunk/coreboot-v2/targets/via/epia-m/Config-abuild.lb 2009-08-19 14:08:42 UTC (rev 4555) @@ -12,14 +12,12 @@ romimage "normal" option CONFIG_USE_FALLBACK_IMAGE=0 - option CONFIG_ROM_IMAGE_SIZE=64*1024 option COREBOOT_EXTRA_VERSION=".0-Normal" payload __PAYLOAD__ end romimage "fallback" option CONFIG_USE_FALLBACK_IMAGE=1 - option CONFIG_ROM_IMAGE_SIZE=64*1024 option COREBOOT_EXTRA_VERSION=".0-Fallback" payload __PAYLOAD__ end

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build service results for r4554
by coreboot information 19 Aug '09

19 Aug '09

Dear coreboot readers! This is the automatic build system of coreboot. The developer "oxygene" checked in revision 4554 to the coreboot repository. This caused the following changes: Change Log: Reduce size of the romstage on various boards that fail to build on QA. This eliminates 56kb of padding in the bootblock. Signed-off-by: Patrick Georgi <patrick.georgi(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Build Log: Compilation of a-trend:atc-6220 has been fixed Compilation of a-trend:atc-6240 has been fixed Compilation of abit:be6-ii_v2_0 has been fixed Compilation of asus:p2b has been fixed Compilation of asus:p2b-d has been fixed Compilation of asus:p2b-ds has been fixed Compilation of asus:p2b-f has been fixed Compilation of asus:p3b-f has been fixed Compilation of azza:pt-6ibd has been fixed Compilation of biostar:m6tba has been fixed Compilation of compaq:deskpro_en_sff_p600 has been fixed Compilation of embeddedplanet:ep405pc is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4554&device=ep405pc&vendor… Compilation of gigabyte:ga-6bxc has been fixed Compilation of iei:nova4899r has been fixed Compilation of motorola:sandpointx3_altimus_mpc7410 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4554&device=sandpointx3_al… Compilation of msi:ms6119 has been fixed Compilation of msi:ms6147 has been fixed Compilation of soyo:sy-6ba-plus-iii has been fixed Compilation of totalimpact:briq is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4554&device=briq&vendor=to… Compilation of tyan:s1846 has been fixed Compilation of via:epia-m is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4554&device=epia-m&vendor=… If something broke during this checkin please be a pain in oxygene's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

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Using a large payload with QEMU 0.9.1
by Roman Brehm 19 Aug '09

19 Aug '09

Hello, I'm still working on a coreboot TPM project and want to boot coreboot with a linux payload (and without GRUB/FILO etc.) in QEMU. The minimum size I'm able to reduce it to, is approx. 9-10MB. When I want to start QEMU with this bios-file, I get a memory error because of the (too) large size of the bios. For QEMU 0.9.0 there exists a bios size patch where you can extend the maximum size but for 0.9.1 (which I have to use) there isn't any patch and the concerning source code parts are completely different to 0.9.0. Do you know what's the maximum bios size with 0.9.1 and if there is a possibility to extend it? Or is there another possibility (e.g. to load a small kernel which loads additional data from a hd image or so)? Thanks a lot! Roman

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coreboot August 2009