coreboot August 2009

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[v2] r4554 - in trunk/coreboot-v2/src/mainboard: a-trend/atc-6220 a-trend/atc-6240 abit/be6-ii_v2_0 asus/p2b asus/p2b-d asus/p2b-ds asus/p2b-f asus/p3b-f azza/pt-6ibd biostar/m6tba compaq/deskpro_en_sff_p600 gigabyte/ga-6bxc iei/nova4899r msi/ms6119 msi/ms6147 soyo/sy-6ba-plus-iii tyan/s1846 via/epia-m
by svn＠coreboot.org 19 Aug '09

19 Aug '09

Author: oxygene Date: 2009-08-19 15:40:20 +0200 (Wed, 19 Aug 2009) New Revision: 4554 Modified: trunk/coreboot-v2/src/mainboard/a-trend/atc-6220/Config.lb trunk/coreboot-v2/src/mainboard/a-trend/atc-6220/Options.lb trunk/coreboot-v2/src/mainboard/a-trend/atc-6240/Config.lb trunk/coreboot-v2/src/mainboard/a-trend/atc-6240/Options.lb trunk/coreboot-v2/src/mainboard/abit/be6-ii_v2_0/Config.lb trunk/coreboot-v2/src/mainboard/abit/be6-ii_v2_0/Options.lb trunk/coreboot-v2/src/mainboard/asus/p2b-d/Config.lb trunk/coreboot-v2/src/mainboard/asus/p2b-d/Options.lb trunk/coreboot-v2/src/mainboard/asus/p2b-ds/Config.lb trunk/coreboot-v2/src/mainboard/asus/p2b-ds/Options.lb trunk/coreboot-v2/src/mainboard/asus/p2b-f/Config.lb trunk/coreboot-v2/src/mainboard/asus/p2b-f/Options.lb trunk/coreboot-v2/src/mainboard/asus/p2b/Config.lb trunk/coreboot-v2/src/mainboard/asus/p2b/Options.lb trunk/coreboot-v2/src/mainboard/asus/p3b-f/Config.lb trunk/coreboot-v2/src/mainboard/asus/p3b-f/Options.lb trunk/coreboot-v2/src/mainboard/azza/pt-6ibd/Config.lb trunk/coreboot-v2/src/mainboard/azza/pt-6ibd/Options.lb trunk/coreboot-v2/src/mainboard/biostar/m6tba/Config.lb trunk/coreboot-v2/src/mainboard/biostar/m6tba/Options.lb trunk/coreboot-v2/src/mainboard/compaq/deskpro_en_sff_p600/Config.lb trunk/coreboot-v2/src/mainboard/compaq/deskpro_en_sff_p600/Options.lb trunk/coreboot-v2/src/mainboard/gigabyte/ga-6bxc/Config.lb trunk/coreboot-v2/src/mainboard/gigabyte/ga-6bxc/Options.lb trunk/coreboot-v2/src/mainboard/iei/nova4899r/Config.lb trunk/coreboot-v2/src/mainboard/iei/nova4899r/Options.lb trunk/coreboot-v2/src/mainboard/msi/ms6119/Config.lb trunk/coreboot-v2/src/mainboard/msi/ms6119/Options.lb trunk/coreboot-v2/src/mainboard/msi/ms6147/Config.lb trunk/coreboot-v2/src/mainboard/msi/ms6147/Options.lb trunk/coreboot-v2/src/mainboard/soyo/sy-6ba-plus-iii/Config.lb trunk/coreboot-v2/src/mainboard/soyo/sy-6ba-plus-iii/Options.lb trunk/coreboot-v2/src/mainboard/tyan/s1846/Config.lb trunk/coreboot-v2/src/mainboard/tyan/s1846/Options.lb trunk/coreboot-v2/src/mainboard/via/epia-m/Config.lb trunk/coreboot-v2/src/mainboard/via/epia-m/Options.lb Log: Reduce size of the romstage on various boards that fail to build on QA. This eliminates 56kb of padding in the bootblock. Signed-off-by: Patrick Georgi <patrick.georgi(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/coreboot-v2/src/mainboard/a-trend/atc-6220/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/a-trend/atc-6220/Config.lb 2009-08-19 07:08:10 UTC (rev 4553) +++ trunk/coreboot-v2/src/mainboard/a-trend/atc-6220/Config.lb 2009-08-19 13:40:20 UTC (rev 4554) @@ -19,8 +19,9 @@ ## ## CONFIG_XIP_ROM_SIZE must be a power of 2. -default CONFIG_XIP_ROM_SIZE = 64 * 1024 +default CONFIG_XIP_ROM_SIZE = 128 * 1024 include /config/nofailovercalculation.lb +default CONFIG_XIP_ROM_BASE = 0xffffffff - CONFIG_XIP_ROM_SIZE + 1 arch i386 end driver mainboard.o Modified: trunk/coreboot-v2/src/mainboard/a-trend/atc-6220/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/a-trend/atc-6220/Options.lb 2009-08-19 07:08:10 UTC (rev 4553) +++ trunk/coreboot-v2/src/mainboard/a-trend/atc-6220/Options.lb 2009-08-19 13:40:20 UTC (rev 4554) @@ -76,7 +76,7 @@ default CONFIG_IRQ_SLOT_COUNT = 0 # Override this in targets/*/Config.lb. default CONFIG_MAINBOARD_VENDOR = "N/A" # Override this in targets/*/Config.lb. default CONFIG_MAINBOARD_PART_NUMBER = "N/A" # Override this in targets/*/Config.lb. -default CONFIG_ROM_IMAGE_SIZE = 64 * 1024 +default CONFIG_ROM_IMAGE_SIZE = 36 * 1024 default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE default CONFIG_STACK_SIZE = 8 * 1024 default CONFIG_HEAP_SIZE = 16 * 1024 Modified: trunk/coreboot-v2/src/mainboard/a-trend/atc-6240/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/a-trend/atc-6240/Config.lb 2009-08-19 07:08:10 UTC (rev 4553) +++ trunk/coreboot-v2/src/mainboard/a-trend/atc-6240/Config.lb 2009-08-19 13:40:20 UTC (rev 4554) @@ -19,8 +19,9 @@ ## ## CONFIG_XIP_ROM_SIZE must be a power of 2. -default CONFIG_XIP_ROM_SIZE = 64 * 1024 +default CONFIG_XIP_ROM_SIZE = 128 * 1024 include /config/nofailovercalculation.lb +default CONFIG_XIP_ROM_BASE = 0xffffffff - CONFIG_XIP_ROM_SIZE + 1 arch i386 end driver mainboard.o Modified: trunk/coreboot-v2/src/mainboard/a-trend/atc-6240/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/a-trend/atc-6240/Options.lb 2009-08-19 07:08:10 UTC (rev 4553) +++ trunk/coreboot-v2/src/mainboard/a-trend/atc-6240/Options.lb 2009-08-19 13:40:20 UTC (rev 4554) @@ -76,7 +76,7 @@ default CONFIG_IRQ_SLOT_COUNT = 0 # Override this in targets/*/Config.lb. default CONFIG_MAINBOARD_VENDOR = "N/A" # Override this in targets/*/Config.lb. default CONFIG_MAINBOARD_PART_NUMBER = "N/A" # Override this in targets/*/Config.lb. -default CONFIG_ROM_IMAGE_SIZE = 64 * 1024 +default CONFIG_ROM_IMAGE_SIZE = 36 * 1024 default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE default CONFIG_STACK_SIZE = 8 * 1024 default CONFIG_HEAP_SIZE = 16 * 1024 Modified: trunk/coreboot-v2/src/mainboard/abit/be6-ii_v2_0/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/abit/be6-ii_v2_0/Config.lb 2009-08-19 07:08:10 UTC (rev 4553) +++ trunk/coreboot-v2/src/mainboard/abit/be6-ii_v2_0/Config.lb 2009-08-19 13:40:20 UTC (rev 4554) @@ -19,8 +19,9 @@ ## ## CONFIG_XIP_ROM_SIZE must be a power of 2. -default CONFIG_XIP_ROM_SIZE = 64 * 1024 +default CONFIG_XIP_ROM_SIZE = 128 * 1024 include /config/nofailovercalculation.lb +default CONFIG_XIP_ROM_BASE = 0xffffffff - CONFIG_XIP_ROM_SIZE + 1 arch i386 end driver mainboard.o Modified: trunk/coreboot-v2/src/mainboard/abit/be6-ii_v2_0/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/abit/be6-ii_v2_0/Options.lb 2009-08-19 07:08:10 UTC (rev 4553) +++ trunk/coreboot-v2/src/mainboard/abit/be6-ii_v2_0/Options.lb 2009-08-19 13:40:20 UTC (rev 4554) @@ -77,7 +77,7 @@ default CONFIG_IRQ_SLOT_COUNT = 0 # Override this in targets/*/Config.lb. default CONFIG_MAINBOARD_VENDOR = "N/A" # Override this in targets/*/Config.lb. default CONFIG_MAINBOARD_PART_NUMBER = "N/A" # Override this in targets/*/Config.lb. -default CONFIG_ROM_IMAGE_SIZE = 64 * 1024 +default CONFIG_ROM_IMAGE_SIZE = 36 * 1024 default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE default CONFIG_STACK_SIZE = 8 * 1024 default CONFIG_HEAP_SIZE = 16 * 1024 Modified: trunk/coreboot-v2/src/mainboard/asus/p2b/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/asus/p2b/Config.lb 2009-08-19 07:08:10 UTC (rev 4553) +++ trunk/coreboot-v2/src/mainboard/asus/p2b/Config.lb 2009-08-19 13:40:20 UTC (rev 4554) @@ -19,8 +19,9 @@ ## ## CONFIG_XIP_ROM_SIZE must be a power of 2. -default CONFIG_XIP_ROM_SIZE = 64 * 1024 +default CONFIG_XIP_ROM_SIZE = 128 * 1024 include /config/nofailovercalculation.lb +default CONFIG_XIP_ROM_BASE = 0xffffffff - CONFIG_XIP_ROM_SIZE + 1 arch i386 end driver mainboard.o Modified: trunk/coreboot-v2/src/mainboard/asus/p2b/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/asus/p2b/Options.lb 2009-08-19 07:08:10 UTC (rev 4553) +++ trunk/coreboot-v2/src/mainboard/asus/p2b/Options.lb 2009-08-19 13:40:20 UTC (rev 4554) @@ -77,7 +77,7 @@ default CONFIG_IRQ_SLOT_COUNT = 0 # Override this in targets/*/Config.lb. default CONFIG_MAINBOARD_VENDOR = "N/A" # Override this in targets/*/Config.lb. default CONFIG_MAINBOARD_PART_NUMBER = "N/A" # Override this in targets/*/Config.lb. -default CONFIG_ROM_IMAGE_SIZE = 64 * 1024 +default CONFIG_ROM_IMAGE_SIZE = 36 * 1024 default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE default CONFIG_STACK_SIZE = 8 * 1024 default CONFIG_HEAP_SIZE = 16 * 1024 Modified: trunk/coreboot-v2/src/mainboard/asus/p2b-d/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/asus/p2b-d/Config.lb 2009-08-19 07:08:10 UTC (rev 4553) +++ trunk/coreboot-v2/src/mainboard/asus/p2b-d/Config.lb 2009-08-19 13:40:20 UTC (rev 4554) @@ -19,8 +19,9 @@ ## ## CONFIG_XIP_ROM_SIZE must be a power of 2. -default CONFIG_XIP_ROM_SIZE = 64 * 1024 +default CONFIG_XIP_ROM_SIZE = 128 * 1024 include /config/nofailovercalculation.lb +default CONFIG_XIP_ROM_BASE = 0xffffffff - CONFIG_XIP_ROM_SIZE + 1 arch i386 end driver mainboard.o Modified: trunk/coreboot-v2/src/mainboard/asus/p2b-d/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/asus/p2b-d/Options.lb 2009-08-19 07:08:10 UTC (rev 4553) +++ trunk/coreboot-v2/src/mainboard/asus/p2b-d/Options.lb 2009-08-19 13:40:20 UTC (rev 4554) @@ -80,7 +80,7 @@ default CONFIG_IRQ_SLOT_COUNT = 0 # Override this in targets/*/Config.lb. default CONFIG_MAINBOARD_VENDOR = "N/A" # Override this in targets/*/Config.lb. default CONFIG_MAINBOARD_PART_NUMBER = "N/A" # Override this in targets/*/Config.lb. -default CONFIG_ROM_IMAGE_SIZE = 64 * 1024 +default CONFIG_ROM_IMAGE_SIZE = 36 * 1024 default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE default CONFIG_STACK_SIZE = 8 * 1024 default CONFIG_HEAP_SIZE = 16 * 1024 Modified: trunk/coreboot-v2/src/mainboard/asus/p2b-ds/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/asus/p2b-ds/Config.lb 2009-08-19 07:08:10 UTC (rev 4553) +++ trunk/coreboot-v2/src/mainboard/asus/p2b-ds/Config.lb 2009-08-19 13:40:20 UTC (rev 4554) @@ -19,8 +19,9 @@ ## ## CONFIG_XIP_ROM_SIZE must be a power of 2. -default CONFIG_XIP_ROM_SIZE = 64 * 1024 +default CONFIG_XIP_ROM_SIZE = 128 * 1024 include /config/nofailovercalculation.lb +default CONFIG_XIP_ROM_BASE = 0xffffffff - CONFIG_XIP_ROM_SIZE + 1 arch i386 end driver mainboard.o Modified: trunk/coreboot-v2/src/mainboard/asus/p2b-ds/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/asus/p2b-ds/Options.lb 2009-08-19 07:08:10 UTC (rev 4553) +++ trunk/coreboot-v2/src/mainboard/asus/p2b-ds/Options.lb 2009-08-19 13:40:20 UTC (rev 4554) @@ -80,7 +80,7 @@ default CONFIG_IRQ_SLOT_COUNT = 0 # Override this in targets/*/Config.lb. default CONFIG_MAINBOARD_VENDOR = "N/A" # Override this in targets/*/Config.lb. default CONFIG_MAINBOARD_PART_NUMBER = "N/A" # Override this in targets/*/Config.lb. -default CONFIG_ROM_IMAGE_SIZE = 64 * 1024 +default CONFIG_ROM_IMAGE_SIZE = 36 * 1024 default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE default CONFIG_STACK_SIZE = 8 * 1024 default CONFIG_HEAP_SIZE = 16 * 1024 Modified: trunk/coreboot-v2/src/mainboard/asus/p2b-f/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/asus/p2b-f/Config.lb 2009-08-19 07:08:10 UTC (rev 4553) +++ trunk/coreboot-v2/src/mainboard/asus/p2b-f/Config.lb 2009-08-19 13:40:20 UTC (rev 4554) @@ -19,8 +19,9 @@ ## ## CONFIG_XIP_ROM_SIZE must be a power of 2. -default CONFIG_XIP_ROM_SIZE = 64 * 1024 +default CONFIG_XIP_ROM_SIZE = 128 * 1024 include /config/nofailovercalculation.lb +default CONFIG_XIP_ROM_BASE = 0xffffffff - CONFIG_XIP_ROM_SIZE + 1 arch i386 end driver mainboard.o Modified: trunk/coreboot-v2/src/mainboard/asus/p2b-f/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/asus/p2b-f/Options.lb 2009-08-19 07:08:10 UTC (rev 4553) +++ trunk/coreboot-v2/src/mainboard/asus/p2b-f/Options.lb 2009-08-19 13:40:20 UTC (rev 4554) @@ -76,7 +76,7 @@ default CONFIG_IRQ_SLOT_COUNT = 0 # Override this in targets/*/Config.lb. default CONFIG_MAINBOARD_VENDOR = "N/A" # Override this in targets/*/Config.lb. default CONFIG_MAINBOARD_PART_NUMBER = "N/A" # Override this in targets/*/Config.lb. -default CONFIG_ROM_IMAGE_SIZE = 64 * 1024 +default CONFIG_ROM_IMAGE_SIZE = 36 * 1024 default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE default CONFIG_STACK_SIZE = 8 * 1024 default CONFIG_HEAP_SIZE = 16 * 1024 Modified: trunk/coreboot-v2/src/mainboard/asus/p3b-f/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/asus/p3b-f/Config.lb 2009-08-19 07:08:10 UTC (rev 4553) +++ trunk/coreboot-v2/src/mainboard/asus/p3b-f/Config.lb 2009-08-19 13:40:20 UTC (rev 4554) @@ -19,8 +19,9 @@ ## ## CONFIG_XIP_ROM_SIZE must be a power of 2. -default CONFIG_XIP_ROM_SIZE = 64 * 1024 +default CONFIG_XIP_ROM_SIZE = 128 * 1024 include /config/nofailovercalculation.lb +default CONFIG_XIP_ROM_BASE = 0xffffffff - CONFIG_XIP_ROM_SIZE + 1 arch i386 end driver mainboard.o Modified: trunk/coreboot-v2/src/mainboard/asus/p3b-f/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/asus/p3b-f/Options.lb 2009-08-19 07:08:10 UTC (rev 4553) +++ trunk/coreboot-v2/src/mainboard/asus/p3b-f/Options.lb 2009-08-19 13:40:20 UTC (rev 4554) @@ -76,7 +76,7 @@ default CONFIG_IRQ_SLOT_COUNT = 0 # Override this in targets/*/Config.lb. default CONFIG_MAINBOARD_VENDOR = "N/A" # Override this in targets/*/Config.lb. default CONFIG_MAINBOARD_PART_NUMBER = "N/A" # Override this in targets/*/Config.lb. -default CONFIG_ROM_IMAGE_SIZE = 64 * 1024 +default CONFIG_ROM_IMAGE_SIZE = 36 * 1024 default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE default CONFIG_STACK_SIZE = 8 * 1024 default CONFIG_HEAP_SIZE = 16 * 1024 Modified: trunk/coreboot-v2/src/mainboard/azza/pt-6ibd/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/azza/pt-6ibd/Config.lb 2009-08-19 07:08:10 UTC (rev 4553) +++ trunk/coreboot-v2/src/mainboard/azza/pt-6ibd/Config.lb 2009-08-19 13:40:20 UTC (rev 4554) @@ -19,8 +19,9 @@ ## ## CONFIG_XIP_ROM_SIZE must be a power of 2. -default CONFIG_XIP_ROM_SIZE = 64 * 1024 +default CONFIG_XIP_ROM_SIZE = 128 * 1024 include /config/nofailovercalculation.lb +default CONFIG_XIP_ROM_BASE = 0xffffffff - CONFIG_XIP_ROM_SIZE + 1 arch i386 end driver mainboard.o if CONFIG_HAVE_PIRQ_TABLE Modified: trunk/coreboot-v2/src/mainboard/azza/pt-6ibd/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/azza/pt-6ibd/Options.lb 2009-08-19 07:08:10 UTC (rev 4553) +++ trunk/coreboot-v2/src/mainboard/azza/pt-6ibd/Options.lb 2009-08-19 13:40:20 UTC (rev 4554) @@ -76,7 +76,7 @@ default CONFIG_IRQ_SLOT_COUNT = 0 # Override this in targets/*/Config.lb. default CONFIG_MAINBOARD_VENDOR = "N/A" # Override this in targets/*/Config.lb. default CONFIG_MAINBOARD_PART_NUMBER = "N/A" # Override this in targets/*/Config.lb. -default CONFIG_ROM_IMAGE_SIZE = 64 * 1024 +default CONFIG_ROM_IMAGE_SIZE = 36 * 1024 default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE default CONFIG_STACK_SIZE = 8 * 1024 default CONFIG_HEAP_SIZE = 16 * 1024 Modified: trunk/coreboot-v2/src/mainboard/biostar/m6tba/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/biostar/m6tba/Config.lb 2009-08-19 07:08:10 UTC (rev 4553) +++ trunk/coreboot-v2/src/mainboard/biostar/m6tba/Config.lb 2009-08-19 13:40:20 UTC (rev 4554) @@ -19,8 +19,9 @@ ## ## CONFIG_XIP_ROM_SIZE must be a power of 2. -default CONFIG_XIP_ROM_SIZE = 64 * 1024 +default CONFIG_XIP_ROM_SIZE = 128 * 1024 include /config/nofailovercalculation.lb +default CONFIG_XIP_ROM_BASE = 0xffffffff - CONFIG_XIP_ROM_SIZE + 1 arch i386 end driver mainboard.o Modified: trunk/coreboot-v2/src/mainboard/biostar/m6tba/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/biostar/m6tba/Options.lb 2009-08-19 07:08:10 UTC (rev 4553) +++ trunk/coreboot-v2/src/mainboard/biostar/m6tba/Options.lb 2009-08-19 13:40:20 UTC (rev 4554) @@ -76,7 +76,7 @@ default CONFIG_IRQ_SLOT_COUNT = 0 # Override this in targets/*/Config.lb. default CONFIG_MAINBOARD_VENDOR = "N/A" # Override this in targets/*/Config.lb. default CONFIG_MAINBOARD_PART_NUMBER = "N/A" # Override this in targets/*/Config.lb. -default CONFIG_ROM_IMAGE_SIZE = 64 * 1024 +default CONFIG_ROM_IMAGE_SIZE = 36 * 1024 default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE default CONFIG_STACK_SIZE = 8 * 1024 default CONFIG_HEAP_SIZE = 16 * 1024 Modified: trunk/coreboot-v2/src/mainboard/compaq/deskpro_en_sff_p600/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/compaq/deskpro_en_sff_p600/Config.lb 2009-08-19 07:08:10 UTC (rev 4553) +++ trunk/coreboot-v2/src/mainboard/compaq/deskpro_en_sff_p600/Config.lb 2009-08-19 13:40:20 UTC (rev 4554) @@ -19,8 +19,9 @@ ## ## CONFIG_XIP_ROM_SIZE must be a power of 2. -default CONFIG_XIP_ROM_SIZE = 64 * 1024 +default CONFIG_XIP_ROM_SIZE = 128 * 1024 include /config/nofailovercalculation.lb +default CONFIG_XIP_ROM_BASE = 0xffffffff - CONFIG_XIP_ROM_SIZE + 1 arch i386 end driver mainboard.o Modified: trunk/coreboot-v2/src/mainboard/compaq/deskpro_en_sff_p600/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/compaq/deskpro_en_sff_p600/Options.lb 2009-08-19 07:08:10 UTC (rev 4553) +++ trunk/coreboot-v2/src/mainboard/compaq/deskpro_en_sff_p600/Options.lb 2009-08-19 13:40:20 UTC (rev 4554) @@ -76,7 +76,7 @@ default CONFIG_IRQ_SLOT_COUNT = 0 # Override this in targets/*/Config.lb. default CONFIG_MAINBOARD_VENDOR = "N/A" # Override this in targets/*/Config.lb. default CONFIG_MAINBOARD_PART_NUMBER = "N/A" # Override this in targets/*/Config.lb. -default CONFIG_ROM_IMAGE_SIZE = 64 * 1024 +default CONFIG_ROM_IMAGE_SIZE = 36 * 1024 default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE default CONFIG_STACK_SIZE = 8 * 1024 default CONFIG_HEAP_SIZE = 16 * 1024 Modified: trunk/coreboot-v2/src/mainboard/gigabyte/ga-6bxc/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/gigabyte/ga-6bxc/Config.lb 2009-08-19 07:08:10 UTC (rev 4553) +++ trunk/coreboot-v2/src/mainboard/gigabyte/ga-6bxc/Config.lb 2009-08-19 13:40:20 UTC (rev 4554) @@ -19,8 +19,9 @@ ## ## CONFIG_XIP_ROM_SIZE must be a power of 2. -default CONFIG_XIP_ROM_SIZE = 64 * 1024 +default CONFIG_XIP_ROM_SIZE = 128 * 1024 include /config/nofailovercalculation.lb +default CONFIG_XIP_ROM_BASE = 0xffffffff - CONFIG_XIP_ROM_SIZE + 1 arch i386 end driver mainboard.o Modified: trunk/coreboot-v2/src/mainboard/gigabyte/ga-6bxc/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/gigabyte/ga-6bxc/Options.lb 2009-08-19 07:08:10 UTC (rev 4553) +++ trunk/coreboot-v2/src/mainboard/gigabyte/ga-6bxc/Options.lb 2009-08-19 13:40:20 UTC (rev 4554) @@ -76,7 +76,7 @@ default CONFIG_IRQ_SLOT_COUNT = 0 # Override this in targets/*/Config.lb. default CONFIG_MAINBOARD_VENDOR = "N/A" # Override this in targets/*/Config.lb. default CONFIG_MAINBOARD_PART_NUMBER = "N/A" # Override this in targets/*/Config.lb. -default CONFIG_ROM_IMAGE_SIZE = 64 * 1024 +default CONFIG_ROM_IMAGE_SIZE = 36 * 1024 default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE default CONFIG_STACK_SIZE = 8 * 1024 default CONFIG_HEAP_SIZE = 16 * 1024 Modified: trunk/coreboot-v2/src/mainboard/iei/nova4899r/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/iei/nova4899r/Config.lb 2009-08-19 07:08:10 UTC (rev 4553) +++ trunk/coreboot-v2/src/mainboard/iei/nova4899r/Config.lb 2009-08-19 13:40:20 UTC (rev 4554) @@ -1,6 +1,7 @@ ## CONFIG_XIP_ROM_SIZE must be a power of 2. -default CONFIG_XIP_ROM_SIZE = 64 * 1024 +default CONFIG_XIP_ROM_SIZE = 128 * 1024 include /config/nofailovercalculation.lb +default CONFIG_XIP_ROM_BASE = 0xffffffff - CONFIG_XIP_ROM_SIZE + 1 ## ## Set all of the defaults for an x86 architecture Modified: trunk/coreboot-v2/src/mainboard/iei/nova4899r/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/iei/nova4899r/Options.lb 2009-08-19 07:08:10 UTC (rev 4553) +++ trunk/coreboot-v2/src/mainboard/iei/nova4899r/Options.lb 2009-08-19 13:40:20 UTC (rev 4554) @@ -97,7 +97,7 @@ ### ## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. -default CONFIG_ROM_IMAGE_SIZE = 65536 +default CONFIG_ROM_IMAGE_SIZE = 36 * 1024 default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE ## Modified: trunk/coreboot-v2/src/mainboard/msi/ms6119/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/msi/ms6119/Config.lb 2009-08-19 07:08:10 UTC (rev 4553) +++ trunk/coreboot-v2/src/mainboard/msi/ms6119/Config.lb 2009-08-19 13:40:20 UTC (rev 4554) @@ -19,8 +19,9 @@ ## ## CONFIG_XIP_ROM_SIZE must be a power of 2. -default CONFIG_XIP_ROM_SIZE = 64 * 1024 +default CONFIG_XIP_ROM_SIZE = 128 * 1024 include /config/nofailovercalculation.lb +default CONFIG_XIP_ROM_BASE = 0xffffffff - CONFIG_XIP_ROM_SIZE + 1 arch i386 end driver mainboard.o Modified: trunk/coreboot-v2/src/mainboard/msi/ms6119/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/msi/ms6119/Options.lb 2009-08-19 07:08:10 UTC (rev 4553) +++ trunk/coreboot-v2/src/mainboard/msi/ms6119/Options.lb 2009-08-19 13:40:20 UTC (rev 4554) @@ -76,7 +76,7 @@ default CONFIG_IRQ_SLOT_COUNT = 0 # Override this in targets/*/Config.lb. default CONFIG_MAINBOARD_VENDOR = "N/A" # Override this in targets/*/Config.lb. default CONFIG_MAINBOARD_PART_NUMBER = "N/A" # Override this in targets/*/Config.lb. -default CONFIG_ROM_IMAGE_SIZE = 64 * 1024 +default CONFIG_ROM_IMAGE_SIZE = 36 * 1024 default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE default CONFIG_STACK_SIZE = 8 * 1024 default CONFIG_HEAP_SIZE = 16 * 1024 Modified: trunk/coreboot-v2/src/mainboard/msi/ms6147/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/msi/ms6147/Config.lb 2009-08-19 07:08:10 UTC (rev 4553) +++ trunk/coreboot-v2/src/mainboard/msi/ms6147/Config.lb 2009-08-19 13:40:20 UTC (rev 4554) @@ -19,8 +19,9 @@ ## ## CONFIG_XIP_ROM_SIZE must be a power of 2. -default CONFIG_XIP_ROM_SIZE = 64 * 1024 +default CONFIG_XIP_ROM_SIZE = 128 * 1024 include /config/nofailovercalculation.lb +default CONFIG_XIP_ROM_BASE = 0xffffffff - CONFIG_XIP_ROM_SIZE + 1 arch i386 end driver mainboard.o Modified: trunk/coreboot-v2/src/mainboard/msi/ms6147/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/msi/ms6147/Options.lb 2009-08-19 07:08:10 UTC (rev 4553) +++ trunk/coreboot-v2/src/mainboard/msi/ms6147/Options.lb 2009-08-19 13:40:20 UTC (rev 4554) @@ -76,7 +76,7 @@ default CONFIG_IRQ_SLOT_COUNT = 0 # Override this in targets/*/Config.lb. default CONFIG_MAINBOARD_VENDOR = "N/A" # Override this in targets/*/Config.lb. default CONFIG_MAINBOARD_PART_NUMBER = "N/A" # Override this in targets/*/Config.lb. -default CONFIG_ROM_IMAGE_SIZE = 64 * 1024 +default CONFIG_ROM_IMAGE_SIZE = 36 * 1024 default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE default CONFIG_STACK_SIZE = 8 * 1024 default CONFIG_HEAP_SIZE = 16 * 1024 Modified: trunk/coreboot-v2/src/mainboard/soyo/sy-6ba-plus-iii/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/soyo/sy-6ba-plus-iii/Config.lb 2009-08-19 07:08:10 UTC (rev 4553) +++ trunk/coreboot-v2/src/mainboard/soyo/sy-6ba-plus-iii/Config.lb 2009-08-19 13:40:20 UTC (rev 4554) @@ -19,8 +19,9 @@ ## ## CONFIG_XIP_ROM_SIZE must be a power of 2. -default CONFIG_XIP_ROM_SIZE = 64 * 1024 +default CONFIG_XIP_ROM_SIZE = 128 * 1024 include /config/nofailovercalculation.lb +default CONFIG_XIP_ROM_BASE = 0xffffffff - CONFIG_XIP_ROM_SIZE + 1 arch i386 end driver mainboard.o Modified: trunk/coreboot-v2/src/mainboard/soyo/sy-6ba-plus-iii/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/soyo/sy-6ba-plus-iii/Options.lb 2009-08-19 07:08:10 UTC (rev 4553) +++ trunk/coreboot-v2/src/mainboard/soyo/sy-6ba-plus-iii/Options.lb 2009-08-19 13:40:20 UTC (rev 4554) @@ -76,7 +76,7 @@ default CONFIG_IRQ_SLOT_COUNT = 0 # Override this in targets/*/Config.lb. default CONFIG_MAINBOARD_VENDOR = "N/A" # Override this in targets/*/Config.lb. default CONFIG_MAINBOARD_PART_NUMBER = "N/A" # Override this in targets/*/Config.lb. -default CONFIG_ROM_IMAGE_SIZE = 64 * 1024 +default CONFIG_ROM_IMAGE_SIZE = 36 * 1024 default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE default CONFIG_STACK_SIZE = 8 * 1024 default CONFIG_HEAP_SIZE = 16 * 1024 Modified: trunk/coreboot-v2/src/mainboard/tyan/s1846/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s1846/Config.lb 2009-08-19 07:08:10 UTC (rev 4553) +++ trunk/coreboot-v2/src/mainboard/tyan/s1846/Config.lb 2009-08-19 13:40:20 UTC (rev 4554) @@ -19,8 +19,9 @@ ## ## CONFIG_XIP_ROM_SIZE must be a power of 2. -default CONFIG_XIP_ROM_SIZE = 64 * 1024 +default CONFIG_XIP_ROM_SIZE = 128 * 1024 include /config/nofailovercalculation.lb +default CONFIG_XIP_ROM_BASE = 0xffffffff - CONFIG_XIP_ROM_SIZE + 1 arch i386 end driver mainboard.o Modified: trunk/coreboot-v2/src/mainboard/tyan/s1846/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s1846/Options.lb 2009-08-19 07:08:10 UTC (rev 4553) +++ trunk/coreboot-v2/src/mainboard/tyan/s1846/Options.lb 2009-08-19 13:40:20 UTC (rev 4554) @@ -77,7 +77,7 @@ default CONFIG_IRQ_SLOT_COUNT = 0 # Override this in targets/*/Config.lb. default CONFIG_MAINBOARD_VENDOR = "N/A" # Override this in targets/*/Config.lb. default CONFIG_MAINBOARD_PART_NUMBER = "N/A" # Override this in targets/*/Config.lb. -default CONFIG_ROM_IMAGE_SIZE = 64 * 1024 +default CONFIG_ROM_IMAGE_SIZE = 36 * 1024 default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE default CONFIG_STACK_SIZE = 8 * 1024 default CONFIG_HEAP_SIZE = 16 * 1024 Modified: trunk/coreboot-v2/src/mainboard/via/epia-m/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/via/epia-m/Config.lb 2009-08-19 07:08:10 UTC (rev 4553) +++ trunk/coreboot-v2/src/mainboard/via/epia-m/Config.lb 2009-08-19 13:40:20 UTC (rev 4554) @@ -1,6 +1,7 @@ ## CONFIG_XIP_ROM_SIZE must be a power of 2. -default CONFIG_XIP_ROM_SIZE = 64 * 1024 +default CONFIG_XIP_ROM_SIZE = 128 * 1024 include /config/nofailovercalculation.lb +default CONFIG_XIP_ROM_BASE = 0xffffffff - CONFIG_XIP_ROM_SIZE + 1 ## ## Set all of the defaults for an x86 architecture Modified: trunk/coreboot-v2/src/mainboard/via/epia-m/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/via/epia-m/Options.lb 2009-08-19 07:08:10 UTC (rev 4553) +++ trunk/coreboot-v2/src/mainboard/via/epia-m/Options.lb 2009-08-19 13:40:20 UTC (rev 4554) @@ -100,7 +100,7 @@ ### ## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. -default CONFIG_ROM_IMAGE_SIZE = 65536 +default CONFIG_ROM_IMAGE_SIZE = 36 * 1024 default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE ##

1 0

[PATCH] Fix some of our boards
by Patrick Georgi 19 Aug '09

19 Aug '09

Hi, attached patch reduces the size of the romstage of various boards to 36kb. As this breaks the automatic XIP mechanism (which requires sizes in powers of two), I added a XIP region of 128kb, which spans both images (and some more). This should fix the build of all currently broken (see qa.coreboot.org) x86 boards. The PPC boards have a different issue and will be handled separately. Signed-off-by: Patrick Georgi <patrick.georgi(a)coresystems.de>

2 1

Re: [coreboot] [filo] How to boot secondary payload from flash using FILO ?
by Harrison, Jon (SELEX GALILEO, UK) 19 Aug '09

19 Aug '09

Ok. So a bit more digging and Bayou looks like something worth looking rather than FILO CBFS support. Drawback is that it looks like Bayou is not really CBFS friendly right now and sort of duplicates some functionality that you get with CBFS too ?? Also, this means ending up with effectively a minimum 3 payloads in precious Flash rather than 2 (Bayou + Payload2 + (FILO --> /dev/hda)) Vs ((FILO --> /dev/hda) + Payload2) Hmmmm. Think I still like the idea of direct CBFS support in FILO. > -----Original Message----- > From: Harrison, Jon (SELEX GALILEO, UK) > Sent: 19 August 2009 13:34 > To: 'coreboot(a)coreboot.org' > Subject: [filo] How to boot secondary payload from flash using FILO ? > > > Hi Guys, > > What I'd like to do now is to use filo to boot either Linux > for SATA (Working already) or a second Payload/ElfImage from Flash. > > Ideally, for maximum efficiency, I'd like to be able to pull > the second payload into the CBFS image that is programmed and > have FILO load the elfImage from CBFS. > > I'm happy to do some work on this, if it's not there right > now, and someone can give me an inital steer into the code. > > Any alterantive suggestions ? > > Jon SELEX Sensors and Airborne Systems Limited Registered Office: Sigma House, Christopher Martin Road, Basildon, Essex SS14 3EL A company registered in England & Wales. Company no. 02426132 ******************************************************************** This email and any attachments are confidential to the intended recipient and may also be privileged. If you are not the intended recipient please delete it from your system and notify the sender. You should not copy it or use it for any purpose nor disclose or distribute its contents to any other person. ********************************************************************

1 0

[filo] How to boot secondary payload from flash using FILO ?
by Harrison, Jon (SELEX GALILEO, UK) 19 Aug '09

19 Aug '09

Hi Guys, What I'd like to do now is to use filo to boot either Linux for SATA (Working already) or a second Payload/ElfImage from Flash. Ideally, for maximum efficiency, I'd like to be able to pull the second payload into the CBFS image that is programmed and have FILO load the elfImage from CBFS. I'm happy to do some work on this, if it's not there right now, and someone can give me an inital steer into the code. Any alterantive suggestions ? Jon SELEX Sensors and Airborne Systems Limited Registered Office: Sigma House, Christopher Martin Road, Basildon, Essex SS14 3EL A company registered in England & Wales. Company no. 02426132 ******************************************************************** This email and any attachments are confidential to the intended recipient and may also be privileged. If you are not the intended recipient please delete it from your system and notify the sender. You should not copy it or use it for any purpose nor disclose or distribute its contents to any other person. ********************************************************************

1 0

Re: [coreboot] build service results for r4549
by Myles Watson 19 Aug '09

19 Aug '09

> Looks like files got patched but new files didn't get added. Yep. Sorry I botched it. Rev 4550. Thanks, Myles

2 2

build service results for r4553
by coreboot information 19 Aug '09

19 Aug '09

Dear coreboot readers! This is the automatic build system of coreboot. The developer "zbao" checked in revision 4553 to the coreboot repository. This caused the following changes: Change Log: The Errata350 is "Write 0000_8000h to register F2x[1, 0]9C_xD080F0C.", instead of F2x[1, 0]9C_x0C. It is a obvious bug. Some typos are also fixed. Signed-off-by: Zheng Bao <zheng.bao(a)amd.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Build Log: Compilation of a-trend:atc-6220 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4553&device=atc-6220&vendo… Compilation of a-trend:atc-6240 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4553&device=atc-6240&vendo… Compilation of abit:be6-ii_v2_0 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4553&device=be6-ii_v2_0&ve… Compilation of asus:p2b is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4553&device=p2b&vendor=asu… Compilation of asus:p2b-d is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4553&device=p2b-d&vendor=a… Compilation of asus:p2b-ds is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4553&device=p2b-ds&vendor=… Compilation of asus:p2b-f is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4553&device=p2b-f&vendor=a… Compilation of asus:p3b-f is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4553&device=p3b-f&vendor=a… Compilation of azza:pt-6ibd is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4553&device=pt-6ibd&vendor… Compilation of biostar:m6tba is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4553&device=m6tba&vendor=b… Compilation of compaq:deskpro_en_sff_p600 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4553&device=deskpro_en_sff… Compilation of embeddedplanet:ep405pc is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4553&device=ep405pc&vendor… Compilation of gigabyte:ga-6bxc is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4553&device=ga-6bxc&vendor… Compilation of iei:nova4899r is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4553&device=nova4899r&vend… Compilation of motorola:sandpointx3_altimus_mpc7410 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4553&device=sandpointx3_al… Compilation of msi:ms6119 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4553&device=ms6119&vendor=… Compilation of msi:ms6147 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4553&device=ms6147&vendor=… Compilation of soyo:sy-6ba-plus-iii is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4553&device=sy-6ba-plus-ii… Compilation of totalimpact:briq is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4553&device=briq&vendor=to… Compilation of tyan:s1846 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4553&device=s1846&vendor=t… Compilation of via:epia-m is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4553&device=epia-m&vendor=… If something broke during this checkin please be a pain in zbao's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

1 0

[PATCH]:The Errata350 is fixed as the way it should be
by Bao, Zheng 19 Aug '09

19 Aug '09

The Errata350 is "Write 0000_8000h to register F2x[1, 0]9C_xD080F0C.", instead of F2x[1, 0]9C_x0C. It is a obvious bug. Some typos are also fixed. Index: src/northbridge/amd/amdmct/wrappers/mcti_d.c =================================================================== --- src/northbridge/amd/amdmct/wrappers/mcti_d.c (revision 4521) +++ src/northbridge/amd/amdmct/wrappers/mcti_d.c (working copy) @@ -347,45 +347,45 @@ u32Addr = mct_GetRcvrSysAddr_D(pMCTstat, pDCTstat, u8Channel, u8Receiver, &u8Valid); if(!u8Valid) { /* Address not supported on current CS */ - print_t("vErrara350: Address not supported on current CS\n"); + print_t("vErrata350: Address not supported on current CS\n"); continue; } - print_t("vErrara350: dummy read \n"); + print_t("vErrata350: dummy read \n"); read32_fs(u32Addr); } } - print_t("vErrara350: step 2a\n"); + print_t("vErrata350: step 2a\n"); /* 2. Write 0000_8000h to register F2x[1, 0]9C_xD080F0C. */ u32DctDev = pDCTstat->dev_dct; - Set_NB32_index_wait(u32DctDev, 0x098, 0x0c, 0x00008000); + Set_NB32_index_wait(u32DctDev, 0x098, 0xD080F0C, 0x00008000); /* ^--- value - ^---F2x[1, 0]9C_x0C DRAM Phy Miscellaneous Register + ^---F2x[1, 0]9C_x0D080F0C, No description in BKDG. ^----F2x[1, 0]98 DRAM Controller Additional Data Offset Register */ if(!pDCTstat->GangedMode) { - print_t("vErrara350: step 2b\n"); - Set_NB32_index_wait(u32DctDev, 0x198, 0x0c, 0x00008000); + print_t("vErrata350: step 2b\n"); + Set_NB32_index_wait(u32DctDev, 0x198, 0xD080F0C, 0x00008000); /* ^--- value - ^---F2x[1, 0]9C_x0C DRAM Phy Miscellaneous Register + ^---F2x[1, 0]9C_x0D080F0C, No description in BKDG ^----F2x[1, 0]98 DRAM Controller Additional Data Offset Register */ } - print_t("vErrara350: step 3\n"); + print_t("vErrata350: step 3\n"); /* 3. Wait at least 300 nanoseconds. */ coreDelay(); - print_t("vErrara350: step 4\n"); + print_t("vErrata350: step 4\n"); /* 4. Write 0000_0000h to register F2x[1, 0]9C_xD080F0C. */ - Set_NB32_index_wait(u32DctDev, 0x098, 0x0c, 0x00000000); + Set_NB32_index_wait(u32DctDev, 0x098, 0xD080F0C, 0x00000000); if(!pDCTstat->GangedMode) { - print_t("vErrara350: step 4b\n"); - Set_NB32_index_wait(u32DctDev, 0x198, 0x0c, 0x00000000); + print_t("vErrata350: step 4b\n"); + Set_NB32_index_wait(u32DctDev, 0x198, 0xD080F0C, 0x00000000); } - print_t("vErrara350: step 5\n"); + print_t("vErrata350: step 5\n"); /* 5. Wait at least 2 microseconds. */ coreDelay();

2 2

[v2] r4553 - trunk/coreboot-v2/src/northbridge/amd/amdmct/wrappers
by svn＠coreboot.org 19 Aug '09

19 Aug '09

Author: zbao Date: 2009-08-19 09:08:10 +0200 (Wed, 19 Aug 2009) New Revision: 4553 Modified: trunk/coreboot-v2/src/northbridge/amd/amdmct/wrappers/mcti_d.c Log: The Errata350 is "Write 0000_8000h to register F2x[1, 0]9C_xD080F0C.", instead of F2x[1, 0]9C_x0C. It is a obvious bug. Some typos are also fixed. Signed-off-by: Zheng Bao <zheng.bao(a)amd.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Modified: trunk/coreboot-v2/src/northbridge/amd/amdmct/wrappers/mcti_d.c =================================================================== --- trunk/coreboot-v2/src/northbridge/amd/amdmct/wrappers/mcti_d.c 2009-08-18 17:15:39 UTC (rev 4552) +++ trunk/coreboot-v2/src/northbridge/amd/amdmct/wrappers/mcti_d.c 2009-08-19 07:08:10 UTC (rev 4553) @@ -347,45 +347,45 @@ u32Addr = mct_GetRcvrSysAddr_D(pMCTstat, pDCTstat, u8Channel, u8Receiver, &u8Valid); if(!u8Valid) { /* Address not supported on current CS */ - print_t("vErrara350: Address not supported on current CS\n"); + print_t("vErrata350: Address not supported on current CS\n"); continue; } - print_t("vErrara350: dummy read \n"); + print_t("vErrata350: dummy read \n"); read32_fs(u32Addr); } } - print_t("vErrara350: step 2a\n"); + print_t("vErrata350: step 2a\n"); /* 2. Write 0000_8000h to register F2x[1, 0]9C_xD080F0C. */ u32DctDev = pDCTstat->dev_dct; - Set_NB32_index_wait(u32DctDev, 0x098, 0x0c, 0x00008000); + Set_NB32_index_wait(u32DctDev, 0x098, 0xD080F0C, 0x00008000); /* ^--- value - ^---F2x[1, 0]9C_x0C DRAM Phy Miscellaneous Register + ^---F2x[1, 0]9C_x0D080F0C, No description in BKDG. ^----F2x[1, 0]98 DRAM Controller Additional Data Offset Register */ if(!pDCTstat->GangedMode) { - print_t("vErrara350: step 2b\n"); - Set_NB32_index_wait(u32DctDev, 0x198, 0x0c, 0x00008000); + print_t("vErrata350: step 2b\n"); + Set_NB32_index_wait(u32DctDev, 0x198, 0xD080F0C, 0x00008000); /* ^--- value - ^---F2x[1, 0]9C_x0C DRAM Phy Miscellaneous Register + ^---F2x[1, 0]9C_x0D080F0C, No description in BKDG ^----F2x[1, 0]98 DRAM Controller Additional Data Offset Register */ } - print_t("vErrara350: step 3\n"); + print_t("vErrata350: step 3\n"); /* 3. Wait at least 300 nanoseconds. */ coreDelay(); - print_t("vErrara350: step 4\n"); + print_t("vErrata350: step 4\n"); /* 4. Write 0000_0000h to register F2x[1, 0]9C_xD080F0C. */ - Set_NB32_index_wait(u32DctDev, 0x098, 0x0c, 0x00000000); + Set_NB32_index_wait(u32DctDev, 0x098, 0xD080F0C, 0x00000000); if(!pDCTstat->GangedMode) { - print_t("vErrara350: step 4b\n"); - Set_NB32_index_wait(u32DctDev, 0x198, 0x0c, 0x00000000); + print_t("vErrata350: step 4b\n"); + Set_NB32_index_wait(u32DctDev, 0x198, 0xD080F0C, 0x00000000); } - print_t("vErrara350: step 5\n"); + print_t("vErrata350: step 5\n"); /* 5. Wait at least 2 microseconds. */ coreDelay();

1 0

SeaBIOS and CBFS floppy images
by Kevin O'Connor 19 Aug '09

19 Aug '09

It is now possible to embed an image of a floppy into a CBFS flash file and then boot from that image with SeaBIOS. I've used this to boot FreeDOS directly from flash on my epia-cn. An lzma compressed bootable FreeDOS floppy uses about 95K (for the base kernel and command interpreter). More information is available on the Coreboot SeaBIOS page: http://www.coreboot.org/SeaBIOS#Adding_a_floppy_image Cheers, -Kevin

5 7

AMD RS780 docs released, coreboot support coming
by Carl-Daniel Hailfinger 19 Aug '09

19 Aug '09

The coreboot community, which includes government organizations, corporations, research labs and individuals from around the world, is very excited to expand on our existing and decade-long collaboration with AMD. This collaboration has, over the years, resulted in the inclusion of coreboot into everything from some of the largest AMD-based supercomputers in the world to some of the smallest embedded systems. Together with the recent SB700/SB710/SB750 documentation release, the Developer Guide release for the RS780 family of Integrated Chipset/ Graphics Processors enables the coreboot community to support any board with AMD chipsets out there, from embedded to enthusiast desktop and high-end server boards. This new release once again demonstrates AMD's commitment to open standards and software that provides an improved user experience and Total Cost of Ownership for users in every walk of life. One cornerstone of this openness is the availability of documentation without NDA, enabling everyone to contribute. Coreboot is a BIOS/EFI alternative with optional BIOS/EFI backwards compatibility. Not only does coreboot enable extremely fast booting with well under one second spent inside coreboot, and total four second boot time from poweron to a working desktop, it also has superior reliability and realtime performance. Coreboot developers have embedded various operating systems, among them Linux and Plan 9, directly into onboard ROM chips yielding systems without moving parts and built-in network manageability. Virtualization is made easier by optionally embedding the KVM hypervisor into the ROM as well. Military strength encryption and access protection add-ons exist for environments where security is key. Its extended diagnostics in plain English are second to none. Of course, coreboot supports Windows XP/Vista/7 as well as Linux, *BSD and Plan 9. Coreboot is open source, so every interested developer or user can modify, tweak and extend it to their heart's content. An additional benefit of this documentation release is flashrom support for all AMD chipsets which enables users to reflash their BIOS/firmware/coreboot from within Linux and *BSD without rebooting. Coreboot code for the SB700 and 780 chipset family is already being worked on by Zheng Bao at AMD in his spare time and the coreboot community is happy to work with him on finishing and integrating the code into the official coreboot codebase. We'd like to thank Sharon Troia at AMD for making these documentation releases possible. The developer guides are available at http://developer.amd.com/documentation/guides/Pages/default.aspx#chipset More information about coreboot is available at http://www.coreboot.org/

5 11

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coreboot August 2009