coreboot August 2009

coreboot@coreboot.org

61 participants
356 discussions

Kconfig for Tyan s2892
by Myles Watson 21 Aug '09

21 Aug '09

It compiles, but there are a lot of warnings about undefined CONFIG_ variables. To apply the patch, first : svn cp src/southbridge/nvidia/ck804/Config.lb src/southbridge/nvidia/ck804/Makefile.inc svn cp src/cpu/amd/socket_F/Kconfig src/cpu/amd/socket_940/Kconfig svn cp src/cpu/amd/socket_F/Makefile.inc src/cpu/amd/socket_940/Makefile.inc svn cp src/mainboard/amd/serengeti_cheetah/Kconfig src/mainboard/tyan/s2892/Kconfig svn cp src/mainboard/amd/serengeti_cheetah/Makefile.inc src/mainboard/tyan/s2892/Makefile.inc Here are the CONFIG variables that aren't defined: CONFIG_VGA CONFIG_CONSOLE_VGA_MULTI CONFIG_CONSOLE_VGA_MULTI CONFIG_USE_WATCHDOG_ON_BOOT CONFIG_SERIAL_POST CONFIG_CONSOLE_VGA_ONBOARD_AT_FIRST CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT CONFIG_PCIX_PLUGIN_SUPPORT CONFIG_PCIEXP_PLUGIN_SUPPORT CONFIG_AGP_PLUGIN_SUPPORT CONFIG_CARDBUS_PLUGIN_SUPPORT CONFIG_PCIX_PLUGIN_SUPPORT CONFIG_AGP_PLUGIN_SUPPORT CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT CONFIG_PCIEXP_PLUGIN_SUPPORT CONFIG_CARDBUS_PLUGIN_SUPPORT CONFIG_CONSOLE_VGA_MULTI CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 CONFIG_GFXUMA Signed-off-by: Myles Watson <mylesgw(a)gmail.com> Thanks, Myles

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Re: [coreboot] Trying to add Kconfig support for M57SLI - build error
by Harald Gutmann 21 Aug '09

21 Aug '09

On Friday 21 August 2009 20:14:29 you wrote: > > -----Original Message----- > > > > On Friday 21 August 2009 19:56:25 you wrote: > > > >> hargut@benchvice:~/cb-v2$ make > > > >> GEN build/build.h > > > >> CC build/northbridge/amd/amdk8/misc_control.o > > > >> In file included from src/northbridge/amd/amdk8/amdk8.h:6, > > > >> from src/northbridge/amd/amdk8/misc_control.c:22: > > > >> src/northbridge/amd/amdk8/amdk8_f.h:524:21: error: macro > > > >> "hard_reset" passed 1 arguments, but takes just 0 > > > > > > > > I'm having similar problems (at least it looks similar to me). My > > > > ck804_reset.c file never gets compiled. > > > > > > I applied your patch, and it doesn't look like you uncomment the line > > > in src/southbridge/nvidia/Makefile.inc so that mcp55 gets built. > > > > Which line do you mean? > > subdirs-y += mcp55 > > This one would be here, except you mean another line... > > Yes that line. When it was commented out I got the same error you're > getting, but when it isn't I don't get that error. > > Do you see the mcp55 files being built? Oh yeah, that was a RIGHT hint! But on a different level of the tree. The line in src/southbridge/nvidia/Makefile.inc was right, but the line " subdirs-y += nvidia" in src/southbridge/Makefile.inc was commented out. Therefor the compiler error of the starting post is now fixed. (This took quite long, to find that little "#" sign...) Thanks Myles! > Thanks, > Myles

2 2

clean up intel Kconfig/Makefile.inc usage
by ron minnich 21 Aug '09

21 Aug '09

ron

2 2

[v2] r4561 - in trunk/coreboot-v2/src/cpu/intel: . socket_PGA370 socket_mFCPGA478 speedstep
by svn＠coreboot.org 21 Aug '09

21 Aug '09

Author: rminnich Date: 2009-08-21 20:08:49 +0200 (Fri, 21 Aug 2009) New Revision: 4561 Modified: trunk/coreboot-v2/src/cpu/intel/Makefile.inc trunk/coreboot-v2/src/cpu/intel/socket_PGA370/Makefile.inc trunk/coreboot-v2/src/cpu/intel/socket_mFCPGA478/Makefile.inc trunk/coreboot-v2/src/cpu/intel/speedstep/Makefile.inc Log: Change the intel cpu makefile.inc so that it fits the model better. - intel/Makefile.inc only mentions sockets - those sockets are conditionally included - makefile.inc in socket directories are almost all unconditionally included - Get rid of if where possible, use -$(CONFIG_VARIABLE) instead as per Kconfig standards in linux kernel See the Kconfig.tex documentation for questions. Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> Acked-by: Patrick Georgi <patrick.georgi(a)coresystems.de> Modified: trunk/coreboot-v2/src/cpu/intel/Makefile.inc =================================================================== --- trunk/coreboot-v2/src/cpu/intel/Makefile.inc 2009-08-21 14:59:14 UTC (rev 4560) +++ trunk/coreboot-v2/src/cpu/intel/Makefile.inc 2009-08-21 18:08:49 UTC (rev 4561) @@ -2,9 +2,8 @@ # Therefore: # ONLY include Makefile.inc from socket directories! -subdirs-y += speedstep -subdirs-y += socket_mFCPGA478 -subdirs-y += socket_PGA370 +subdirs-$(CONFIG_CPU_INTEL_SOCKET_MFCPGA478) += socket_mFCPGA478 +subdirs-$(CONFIG_CPU_INTEL_SOCKET_PGA370) += socket_PGA370 #socket_mPGA478 #socket_mPGA479M Modified: trunk/coreboot-v2/src/cpu/intel/socket_PGA370/Makefile.inc =================================================================== --- trunk/coreboot-v2/src/cpu/intel/socket_PGA370/Makefile.inc 2009-08-21 14:59:14 UTC (rev 4560) +++ trunk/coreboot-v2/src/cpu/intel/socket_PGA370/Makefile.inc 2009-08-21 18:08:49 UTC (rev 4561) @@ -18,17 +18,16 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -ifeq ($(CONFIG_CPU_INTEL_SOCKET_PGA370),y) - obj-y += socket_PGA370.o - subdirs-y += ../model_6xx - subdirs-y += ../../x86/tsc - subdirs-y += ../../x86/mtrr - subdirs-y += ../../x86/fpu - subdirs-y += ../../x86/mmx - subdirs-y += ../../x86/sse - subdirs-y += ../../x86/lapic - subdirs-y += ../../x86/cache - subdirs-y += ../../x86/smm - subdirs-y += ../microcode -endif +obj-y += socket_PGA370.o +subdirs-y += ../model_6xx +subdirs-y += ../../x86/tsc +subdirs-y += ../../x86/mtrr +subdirs-y += ../../x86/fpu +subdirs-y += ../../x86/mmx +subdirs-y += ../../x86/sse +subdirs-y += ../../x86/lapic +subdirs-y += ../../x86/cache +subdirs-y += ../../x86/smm +subdirs-y += ../microcode + Modified: trunk/coreboot-v2/src/cpu/intel/socket_mFCPGA478/Makefile.inc =================================================================== --- trunk/coreboot-v2/src/cpu/intel/socket_mFCPGA478/Makefile.inc 2009-08-21 14:59:14 UTC (rev 4560) +++ trunk/coreboot-v2/src/cpu/intel/socket_mFCPGA478/Makefile.inc 2009-08-21 18:08:49 UTC (rev 4561) @@ -1,17 +1,17 @@ -ifeq ($(CONFIG_CPU_INTEL_SOCKET_MFCPGA478),y) - obj-y += socket_mFCPGA478.o - subdirs-y += ../model_69x - subdirs-y += ../model_6dx - subdirs-y += ../model_6ex - subdirs-y += ../model_6fx - subdirs-y += ../../x86/tsc - subdirs-y += ../../x86/mtrr - subdirs-y += ../../x86/fpu - subdirs-y += ../../x86/mmx - subdirs-y += ../../x86/sse - subdirs-y += ../../x86/lapic - subdirs-y += ../../x86/cache - subdirs-y += ../../x86/smm - subdirs-y += ../microcode - subdirs-y += ../hyperthreading -endif +obj-y += socket_mFCPGA478.o +subdirs-y += ../model_69x +subdirs-y += ../model_6dx +subdirs-y += ../model_6ex +subdirs-y += ../model_6fx +subdirs-y += ../../x86/tsc +subdirs-y += ../../x86/mtrr +subdirs-y += ../../x86/fpu +subdirs-y += ../../x86/mmx +subdirs-y += ../../x86/sse +subdirs-y += ../../x86/lapic +subdirs-y += ../../x86/cache +subdirs-y += ../../x86/smm +subdirs-y += ../microcode +subdirs-y += ../hyperthreading +subdirs-y += ../speedstep + Modified: trunk/coreboot-v2/src/cpu/intel/speedstep/Makefile.inc =================================================================== --- trunk/coreboot-v2/src/cpu/intel/speedstep/Makefile.inc 2009-08-21 14:59:14 UTC (rev 4560) +++ trunk/coreboot-v2/src/cpu/intel/speedstep/Makefile.inc 2009-08-21 18:08:49 UTC (rev 4561) @@ -1,5 +1 @@ -ifeq ($(CONFIG_HAVE_ACPI_TABLES), y) -ifeq ($(CONFIG_CPU_INTEL_SOCKET_MFCPGA478), y) - obj-y += acpi.o -endif -endif +obj-$(CONFIG_HAVE_ACPI_TABLES) += acpi.o

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Fwd: Re: Trying to add Kconfig support for M57SLI - build error
by Harald Gutmann 21 Aug '09

21 Aug '09

Replied in the wrong directory. Sorry.

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SeaBIOS payload without a menu
by Myles Watson 21 Aug '09

21 Aug '09

Kevin, Have you implemented a streamlined boot process for SeaBIOS with a payload in CBFS? Jon would like to boot Filo as quickly as possible after SeaBIOS runs his ROMs. What would you suggest? Thanks, Myles

4 4

[v2] r4560 - trunk/coreboot-v2/src/devices
by svn＠coreboot.org 21 Aug '09

21 Aug '09

Author: myles Date: 2009-08-21 16:59:14 +0200 (Fri, 21 Aug 2009) New Revision: 4560 Modified: trunk/coreboot-v2/src/devices/pci_device.c Log: Trivial spelling corrections. Signed-off-by: Myles Watson <mylesgw(a)gmail.com> Acked-by: Myles Watson <mylesgw(a)gmail.com> Modified: trunk/coreboot-v2/src/devices/pci_device.c =================================================================== --- trunk/coreboot-v2/src/devices/pci_device.c 2009-08-20 18:05:31 UTC (rev 4559) +++ trunk/coreboot-v2/src/devices/pci_device.c 2009-08-21 14:59:14 UTC (rev 4560) @@ -747,7 +747,7 @@ #if CONFIG_PCIX_PLUGIN_SUPPORT == 1 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX); if (pos) { - printk_debug("%s subbordinate bus PCI-X\n", dev_path(dev)); + printk_debug("%s subordinate bus PCI-X\n", dev_path(dev)); return &default_pcix_ops_bus; } #endif @@ -761,7 +761,7 @@ flags = pci_read_config16(dev, pos + PCI_CAP_FLAGS); if ((flags >> 13) == 1) { /* Host or Secondary Interface */ - printk_debug("%s subbordinate bus Hypertransport\n", + printk_debug("%s subordinate bus Hypertransport\n", dev_path(dev)); return &default_ht_ops_bus; } @@ -776,11 +776,11 @@ case PCI_EXP_TYPE_ROOT_PORT: case PCI_EXP_TYPE_UPSTREAM: case PCI_EXP_TYPE_DOWNSTREAM: - printk_debug("%s subbordinate bus PCI Express\n", + printk_debug("%s subordinate bus PCI Express\n", dev_path(dev)); return &default_pciexp_ops_bus; case PCI_EXP_TYPE_PCI_BRIDGE: - printk_debug("%s subbordinate PCI\n", dev_path(dev)); + printk_debug("%s subordinate PCI\n", dev_path(dev)); return &default_pci_ops_bus; default: break;

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Problem with the size of the payload
by Björn Zadow 21 Aug '09

21 Aug '09

Hello, I tried to build a rom Image for an Axus TC 320 using filo as payload. Everything seems OK until the message " There is not enough room in this ROM" The size of my filo.elf file is 88400 Byte. Is this too large? What can I do to make it smaller. Or what am i doing wrong? I use coreboot-v2-4559. rm -f ./coreboot.rom cat normal/coreboot.rom fallback/coreboot.rom > ./coreboot.rom.bootblock ./cbfs/cbfstool ./coreboot.rom create 262144 131072 ./coreboot.rom.bootblock ./cbfs/cbfstool ./coreboot.rom add-payload ../filo.elf normal/payload ./cbfs/cbfstool ./coreboot.rom add-stage normal/coreboot_ram normal/coreboot_ram if [ -f normal/coreboot_apc ]; then ./cbfs/cbfstool ./coreboot.rom add-stage normal/coreboot_apc normal/coreboot_apc ; fi ./cbfs/cbfstool ./coreboot.rom add-payload ../filo.elf fallback/payload (cbfstool) E: There is not enough room in this ROM make: *** [coreboot.rom] Error 255 Thanks for help Bjoern ______________________________________________________ GRATIS für alle WEB.DE-Nutzer: Die maxdome Movie-FLAT! Jetzt freischalten unter http://movieflat.web.de

3 2

Fwd: AMD RS690 TMDS
by Daniel Toussaint 21 Aug '09

21 Aug '09

---------- Forwarded message ---------- From: Daniel Toussaint <daniel(a)dmhome.net> Date: Fri, Aug 21, 2009 at 2:33 PM Subject: Re: [coreboot] AMD RS690 TMDS To: Karl-Heinz Nirschl <kh.nirschl(a)googlemail.com> Hello, Meanwhile one of my team members has solved the problem, the info was all in the BIOS porting guide, it was just not very obvious. Below is his patch: Enable Direct TMDS for the RS690, which allows to display on HDMI and DVI monitors. Signed-off-by: Libra Li <libra.li(a)technexion.com> On Tue, Aug 18, 2009 at 2:33 AM, Karl-Heinz Nirschl < kh.nirschl(a)googlemail.com> wrote: > hi, > > i have a m2a-vm hdmi and could provide dumps if needed. just tell me > exactly what you need. > > best regards > > khn > > 2009/8/17 Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net>: > > Hi Daniel, > > > > On 11.08.2009 18:32, Daniel Toussaint wrote: > >> I am using the open source drivers , radeon and radeonhd. When I try it > on a > >> similar board with AMI bios , xrandr can switch on the HDMI port without > any > >> problems - with radeon and radeonhd. I guess I could give Catalyst a try > to > >> see if it makes any difference(maybe it does magic with the vga bios) I > >> think however, that the problem lies in the fact that some config needs > to > >> be done in PCIE-GFX , so that one of the ports gets configured as TMDS. > >> Right now, I am trying to get that to work - so far no results yet .... > >> Another interesting fact is that I am working with this board that does > not > >> have another BIOS except for coreboot .... so I have nothing to compare > >> register values with. > >> > > > > I never tested HDMI on my board and I know that most boards need special > > PCIe setup to get HDMI working. So unless this is implemented already, > > you probably need to code it up yourself. > > The issue should be independent of the video driver you're using. > > > > Maybe someone who has a board with working HDMI under the proprietary > > BIOS can give you the register dumps you need. > > > > Regards, > > Carl-Daniel > > > > -- > > http://www.hailfinger.org/ > > > > > > -- > > coreboot mailing list: coreboot(a)coreboot.org > > http://www.coreboot.org/mailman/listinfo/coreboot > > >

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[PATCH] Add support for 64bits payloads
by Thomas Jourdan 20 Aug '09

20 Aug '09

Hi guys This series of patches adds support for 64 bits payloads. With them, it is possible to use a 64 bit payload. It works with old elf boot process and new CBFS selfboot. With CBFS, when parsing the ELF, the elfclass will be stored in a new field of the cbfs_payload structure. This field is used later to decide or not if we need to switch to 64 bits mode before jumping into the payload. 64 bits mode needs paging and paging needs some memory to store the page tables. It's hardcoded and needs to be improved. It's far from perfect and I don't think it can be included as it in the main coreboot trunk. But it may give some ideas. It is required so : Signed-off-by: Thomas Jourdan <thomas.jourdan(a)gmail.com> But all the assembly code to switch to 64 bits mode is taken from the EDK2 project (https://edk2.tianocore.org). So credits are for them. Regards, Thomas

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coreboot August 2009