coreboot July 2009

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AMD SB700/SB710/SB750 docs have been released!
by Carl-Daniel Hailfinger 10 Jul '09

10 Jul '09

AMD just released the following docs we need for SB700/SB710/SB750 coreboot support: * AMD SB700/710/750 Register Reference Guide * AMD SB700/710/750 BIOS Developer’s Guide * AMD SB700/710/750 Register Programming Requirements * AMD SB710 Databook Links to all data sheets are at http://www.coreboot.org/Datasheets#AMD_SB700.2FSB710.2FSB750 This is a great step towards supporting current RS780/SB700 family systems. Immediate benefits of this doc release are: - We can implement SB700/SB710/SB750 support without NDA. - We can study the embedded controller environment and the SuperI/O functionality in some SB7x0 southbridges. Future benefits are: - We can support 690/SB700 boards once the SB700 code is done. - We can test SB700 code in 690/SB700 boards and make sure it works perfectly before we start working on RS780 code. - We have 50% of the docs we need for almost all boards with AMD chipset on sale today. What can we do next? - Implement SB700 code. - RS690/SB700 boards do not exist. However, it seems that RS740 is RS690 with a modified graphics core, so RS740/SB700 boards are the best targets we can pick. List of possible targets with RS740/SB700: - ECS Elitegroup A740GM-M (89-206-V15102) http://www.ecs.com.tw/ECSWebSite/Products/ProductsDetail.aspx?detailid=864&… - Gigabyte GA-MA74GM-S2 (rev 1.x and 2.0) http://www.gigabyte.com.tw/Products/Motherboard/Products_Overview.aspx?Prod… http://www.gigabyte.com.tw/Products/Motherboard/Products_Overview.aspx?Prod… - Gigabyte GA-MA74GM-S2 (rev 1.x and 2.0) http://www.gigabyte.com.tw/Products/Motherboard/Products_Overview.aspx?Prod… http://www.gigabyte.com.tw/Products/Motherboard/Products_Overview.aspx?Prod… - ASUS M2A74-AM http://www.asus.com/product.aspx?P_ID=YPZrr3KRcW3MBX5G - MSI K9A2GM-F V3 (MS-7302-020, there seem to be many variants of this board, some of them may have a 740 variant which is not compatible with 690) http://us.msi.com/product/p_spec.asp?model=K9A2GM-F_V3&class=mb Thanks to AMD for releasing these docs! Regards, Carl-Daniel

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msrtool CS5536 interrupt and DIVIL LBAR MSRs
by Peter Stuge 10 Jul '09

10 Jul '09

Can someone please review these register definitions? Thank you! //Peter

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PCI: Left over static devices about the pci 1.1 device
by wan2 michal 09 Jul '09

09 Jul '09

Hi in the file src/mainboard/amd/norwich/Config.lb, I use the pci 1.1 device which is Graphics, because I want to request one irq in framebuffer driver (drivers/video/geode/lxfb_core.c). but when booting, it outputs "PCI: Left over static devices". I don't know why it can not find the graphic device. Any help would be greatly appreciated! michaelwan

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[Patch] superiotool: add vt1211 support.
by Luc Verhaegen 09 Jul '09

09 Jul '09

I spent a bit of time on adding support for the vt1211 superio found on the epia-m board. It does not add io dumping, yet. Compared to the rest of the superiotool, this support is highly different; i see quite a lot of possibility for superiotool to be improved (more on that later in this mail). This here is the output of superiotool on my vt1211: VT1211 LDN 0: "Floppy Disk Controller" 0x30: 0x01 (0x00) "Activate" 0x60: 0xFC (0xFC) "I/O Base Address" 0x70: 0x06 (0x06) "IRQ Select" 0x74: 0x02 (0x01) "DRQ Select" 0xF0: 0x00 (0x00) "Configuration" 0xF1: 0x00 (0x00) "Drive Select" Notice how it lists one register per line, with: index: value (default). The string is just there because it was easy to add while adding the other information. Why do i prefer 1 register per line as opposed to whole blobs for other chipsets: * we're human and this is easier to read. * diff is also surprisingly human. I would like to alter the printing of other superios to the same, one per line, output. I have been told on irc that this might break some peoples scripts (if there are any), but for humans, this is the sanest thing to do. Further changes that might be good: * decouple probing from dumping. * add single value dumping and then also writing (requires tracking of RO/WO). * there are only a few probe routines out there, create a general table so that we can tie io_port and the return value of the probe routine to an id and thus reduce probing to once per probe routine. * etc, etc... Tons of room for improvement and also discussion :) But first, let's scrutinize this way of outputting and if acceptable, also alter the output of other superio dumps. I will be adding IT8103F support today, which will also further my view of what needs to be done here. Luc Verhaegen.

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Re: [coreboot] error in Building coreboot: Corrupt rom -- found no header at 2031584
by Myles Watson 09 Jul '09

09 Jul '09

> I made two changes in the Config.lb file first one is ROM_SIZE i made as > 2048*1024 and second i specified the location of my payload. That's all you needed to do, as long as your payload fits in 2M. > yea I also think i misconfigured the Config.lb file. I modified the > ROM_SIZE but forgot to change the ROM_IMAGE_SIZE in the Config.lb file > according to it. ROM_IMAGE_SIZE doesn't need to be changed. > the size of the linux.elf image was 10 MB. So this may be problem also. Yes. This is the problem. > So I dont know how to decrease the size of linux.elf, Any help would be > greatly appreciated. Check out buildrom, and see how it builds Linux kernels that fit in the ROM. Thanks, Myles

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PCI: Left over static devices about the pci 1.1 device
by wan michael 09 Jul '09

09 Jul '09

1 0

Re: [coreboot] error in Building coreboot: Corrupt rom -- found no header at 2031584
by Anurag_Vashisth 09 Jul '09

09 Jul '09

Hi All, I made two changes in the Config.lb file first one is ROM_SIZE i made as 2048*1024 and second i specified the location of my payload. yea I also think i misconfigured the Config.lb file. I modified the ROM_SIZE but forgot to change the ROM_IMAGE_SIZE in the Config.lb file according to it. The modified version of this file i've attached. and then again tried to rebuild the coreboot but this time after executing the make command i got the error message as: /usr/bin/ld: _start too low. Please decrease ROM_IMAGE_SIZE collect2: ld returned 1 exit status make[1]: *** [coreboot] Error 1 So i think the problm is with my paylod linux.elf. Its description is as follows Actually i am going to build qemu without using FILO, for that i took the vmlinuz and initrd image from my system(development machine) whose size is 2.1 MB and 7.8 MB respectively when i used the mkelfImage utilty to generate the elf image using the command: mkelfImage --append="console=ttyS0" --initrd=/boot/initrd.img-2.6.27-7-generic /boot/vmlinuz-2.6.27-7-generic linux.elf the size of the linux.elf image was 10 MB. So this may be problem also. So I dont know how to decrease the size of linux.elf, Any help would be greatly appreciated. Thanks Anurag Vashisth 9739278384 ________________________________________ From: coreboot-bounces(a)coreboot.org [coreboot-bounces(a)coreboot.org] On Behalf Of coreboot-request(a)coreboot.org [coreboot-request(a)coreboot.org] Sent: Thursday, July 09, 2009 2:18 AM To: coreboot(a)coreboot.org Subject: coreboot Digest, Vol 53, Issue 44 Send coreboot mailing list submissions to coreboot(a)coreboot.org To subscribe or unsubscribe via the World Wide Web, visit http://www.coreboot.org/mailman/listinfo/coreboot or, via email, send a message with subject or body 'help' to coreboot-request(a)coreboot.org You can reach the person managing the list at coreboot-owner(a)coreboot.org When replying, please edit your Subject line so it is more specific than "Re: Contents of coreboot digest..." Today's Topics: 1. Re: excessive whitespace; was: fam10 resource can not allocated. (Peter Stuge) 2. Re: Holding the s2895 in reset powers off the machine (Myles Watson) 3. Re: error in Building coreboot: Corrupt rom -- found no header at 2031584 (Myles Watson) 4. Re: error in Building coreboot: Corrupt rom -- found no header at 2031584 (ron minnich) 5. Re: error in Building coreboot: Corrupt rom -- found no header at 2031584 (ron minnich) 6. Re: error in Building coreboot: Corrupt rom -- found no header at 2031584 (Myles Watson) 7. GPLv2 vs GPLv3 (Joseph Smith) 8. Re: GPLv2 vs GPLv3 (ron minnich) 9. Re: GPLv2 vs GPLv3 (Joseph Smith) 10. Re: GPLv2 vs GPLv3 (Robinson Tryon) ---------------------------------------------------------------------- Message: 1 Date: Wed, 8 Jul 2009 14:03:27 +0200 From: Peter Stuge <peter(a)stuge.se> To: coreboot(a)coreboot.org Subject: Re: [coreboot] excessive whitespace; was: fam10 resource can not allocated. Message-ID: <20090708120327.29828.qmail(a)stuge.se> Content-Type: text/plain; charset=us-ascii Russell Whitaker wrote: > If the program writing the display does not word-wrap at the edge > of the screen then some data just disappears. Doesn't that depend on the console driver? //Peter ------------------------------ Message: 2 Date: Wed, 8 Jul 2009 07:52:09 -0600 From: Myles Watson <mylesgw(a)gmail.com> To: Rudolf Marek <r.marek(a)assembler.cz> Cc: coreboot(a)coreboot.org Subject: Re: [coreboot] Holding the s2895 in reset powers off the machine Message-ID: <2831fecf0907080652w7ee046a0ub093c9bb30f239ab(a)mail.gmail.com> Content-Type: text/plain; charset="iso-8859-1" On Wed, Jul 8, 2009 at 1:13 AM, Rudolf Marek <r.marek(a)assembler.cz> wrote: > Hi, > > Please tell what superios are there. The pwrgood is sometimes involved. It > looks like a SIO thingie. smsc lpc47b397. On Tue, Jul 7, 2009 at 6:17 PM, Carl-Daniel Hailfinger < c-d.hailfinger.devel.2006(a)gmx.net> wrote: > I have no idea if the reset button directly triggers a reset line or > something similar on the processor, but it would be interesting to know: > 1. Does the power off also happen if you hold reset after the machine > has already been booted? (Do n seconds of reset always trigger a poweroff?) > No. After a few seconds of booting you can hold it in reset as long as you want. Since there is no output (no post codes either), I haven't been able to narrow it down. What I'm hoping is that it is some setting that can be saved by the device for the next boot. Otherwise I have to figure out a workaround, since I can't access the SuperIO before HT is initialized, and I need to hold the board in reset before HT is initialized. > 2. Which part of the board reacts to the held reset line and triggers > the poweroff? > I don't know. > 3. Is reset maybe somehow coupled to PWRGOOD and holding down reset is > perceived as electrical problem of the power supply? > Since #1 is no, I don't think so. Thanks, Myles

1 0

[PATCH] flashrom: Call programmer_shutdown() where needed
by Uwe Hermann 09 Jul '09

09 Jul '09

See patch. Uwe. -- http://www.hermann-uwe.de | http://www.holsham-traders.de http://www.crazy-hacks.org | http://www.unmaintained-free-software.org

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Re: [coreboot] [v2] r4394 - in trunk/coreboot-v2/src: cpu/amd/sc520cpu/emulation/qemu-x86 cpu/ppc/ppc4xx devices include/devicenorthbridge/amd/amdfam10 northbridge/amd/amdk8northbridge/amd/gx1 northbridge/amd/gx2 northbridge/amd/lxnorthbridge/ibm/cpc710 n
by Bao, Zheng 09 Jul '09

09 Jul '09

This patch makes my AMD fam10 board not work (K8 works). The resource can not be allocated correctly. Zheng -----Original Message----- From: coreboot-bounces(a)coreboot.org [mailto:coreboot-bounces@coreboot.org] On Behalf Of svn(a)coreboot.org Sent: Friday, July 03, 2009 2:56 AM To: coreboot(a)coreboot.org Subject: [coreboot] [v2] r4394 - in trunk/coreboot-v2/src: cpu/amd/sc520cpu/emulation/qemu-x86 cpu/ppc/ppc4xx devices include/devicenorthbridge/amd/amdfam10 northbridge/amd/amdk8northbridge/amd/gx1 northbridge/amd/gx2 northbridge/amd/lxnorthbridge/ibm/cpc710 north Author: myles Date: 2009-07-02 20:56:24 +0200 (Thu, 02 Jul 2009) New Revision: 4394 Modified: trunk/coreboot-v2/src/cpu/amd/sc520/sc520.c trunk/coreboot-v2/src/cpu/emulation/qemu-x86/northbridge.c trunk/coreboot-v2/src/cpu/ppc/ppc4xx/pci_domain.c trunk/coreboot-v2/src/devices/cardbus_device.c trunk/coreboot-v2/src/devices/device.c trunk/coreboot-v2/src/devices/device_util.c trunk/coreboot-v2/src/devices/pci_device.c trunk/coreboot-v2/src/devices/root_device.c trunk/coreboot-v2/src/include/device/device.h trunk/coreboot-v2/src/include/device/resource.h trunk/coreboot-v2/src/northbridge/amd/amdfam10/northbridge.c trunk/coreboot-v2/src/northbridge/amd/amdk8/misc_control.c trunk/coreboot-v2/src/northbridge/amd/amdk8/northbridge.c trunk/coreboot-v2/src/northbridge/amd/gx1/northbridge.c trunk/coreboot-v2/src/northbridge/amd/gx2/northbridge.c trunk/coreboot-v2/src/northbridge/amd/lx/northbridge.c trunk/coreboot-v2/src/northbridge/ibm/cpc710/cpc710_northbridge.c trunk/coreboot-v2/src/northbridge/ibm/cpc925/cpc925_northbridge.c trunk/coreboot-v2/src/northbridge/intel/e7501/northbridge.c trunk/coreboot-v2/src/northbridge/intel/e7520/northbridge.c trunk/coreboot-v2/src/northbridge/intel/e7525/northbridge.c trunk/coreboot-v2/src/northbridge/intel/i3100/northbridge.c trunk/coreboot-v2/src/northbridge/intel/i440bx/northbridge.c trunk/coreboot-v2/src/northbridge/intel/i82810/northbridge.c trunk/coreboot-v2/src/northbridge/intel/i82830/northbridge.c trunk/coreboot-v2/src/northbridge/intel/i855gme/northbridge.c trunk/coreboot-v2/src/northbridge/intel/i855pm/northbridge.c trunk/coreboot-v2/src/northbridge/intel/i945/northbridge.c trunk/coreboot-v2/src/northbridge/motorola/mpc107/mpc107_northbridge.c trunk/coreboot-v2/src/northbridge/via/cn400/northbridge.c trunk/coreboot-v2/src/northbridge/via/cn700/northbridge.c trunk/coreboot-v2/src/northbridge/via/cx700/cx700_lpc.c trunk/coreboot-v2/src/northbridge/via/cx700/northbridge.c trunk/coreboot-v2/src/northbridge/via/vt8601/northbridge.c trunk/coreboot-v2/src/northbridge/via/vt8623/northbridge.c trunk/coreboot-v2/src/northbridge/via/vx800/northbridge.c trunk/coreboot-v2/src/southbridge/amd/amd8111/amd8111_lpc.c trunk/coreboot-v2/src/southbridge/amd/amd8131/amd8131_bridge.c trunk/coreboot-v2/src/southbridge/amd/amd8132/amd8132_bridge.c trunk/coreboot-v2/src/southbridge/amd/cs5530/cs5530_isa.c trunk/coreboot-v2/src/southbridge/amd/cs5535/cs5535.c trunk/coreboot-v2/src/southbridge/amd/cs5536/cs5536.c trunk/coreboot-v2/src/southbridge/amd/sb600/sb600_lpc.c trunk/coreboot-v2/src/southbridge/broadcom/bcm5785/bcm5785_lpc.c trunk/coreboot-v2/src/southbridge/broadcom/bcm5785/bcm5785_sb_pci_main.c trunk/coreboot-v2/src/southbridge/intel/esb6300/esb6300_lpc.c trunk/coreboot-v2/src/southbridge/intel/i3100/i3100_lpc.c trunk/coreboot-v2/src/southbridge/intel/i82371eb/i82371eb_isa.c trunk/coreboot-v2/src/southbridge/intel/i82801ca/i82801ca_lpc.c trunk/coreboot-v2/src/southbridge/intel/i82801dbm/i82801dbm_lpc.c trunk/coreboot-v2/src/southbridge/intel/i82801er/i82801er_lpc.c trunk/coreboot-v2/src/southbridge/intel/i82801gx/i82801gx_lpc.c trunk/coreboot-v2/src/southbridge/intel/i82801xx/i82801xx_lpc.c trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_lpc.c trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_pci.c trunk/coreboot-v2/src/southbridge/nvidia/mcp55/mcp55_lpc.c trunk/coreboot-v2/src/southbridge/nvidia/mcp55/mcp55_pci.c trunk/coreboot-v2/src/southbridge/ricoh/rl5c476/rl5c476.c trunk/coreboot-v2/src/southbridge/sis/sis966/sis966_lpc.c trunk/coreboot-v2/src/southbridge/via/vt8231/vt8231_lpc.c trunk/coreboot-v2/src/southbridge/via/vt8235/vt8235_lpc.c trunk/coreboot-v2/src/southbridge/winbond/w83c553/w83c553f.c Log: Move the v3 resource allocator to v2. Major changes: 1. Separate resource allocation into: A. Read Resources B. Avoid fixed resources (constrain limits) C. Allocate resources D. Set resources Usage notes: Resources which have IORESOURCE_FIXED set in the flags constrain the placement of other resources. All fixed resources will end up outside (above or below) the allocated resources. Domains usually start with base = 0 and limit = 2^address_bits - 1. I've added an IOAPIC to all platforms so that the old limit of 0xfec00000 is still there for resources. Some platforms may want to change that, but I didn't want to break anyone's board. Resources are allocated in a single block for memory and another for I/O. Currently the resource allocator doesn't support holes. Signed-off-by: Myles Watson <mylesgw(a)gmail.com> Acked-by: Ronald G. Minnich <rminnich(a)gmail.com> Acked-by: Patrick Georgi <patrick.georgi(a)coresystems.de> Modified: trunk/coreboot-v2/src/cpu/amd/sc520/sc520.c =================================================================== --- trunk/coreboot-v2/src/cpu/amd/sc520/sc520.c 2009-07-02 18:27:02 UTC (rev 4393) +++ trunk/coreboot-v2/src/cpu/amd/sc520/sc520.c 2009-07-02 18:56:24 UTC (rev 4394) @@ -62,9 +62,27 @@ } +static void sc520_read_resources(device_t dev) +{ + struct resource* res; + pci_dev_read_resources(dev); + + res = new_resource(dev, 1); + res->base = 0x0UL; + res->size = 0x400UL; + res->limit = 0xffffUL; + res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; + + res = new_resource(dev, 3); /* IOAPIC */ + res->base = 0xfec00000; + res->size = 0x00001000; + res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; +} + + static struct device_operations cpu_operations = { - .read_resources = pci_dev_read_resources, + .read_resources = sc520_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = sc520_enable_resources, .init = cpu_init, @@ -78,25 +96,6 @@ .device = 0x3000 }; - - -#define BRIDGE_IO_MASK (IORESOURCE_IO | IORESOURCE_MEM) - -static void pci_domain_read_resources(device_t dev) -{ - struct resource *resource; - printk_spew("%s\n", __func__); - /* Initialize the system wide io space constraints */ - resource = new_resource(dev, IOINDEX_SUBTRACTIVE(0,0)); - resource->limit = 0xffffUL; - resource->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED; - - /* Initialize the system wide memory resources constraints */ - resource = new_resource(dev, IOINDEX_SUBTRACTIVE(1,0)); - resource->limit = 0xffffffffULL; - resource->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED; -} - static void ram_resource(device_t dev, unsigned long index, unsigned long basek, unsigned long sizek) { @@ -184,14 +183,6 @@ assign_resources(&dev->link[0]); } -static unsigned int pci_domain_scan_bus(device_t dev, unsigned int max) -{ - printk_spew("%s\n", __func__); - max = pci_scan_bus(&dev->link[0], PCI_DEVFN(0, 0), 0xff, max); - return max; -} - - #if 0 void sc520_enable_resources(device_t dev) { @@ -219,7 +210,7 @@ * If enable_resources is set to the generic enable_resources * function the whole thing will hang in an endless loop on * the ts5300. If this is really needed on another platform, - * something is conceptionally wrong. + * something is conceptually wrong. */ .enable_resources = 0, //enable_resources, .init = 0, Modified: trunk/coreboot-v2/src/cpu/emulation/qemu-x86/northbridge.c =================================================================== --- trunk/coreboot-v2/src/cpu/emulation/qemu-x86/northbridge.c 2009-07-02 18:27:02 UTC (rev 4393) +++ trunk/coreboot-v2/src/cpu/emulation/qemu-x86/northbridge.c 2009-07-02 18:56:24 UTC (rev 4394) @@ -9,23 +9,6 @@ #include "chip.h" #include "northbridge.h" -#define BRIDGE_IO_MASK (IORESOURCE_IO | IORESOURCE_MEM) - -static void pci_domain_read_resources(device_t dev) -{ - struct resource *resource; - - /* Initialize the system wide io space constraints */ - resource = new_resource(dev, IOINDEX_SUBTRACTIVE(0,0)); - resource->limit = 0xffffUL; - resource->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED; - - /* Initialize the system wide memory resources constraints */ - resource = new_resource(dev, IOINDEX_SUBTRACTIVE(1,0)); - resource->limit = 0xffffffffULL; - resource->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED; -} - static void ram_resource(device_t dev, unsigned long index, unsigned long basek, unsigned long sizek) { @@ -70,7 +53,7 @@ extern uint64_t high_tables_base, high_tables_size; #endif -static void pci_domain_set_resources(device_t dev) +static void cpu_pci_domain_set_resources(device_t dev) { static const uint8_t ramregs[] = { 0x5a, 0x5b, 0x5c, 0x5d, 0x5e, 0x5f, 0x56, 0x57 @@ -127,15 +110,34 @@ assign_resources(&dev->link[0]); } -static unsigned int pci_domain_scan_bus(device_t dev, unsigned int max) +static void cpu_pci_domain_read_resources(struct device *dev) { - max = pci_scan_bus(&dev->link[0], PCI_DEVFN(0, 0), 0xff, max); - return max; + struct resource *res; + + pci_domain_read_resources(dev); + + /* Reserve space for the IOAPIC. This should be in the Southbridge, + * but I couldn't tell which device to put it in. */ + res = new_resource(dev, 2); + res->base = 0xfec00000UL; + res->size = 0x100000UL; + res->limit = 0xffffffffUL; + res->flags = IORESOURCE_MEM | IORESOURCE_FIXED | IORESOURCE_STORED | + IORESOURCE_ASSIGNED; + + /* Reserve space for the LAPIC. There's one in every processor, but + * the space only needs to be reserved once, so we do it here. */ + res = new_resource(dev, 3); + res->base = 0xfee00000UL; + res->size = 0x10000UL; + res->limit = 0xffffffffUL; + res->flags = IORESOURCE_MEM | IORESOURCE_FIXED | IORESOURCE_STORED | + IORESOURCE_ASSIGNED; } static struct device_operations pci_domain_ops = { - .read_resources = pci_domain_read_resources, - .set_resources = pci_domain_set_resources, + .read_resources = cpu_pci_domain_read_resources, + .set_resources = cpu_pci_domain_set_resources, .enable_resources = enable_childrens_resources, .init = 0, .scan_bus = pci_domain_scan_bus, Modified: trunk/coreboot-v2/src/cpu/ppc/ppc4xx/pci_domain.c =================================================================== --- trunk/coreboot-v2/src/cpu/ppc/ppc4xx/pci_domain.c 2009-07-02 18:27:02 UTC (rev 4393) +++ trunk/coreboot-v2/src/cpu/ppc/ppc4xx/pci_domain.c 2009-07-02 18:56:24 UTC (rev 4394) @@ -7,27 +7,6 @@ #include <device/pci_ids.h> #include <console/console.h> -static unsigned int pci_domain_scan_bus(device_t dev, unsigned int max) -{ - max = pci_scan_bus(&dev->link[0], PCI_DEVFN(0, 0), 0xff, max); - return max; -} - -static void pci_domain_read_resources(device_t dev) -{ - struct resource *resource; - - /* Initialize the system wide io space constraints */ - resource = new_resource(dev, IOINDEX_SUBTRACTIVE(0,0)); - resource->limit = 0xffffUL; - resource->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED; - - /* Initialize the system wide memory resources constraints */ - resource = new_resource(dev, IOINDEX_SUBTRACTIVE(1,0)); - resource->limit = 0xffffffffULL; - resource->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED; -} - static void ram_resource(device_t dev, unsigned long index, unsigned long basek, unsigned long sizek) { Modified: trunk/coreboot-v2/src/devices/cardbus_device.c =================================================================== --- trunk/coreboot-v2/src/devices/cardbus_device.c 2009-07-02 18:27:02 UTC (rev 4393) +++ trunk/coreboot-v2/src/devices/cardbus_device.c 2009-07-02 18:56:24 UTC (rev 4394) @@ -77,8 +77,6 @@ resource = find_resource(dev, index); if (resource) { min_size = resource->size; - compute_allocate_resource(&dev->link[0], resource, - resource->flags, resource->flags); /* Allways allocate at least the miniumum size to a * cardbus bridge in case a new card is plugged in. */ Modified: trunk/coreboot-v2/src/devices/device.c =================================================================== --- trunk/coreboot-v2/src/devices/device.c 2009-07-02 18:27:02 UTC (rev 4393) +++ trunk/coreboot-v2/src/devices/device.c 2009-07-02 18:56:24 UTC (rev 4394) @@ -12,6 +12,7 @@ * Copyright (C) 2005-2006 Tyan * (Written by Yinghai Lu <yhlu(a)tyan.com> for Tyan) * Copyright (C) 2005-2006 Stefan Reinauer <stepan(a)openbios.org> + * Copyright (C) 2009 Myles Watson <mylesgw(a)gmail.com> */ /* @@ -43,12 +44,6 @@ /** Pointer to the last device */ extern struct device **last_dev_p; -/** The upper limit of MEM resource of the devices. - * Reserve 20M for the system */ -#define DEVICE_MEM_HIGH 0xFEBFFFFFUL -/** The lower limit of IO resource of the devices. - * Reserve 4k for ISA/Legacy devices */ -#define DEVICE_IO_START 0x1000 /** * @brief Allocate a new device structure. @@ -71,25 +66,25 @@ spin_lock(&dev_lock); - /* Find the last child of our parent */ - for(child = parent->children; child && child->sibling; ) { + /* Find the last child of our parent. */ + for (child = parent->children; child && child->sibling; /* */ ) { child = child->sibling; } dev = malloc(sizeof(*dev)); - if (dev == 0) { + if (dev == 0) die("DEV: out of memory.\n"); - } + memset(dev, 0, sizeof(*dev)); memcpy(&dev->path, path, sizeof(*path)); - /* Initialize the back pointers in the link fields */ - for(link = 0; link < MAX_LINKS; link++) { - dev->link[link].dev = dev; + /* Initialize the back pointers in the link fields. */ + for (link = 0; link < MAX_LINKS; link++) { + dev->link[link].dev = dev; dev->link[link].link = link; } - /* By default devices are enabled */ + /* By default devices are enabled. */ dev->enabled = 1; /* Add the new device to the list of children of the bus. */ @@ -132,64 +127,46 @@ { struct device *curdev; - printk_spew("%s read_resources bus %d link: %d\n", - dev_path(bus->dev), bus->secondary, bus->link); + printk_spew("%s %s bus %x link: %d\n", dev_path(bus->dev), __func__, + bus->secondary, bus->link); - /* Walk through all of the devices and find which resources they need. */ - for(curdev = bus->children; curdev; curdev = curdev->sibling) { - unsigned links; + /* Walk through all devices and find which resources they need. */ + for (curdev = bus->children; curdev; curdev = curdev->sibling) { int i; - if (curdev->have_resources) { - continue; - } if (!curdev->enabled) { continue; } if (!curdev->ops || !curdev->ops->read_resources) { printk_err("%s missing read_resources\n", - dev_path(curdev)); + dev_path(curdev)); continue; } curdev->ops->read_resources(curdev); - curdev->have_resources = 1; - /* Read in subtractive resources behind the current device */ - links = 0; - for(i = 0; i < curdev->resources; i++) { - struct resource *resource; - unsigned link; - resource = &curdev->resource[i]; - if (!(resource->flags & IORESOURCE_SUBTRACTIVE)) - continue; - link = IOINDEX_SUBTRACTIVE_LINK(resource->index); - if (link > MAX_LINKS) { - printk_err("%s subtractive index on link: %d\n", - dev_path(curdev), link); - continue; - } - if (!(links & (1 << link))) { - links |= (1 << link); - read_resources(&curdev->link[link]); - } - } + + /* Read in the resources behind the current device's links. */ + for (i = 0; i < curdev->links; i++) + read_resources(&curdev->link[i]); } printk_spew("%s read_resources bus %d link: %d done\n", - dev_path(bus->dev), bus->secondary, bus->link); + dev_path(bus->dev), bus->secondary, bus->link); } struct pick_largest_state { struct resource *last; - struct device *result_dev; + struct device *result_dev; struct resource *result; int seen_last; }; -static void pick_largest_resource(void *gp, - struct device *dev, struct resource *resource) +static void pick_largest_resource(void *gp, struct device *dev, + struct resource *resource) { struct pick_largest_state *state = gp; struct resource *last; + last = state->last; - /* Be certain to pick the successor to last */ + + /* Be certain to pick the successor to last. */ if (resource == last) { state->seen_last = 1; return; @@ -206,21 +183,22 @@ if (!state->result || (state->result->align < resource->align) || ((state->result->align == resource->align) && - (state->result->size < resource->size))) - { + (state->result->size < resource->size))) { state->result_dev = dev; state->result = resource; } } -static struct device *largest_resource(struct bus *bus, struct resource **result_res, - unsigned long type_mask, unsigned long type) +static struct device *largest_resource(struct bus *bus, + struct resource **result_res, + unsigned long type_mask, + unsigned long type) { struct pick_largest_state state; state.last = *result_res; - state.result_dev = 0; - state.result = 0; + state.result_dev = NULL; + state.result = NULL; state.seen_last = 0; search_bus_resources(bus, type_mask, type, pick_largest_resource, @@ -233,144 +211,136 @@ /* Compute allocate resources is the guts of the resource allocator. * * The problem. - * - Allocate resources locations for every device. + * - Allocate resource locations for every device. * - Don't overlap, and follow the rules of bridges. * - Don't overlap with resources in fixed locations. * - Be efficient so we don't have ugly strategies. * * The strategy. * - Devices that have fixed addresses are the minority so don't - * worry about them too much. Instead only use part of the address - * space for devices with programmable addresses. This easily handles + * worry about them too much. Instead only use part of the address + * space for devices with programmable addresses. This easily handles * everything except bridges. * - * - PCI devices are required to have thier sizes and their alignments - * equal. In this case an optimal solution to the packing problem - * exists. Allocate all devices from highest alignment to least - * alignment or vice versa. Use this. + * - PCI devices are required to have their sizes and their alignments + * equal. In this case an optimal solution to the packing problem + * exists. Allocate all devices from highest alignment to least + * alignment or vice versa. Use this. * - * - So we can handle more than PCI run two allocation passes on - * bridges. The first to see how large the resources are behind - * the bridge, and what their alignment requirements are. The - * second to assign a safe address to the devices behind the - * bridge. This allows me to treat a bridge as just a device with - * a couple of resources, and not need to special case it in the - * allocator. Also this allows handling of other types of bridges. + * - So we can handle more than PCI run two allocation passes on bridges. The + * first to see how large the resources are behind the bridge, and what + * their alignment requirements are. The second to assign a safe address to + * the devices behind the bridge. This allows us to treat a bridge as just + * a device with a couple of resources, and not need to special case it in + * the allocator. Also this allows handling of other types of bridges. * */ - -void compute_allocate_resource( - struct bus *bus, - struct resource *bridge, - unsigned long type_mask, - unsigned long type) +void compute_resources(struct bus *bus, struct resource *bridge, + unsigned long type_mask, unsigned long type) { struct device *dev; struct resource *resource; resource_t base; - unsigned long align, min_align; - min_align = 0; - base = bridge->base; + base = round(bridge->base, bridge->align); - printk_spew("%s compute_allocate_resource %s: base: %08Lx size: %08Lx align: %d gran: %d\n", - dev_path(bus->dev), - (bridge->flags & IORESOURCE_IO)? "io": - (bridge->flags & IORESOURCE_PREFETCH)? "prefmem" : "mem", - base, bridge->size, bridge->align, bridge->gran); + printk_spew( "%s %s_%s: base: %llx size: %llx align: %d gran: %d limit: %llx\n", + dev_path(bus->dev), __func__, + (type & IORESOURCE_IO) ? "io" : (type & IORESOURCE_PREFETCH) ? + "prefmem" : "mem", + base, bridge->size, bridge->align, bridge->gran, bridge->limit); - /* We want different minimum alignments for different kinds of - * resources. These minimums are not device type specific - * but resource type specific. - */ - if (bridge->flags & IORESOURCE_IO) { - min_align = log2(DEVICE_IO_ALIGN); - } - if (bridge->flags & IORESOURCE_MEM) { - min_align = log2(DEVICE_MEM_ALIGN); - } + /* For each child which is a bridge, compute_resource_needs. */ + for (dev = bus->children; dev; dev = dev->sibling) { + unsigned i; + struct resource *child_bridge; - /* Make certain I have read in all of the resources */ - read_resources(bus); + if (!dev->links) + continue; - /* Remember I haven't found anything yet. */ - resource = 0; + /* Find the resources with matching type flags. */ + for (i = 0; i < dev->resources; i++) { + unsigned link; + child_bridge = &dev->resource[i]; - /* Walk through all the devices on the current bus and - * compute the addresses. - */ - while((dev = largest_resource(bus, &resource, type_mask, type))) { - resource_t size; - /* Do NOT I repeat do not ignore resources which have zero size. - * If they need to be ignored dev->read_resources should not even - * return them. Some resources must be set even when they have - * no size. PCI bridge resources are a good example of this. - */ - /* Make certain we are dealing with a good minimum size */ - size = resource->size; - align = resource->align; - if (align < min_align) { - align = min_align; - } + if (!(child_bridge->flags & IORESOURCE_BRIDGE) || + (child_bridge->flags & type_mask) != type) + continue; - /* Propagate the resource alignment to the bridge register */ - if (align > bridge->align) { - bridge->align = align; + /* Split prefetchable memory if combined. Many domains + * use the same address space for prefetchable memory + * and non-prefetchable memory. Bridges below them + * need it separated. Add the PREFETCH flag to the + * type_mask and type. + */ + link = IOINDEX_LINK(child_bridge->index); + compute_resources(&dev->link[link], child_bridge, + type_mask | IORESOURCE_PREFETCH, + type | (child_bridge->flags & + IORESOURCE_PREFETCH)); } + } - if (resource->flags & IORESOURCE_FIXED) { + /* Remember we haven't found anything yet. */ + resource = NULL; + + /* Walk through all the resources on the current bus and compute the + * amount of address space taken by them. Take granularity and + * alignment into account. + */ + while ((dev = largest_resource(bus, &resource, type_mask, type))) { + + /* Size 0 resources can be skipped. */ + if (!resource->size) { continue; } - /* Propogate the resource limit to the bridge register */ + /* Propagate the resource alignment to the bridge resource. */ + if (resource->align > bridge->align) { + bridge->align = resource->align; + } + + /* Propagate the resource limit to the bridge register. */ if (bridge->limit > resource->limit) { bridge->limit = resource->limit; } -#warning This heuristic should be replaced by real devices with fixed resources. - /* Artificially deny limits between DEVICE_MEM_HIGH and 0xffffffff */ - if ((bridge->limit > DEVICE_MEM_HIGH) && (bridge->limit <= 0xffffffff)) { - bridge->limit = DEVICE_MEM_HIGH; + + /* Warn if it looks like APICs aren't declared. */ + if ((resource->limit == 0xffffffff) && + (resource->flags & IORESOURCE_ASSIGNED)) { + printk_err("Resource limit looks wrong! (no APIC?)\n"); + printk_err("%s %02lx limit %08Lx\n", dev_path(dev), + resource->index, resource->limit); } if (resource->flags & IORESOURCE_IO) { - /* Don't allow potential aliases over the - * legacy pci expansion card addresses. - * The legacy pci decodes only 10 bits, - * uses 100h - 3ffh. Therefor, only 0 - ff - * can be used out of each 400h block of io - * space. + /* Don't allow potential aliases over the legacy PCI + * expansion card addresses. The legacy PCI decodes + * only 10 bits, uses 0x100 - 0x3ff. Therefore, only + * 0x00 - 0xff can be used out of each 0x400 block of + * I/O space. */ if ((base & 0x300) != 0) { base = (base & ~0x3ff) + 0x400; } - /* Don't allow allocations in the VGA IO range. + /* Don't allow allocations in the VGA I/O range. * PCI has special cases for that. */ else if ((base >= 0x3b0) && (base <= 0x3df)) { base = 0x3e0; } } - if (((round(base, align) + size) -1) <= resource->limit) { - /* base must be aligned to size */ - base = round(base, align); - resource->base = base; - resource->flags |= IORESOURCE_ASSIGNED; - resource->flags &= ~IORESOURCE_STORED; - base += size; + /* Base must be aligned. */ + base = round(base, resource->align); + resource->base = base; + base += resource->size; - printk_spew("%s %02lx * [0x%08Lx - 0x%08Lx] %s\n", - dev_path(dev), - resource->index, - resource->base, - resource->base + resource->size - 1, - (resource->flags & IORESOURCE_IO)? "io": - (resource->flags & IORESOURCE_PREFETCH)? "prefmem": "mem"); - } -#if CONFIG_PCIE_CONFIGSPACE_HOLE -#warning Handle PCIe hole differently... - if (base >= 0xf0000000 && base < 0xf4000000) { - base = 0xf4000000; - } -#endif + printk_spew("%s %02lx * [0x%llx - 0x%llx] %s\n", + dev_path(dev), resource->index, + resource->base, + resource->base + resource->size - 1, + (resource->flags & IORESOURCE_IO) ? "io" : + (resource->flags & IORESOURCE_PREFETCH) ? + "prefmem" : "mem"); } /* A pci bridge resource does not need to be a power * of two size, but it does have a minimum granularity. @@ -378,23 +348,327 @@ * know not to place something else at an address postitively * decoded by the bridge. */ - bridge->size = round(base, bridge->gran) - bridge->base; + bridge->size = round(base, bridge->gran) - + round(bridge->base, bridge->align); - printk_spew("%s compute_allocate_resource %s: base: %08Lx size: %08Lx align: %d gran: %d done\n", - dev_path(bus->dev), - (bridge->flags & IORESOURCE_IO)? "io": - (bridge->flags & IORESOURCE_PREFETCH)? "prefmem" : "mem", - base, bridge->size, bridge->align, bridge->gran); + printk_spew("%s %s_%s: base: %llx size: %llx align: %d gran: %d limit: %llx done\n", + dev_path(bus->dev), __func__, + (bridge->flags & IORESOURCE_IO) ? "io" : + (bridge->flags & IORESOURCE_PREFETCH) ? "prefmem" : "mem", + base, bridge->size, bridge->align, bridge->gran, bridge->limit); } +/** + * This function is the second part of the resource allocator. + * + * The problem. + * - Allocate resource locations for every device. + * - Don't overlap, and follow the rules of bridges. + * - Don't overlap with resources in fixed locations. + * - Be efficient so we don't have ugly strategies. + * + * The strategy. + * - Devices that have fixed addresses are the minority so don't + * worry about them too much. Instead only use part of the address + * space for devices with programmable addresses. This easily handles + * everything except bridges. + * + * - PCI devices are required to have their sizes and their alignments + * equal. In this case an optimal solution to the packing problem + * exists. Allocate all devices from highest alignment to least + * alignment or vice versa. Use this. + * + * - So we can handle more than PCI run two allocation passes on bridges. The + * first to see how large the resources are behind the bridge, and what + * their alignment requirements are. The second to assign a safe address to + * the devices behind the bridge. This allows us to treat a bridge as just + * a device with a couple of resources, and not need to special case it in + * the allocator. Also this allows handling of other types of bridges. + * + * - This function assigns the resources a value. + * + * @param bus The bus we are traversing. + * @param bridge The bridge resource which must contain the bus' resources. + * @param type_mask This value gets anded with the resource type. + * @param type This value must match the result of the and. + */ +void allocate_resources(struct bus *bus, struct resource *bridge, + unsigned long type_mask, unsigned long type) +{ + struct device *dev; + struct resource *resource; + resource_t base; + base = bridge->base; + + printk_spew("%s %s_%s: base:%llx size:%llx align:%d gran:%d limit:%llx\n", + dev_path(bus->dev), __func__, + (type & IORESOURCE_IO) ? "io" : (type & IORESOURCE_PREFETCH) ? + "prefmem" : "mem", + base, bridge->size, bridge->align, bridge->gran, bridge->limit); + + /* Remember we haven't found anything yet. */ + resource = NULL; + + /* Walk through all the resources on the current bus and allocate them + * address space. + */ + while ((dev = largest_resource(bus, &resource, type_mask, type))) { + + /* Propagate the bridge limit to the resource register. */ + if (resource->limit > bridge->limit) { + resource->limit = bridge->limit; + } + + /* Size 0 resources can be skipped. */ + if (!resource->size) { + /* Set the base to limit so it doesn't confuse tolm. */ + resource->base = resource->limit; + resource->flags |= IORESOURCE_ASSIGNED; + continue; + } + + if (resource->flags & IORESOURCE_IO) { + /* Don't allow potential aliases over the legacy PCI + * expansion card addresses. The legacy PCI decodes + * only 10 bits, uses 0x100 - 0x3ff. Therefore, only + * 0x00 - 0xff can be used out of each 0x400 block of + * I/O space. + */ + if ((base & 0x300) != 0) { + base = (base & ~0x3ff) + 0x400; + } + /* Don't allow allocations in the VGA I/O range. + * PCI has special cases for that. + */ + else if ((base >= 0x3b0) && (base <= 0x3df)) { + base = 0x3e0; + } + } + + if ((round(base, resource->align) + resource->size - 1) <= + resource->limit) { + /* Base must be aligned. */ + base = round(base, resource->align); + resource->base = base; + resource->flags |= IORESOURCE_ASSIGNED; + resource->flags &= ~IORESOURCE_STORED; + base += resource->size; + } else { + printk_err("!! Resource didn't fit !!\n"); + printk_err(" aligned base %llx size %llx limit %llx\n", + round(base, resource->align), resource->size, + resource->limit); + printk_err(" %llx needs to be <= %llx (limit)\n", + (round(base, resource->align) + + resource->size) - 1, resource->limit); + printk_err(" %s%s %02lx * [0x%llx - 0x%llx] %s\n", + (resource-> + flags & IORESOURCE_ASSIGNED) ? "Assigned: " : + "", dev_path(dev), resource->index, + resource->base, + resource->base + resource->size - 1, + (resource-> + flags & IORESOURCE_IO) ? "io" : (resource-> + flags & + IORESOURCE_PREFETCH) + ? "prefmem" : "mem"); + } + + printk_spew("%s%s %02lx * [0x%llx - 0x%llx] %s\n", + (resource->flags & IORESOURCE_ASSIGNED) ? "Assigned: " + : "", + dev_path(dev), resource->index, resource->base, + resource->size ? resource->base + resource->size - 1 : + resource->base, + (resource->flags & IORESOURCE_IO) ? "io" : + (resource->flags & IORESOURCE_PREFETCH) ? "prefmem" : + "mem"); + } + /* A PCI bridge resource does not need to be a power of two size, but + * it does have a minimum granularity. Round the size up to that + * minimum granularity so we know not to place something else at an + * address positively decoded by the bridge. + */ + + bridge->flags |= IORESOURCE_ASSIGNED; + + printk_spew("%s %s_%s: next_base: %llx size: %llx align: %d gran: %d done\n", + dev_path(bus->dev), __func__, + (type & IORESOURCE_IO) ? "io" : (type & IORESOURCE_PREFETCH) ? + "prefmem" : "mem", + base, bridge->size, bridge->align, bridge->gran); + + /* For each child which is a bridge, allocate_resources. */ + for (dev = bus->children; dev; dev = dev->sibling) { + unsigned i; + struct resource *child_bridge; + + if (!dev->links) + continue; + + /* Find the resources with matching type flags. */ + for (i = 0; i < dev->resources; i++) { + unsigned link; + child_bridge = &dev->resource[i]; + + if (!(child_bridge->flags & IORESOURCE_BRIDGE) || + (child_bridge->flags & type_mask) != type) + continue; + + /* Split prefetchable memory if combined. Many domains + * use the same address space for prefetchable memory + * and non-prefetchable memory. Bridges below them + * need it separated. Add the PREFETCH flag to the + * type_mask and type. + */ + link = IOINDEX_LINK(child_bridge->index); + allocate_resources(&dev->link[link], child_bridge, + type_mask | IORESOURCE_PREFETCH, + type | (child_bridge->flags & + IORESOURCE_PREFETCH)); + } + } +} + +#if CONFIG_PCI_64BIT_PREF_MEM == 1 + #define MEM_MASK (IORESOURCE_PREFETCH | IORESOURCE_MEM) +#else + #define MEM_MASK (IORESOURCE_MEM) +#endif +#define IO_MASK (IORESOURCE_IO) +#define PREF_TYPE (IORESOURCE_PREFETCH | IORESOURCE_MEM) +#define MEM_TYPE (IORESOURCE_MEM) +#define IO_TYPE (IORESOURCE_IO) + +struct constraints { + struct resource pref, io, mem; +}; + +static void constrain_resources(struct device *dev, struct constraints* limits) +{ + struct device *child; + struct resource *res; + struct resource *lim; + int i; + + printk_spew("%s: %s\n", __func__, dev_path(dev)); + + /* Constrain limits based on the fixed resources of this device. */ + for (i = 0; i < dev->resources; i++) { + res = &dev->resource[i]; + if (!(res->flags & IORESOURCE_FIXED)) + continue; + + /* PREFETCH, MEM, or I/O - skip any others. */ + if ((res->flags & MEM_MASK) == PREF_TYPE) + lim = &limits->pref; + else if ((res->flags & MEM_MASK) == MEM_TYPE) + lim = &limits->mem; + else if ((res->flags & IO_MASK) == IO_TYPE) + lim = &limits->io; + else + continue; + + /* Is it already outside the limits? */ + if (res->size && (((res->base + res->size -1) < lim->base) || + (res->base > lim->limit))) + continue; + + /* Choose to be above or below fixed resources. This + * check is signed so that "negative" amounts of space + * are handled correctly. + */ + if ((signed long long)(lim->limit - (res->base + res->size -1)) > + (signed long long)(res->base - lim->base)) + lim->base = res->base + res->size; + else + lim->limit = res->base -1; + } + + /* Descend into every enabled child and look for fixed resources. */ + for (i = 0; i < dev->links; i++) + for (child = dev->link[i].children; child; + child = child->sibling) + if (child->enabled) + constrain_resources(child, limits); +} + +static void avoid_fixed_resources(struct device *dev) +{ + struct constraints limits; + struct resource *res; + int i; + + printk_spew("%s: %s\n", __func__, dev_path(dev)); + /* Initialize constraints to maximum size. */ + + limits.pref.base = 0; + limits.pref.limit = 0xffffffffffffffffULL; + limits.io.base = 0; + limits.io.limit = 0xffffffffffffffffULL; + limits.mem.base = 0; + limits.mem.limit = 0xffffffffffffffffULL; + + /* Constrain the limits to dev's initial resources. */ + for (i = 0; i < dev->resources; i++) { + res = &dev->resource[i]; + if ((res->flags & IORESOURCE_FIXED)) + continue; + printk_spew("%s:@%s %02lx limit %08Lx\n", __func__, + dev_path(dev), res->index, res->limit); + if ((res->flags & MEM_MASK) == PREF_TYPE && + (res->limit < limits.pref.limit)) + limits.pref.limit = res->limit; + if ((res->flags & MEM_MASK) == MEM_TYPE && + (res->limit < limits.mem.limit)) + limits.mem.limit = res->limit; + if ((res->flags & IO_MASK) == IO_TYPE && + (res->limit < limits.io.limit)) + limits.io.limit = res->limit; + } + + /* Look through the tree for fixed resources and update the limits. */ + constrain_resources(dev, &limits); + + /* Update dev's resources with new limits. */ + for (i = 0; i < dev->resources; i++) { + struct resource *lim; + res = &dev->resource[i]; + + if ((res->flags & IORESOURCE_FIXED)) + continue; + + /* PREFETCH, MEM, or I/O - skip any others. */ + if ((res->flags & MEM_MASK) == PREF_TYPE) + lim = &limits.pref; + else if ((res->flags & MEM_MASK) == MEM_TYPE) + lim = &limits.mem; + else if ((res->flags & IO_MASK) == IO_TYPE) + lim = &limits.io; + else + continue; + + printk_spew("%s2: %s@%02lx limit %08Lx\n", __func__, + dev_path(dev), res->index, res->limit); + printk_spew("\tlim->base %08Lx lim->limit %08Lx\n", + lim->base, lim->limit); + + /* Is the resource outside the limits? */ + if (lim->base > res->base) + res->base = lim->base; + if (res->limit > lim->limit) + res->limit = lim->limit; + } +} + #if CONFIG_CONSOLE_VGA == 1 device_t vga_pri = 0; static void allocate_vga_resource(void) { #warning "FIXME modify allocate_vga_resource so it is less pci centric!" -#warning "This function knows to much about PCI stuff, it should be just a ietrator/visitor." +#warning "This function knows too much about PCI stuff, it should be just a iterator/visitor." - /* FIXME handle the VGA pallette snooping */ + /* FIXME: Handle the VGA palette snooping. */ struct device *dev, *vga, *vga_onboard, *vga_first, *vga_last; struct bus *bus; bus = 0; @@ -402,66 +676,63 @@ vga_onboard = 0; vga_first = 0; vga_last = 0; - for(dev = all_devices; dev; dev = dev->next) { - if (!dev->enabled) continue; + for (dev = all_devices; dev; dev = dev->next) { + if (!dev->enabled) + continue; if (((dev->class >> 16) == PCI_BASE_CLASS_DISPLAY) && - ((dev->class >> 8) != PCI_CLASS_DISPLAY_OTHER)) - { - if (!vga_first) { - if (dev->on_mainboard) { - vga_onboard = dev; - } else { - vga_first = dev; - } - } else { - if (dev->on_mainboard) { - vga_onboard = dev; - } else { - vga_last = dev; - } - } + ((dev->class >> 8) != PCI_CLASS_DISPLAY_OTHER)) { + if (!vga_first) { + if (dev->on_mainboard) { + vga_onboard = dev; + } else { + vga_first = dev; + } + } else { + if (dev->on_mainboard) { + vga_onboard = dev; + } else { + vga_last = dev; + } + } - /* It isn't safe to enable other VGA cards */ + /* It isn't safe to enable other VGA cards. */ dev->command &= ~(PCI_COMMAND_MEMORY | PCI_COMMAND_IO); } } - vga = vga_last; + vga = vga_last; - if(!vga) { - vga = vga_first; - } - + if (!vga) { + vga = vga_first; + } #if CONFIG_CONSOLE_VGA_ONBOARD_AT_FIRST == 1 - if (vga_onboard) // will use on board vga as pri + if (vga_onboard) // Will use on board VGA as pri. #else - if (!vga) // will use last add on adapter as pri + if (!vga) // Will use last add on adapter as pri. #endif - { - vga = vga_onboard; - } + { + vga = vga_onboard; + } - if (vga) { - /* vga is first add on card or the only onboard vga */ + /* VGA is first add on card or the only onboard VGA. */ printk_debug("Allocating VGA resource %s\n", dev_path(vga)); - /* All legacy VGA cards have MEM & I/O space registers */ + /* All legacy VGA cards have MEM & I/O space registers. */ vga->command |= (PCI_COMMAND_MEMORY | PCI_COMMAND_IO); vga_pri = vga; bus = vga->bus; } - /* Now walk up the bridges setting the VGA enable */ - while(bus) { + /* Now walk up the bridges setting the VGA enable. */ + while (bus) { printk_debug("Setting PCI_BRIDGE_CTL_VGA for bridge %s\n", dev_path(bus->dev)); bus->bridge_ctrl |= PCI_BRIDGE_CTL_VGA; - bus = (bus == bus->dev->bus)? 0 : bus->dev->bus; + bus = (bus == bus->dev->bus) ? 0 : bus->dev->bus; } } #endif - /** * @brief Assign the computed resources to the devices on the bus. * @@ -480,21 +751,21 @@ struct device *curdev; printk_spew("%s assign_resources, bus %d link: %d\n", - dev_path(bus->dev), bus->secondary, bus->link); + dev_path(bus->dev), bus->secondary, bus->link); - for(curdev = bus->children; curdev; curdev = curdev->sibling) { + for (curdev = bus->children; curdev; curdev = curdev->sibling) { if (!curdev->enabled || !curdev->resources) { continue; } if (!curdev->ops || !curdev->ops->set_resources) { printk_err("%s missing set_resources\n", - dev_path(curdev)); + dev_path(curdev)); continue; } curdev->ops->set_resources(curdev); } printk_spew("%s assign_resources, bus %d link: %d\n", - dev_path(bus->dev), bus->secondary, bus->link); + dev_path(bus->dev), bus->secondary, bus->link); } /** @@ -539,8 +810,7 @@ */ int reset_bus(struct bus *bus) { - if (bus && bus->dev && bus->dev->ops && bus->dev->ops->reset_bus) - { + if (bus && bus->dev && bus->dev->ops && bus->dev->ops->reset_bus) { bus->dev->ops->reset_bus(bus); bus->reset_needed = 0; return 1; @@ -551,37 +821,34 @@ /** * @brief Scan for devices on a bus. * - * If there are bridges on the bus, recursively scan the buses behind the bridges. - * If the setting up and tuning of the bus causes a reset to be required, - * reset the bus and scan it again. + * If there are bridges on the bus, recursively scan the buses behind the + * bridges. If the setting up and tuning of the bus causes a reset to be + * required, reset the bus and scan it again. * - * @param bus pointer to the bus device - * @param max current bus number - * - * @return The maximum bus number found, after scanning all subordinate busses + * @param busdev Pointer to the bus device. + * @param max Current bus number. + * @return The maximum bus number found, after scanning all subordinate buses. */ -unsigned int scan_bus(device_t bus, unsigned int max) +unsigned int scan_bus(struct device *busdev, unsigned int max) { unsigned int new_max; int do_scan_bus; - if ( !bus || - !bus->enabled || - !bus->ops || - !bus->ops->scan_bus) - { + if (!busdev || !busdev->enabled || !busdev->ops || + !busdev->ops->scan_bus) { return max; } + do_scan_bus = 1; - while(do_scan_bus) { + while (do_scan_bus) { int link; - new_max = bus->ops->scan_bus(bus, max); + new_max = busdev->ops->scan_bus(busdev, max); do_scan_bus = 0; - for(link = 0; link < bus->links; link++) { - if (bus->link[link].reset_needed) { - if (reset_bus(&bus->link[link])) { + for (link = 0; link < busdev->links; link++) { + if (busdev->link[link].reset_needed) { + if (reset_bus(&busdev->link[link])) { do_scan_bus = 1; } else { - bus->bus->reset_needed = 1; + busdev->bus->reset_needed = 1; } } } @@ -589,7 +856,6 @@ return new_max; } - /** * @brief Determine the existence of devices and extend the device tree. * @@ -619,7 +885,7 @@ printk_info("Enumerating buses...\n"); root = &dev_root; - show_all_devs(BIOS_DEBUG, "Before Phase 3."); + show_all_devs(BIOS_DEBUG, "Before Device Enumeration."); printk_debug("Compare with tree...\n"); show_devs_tree(root, BIOS_DEBUG, 0, 0); @@ -643,66 +909,115 @@ * requried by each device. In the second pass, the resources ranges are * relocated to their final position and stored to the hardware. * - * I/O resources start at DEVICE_IO_START and grow upward. MEM resources start - * at DEVICE_MEM_HIGH and grow downward. + * I/O resources grow upward. MEM resources grow downward. * * Since the assignment is hierarchical we set the values into the dev_root * struct. */ void dev_configure(void) { - struct resource *io, *mem; + struct resource *res; struct device *root; + struct device *child; + int i; printk_info("Allocating resources...\n"); root = &dev_root; - print_resource_tree(root, BIOS_DEBUG, "Original."); + /* Each domain should create resources which contain the entire address + * space for IO, MEM, and PREFMEM resources in the domain. The + * allocation of device resources will be done from this address space. + */ - if (!root->ops || !root->ops->read_resources) { - printk_err("dev_root missing read_resources\n"); - return; - } - if (!root->ops || !root->ops->set_resources) { - printk_err("dev_root missing set_resources\n"); - return; - } + /* Read the resources for the entire tree. */ printk_info("Reading resources...\n"); - root->ops->read_resources(root); + read_resources(&root->link[0]); printk_info("Done reading resources.\n"); print_resource_tree(root, BIOS_DEBUG, "After reading."); - /* Get the resources */ - io = &root->resource[0]; - mem = &root->resource[1]; - /* Make certain the io devices are allocated somewhere safe. */ - io->base = DEVICE_IO_START; - io->flags |= IORESOURCE_ASSIGNED; - io->flags &= ~IORESOURCE_STORED; - /* Now reallocate the pci resources memory with the - * highest addresses I can manage. + /* Compute resources for all domains. */ + for (child = root->link[0].children; child; child = child->sibling) { + if (!(child->path.type == DEVICE_PATH_PCI_DOMAIN)) + continue; + for (i = 0; i < child->resources; i++) { + res = &child->resource[i]; + if (res->flags & IORESOURCE_FIXED) + continue; + if (res->flags & IORESOURCE_PREFETCH) { + compute_resources(&child->link[0], + res, MEM_MASK, PREF_TYPE); + continue; + } + if (res->flags & IORESOURCE_MEM) { + compute_resources(&child->link[0], + res, MEM_MASK, MEM_TYPE); + continue; + } + if (res->flags & IORESOURCE_IO) { + compute_resources(&child->link[0], + res, IO_MASK, IO_TYPE); + continue; + } + } + } + + /* For all domains. */ + for (child = root->link[0].children; child; child=child->sibling) + if (child->path.type == DEVICE_PATH_PCI_DOMAIN) + avoid_fixed_resources(child); + + /* Now we need to adjust the resources. MEM resources need to start at + * the highest address managable. */ - mem->base = resource_max(&root->resource[1]); - mem->flags |= IORESOURCE_ASSIGNED; - mem->flags &= ~IORESOURCE_STORED; + for (child = root->link[0].children; child; child = child->sibling) { + if (child->path.type != DEVICE_PATH_PCI_DOMAIN) + continue; + for (i = 0; i < child->resources; i++) { + res = &child->resource[i]; + if (!(res->flags & IORESOURCE_MEM) || + res->flags & IORESOURCE_FIXED) + continue; + res->base = resource_max(res); + } + } #if CONFIG_CONSOLE_VGA == 1 - /* Allocate the VGA I/O resource.. */ + /* Allocate the VGA I/O resource. */ allocate_vga_resource(); print_resource_tree(root, BIOS_DEBUG, "After VGA."); #endif /* Store the computed resource allocations into device registers ... */ printk_info("Setting resources...\n"); - root->ops->set_resources(root); + for (child = root->link[0].children; child; child = child->sibling) { + if (!(child->path.type == DEVICE_PATH_PCI_DOMAIN)) + continue; + for (i = 0; i < child->resources; i++) { + res = &child->resource[i]; + if (res->flags & IORESOURCE_FIXED) + continue; + if (res->flags & IORESOURCE_PREFETCH) { + allocate_resources(&child->link[0], + res, MEM_MASK, PREF_TYPE); + continue; + } + if (res->flags & IORESOURCE_MEM) { + allocate_resources(&child->link[0], + res, MEM_MASK, MEM_TYPE); + continue; + } + if (res->flags & IORESOURCE_IO) { + allocate_resources(&child->link[0], + res, IO_MASK, IO_TYPE); + continue; + } + } + } + assign_resources(&root->link[0]); printk_info("Done setting resources.\n"); -#if 0 - mem->flags |= IORESOURCE_STORED; - report_resource_stored(root, mem, ""); -#endif print_resource_tree(root, BIOS_DEBUG, "After assigning values."); printk_info("Done allocating resources.\n"); @@ -736,13 +1051,13 @@ struct device *dev; printk_info("Initializing devices...\n"); - for(dev = all_devices; dev; dev = dev->next) { + for (dev = all_devices; dev; dev = dev->next) { if (dev->enabled && !dev->initialized && - dev->ops && dev->ops->init) - { + dev->ops && dev->ops->init) { if (dev->path.type == DEVICE_PATH_I2C) { - printk_debug("smbus: %s[%d]->", - dev_path(dev->bus->dev), dev->bus->link); + printk_debug("smbus: %s[%d]->", + dev_path(dev->bus->dev), + dev->bus->link); } printk_debug("%s init\n", dev_path(dev)); dev->initialized = 1; @@ -752,4 +1067,3 @@ printk_info("Devices initialized\n"); show_all_devs(BIOS_DEBUG, "After init."); } - Modified: trunk/coreboot-v2/src/devices/device_util.c =================================================================== --- trunk/coreboot-v2/src/devices/device_util.c 2009-07-02 18:27:02 UTC (rev 4393) +++ trunk/coreboot-v2/src/devices/device_util.c 2009-07-02 18:56:24 UTC (rev 4394) @@ -487,7 +487,7 @@ for(curdev = bus->children; curdev; curdev = curdev->sibling) { int i; /* Ignore disabled devices */ - if (!curdev->have_resources) continue; + if (!curdev->enabled) continue; for(i = 0; i < curdev->resources; i++) { struct resource *resource = &curdev->resource[i]; /* If it isn't the right kind of resource ignore it */ @@ -514,7 +514,7 @@ for(curdev = all_devices; curdev; curdev = curdev->next) { int i; /* Ignore disabled devices */ - if (!curdev->have_resources) continue; + if (!curdev->enabled) continue; for(i = 0; i < curdev->resources; i++) { struct resource *resource = &curdev->resource[i]; /* If it isn't the right kind of resource ignore it */ Modified: trunk/coreboot-v2/src/devices/pci_device.c =================================================================== --- trunk/coreboot-v2/src/devices/pci_device.c 2009-07-02 18:27:02 UTC (rev 4393) +++ trunk/coreboot-v2/src/devices/pci_device.c 2009-07-02 18:56:24 UTC (rev 4394) @@ -15,12 +15,12 @@ */ /* - * PCI Bus Services, see include/linux/pci.h for further explanation. + * PCI Bus Services, see include/linux/pci.h for further explanation. * - * Copyright 1993 -- 1997 Drew Eckhardt, Frederic Potter, - * David Mosberger-Tang + * Copyright 1993 -- 1997 Drew Eckhardt, Frederic Potter, + * David Mosberger-Tang * - * Copyright 1997 -- 1999 Martin Mares <mj(a)atrey.karlin.mff.cuni.cz> + * Copyright 1997 -- 1999 Martin Mares <mj(a)atrey.karlin.mff.cuni.cz> */ #include <console/console.h> @@ -51,9 +51,9 @@ #include <device/cardbus.h> #endif -uint8_t pci_moving_config8(struct device *dev, unsigned reg) +u8 pci_moving_config8(struct device *dev, unsigned int reg) { - uint8_t value, ones, zeroes; + u8 value, ones, zeroes; value = pci_read_config8(dev, reg); pci_write_config8(dev, reg, 0xff); @@ -67,9 +67,9 @@ return ones ^ zeroes; } -uint16_t pci_moving_config16(struct device *dev, unsigned reg) +u16 pci_moving_config16(struct device * dev, unsigned int reg) { - uint16_t value, ones, zeroes; + u16 value, ones, zeroes; value = pci_read_config16(dev, reg); pci_write_config16(dev, reg, 0xffff); @@ -83,9 +83,9 @@ return ones ^ zeroes; } -uint32_t pci_moving_config32(struct device *dev, unsigned reg) +u32 pci_moving_config32(struct device * dev, unsigned int reg) { - uint32_t value, ones, zeroes; + u32 value, ones, zeroes; value = pci_read_config32(dev, reg); pci_write_config32(dev, reg, 0xffffffff); @@ -99,7 +99,16 @@ return ones ^ zeroes; } -unsigned pci_find_next_capability(device_t dev, unsigned cap, unsigned last) +/** + * Given a device, a capability type, and a last position, return the next + * matching capability. Always start at the head of the list. + * + * @param dev Pointer to the device structure. + * @param cap_type PCI_CAP_LIST_ID of the PCI capability we're looking for. + * @param last Location of the PCI capability register to start from. + */ +unsigned pci_find_next_capability(struct device *dev, unsigned cap, + unsigned last) { unsigned pos; unsigned status; @@ -109,7 +118,7 @@ if (!(status & PCI_STATUS_CAP_LIST)) { return 0; } - switch(dev->hdr_type & 0x7f) { + switch (dev->hdr_type & 0x7f) { case PCI_HEADER_TYPE_NORMAL: case PCI_HEADER_TYPE_BRIDGE: pos = PCI_CAPABILITY_LIST; @@ -121,11 +130,12 @@ return 0; } pos = pci_read_config8(dev, pos); - while(reps-- && (pos >= 0x40)) { /* loop through the linked list */ + while (reps-- && (pos >= 0x40)) { /* Loop through the linked list. */ int this_cap; pos &= ~3; this_cap = pci_read_config8(dev, pos + PCI_CAP_LIST_ID); - printk_spew("Capability: 0x%02x @ 0x%02x\n", cap, pos); + printk_spew("Capability: type 0x%02x @ 0x%02x\n", this_cap, + pos); if (this_cap == 0xff) { break; } @@ -140,64 +150,71 @@ return 0; } +/** + * Given a device, and a capability type, return the next matching + * capability. Always start at the head of the list. + * + * @param dev Pointer to the device structure. + * @param cap_type PCI_CAP_LIST_ID of the PCI capability we're looking for. + */ unsigned pci_find_capability(device_t dev, unsigned cap) { return pci_find_next_capability(dev, cap, 0); - } -/** Given a device and register, read the size of the BAR for that register. - * @param dev Pointer to the device structure - * @param resource Pointer to the resource structure - * @param index Address of the pci configuration register +/** + * Given a device and register, read the size of the BAR for that register. + * + * @param dev Pointer to the device structure. + * @param index Address of the PCI configuration register. */ struct resource *pci_get_resource(struct device *dev, unsigned long index) { struct resource *resource; unsigned long value, attr; - resource_t moving, limit; + resource_t moving, limit; - /* Initialize the resources to nothing */ + /* Initialize the resources to nothing. */ resource = new_resource(dev, index); - /* Get the initial value */ + /* Get the initial value. */ value = pci_read_config32(dev, index); - /* See which bits move */ + /* See which bits move. */ moving = pci_moving_config32(dev, index); - /* Initialize attr to the bits that do not move */ + /* Initialize attr to the bits that do not move. */ attr = value & ~moving; - /* If it is a 64bit resource look at the high half as well */ + /* If it is a 64bit resource look at the high half as well. */ if (((attr & PCI_BASE_ADDRESS_SPACE_IO) == 0) && - ((attr & PCI_BASE_ADDRESS_MEM_LIMIT_MASK) == PCI_BASE_ADDRESS_MEM_LIMIT_64)) - { - /* Find the high bits that move */ - moving |= ((resource_t)pci_moving_config32(dev, index + 4)) << 32; + ((attr & PCI_BASE_ADDRESS_MEM_LIMIT_MASK) == + PCI_BASE_ADDRESS_MEM_LIMIT_64)) { + /* Find the high bits that move. */ + moving |= + ((resource_t) pci_moving_config32(dev, index + 4)) << 32; } /* Find the resource constraints. - * * Start by finding the bits that move. From there: * - Size is the least significant bit of the bits that move. * - Limit is all of the bits that move plus all of the lower bits. - * See PCI Spec 6.2.5.1 ... + * See PCI Spec 6.2.5.1. */ limit = 0; if (moving) { resource->size = 1; resource->align = resource->gran = 0; - while(!(moving & resource->size)) { + while (!(moving & resource->size)) { resource->size <<= 1; resource->align += 1; - resource->gran += 1; + resource->gran += 1; } resource->limit = limit = moving | (resource->size - 1); } - /* - * some broken hardware has read-only registers that do not + + /* Some broken hardware has read-only registers that do not * really size correctly. - * Example: the acer m7229 has BARs 1-4 normally read-only. + * Example: the Acer M7229 has BARs 1-4 normally read-only. * so BAR1 at offset 0x10 reads 0x1f1. If you size that register * by writing 0xffffffff to it, it will read back as 0x1f1 -- a * violation of the spec. @@ -207,21 +224,19 @@ */ if (moving == 0) { if (value != 0) { - printk_debug( - "%s register %02lx(%08lx), read-only ignoring it\n", - dev_path(dev), index, value); + printk_debug + ("%s register %02lx(%08lx), read-only ignoring it\n", + dev_path(dev), index, value); } resource->flags = 0; - } - else if (attr & PCI_BASE_ADDRESS_SPACE_IO) { - /* An I/O mapped base address */ + } else if (attr & PCI_BASE_ADDRESS_SPACE_IO) { + /* An I/O mapped base address. */ attr &= PCI_BASE_ADDRESS_IO_ATTR_MASK; resource->flags |= IORESOURCE_IO; - /* I don't want to deal with 32bit I/O resources */ + /* I don't want to deal with 32bit I/O resources. */ resource->limit = 0xffff; - } - else { - /* A Memory mapped base address */ + } else { + /* A Memory mapped base address. */ attr &= PCI_BASE_ADDRESS_MEM_ATTR_MASK; resource->flags |= IORESOURCE_MEM; if (attr & PCI_BASE_ADDRESS_MEM_PREFETCH) { @@ -229,73 +244,65 @@ } attr &= PCI_BASE_ADDRESS_MEM_LIMIT_MASK; if (attr == PCI_BASE_ADDRESS_MEM_LIMIT_32) { - /* 32bit limit */ + /* 32bit limit. */ resource->limit = 0xffffffffUL; - } - else if (attr == PCI_BASE_ADDRESS_MEM_LIMIT_1M) { - /* 1MB limit */ + } else if (attr == PCI_BASE_ADDRESS_MEM_LIMIT_1M) { + /* 1MB limit. */ resource->limit = 0x000fffffUL; - } - else if (attr == PCI_BASE_ADDRESS_MEM_LIMIT_64) { - /* 64bit limit */ + } else if (attr == PCI_BASE_ADDRESS_MEM_LIMIT_64) { + /* 64bit limit. */ resource->limit = 0xffffffffffffffffULL; resource->flags |= IORESOURCE_PCI64; - } - else { - /* Invalid value */ + } else { + /* Invalid value. */ + printk_err("Broken BAR with value %lx\n", attr); + printk_err(" on dev %s at index %02lx\n", + dev_path(dev), index); resource->flags = 0; } } - /* Don't let the limit exceed which bits can move */ + /* Don't let the limit exceed which bits can move. */ if (resource->limit > limit) { resource->limit = limit; } -#if 0 - if (resource->flags) { - printk_debug("%s %02x ->", - dev_path(dev), resource->index); - printk_debug(" value: 0x%08Lx zeroes: 0x%08Lx ones: 0x%08Lx attr: %08lx\n", - value, zeroes, ones, attr); - printk_debug( - "%s %02x -> size: 0x%08Lx max: 0x%08Lx %s\n ", - dev_path(dev), - resource->index, - resource->size, resource->limit, - resource_type(resource)); - } -#endif return resource; } +/** + * Given a device and an index, read the size of the BAR for that register. + * + * @param dev Pointer to the device structure. + * @param index Address of the PCI configuration register. + */ static void pci_get_rom_resource(struct device *dev, unsigned long index) { struct resource *resource; unsigned long value; - resource_t moving; + resource_t moving; - if ((dev->on_mainboard) && (dev->rom_address == 0)) { - //skip it if rom_address is not set in MB Config.lb - return; - } + if ((dev->on_mainboard) && (dev->rom_address == 0)) { + /* Skip it if rom_address is not set in the MB Config.lb. */ + return; + } - /* Initialize the resources to nothing */ + /* Initialize the resources to nothing. */ resource = new_resource(dev, index); - /* Get the initial value */ + /* Get the initial value. */ value = pci_read_config32(dev, index); - /* See which bits move */ + /* See which bits move. */ moving = pci_moving_config32(dev, index); - /* clear the Enable bit */ + + /* Clear the Enable bit. */ moving = moving & ~PCI_ROM_ADDRESS_ENABLE; /* Find the resource constraints. - * * Start by finding the bits that move. From there: * - Size is the least significant bit of the bits that move. * - Limit is all of the bits that move plus all of the lower bits. - * See PCI Spec 6.2.5.1 ... + * See PCI Spec 6.2.5.1. */ if (moving) { resource->size = 1; @@ -303,59 +310,57 @@ while (!(moving & resource->size)) { resource->size <<= 1; resource->align += 1; - resource->gran += 1; + resource->gran += 1; } resource->limit = moving | (resource->size - 1); - } - - if (moving == 0) { + resource->flags |= IORESOURCE_MEM | IORESOURCE_READONLY; + } else { if (value != 0) { - printk_debug("%s register %02lx(%08lx), read-only ignoring it\n", - dev_path(dev), index, value); + printk_debug + ("%s register %02lx(%08lx), read-only ignoring it\n", + dev_path(dev), index, value); } resource->flags = 0; - } else { - resource->flags |= IORESOURCE_MEM | IORESOURCE_READONLY; } - /* for on board device with embedded ROM image, the ROM image is at + /* For on board device with embedded ROM image, the ROM image is at * fixed address specified in the Config.lb, the dev->rom_address is * inited by driver_pci_onboard_ops::enable_dev() */ if ((dev->on_mainboard) && (dev->rom_address != 0)) { - resource->base = dev->rom_address; + resource->base = dev->rom_address; resource->flags |= IORESOURCE_MEM | IORESOURCE_READONLY | - IORESOURCE_ASSIGNED | IORESOURCE_FIXED; + IORESOURCE_ASSIGNED | IORESOURCE_FIXED; } compact_resources(dev); } -/** Read the base address registers for a given device. - * @param dev Pointer to the dev structure - * @param howmany How many registers to read (6 for device, 2 for bridge) +/** + * Read the base address registers for a given device. + * + * @param dev Pointer to the dev structure. + * @param howmany How many registers to read (6 for device, 2 for bridge). */ static void pci_read_bases(struct device *dev, unsigned int howmany) { unsigned long index; - for(index = PCI_BASE_ADDRESS_0; (index < PCI_BASE_ADDRESS_0 + (howmany << 2)); ) { + for (index = PCI_BASE_ADDRESS_0; + (index < PCI_BASE_ADDRESS_0 + (howmany << 2));) { struct resource *resource; resource = pci_get_resource(dev, index); - index += (resource->flags & IORESOURCE_PCI64)?8:4; + index += (resource->flags & IORESOURCE_PCI64) ? 8 : 4; } compact_resources(dev); } -static void pci_set_resource(struct device *dev, struct resource *resource); - -static void pci_record_bridge_resource( - struct device *dev, resource_t moving, - unsigned index, unsigned long mask, unsigned long type) +static void pci_record_bridge_resource(struct device *dev, resource_t moving, + unsigned index, unsigned long type) { - /* Initiliaze the constraints on the current bus */ + /* Initialize the constraints on the current bus. */ struct resource *resource; - resource = 0; + resource = NULL; if (moving) { unsigned long gran; resource_t step; @@ -363,29 +368,15 @@ resource->size = 0; gran = 0; step = 1; - while((moving & step) == 0) { + while ((moving & step) == 0) { gran += 1; step <<= 1; } resource->gran = gran; resource->align = gran; resource->limit = moving | (step - 1); - resource->flags = type | IORESOURCE_PCI_BRIDGE; - compute_allocate_resource(&dev->link[0], resource, mask, type); - /* If there is nothing behind the resource, - * clear it and forget it. - */ - if (resource->size == 0) { -#if CONFIG_PCI_64BIT_PREF_MEM == 1 - resource->base = moving; -#else - resource->base = moving & 0xffffffff; -#endif - resource->flags |= IORESOURCE_ASSIGNED; - resource->flags &= ~IORESOURCE_STORED; - pci_set_resource(dev, resource); - resource->flags = 0; - } + resource->flags = type | IORESOURCE_PCI_BRIDGE | + IORESOURCE_BRIDGE; } return; } @@ -394,47 +385,48 @@ { resource_t moving_base, moving_limit, moving; - /* See if the bridge I/O resources are implemented */ - moving_base = ((uint32_t)pci_moving_config8(dev, PCI_IO_BASE)) << 8; - moving_base |= ((uint32_t)pci_moving_config16(dev, PCI_IO_BASE_UPPER16)) << 16; + /* See if the bridge I/O resources are implemented. */ + moving_base = ((u32) pci_moving_config8(dev, PCI_IO_BASE)) << 8; + moving_base |= + ((u32) pci_moving_config16(dev, PCI_IO_BASE_UPPER16)) << 16; - moving_limit = ((uint32_t)pci_moving_config8(dev, PCI_IO_LIMIT)) << 8; - moving_limit |= ((uint32_t)pci_moving_config16(dev, PCI_IO_LIMIT_UPPER16)) << 16; + moving_limit = ((u32) pci_moving_config8(dev, PCI_IO_LIMIT)) << 8; + moving_limit |= + ((u32) pci_moving_config16(dev, PCI_IO_LIMIT_UPPER16)) << 16; moving = moving_base & moving_limit; - /* Initialize the io space constraints on the current bus */ - pci_record_bridge_resource( - dev, moving, PCI_IO_BASE, - IORESOURCE_IO, IORESOURCE_IO); + /* Initialize the I/O space constraints on the current bus. */ + pci_record_bridge_resource(dev, moving, PCI_IO_BASE, IORESOURCE_IO); + /* See if the bridge prefmem resources are implemented. */ + moving_base = + ((resource_t) pci_moving_config16(dev, PCI_PREF_MEMORY_BASE)) << 16; + moving_base |= + ((resource_t) pci_moving_config32(dev, PCI_PREF_BASE_UPPER32)) << + 32; - /* See if the bridge prefmem resources are implemented */ - moving_base = ((resource_t)pci_moving_config16(dev, PCI_PREF_MEMORY_BASE)) << 16; - moving_base |= ((resource_t)pci_moving_config32(dev, PCI_PREF_BASE_UPPER32)) << 32; + moving_limit = + ((resource_t) pci_moving_config16(dev, PCI_PREF_MEMORY_LIMIT)) << + 16; + moving_limit |= + ((resource_t) pci_moving_config32(dev, PCI_PREF_LIMIT_UPPER32)) << + 32; - moving_limit = ((resource_t)pci_moving_config16(dev, PCI_PREF_MEMORY_LIMIT)) << 16; - moving_limit |= ((resource_t)pci_moving_config32(dev, PCI_PREF_LIMIT_UPPER32)) << 32; - moving = moving_base & moving_limit; - /* Initiliaze the prefetchable memory constraints on the current bus */ - pci_record_bridge_resource( - dev, moving, PCI_PREF_MEMORY_BASE, - IORESOURCE_MEM | IORESOURCE_PREFETCH, - IORESOURCE_MEM | IORESOURCE_PREFETCH); + /* Initialize the prefetchable memory constraints on the current bus. */ + pci_record_bridge_resource(dev, moving, PCI_PREF_MEMORY_BASE, + IORESOURCE_MEM | IORESOURCE_PREFETCH); + /* See if the bridge mem resources are implemented. */ + moving_base = ((u32) pci_moving_config16(dev, PCI_MEMORY_BASE)) << 16; + moving_limit = ((u32) pci_moving_config16(dev, PCI_MEMORY_LIMIT)) << 16; - /* See if the bridge mem resources are implemented */ - moving_base = ((uint32_t)pci_moving_config16(dev, PCI_MEMORY_BASE)) << 16; - moving_limit = ((uint32_t)pci_moving_config16(dev, PCI_MEMORY_LIMIT)) << 16; - moving = moving_base & moving_limit; - /* Initialize the memory resources on the current bus */ - pci_record_bridge_resource( - dev, moving, PCI_MEMORY_BASE, - IORESOURCE_MEM | IORESOURCE_PREFETCH, - IORESOURCE_MEM); + /* Initialize the memory resources on the current bus. */ + pci_record_bridge_resource(dev, moving, PCI_MEMORY_BASE, + IORESOURCE_MEM); compact_resources(dev); } @@ -452,34 +444,50 @@ pci_get_rom_resource(dev, PCI_ROM_ADDRESS1); } +void pci_domain_read_resources(struct device *dev) +{ + struct resource *res; + + /* Initialize the system-wide I/O space constraints. */ + res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0)); + res->limit = 0xffffUL; + res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | + IORESOURCE_ASSIGNED; + + /* Initialize the system-wide memory resources constraints. */ + res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0)); + res->limit = 0xffffffffULL; + res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | + IORESOURCE_ASSIGNED; +} + static void pci_set_resource(struct device *dev, struct resource *resource) { resource_t base, end; - /* Make certain the resource has actually been set */ + /* Make certain the resource has actually been assigned a value. */ if (!(resource->flags & IORESOURCE_ASSIGNED)) { - printk_err("ERROR: %s %02lx %s size: 0x%010Lx not assigned\n", - dev_path(dev), resource->index, - resource_type(resource), - resource->size); + printk_err("ERROR: %s %02lx %s size: 0x%010llx not assigned\n", + dev_path(dev), resource->index, + resource_type(resource), resource->size); return; } - /* If I have already stored this resource don't worry about it */ + /* If I have already stored this resource don't worry about it. */ if (resource->flags & IORESOURCE_STORED) { return; } - /* If the resources is substractive don't worry about it */ + /* If the resource is subtractive don't worry about it. */ if (resource->flags & IORESOURCE_SUBTRACTIVE) { return; } - /* Only handle PCI memory and IO resources for now */ - if (!(resource->flags & (IORESOURCE_MEM |IORESOURCE_IO))) + /* Only handle PCI memory and I/O resources for now. */ + if (!(resource->flags & (IORESOURCE_MEM | IORESOURCE_IO))) return; - /* Enable the resources in the command register */ + /* Enable the resources in the command register. */ if (resource->size) { if (resource->flags & IORESOURCE_MEM) { dev->command |= PCI_COMMAND_MEMORY; @@ -491,19 +499,29 @@ dev->command |= PCI_COMMAND_MASTER; } } - /* Get the base address */ + /* Get the base address. */ base = resource->base; - /* Get the end */ + /* Get the end. */ end = resource_end(resource); - /* Now store the resource */ + /* Now store the resource. */ resource->flags |= IORESOURCE_STORED; + + /* PCI Bridges have no enable bit. They are disabled if the base of + * the range is greater than the limit. If the size is zero, disable + * by setting the base = limit and end = limit - 2^gran. + */ + if (resource->size == 0 && (resource->flags & IORESOURCE_PCI_BRIDGE)) { + base = resource->limit; + end = resource->limit - (1 << resource->gran); + resource->base = base; + } + if (!(resource->flags & IORESOURCE_PCI_BRIDGE)) { unsigned long base_lo, base_hi; - /* - * some chipsets allow us to set/clear the IO bit. - * (e.g. VIA 82c686a.) So set it to be safe) + /* Some chipsets allow us to set/clear the I/O bit + * (e.g. VIA 82c686a). So set it to be safe. */ base_lo = base & 0xffffffff; base_hi = (base >> 32) & 0xffffffff; @@ -514,39 +532,27 @@ if (resource->flags & IORESOURCE_PCI64) { pci_write_config32(dev, resource->index + 4, base_hi); } - } - else if (resource->index == PCI_IO_BASE) { - /* set the IO ranges */ - compute_allocate_resource(&dev->link[0], resource, - IORESOURCE_IO, IORESOURCE_IO); - pci_write_config8(dev, PCI_IO_BASE, base >> 8); + } else if (resource->index == PCI_IO_BASE) { + /* Set the I/O ranges. */ + pci_write_config8(dev, PCI_IO_BASE, base >> 8); pci_write_config16(dev, PCI_IO_BASE_UPPER16, base >> 16); - pci_write_config8(dev, PCI_IO_LIMIT, end >> 8); + pci_write_config8(dev, PCI_IO_LIMIT, end >> 8); pci_write_config16(dev, PCI_IO_LIMIT_UPPER16, end >> 16); - } - else if (resource->index == PCI_MEMORY_BASE) { - /* set the memory range */ - compute_allocate_resource(&dev->link[0], resource, - IORESOURCE_MEM | IORESOURCE_PREFETCH, - IORESOURCE_MEM); + } else if (resource->index == PCI_MEMORY_BASE) { + /* Set the memory range. */ pci_write_config16(dev, PCI_MEMORY_BASE, base >> 16); pci_write_config16(dev, PCI_MEMORY_LIMIT, end >> 16); - } - else if (resource->index == PCI_PREF_MEMORY_BASE) { - /* set the prefetchable memory range */ - compute_allocate_resource(&dev->link[0], resource, - IORESOURCE_MEM | IORESOURCE_PREFETCH, - IORESOURCE_MEM | IORESOURCE_PREFETCH); + } else if (resource->index == PCI_PREF_MEMORY_BASE) { + /* Set the prefetchable memory range. */ pci_write_config16(dev, PCI_PREF_MEMORY_BASE, base >> 16); pci_write_config32(dev, PCI_PREF_BASE_UPPER32, base >> 32); pci_write_config16(dev, PCI_PREF_MEMORY_LIMIT, end >> 16); pci_write_config32(dev, PCI_PREF_LIMIT_UPPER32, end >> 32); - } - else { - /* Don't let me think I stored the resource */ + } else { + /* Don't let me think I stored the resource. */ resource->flags &= ~IORESOURCE_STORED; printk_err("ERROR: invalid resource->index %lx\n", - resource->index); + resource->index); } report_resource_stored(dev, resource, ""); return; @@ -556,14 +562,14 @@ { struct resource *resource, *last; unsigned link; - uint8_t line; + u8 line; last = &dev->resource[dev->resources]; - for(resource = &dev->resource[0]; resource < last; resource++) { + for (resource = &dev->resource[0]; resource < last; resource++) { pci_set_resource(dev, resource); } - for(link = 0; link < dev->links; link++) { + for (link = 0; link < dev->links; link++) { struct bus *bus; bus = &dev->link[link]; if (bus->children) { @@ -571,60 +577,64 @@ } } - /* set a default latency timer */ + /* Set a default latency timer. */ pci_write_config8(dev, PCI_LATENCY_TIMER, 0x40); - /* set a default secondary latency timer */ + /* Set a default secondary latency timer. */ if ((dev->hdr_type & 0x7f) == PCI_HEADER_TYPE_BRIDGE) { pci_write_config8(dev, PCI_SEC_LATENCY_TIMER, 0x40); } - /* zero the irq settings */ + /* Zero the IRQ settings. */ line = pci_read_config8(dev, PCI_INTERRUPT_PIN); if (line) { pci_write_config8(dev, PCI_INTERRUPT_LINE, 0); } - /* set the cache line size, so far 64 bytes is good for everyone */ + /* Set the cache line size, so far 64 bytes is good for everyone. */ pci_write_config8(dev, PCI_CACHE_LINE_SIZE, 64 >> 2); } void pci_dev_enable_resources(struct device *dev) { const struct pci_operations *ops; - uint16_t command; + u16 command; - /* Set the subsystem vendor and device id for mainboard devices */ + /* Set the subsystem vendor and device id for mainboard devices. */ ops = ops_pci(dev); if (dev->on_mainboard && ops && ops->set_subsystem) { printk_debug("%s subsystem <- %02x/%02x\n", - dev_path(dev), - CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID, - CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID); + dev_path(dev), + CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID, + CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID); ops->set_subsystem(dev, - CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID, - CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID); + CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID, + CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID); } command = pci_read_config16(dev, PCI_COMMAND); command |= dev->command; + /* v3 has + * command |= (PCI_COMMAND_PARITY + PCI_COMMAND_SERR); // Error check. + */ printk_debug("%s cmd <- %02x\n", dev_path(dev), command); pci_write_config16(dev, PCI_COMMAND, command); } void pci_bus_enable_resources(struct device *dev) { - uint16_t ctrl; - /* enable IO in command register if there is VGA card - * connected with (even it does not claim IO resource) */ + u16 ctrl; + + /* Enable I/O in command register if there is VGA card + * connected with (even it does not claim I/O resource). + */ if (dev->link[0].bridge_ctrl & PCI_BRIDGE_CTL_VGA) dev->command |= PCI_COMMAND_IO; ctrl = pci_read_config16(dev, PCI_BRIDGE_CONTROL); ctrl |= dev->link[0].bridge_ctrl; - ctrl |= (PCI_BRIDGE_CTL_PARITY + PCI_BRIDGE_CTL_SERR); /* error check */ + ctrl |= (PCI_BRIDGE_CTL_PARITY + PCI_BRIDGE_CTL_SERR); /* Error check. */ printk_debug("%s bridge ctrl <- %04x\n", dev_path(dev), ctrl); pci_write_config16(dev, PCI_BRIDGE_CONTROL, ctrl); pci_dev_enable_resources(dev); - enable_childrens_resources(dev); } @@ -640,17 +650,17 @@ delay(1); } -void pci_dev_set_subsystem(device_t dev, unsigned vendor, unsigned device) +void pci_dev_set_subsystem(struct device *dev, unsigned vendor, unsigned device) { pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - ((device & 0xffff) << 16) | (vendor & 0xffff)); + ((device & 0xffff) << 16) | (vendor & 0xffff)); } /** default handler: only runs the relevant pci bios. */ void pci_dev_init(struct device *dev) { #if CONFIG_PCI_ROM_RUN == 1 || CONFIG_VGA_ROM_RUN == 1 - void run_bios(struct device * dev, unsigned long addr); + void run_bios(struct device *dev, unsigned long addr); struct rom_header *rom, *ram; #if CONFIG_PCI_ROM_RUN != 1 @@ -658,7 +668,7 @@ * is set but CONFIG_PCI_ROM_RUN is not. In this case we skip * all other option ROM types. */ - if ((dev->class>>8)!=PCI_CLASS_DISPLAY_VGA) + if ((dev->class >> 8) != PCI_CLASS_DISPLAY_VGA) return; #endif @@ -685,13 +695,13 @@ }; struct device_operations default_pci_ops_dev = { - .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, - .init = pci_dev_init, - .scan_bus = 0, - .enable = 0, - .ops_pci = &pci_dev_ops_pci, + .init = pci_dev_init, + .scan_bus = 0, + .enable = 0, + .ops_pci = &pci_dev_ops_pci, }; /** Default device operations for PCI bridges */ @@ -700,32 +710,29 @@ }; struct device_operations default_pci_ops_bus = { - .read_resources = pci_bus_read_resources, - .set_resources = pci_dev_set_resources, + .read_resources = pci_bus_read_resources, + .set_resources = pci_dev_set_resources, .enable_resources = pci_bus_enable_resources, - .init = 0, - .scan_bus = pci_scan_bridge, - .enable = 0, - .reset_bus = pci_bus_reset, - .ops_pci = &pci_bus_ops_pci, + .init = 0, + .scan_bus = pci_scan_bridge, + .enable = 0, + .reset_bus = pci_bus_reset, + .ops_pci = &pci_bus_ops_pci, }; /** * @brief Detect the type of downstream bridge * - * This function is a heuristic to detect which type - * of bus is downstream of a pci to pci bridge. This - * functions by looking for various capability blocks - * to figure out the type of downstream bridge. PCI-X - * PCI-E, and Hypertransport all seem to have appropriate - * capabilities. + * This function is a heuristic to detect which type of bus is downstream + * of a PCI-to-PCI bridge. This functions by looking for various capability + * blocks to figure out the type of downstream bridge. PCI-X, PCI-E, and + * Hypertransport all seem to have appropriate capabilities. * * When only a PCI-Express capability is found the type * is examined to see which type of bridge we have. * - * @param dev - * - * @return appropriate bridge operations + * @param dev Pointer to the device structure of the bridge. + * @return Appropriate bridge operations. */ static struct device_operations *get_pci_bridge_ops(device_t dev) { @@ -743,13 +750,13 @@ #endif #if CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT == 1 pos = 0; - while((pos = pci_find_next_capability(dev, PCI_CAP_ID_HT, pos))) { + while ((pos = pci_find_next_capability(dev, PCI_CAP_ID_HT, pos))) { unsigned flags; flags = pci_read_config16(dev, pos + PCI_CAP_FLAGS); if ((flags >> 13) == 1) { /* Host or Secondary Interface */ printk_debug("%s subbordinate bus Hypertransport\n", - dev_path(dev)); + dev_path(dev)); return &default_ht_ops_bus; } } @@ -759,16 +766,15 @@ if (pos) { unsigned flags; flags = pci_read_config16(dev, pos + PCI_EXP_FLAGS); - switch((flags & PCI_EXP_FLAGS_TYPE) >> 4) { + switch ((flags & PCI_EXP_FLAGS_TYPE) >> 4) { case PCI_EXP_TYPE_ROOT_PORT: case PCI_EXP_TYPE_UPSTREAM: case PCI_EXP_TYPE_DOWNSTREAM: printk_debug("%s subbordinate bus PCI Express\n", - dev_path(dev)); + dev_path(dev)); return &default_pciexp_ops_bus; case PCI_EXP_TYPE_PCI_BRIDGE: - printk_debug("%s subbordinate PCI\n", - dev_path(dev)); + printk_debug("%s subbordinate PCI\n", dev_path(dev)); return &default_pci_ops_bus; default: break; @@ -779,11 +785,10 @@ } /** - * @brief Set up PCI device operation + * Set up PCI device operation. Check if it already has a driver. If not, use + * find_device_operations, or set to a default based on type. * - * - * @param dev - * + * @param dev Pointer to the device whose pci_ops you want to set. * @see pci_drivers */ static void set_pci_ops(struct device *dev) @@ -794,23 +799,22 @@ } /* Look through the list of setup drivers and find one for - * this pci device + * this PCI device. */ - for(driver = &pci_drivers[0]; driver != &epci_drivers[0]; driver++) { + for (driver = &pci_drivers[0]; driver != &epci_drivers[0]; driver++) { if ((driver->vendor == dev->vendor) && - (driver->device == dev->device)) - { + (driver->device == dev->device)) { dev->ops = driver->ops; printk_spew("%s [%04x/%04x] %sops\n", - dev_path(dev), - driver->vendor, driver->device, - (driver->ops->scan_bus?"bus ":"")); + dev_path(dev), + driver->vendor, driver->device, + (driver->ops->scan_bus ? "bus " : "")); return; } } /* If I don't have a specific driver use the default operations */ - switch(dev->hdr_type & 0x7f) { /* header type */ + switch (dev->hdr_type & 0x7f) { /* header type */ case PCI_HEADER_TYPE_NORMAL: /* standard header */ if ((dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) goto bad; @@ -827,20 +831,18 @@ break; #endif default: - bad: + bad: if (dev->enabled) { printk_err("%s [%04x/%04x/%06x] has unknown header " - "type %02x, ignoring.\n", - dev_path(dev), - dev->vendor, dev->device, - dev->class >> 8, dev->hdr_type); + "type %02x, ignoring.\n", + dev_path(dev), + dev->vendor, dev->device, + dev->class >> 8, dev->hdr_type); } } return; } - - /** * @brief See if we have already allocated a device structure for a given devfn. * @@ -848,42 +850,43 @@ * device structure correspond to the devfn, if present. This function also * removes the device structure from the linked list. * - * @param list the device structure list - * @param devfn a device/function number + * @param list The device structure list. + * @param devfn A device/function number. * - * @return pointer to the device structure found or null of we have not + * @return Pointer to the device structure found or NULL if we have not * allocated a device for this devfn yet. */ static struct device *pci_scan_get_dev(struct device **list, unsigned int devfn) { struct device *dev; dev = 0; - for(; *list; list = &(*list)->sibling) { + for (; *list; list = &(*list)->sibling) { if ((*list)->path.type != DEVICE_PATH_PCI) { printk_err("child %s not a pci device\n", - dev_path(*list)); + dev_path(*list)); continue; } if ((*list)->path.pci.devfn == devfn) { - /* Unlink from the list */ + /* Unlink from the list. */ dev = *list; *list = (*list)->sibling; - dev->sibling = 0; + dev->sibling = NULL; break; } } - /* Just like alloc_dev add the device to the list of device on the bus. - * When the list of devices was formed we removed all of the parents - * children, and now we are interleaving static and dynamic devices in - * order on the bus. + + /* Just like alloc_dev() add the device to the list of devices on the + * bus. When the list of devices was formed we removed all of the + * parents children, and now we are interleaving static and dynamic + * devices in order on the bus. */ if (dev) { - device_t child; - /* Find the last child of our parent */ - for(child = dev->bus->children; child && child->sibling; ) { + struct device *child; + /* Find the last child of our parent. */ + for (child = dev->bus->children; child && child->sibling;) { child = child->sibling; } - /* Place the device on the list of children of it's parent. */ + /* Place the device on the list of children of its parent. */ if (child) { child->sibling = dev; } else { @@ -897,7 +900,8 @@ /** * @brief Scan a PCI bus. * - * Determine the existence of a given PCI device. + * Determine the existence of a given PCI device. Allocate a new struct device + * if dev==NULL was passed in and the device exists in hardware. * * @param bus pointer to the bus structure * @param devfn to look at @@ -905,107 +909,94 @@ * @return The device structure for hte device (if found) * or the NULL if no device is found. */ -device_t pci_probe_dev(device_t dev, struct bus *bus, unsigned devfn) +device_t pci_probe_dev(device_t dev, struct bus * bus, unsigned devfn) { - uint32_t id, class; - uint8_t hdr_type; + u32 id, class; + u8 hdr_type; - /* Detect if a device is present */ + /* Detect if a device is present. */ if (!dev) { struct device dummy; - dummy.bus = bus; - dummy.path.type = DEVICE_PATH_PCI; + dummy.bus = bus; + dummy.path.type = DEVICE_PATH_PCI; dummy.path.pci.devfn = devfn; id = pci_read_config32(&dummy, PCI_VENDOR_ID); - /* Have we found somthing? + /* Have we found something? * Some broken boards return 0 if a slot is empty. */ - if ( (id == 0xffffffff) || (id == 0x00000000) || - (id == 0x0000ffff) || (id == 0xffff0000)) - { + if ((id == 0xffffffff) || (id == 0x00000000) || + (id == 0x0000ffff) || (id == 0xffff0000)) { printk_spew("%s, bad id 0x%x\n", dev_path(&dummy), id); return NULL; } dev = alloc_dev(bus, &dummy.path); - } - else { - /* Enable/disable the device. Once we have - * found the device specific operations this - * operations we will disable the device with - * those as well. + } else { + /* Enable/disable the device. Once we have found the device- + * specific operations this operations we will disable the + * device with those as well. * * This is geared toward devices that have subfunctions * that do not show up by default. * * If a device is a stuff option on the motherboard - * it may be absent and enable_dev must cope. - * + * it may be absent and enable_dev() must cope. */ - /* Run the magice enable sequence for the device */ + /* Run the magic enable sequence for the device. */ if (dev->chip_ops && dev->chip_ops->enable_dev) { dev->chip_ops->enable_dev(dev); } - /* Now read the vendor and device id */ + /* Now read the vendor and device ID. */ id = pci_read_config32(dev, PCI_VENDOR_ID); - - /* If the device does not have a pci id disable it. - * Possibly this is because we have already disabled - * the device. But this also handles optional devices - * that may not always show up. + /* If the device does not have a PCI ID disable it. Possibly + * this is because we have already disabled the device. But + * this also handles optional devices that may not always + * show up. */ /* If the chain is fully enumerated quit */ - if ( (id == 0xffffffff) || (id == 0x00000000) || - (id == 0x0000ffff) || (id == 0xffff0000)) - { + if ((id == 0xffffffff) || (id == 0x00000000) || + (id == 0x0000ffff) || (id == 0xffff0000)) { if (dev->enabled) { printk_info("Disabling static device: %s\n", - dev_path(dev)); + dev_path(dev)); dev->enabled = 0; } return dev; } } - /* Read the rest of the pci configuration information */ + /* Read the rest of the PCI configuration information. */ hdr_type = pci_read_config8(dev, PCI_HEADER_TYPE); class = pci_read_config32(dev, PCI_CLASS_REVISION); - /* Store the interesting information in the device structure */ + /* Store the interesting information in the device structure. */ dev->vendor = id & 0xffff; dev->device = (id >> 16) & 0xffff; dev->hdr_type = hdr_type; - /* class code, the upper 3 bytes of PCI_CLASS_REVISION */ + + /* Class code, the upper 3 bytes of PCI_CLASS_REVISION. */ dev->class = class >> 8; - - /* Architectural/System devices always need to - * be bus masters. - */ + /* Architectural/System devices always need to be bus masters. */ if ((dev->class >> 16) == PCI_BASE_CLASS_SYSTEM) { dev->command |= PCI_COMMAND_MASTER; } - /* Look at the vendor and device id, or at least the - * header type and class and figure out which set of - * configuration methods to use. Unless we already - * have some pci ops. + /* Look at the vendor and device ID, or at least the header type and + * class and figure out which set of configuration methods to use. + * Unless we already have some PCI ops. */ set_pci_ops(dev); - /* Now run the magic enable/disable sequence for the device */ + /* Now run the magic enable/disable sequence for the device. */ if (dev->ops && dev->ops->enable) { dev->ops->enable(dev); } - - /* Display the device and error if we don't have some pci operations - * for it. - */ + /* Display the device. */ printk_debug("%s [%04x/%04x] %s%s\n", - dev_path(dev), - dev->vendor, dev->device, - dev->enabled?"enabled": "disabled", - dev->ops?"" : " No operations" - ); + dev_path(dev), + dev->vendor, dev->device, + dev->enabled ? "enabled" : "disabled", + dev->ops ? "" : " No operations"); return dev; } @@ -1027,73 +1018,69 @@ * @return The maximum bus number found, after scanning all subordinate busses */ unsigned int pci_scan_bus(struct bus *bus, - unsigned min_devfn, unsigned max_devfn, - unsigned int max) + unsigned min_devfn, unsigned max_devfn, + unsigned int max) { unsigned int devfn; - device_t old_devices; - device_t child; + struct device *old_devices; + struct device *child; #if CONFIG_PCI_BUS_SEGN_BITS - printk_debug("PCI: pci_scan_bus for bus %04x:%02x\n", bus->secondary >> 8, bus->secondary & 0xff); + printk_debug("PCI: pci_scan_bus for bus %04x:%02x\n", + bus->secondary >> 8, bus->secondary & 0xff); #else printk_debug("PCI: pci_scan_bus for bus %02x\n", bus->secondary); #endif old_devices = bus->children; - bus->children = 0; + bus->children = NULL; post_code(0x24); - /* probe all devices/functions on this bus with some optimization for - * non-existence and single funcion devices + /* Probe all devices/functions on this bus with some optimization for + * non-existence and single function devices. */ for (devfn = min_devfn; devfn <= max_devfn; devfn++) { - device_t dev; + struct device *dev; /* First thing setup the device structure */ dev = pci_scan_get_dev(&old_devices, devfn); - /* See if a device is present and setup the device - * structure. - */ + /* See if a device is present and setup the device structure. */ dev = pci_probe_dev(dev, bus, devfn); - /* if this is not a multi function device, - * or the device is not present don't waste - * time probing another function. + /* If this is not a multi function device, or the device is + * not present don't waste time probing another function. * Skip to next device. */ if ((PCI_FUNC(devfn) == 0x00) && - (!dev || (dev->enabled && ((dev->hdr_type & 0x80) != 0x80)))) - { + (!dev + || (dev->enabled && ((dev->hdr_type & 0x80) != 0x80)))) { devfn += 0x07; } } post_code(0x25); - /* Die if any left over static devices are are found. + /* Warn if any leftover static devices are are found. * There's probably a problem in the Config.lb. - */ - if(old_devices) { + */ + if (old_devices) { device_t left; - for(left = old_devices; left; left = left->sibling) { - printk_err("%s\n", dev_path(left)); + printk_warning("PCI: Left over static devices:\n"); + for (left = old_devices; left; left = left->sibling) { + printk_warning("%s\n", dev_path(left)); } - printk_warning("PCI: Left over static devices. Check your mainboard Config.lb\n"); + printk_warning("PCI: Check your mainboard Config.lb.\n"); } - /* For all children that implement scan_bus (i.e. bridges) + /* For all children that implement scan_bus() (i.e. bridges) * scan the bus behind that child. */ - for(child = bus->children; child; child = child->sibling) { + for (child = bus->children; child; child = child->sibling) { max = scan_bus(child, max); } - /* - * We've scanned the bus and so we know all about what's on - * the other side of any bridges that may be on this bus plus - * any devices. - * + /* We've scanned the bus and so we know all about what's on the other + * side of any bridges that may be on this bus plus any devices. * Return how far we've got finding sub-buses. */ printk_debug("PCI: pci_scan_bus returning with max=%03x\n", max); @@ -1101,7 +1088,6 @@ return max; } - /** * @brief Scan a PCI bridge and the buses behind the bridge. * @@ -1110,18 +1096,19 @@ * * This function is the default scan_bus() method for PCI bridge devices. * - * @param dev pointer to the bridge device - * @param max the highest bus number assgined up to now - * - * @return The maximum bus number found, after scanning all subordinate busses + * @param dev Pointer to the bridge device. + * @param max The highest bus number assigned up to now. + * @return The maximum bus number found, after scanning all subordinate buses. */ unsigned int do_pci_scan_bridge(struct device *dev, unsigned int max, - unsigned int (*do_scan_bus)(struct bus *bus, - unsigned min_devfn, unsigned max_devfn, unsigned int max)) + unsigned int (*do_scan_bus) (struct bus * bus, + unsigned min_devfn, + unsigned max_devfn, + unsigned int max)) { struct bus *bus; - uint32_t buses; - uint16_t cr; + u32 buses; + u16 cr; printk_spew("%s for %s\n", __func__, dev_path(dev)); @@ -1141,8 +1128,7 @@ pci_write_config16(dev, PCI_COMMAND, 0x0000); pci_write_config16(dev, PCI_STATUS, 0xffff); - /* - * Read the existing primary/secondary/subordinate bus + /* Read the existing primary/secondary/subordinate bus * number configuration. */ buses = pci_read_config32(dev, PCI_PRIMARY_BUS); @@ -1152,9 +1138,9 @@ * correctly configured. */ buses &= 0xff000000; - buses |= (((unsigned int) (dev->bus->secondary) << 0) | - ((unsigned int) (bus->secondary) << 8) | - ((unsigned int) (bus->subordinate) << 16)); + buses |= (((unsigned int)(dev->bus->secondary) << 0) | + ((unsigned int)(bus->secondary) << 8) | + ((unsigned int)(bus->subordinate) << 16)); pci_write_config32(dev, PCI_PRIMARY_BUS, buses); /* Now we can scan all subordinate buses @@ -1166,8 +1152,7 @@ * bus number to its real value. */ bus->subordinate = max; - buses = (buses & 0xff00ffff) | - ((unsigned int) (bus->subordinate) << 16); + buses = (buses & 0xff00ffff) | ((unsigned int)(bus->subordinate) << 16); pci_write_config32(dev, PCI_PRIMARY_BUS, buses); pci_write_config16(dev, PCI_COMMAND, cr); @@ -1183,90 +1168,109 @@ * * This function is the default scan_bus() method for PCI bridge devices. * - * @param dev pointer to the bridge device + * @param dev Pointer to the bridge device. + * @param max The highest bus number assigned up to now. + * @return The maximum bus number found, after scanning all subordinate buses. + */ +unsigned int pci_scan_bridge(struct device *dev, unsigned int max) +{ + return do_pci_scan_bridge(dev, max, pci_scan_bus); +} + +/** + * @brief Scan a PCI domain. + * + * This function is the default scan_bus() method for PCI domains. + * + * @param dev pointer to the domain * @param max the highest bus number assgined up to now * * @return The maximum bus number found, after scanning all subordinate busses */ -unsigned int pci_scan_bridge(struct device *dev, unsigned int max) +unsigned int pci_domain_scan_bus(device_t dev, unsigned int max) { - return do_pci_scan_bridge(dev, max, pci_scan_bus); + max = pci_scan_bus(&dev->link[0], PCI_DEVFN(0, 0), 0xff, max); + return max; } -/* - Tell the EISA int controller this int must be level triggered - THIS IS A KLUDGE -- sorry, this needs to get cleaned up. -*/ +/** + * Tell the EISA int controller this int must be level triggered. + * + * THIS IS A KLUDGE -- sorry, this needs to get cleaned up. + */ void pci_level_irq(unsigned char intNum) { - unsigned short intBits = inb(0x4d0) | (((unsigned) inb(0x4d1)) << 8); + unsigned short intBits = inb(0x4d0) | (((unsigned)inb(0x4d1)) << 8); printk_spew("%s: current ints are 0x%x\n", __func__, intBits); intBits |= (1 << intNum); printk_spew("%s: try to set ints 0x%x\n", __func__, intBits); - // Write new values - outb((unsigned char) intBits, 0x4d0); - outb((unsigned char) (intBits >> 8), 0x4d1); + /* Write new values. */ + outb((unsigned char)intBits, 0x4d0); + outb((unsigned char)(intBits >> 8), 0x4d1); - /* this seems like an error but is not ... */ -#if 1 + /* This seems like an error but is not. */ if (inb(0x4d0) != (intBits & 0xff)) { - printk_err("%s: lower order bits are wrong: want 0x%x, got 0x%x\n", - __func__, intBits &0xff, inb(0x4d0)); + printk_err( + "%s: lower order bits are wrong: want 0x%x, got 0x%x\n", + __func__, intBits & 0xff, inb(0x4d0)); } if (inb(0x4d1) != ((intBits >> 8) & 0xff)) { - printk_err("%s: lower order bits are wrong: want 0x%x, got 0x%x\n", - __func__, (intBits>>8) &0xff, inb(0x4d1)); + printk_err( + "%s: lower order bits are wrong: want 0x%x, got 0x%x\n", + __func__, (intBits >> 8) & 0xff, inb(0x4d1)); } -#endif } -/* - This function assigns IRQs for all functions contained within - the indicated device address. If the device does not exist or does - not require interrupts then this function has no effect. - - This function should be called for each PCI slot in your system. - - pIntAtoD is an array of IRQ #s that are assigned to PINTA through PINTD of - this slot. - The particular irq #s that are passed in depend on the routing inside - your southbridge and on your motherboard. - - -kevinh(a)ispiri.com +/** + * This function assigns IRQs for all functions contained within the + * indicated device address. If the device does not exist or does not + * require interrupts then this function has no effect. + * + * This function should be called for each PCI slot in your system. + * + * pIntAtoD is an array of IRQ #s that are assigned to PINTA through PINTD of + * this slot. + * + * The particular irq #s that are passed in depend on the routing inside + * your southbridge and on your motherboard. + * + * -kevinh(a)ispiri.com + * */ void pci_assign_irqs(unsigned bus, unsigned slot, - const unsigned char pIntAtoD[4]) + const unsigned char pIntAtoD[4]) { unsigned functNum; - device_t pdev; + struct device *pdev; unsigned char line; unsigned char irq; unsigned char readback; - /* Each slot may contain up to eight functions */ + /* Each slot may contain up to eight functions. */ for (functNum = 0; functNum < 8; functNum++) { pdev = dev_find_slot(bus, (slot << 3) + functNum); if (pdev) { - line = pci_read_config8(pdev, PCI_INTERRUPT_PIN); + line = pci_read_config8(pdev, PCI_INTERRUPT_PIN); - // PCI spec says all other values are reserved + /* PCI spec says all other values are reserved. */ if ((line >= 1) && (line <= 4)) { irq = pIntAtoD[line - 1]; - printk_debug("Assigning IRQ %d to %d:%x.%d\n", \ - irq, bus, slot, functNum); + printk_debug("Assigning IRQ %d to %d:%x.%d\n", + irq, bus, slot, functNum); - pci_write_config8(pdev, PCI_INTERRUPT_LINE,\ - pIntAtoD[line - 1]); + pci_write_config8(pdev, PCI_INTERRUPT_LINE, + pIntAtoD[line - 1]); - readback = pci_read_config8(pdev, PCI_INTERRUPT_LINE); + readback = + pci_read_config8(pdev, PCI_INTERRUPT_LINE); printk_debug(" Readback = %d\n", readback); - // Change to level triggered + // Change to level triggered. pci_level_irq(pIntAtoD[line - 1]); } } Modified: trunk/coreboot-v2/src/devices/root_device.c =================================================================== --- trunk/coreboot-v2/src/devices/root_device.c 2009-07-02 18:27:02 UTC (rev 4393) +++ trunk/coreboot-v2/src/devices/root_device.c 2009-07-02 18:56:24 UTC (rev 4394) @@ -34,29 +34,7 @@ */ void root_dev_read_resources(device_t root) { - struct resource *resource; - - /* Initialize the system wide io space constraints */ - resource = new_resource(root, 0); - resource->base = 0x400; - resource->size = 0; - resource->align = 0; - resource->gran = 0; - resource->limit = 0xffffUL; - resource->flags = IORESOURCE_IO; - compute_allocate_resource(&root->link[0], resource, - IORESOURCE_IO, IORESOURCE_IO); - - /* Initialize the system wide memory resources constraints */ - resource = new_resource(root, 1); - resource->base = 0; - resource->size = 0; - resource->align = 0; - resource->gran = 0; - resource->limit = 0xffffffffUL; - resource->flags = IORESOURCE_MEM; - compute_allocate_resource(&root->link[0], resource, - IORESOURCE_MEM, IORESOURCE_MEM); + printk_err("%s should never be called.\n", __func__); } /** @@ -68,14 +46,7 @@ */ void root_dev_set_resources(device_t root) { - struct bus *bus; - - bus = &root->link[0]; - compute_allocate_resource(bus, - &root->resource[0], IORESOURCE_IO, IORESOURCE_IO); - compute_allocate_resource(bus, - &root->resource[1], IORESOURCE_MEM, IORESOURCE_MEM); - assign_resources(bus); + printk_err("%s should never be called.\n", __func__); } /** Modified: trunk/coreboot-v2/src/include/device/device.h =================================================================== --- trunk/coreboot-v2/src/include/device/device.h 2009-07-02 18:27:02 UTC (rev 4393) +++ trunk/coreboot-v2/src/include/device/device.h 2009-07-02 18:56:24 UTC (rev 4394) @@ -69,17 +69,16 @@ unsigned int hdr_type; /* PCI header type */ unsigned int enabled : 1; /* set if we should enable the device */ unsigned int initialized : 1; /* set if we have initialized the device */ - unsigned int have_resources : 1; /* Set if we have read the devices resources */ unsigned int on_mainboard : 1; unsigned long rom_address; - uint8_t command; + u8 command; /* Base registers for this device. I/O, MEM and Expansion ROM */ struct resource resource[MAX_RESOURCES]; unsigned int resources; - /* link are (down stream) buses attached to the device, usually a leaf + /* links are (downstream) buses attached to the device, usually a leaf * device with no children have 0 buses attached and a bridge has 1 bus */ struct bus link[MAX_LINKS]; @@ -106,8 +105,6 @@ /* Generic device helper functions */ int reset_bus(struct bus *bus); unsigned int scan_bus(struct device *bus, unsigned int max); -void compute_allocate_resource(struct bus *bus, struct resource *bridge, - unsigned long type_mask, unsigned long type); void assign_resources(struct bus *bus); void enable_resources(struct device *dev); void enumerate_static_device(void); @@ -142,6 +139,8 @@ #define DEVICE_MEM_ALIGN 4096 extern struct device_operations default_dev_ops_root; +void pci_domain_read_resources(struct device *dev); +unsigned int pci_domain_scan_bus(struct device *dev, unsigned int max); void root_dev_read_resources(device_t dev); void root_dev_set_resources(device_t dev); unsigned int scan_static_bus(device_t bus, unsigned int max); Modified: trunk/coreboot-v2/src/include/device/resource.h =================================================================== --- trunk/coreboot-v2/src/include/device/resource.h 2009-07-02 18:27:02 UTC (rev 4393) +++ trunk/coreboot-v2/src/include/device/resource.h 2009-07-02 18:56:24 UTC (rev 4394) @@ -1,5 +1,5 @@ -#ifndef RESOURCE_H -#define RESOURCE_H +#ifndef DEVICE_RESOURCE_H +#define DEVICE_RESOURCE_H #include <stdint.h> @@ -19,6 +19,7 @@ #define IORESOURCE_SUBTRACTIVE 0x00040000 /* This resource filters all of the unclaimed transactions * to the bus below. */ +#define IORESOURCE_BRIDGE 0x00080000 /* The IO resource has a bus below it. */ #define IORESOURCE_STORED 0x20000000 /* The IO resource assignment has been stored in the device */ #define IORESOURCE_ASSIGNED 0x40000000 /* An IO resource that has been assigned a value */ #define IORESOURCE_FIXED 0x80000000 /* An IO resource the allocator must not change */ @@ -62,7 +63,7 @@ #define IORESOURCE_MEM_EXPANSIONROM (1<<6) -typedef uint64_t resource_t; +typedef u64 resource_t; struct resource { resource_t base; /* Base address of the resource */ resource_t size; /* Size of the resource */ @@ -74,10 +75,14 @@ /* Alignment must be >= the granularity of the resource */ }; -/* Macros to generate index values for subtractive resources */ +/* Macros to generate index values for resources */ #define IOINDEX_SUBTRACTIVE(IDX,LINK) (0x10000000 + ((IDX) << 8) + LINK) #define IOINDEX_SUBTRACTIVE_LINK(IDX) (IDX & 0xff) +#define IOINDEX(IDX,LINK) (((LINK) << 16) + IDX) +#define IOINDEX_LINK(IDX) (( IDX & 0xf0000) >> 16) +#define IOINDEX_IDX(IDX) (IDX & 0xffff) + /* Generic resource helper functions */ struct device; struct bus; @@ -101,4 +106,4 @@ #define RESOURCE_TYPE_MAX 20 extern const char *resource_type(struct resource *resource); -#endif /* RESOURCE_H */ +#endif /* DEVICE_RESOURCE_H */ Modified: trunk/coreboot-v2/src/northbridge/amd/amdfam10/northbridge.c =================================================================== --- trunk/coreboot-v2/src/northbridge/amd/amdfam10/northbridge.c 2009-07-02 18:27:02 UTC (rev 4393) +++ trunk/coreboot-v2/src/northbridge/amd/amdfam10/northbridge.c 2009-07-02 18:56:24 UTC (rev 4394) @@ -341,7 +341,7 @@ if (!dev) continue; for(link = 0; !res && (link < 8); link++) { - res = probe_resource(dev, 0x1000 + reg + (link<<16)); // 8 links, 0x1000 man f1, + res = probe_resource(dev, IOINDEX(0x1000 + reg, link)); } } result = 2; @@ -385,7 +385,7 @@ reg = 0x110+ (index<<24) + (4<<20); // index could be 0, 255 } - resource = new_resource(dev, 0x1000 + reg + (link<<16)); + resource = new_resource(dev, IOINDEX(0x1000 + reg, link)); return resource; } @@ -421,7 +421,7 @@ reg = 0x110+ (index<<24) + (6<<20); // index could be 0, 63 } - resource = new_resource(dev, 0x1000 + reg + (link<<16)); + resource = new_resource(dev, IOINDEX(0x1000 + reg, link)); return resource; } @@ -447,8 +447,6 @@ resource->gran = align; resource->limit = 0xffffUL; resource->flags = IORESOURCE_IO; - compute_allocate_resource(&dev->link[link], resource, - IORESOURCE_IO, IORESOURCE_IO); } /* Initialize the prefetchable memory constraints on the current bus */ @@ -460,9 +458,6 @@ resource->gran = log2(HT_MEM_HOST_ALIGN); resource->limit = 0xffffffffffULL; resource->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH; - compute_allocate_resource(&dev->link[link], resource, - IORESOURCE_MEM | IORESOURCE_PREFETCH, - IORESOURCE_MEM | IORESOURCE_PREFETCH); #if CONFIG_EXT_CONF_SUPPORT == 1 if((resource->index & 0x1fff) == 0x1110) { // ext @@ -481,9 +476,6 @@ resource->gran = log2(HT_MEM_HOST_ALIGN); resource->limit = 0xffffffffffULL; resource->flags = IORESOURCE_MEM; - compute_allocate_resource(&dev->link[link], resource, - IORESOURCE_MEM | IORESOURCE_PREFETCH, - IORESOURCE_MEM); #if CONFIG_EXT_CONF_SUPPORT == 1 if((resource->index & 0x1fff) == 0x1110) { // ext @@ -541,19 +533,14 @@ /* Get the register and link */ reg = resource->index & 0xfff; // 4k - link = ( resource->index>> 16)& 0x7; // 8 links + link = IOINDEX_LINK(resource->index); if (resource->flags & IORESOURCE_IO) { - compute_allocate_resource(&dev->link[link], resource, - IORESOURCE_IO, IORESOURCE_IO); set_io_addr_reg(dev, nodeid, link, reg, rbase>>8, rend>>8); store_conf_io_addr(nodeid, link, reg, (resource->index >> 24), rbase>>8, rend>>8); } else if (resource->flags & IORESOURCE_MEM) { - compute_allocate_resource(&dev->link[link], resource, - IORESOURCE_MEM | IORESOURCE_PREFETCH, - resource->flags & (IORESOURCE_MEM | IORESOURCE_PREFETCH)); set_mmio_addr_reg(nodeid, link, reg, (resource->index >>24), rbase>>8, rend>>8, sysconf.nodes) ;// [39:8] store_conf_mmio_addr(nodeid, link, reg, (resource->index >>24), rbase>>8, rend>>8); } @@ -657,7 +644,7 @@ .enable_dev = 0, }; -static void pci_domain_read_resources(device_t dev) +static void amdfam10_domain_read_resources(device_t dev) { struct resource *resource; unsigned reg; @@ -672,20 +659,20 @@ /* Is this register allocated? */ if ((base & 3) != 0) { unsigned nodeid, link; - device_t dev; + device_t reg_dev; if(reg<0xc0) { // mmio nodeid = (limit & 0xf) + (base&0x30); } else { // io nodeid = (limit & 0xf) + ((base>>4)&0x30); } link = (limit >> 4) & 7; - dev = __f0_dev[nodeid]; - if (dev) { - /* Reserve the resource */ - struct resource *resource; - resource = new_resource(dev, 0x1000 + reg + (link<<16)); - if (resource) { - resource->flags = 1; + reg_dev = __f0_dev[nodeid]; + if (reg_dev) { + /* Reserve the resource */ + struct resource *reg_resource; + reg_resource = new_resource(reg_dev, IOINDEX(0x1000 + reg, link)); + if (reg_resource) { + reg_resource->flags = 1; } } } @@ -711,24 +698,16 @@ resource->base = 0x400; resource->limit = 0xffffUL; resource->flags = IORESOURCE_IO; - compute_allocate_resource(&dev->link[link], resource, - IORESOURCE_IO, IORESOURCE_IO); /* Initialize the system wide prefetchable memory resources constraints */ resource = new_resource(dev, 1|(link<<2)); resource->limit = 0xfcffffffffULL; resource->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH; - compute_allocate_resource(&dev->link[link], resource, - IORESOURCE_MEM | IORESOURCE_PREFETCH, - IORESOURCE_MEM | IORESOURCE_PREFETCH); /* Initialize the system wide memory resources constraints */ resource = new_resource(dev, 2|(link<<2)); resource->limit = 0xfcffffffffULL; resource->flags = IORESOURCE_MEM; - compute_allocate_resource(&dev->link[link], resource, - IORESOURCE_MEM | IORESOURCE_PREFETCH, - IORESOURCE_MEM); } #endif } @@ -770,10 +749,6 @@ return tolm; } -#if CONFIG_PCI_64BIT_PREF_MEM == 1 -#define BRIDGE_IO_MASK (IORESOURCE_IO | IORESOURCE_MEM | IORESOURCE_PREFETCH) -#endif - #if CONFIG_HW_MEM_HOLE_SIZEK != 0 struct hw_mem_hole_info { @@ -980,9 +955,6 @@ resource->flags |= IORESOURCE_ASSIGNED; resource->flags &= ~IORESOURCE_STORED; link = (resource>>2) & 3; - compute_allocate_resource(&dev->link[link], resource, - BRIDGE_IO_MASK, resource->flags & BRIDGE_IO_MASK); - resource->flags |= IORESOURCE_STORED; report_resource_stored(dev, resource, ""); @@ -1142,7 +1114,7 @@ } } -static u32 pci_domain_scan_bus(device_t dev, u32 max) +static u32 amdfam10_domain_scan_bus(device_t dev, u32 max) { u32 reg; int i; @@ -1192,11 +1164,11 @@ } static struct device_operations pci_domain_ops = { - .read_resources = pci_domain_read_resources, + .read_resources = amdfam10_domain_read_resources, .set_resources = pci_domain_set_resources, .enable_resources = enable_childrens_resources, .init = 0, - .scan_bus = pci_domain_scan_bus, + .scan_bus = amdfam10_domain_scan_bus, #if CONFIG_MMCONF_SUPPORT_DEFAULT .ops_pci_bus = &pci_ops_mmconf, #else Modified: trunk/coreboot-v2/src/northbridge/amd/amdk8/misc_control.c =================================================================== --- trunk/coreboot-v2/src/northbridge/amd/amdk8/misc_control.c 2009-07-02 18:27:02 UTC (rev 4393) +++ trunk/coreboot-v2/src/northbridge/amd/amdk8/misc_control.c 2009-07-02 18:56:24 UTC (rev 4394) @@ -53,7 +53,7 @@ if (iommu) { /* Add a Gart apeture resource */ resource = new_resource(dev, 0x94); - resource->size = iommu?CONFIG_AGP_APERTURE_SIZE:1; + resource->size = CONFIG_AGP_APERTURE_SIZE; resource->align = log2(resource->size); resource->gran = log2(resource->size); resource->limit = 0xffffffff; /* 4G */ Modified: trunk/coreboot-v2/src/northbridge/amd/amdk8/northbridge.c =================================================================== --- trunk/coreboot-v2/src/northbridge/amd/amdk8/northbridge.c 2009-07-02 18:27:02 UTC (rev 4393) +++ trunk/coreboot-v2/src/northbridge/amd/amdk8/northbridge.c 2009-07-02 18:56:24 UTC (rev 4394) @@ -297,7 +297,7 @@ if (!dev) continue; for(link = 0; !res && (link < 3); link++) { - res = probe_resource(dev, 0x100 + (reg | link)); + res = probe_resource(dev, IOINDEX(0x100 + reg, link)); } } result = 2; @@ -335,7 +335,7 @@ reg = free_reg; } if (reg > 0) { - resource = new_resource(dev, 0x100 + (reg | link)); + resource = new_resource(dev, IOINDEX(0x100 + reg, link)); } return resource; } @@ -362,7 +362,7 @@ reg = free_reg; } if (reg > 0) { - resource = new_resource(dev, 0x100 + (reg | link)); + resource = new_resource(dev, IOINDEX(0x100 + reg, link)); } return resource; } @@ -379,9 +379,7 @@ resource->align = log2(HT_IO_HOST_ALIGN); resource->gran = log2(HT_IO_HOST_ALIGN); resource->limit = 0xffffUL; - resource->flags = IORESOURCE_IO; - compute_allocate_resource(&dev->link[link], resource, - IORESOURCE_IO, IORESOURCE_IO); + resource->flags = IORESOURCE_IO | IORESOURCE_BRIDGE; } /* Initialize the prefetchable memory constraints on the current bus */ @@ -393,9 +391,9 @@ resource->gran = log2(HT_MEM_HOST_ALIGN); resource->limit = 0xffffffffffULL; resource->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH; - compute_allocate_resource(&dev->link[link], resource, - IORESOURCE_MEM | IORESOURCE_PREFETCH, - IORESOURCE_MEM | IORESOURCE_PREFETCH); +#ifdef CONFIG_PCI_64BIT_PREF_MEM + resource->flags |= IORESOURCE_BRIDGE; +#endif } /* Initialize the memory constraints on the current bus */ @@ -405,11 +403,8 @@ resource->size = 0; resource->align = log2(HT_MEM_HOST_ALIGN); resource->gran = log2(HT_MEM_HOST_ALIGN); - resource->limit = 0xffffffffffULL; - resource->flags = IORESOURCE_MEM; - compute_allocate_resource(&dev->link[link], resource, - IORESOURCE_MEM | IORESOURCE_PREFETCH, - IORESOURCE_MEM); + resource->limit = 0xffffffffULL; + resource->flags = IORESOURCE_MEM | IORESOURCE_BRIDGE; } } @@ -432,11 +427,15 @@ /* Make certain the resource has actually been set */ if (!(resource->flags & IORESOURCE_ASSIGNED)) { + printk_err("%s: can't set unassigned resource @%lx %lx\n", + __func__, resource->index, resource->flags); return; } /* If I have already stored this resource don't worry about it */ if (resource->flags & IORESOURCE_STORED) { + printk_err("%s: can't set stored resource @%lx %lx\n", __func__, + resource->index, resource->flags); return; } @@ -448,6 +447,10 @@ if (resource->index < 0x100) { return; } + + if (resource->size == 0) + return; + /* Get the base address */ rbase = resource->base; @@ -456,12 +459,10 @@ /* Get the register and link */ reg = resource->index & 0xfc; - link = resource->index & 3; + link = IOINDEX_LINK(resource->index); if (resource->flags & IORESOURCE_IO) { uint32_t base, limit; - compute_allocate_resource(&dev->link[link], resource, - IORESOURCE_IO, IORESOURCE_IO); base = f1_read_config32(reg); limit = f1_read_config32(reg + 0x4); base &= 0xfe000fcc; @@ -486,9 +487,6 @@ } else if (resource->flags & IORESOURCE_MEM) { uint32_t base, limit; - compute_allocate_resource(&dev->link[link], resource, - IORESOURCE_MEM | IORESOURCE_PREFETCH, - resource->flags & (IORESOURCE_MEM | IORESOURCE_PREFETCH)); base = f1_read_config32(reg); limit = f1_read_config32(reg + 0x4); base &= 0x000000f0; @@ -634,7 +632,7 @@ .enable_dev = 0, }; -static void pci_domain_read_resources(device_t dev) +static void amdk8_domain_read_resources(device_t dev) { struct resource *resource; unsigned reg; @@ -655,48 +653,21 @@ if (reg_dev) { /* Reserve the resource */ struct resource *reg_resource; - reg_resource = new_resource(reg_dev, 0x100 + (reg | link)); + reg_resource = new_resource(reg_dev, IOINDEX(0x100 + reg, link)); if (reg_resource) { reg_resource->flags = 1; } } } } -#if CONFIG_PCI_64BIT_PREF_MEM == 0 - /* Initialize the system wide io space constraints */ - resource = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0)); - resource->base = 0x400; - resource->limit = 0xffffUL; - resource->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED; - /* Initialize the system wide memory resources constraints */ - resource = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0)); - resource->limit = 0xfcffffffffULL; - resource->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED; -#else - /* Initialize the system wide io space constraints */ - resource = new_resource(dev, 0); - resource->base = 0x400; - resource->limit = 0xffffUL; - resource->flags = IORESOURCE_IO; - compute_allocate_resource(&dev->link[0], resource, - IORESOURCE_IO, IORESOURCE_IO); + pci_domain_read_resources(dev); +#if CONFIG_PCI_64BIT_PREF_MEM == 1 /* Initialize the system wide prefetchable memory resources constraints */ - resource = new_resource(dev, 1); - resource->limit = 0xfcffffffffULL; - resource->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH; - compute_allocate_resource(&dev->link[0], resource, - IORESOURCE_MEM | IORESOURCE_PREFETCH, - IORESOURCE_MEM | IORESOURCE_PREFETCH); - - /* Initialize the system wide memory resources constraints */ resource = new_resource(dev, 2); resource->limit = 0xfcffffffffULL; - resource->flags = IORESOURCE_MEM; - compute_allocate_resource(&dev->link[0], resource, - IORESOURCE_MEM | IORESOURCE_PREFETCH, - IORESOURCE_MEM); + resource->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH; #endif } @@ -739,10 +710,6 @@ return tolm; } -#if CONFIG_PCI_64BIT_PREF_MEM == 1 -#define BRIDGE_IO_MASK (IORESOURCE_IO | IORESOURCE_MEM | IORESOURCE_PREFETCH) -#endif - #if CONFIG_HW_MEM_HOLE_SIZEK != 0 struct hw_mem_hole_info { @@ -898,7 +865,7 @@ extern uint64_t high_tables_base, high_tables_size; #endif -static void pci_domain_set_resources(device_t dev) +static void amdk8_domain_set_resources(device_t dev) { #if CONFIG_PCI_64BIT_PREF_MEM == 1 struct resource *io, *mem1, *mem2; @@ -964,13 +931,7 @@ last = &dev->resource[dev->resources]; for(resource = &dev->resource[0]; resource < last; resource++) { -#if 1 resource->flags |= IORESOURCE_ASSIGNED; - resource->flags &= ~IORESOURCE_STORED; -#endif - compute_allocate_resource(&dev->link[0], resource, - BRIDGE_IO_MASK, resource->flags & BRIDGE_IO_MASK); - resource->flags |= IORESOURCE_STORED; report_resource_stored(dev, resource, ""); @@ -1125,7 +1086,7 @@ } -static unsigned int pci_domain_scan_bus(device_t dev, unsigned int max) +static unsigned int amdk8_domain_scan_bus(device_t dev, unsigned int max) { unsigned reg; int i; @@ -1160,11 +1121,11 @@ } static struct device_operations pci_domain_ops = { - .read_resources = pci_domain_read_resources, - .set_resources = pci_domain_set_resources, + .read_resources = amdk8_domain_read_resources, + .set_resources = amdk8_domain_set_resources, .enable_resources = enable_childrens_resources, .init = 0, - .scan_bus = pci_domain_scan_bus, + .scan_bus = amdk8_domain_scan_bus, .ops_pci_bus = &pci_cf8_conf1, }; Modified: trunk/coreboot-v2/src/northbridge/amd/gx1/northbridge.c =================================================================== --- trunk/coreboot-v2/src/northbridge/amd/gx1/northbridge.c 2009-07-02 18:27:02 UTC (rev 4393) +++ trunk/coreboot-v2/src/northbridge/amd/gx1/northbridge.c 2009-07-02 18:56:24 UTC (rev 4394) @@ -66,27 +66,6 @@ .device = PCI_DEVICE_ID_CYRIX_PCI_MASTER, }; - - -#define BRIDGE_IO_MASK (IORESOURCE_IO | IORESOURCE_MEM) - -static void pci_domain_read_resources(device_t dev) -{ - struct resource *resource; - - printk_spew("%s:%s()\n", NORTHBRIDGE_FILE, __func__); - - /* Initialize the system wide io space constraints */ - resource = new_resource(dev, IOINDEX_SUBTRACTIVE(0,0)); - resource->limit = 0xffffUL; - resource->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED; - - /* Initialize the system wide memory resources constraints */ - resource = new_resource(dev, IOINDEX_SUBTRACTIVE(1,0)); - resource->limit = 0xffffffffULL; - resource->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED; -} - static void ram_resource(device_t dev, unsigned long index, unsigned long basek, unsigned long sizek) { @@ -187,12 +166,6 @@ assign_resources(&dev->link[0]); } -static unsigned int pci_domain_scan_bus(device_t dev, unsigned int max) -{ - max = pci_scan_bus(&dev->link[0], PCI_DEVFN(0, 0), 0xff, max); - return max; -} - static struct device_operations pci_domain_ops = { .read_resources = pci_domain_read_resources, .set_resources = pci_domain_set_resources, Modified: trunk/coreboot-v2/src/northbridge/amd/gx2/northbridge.c =================================================================== --- trunk/coreboot-v2/src/northbridge/amd/gx2/northbridge.c 2009-07-02 18:27:02 UTC (rev 4393) +++ trunk/coreboot-v2/src/northbridge/amd/gx2/northbridge.c 2009-07-02 18:56:24 UTC (rev 4394) @@ -356,25 +356,6 @@ .device = PCI_DEVICE_ID_NS_GX2, }; -#define BRIDGE_IO_MASK (IORESOURCE_IO | IORESOURCE_MEM) - -static void pci_domain_read_resources(device_t dev) -{ - struct resource *resource; - - printk_spew("%s:%s()\n", NORTHBRIDGE_FILE, __func__); - - /* Initialize the system wide io space constraints */ - resource = new_resource(dev, IOINDEX_SUBTRACTIVE(0,0)); - resource->limit = 0xffffUL; - resource->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED; - - /* Initialize the system wide memory resources constraints */ - resource = new_resource(dev, IOINDEX_SUBTRACTIVE(1,0)); - resource->limit = 0xffffffffULL; - resource->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED; -} - static void ram_resource(device_t dev, unsigned long index, unsigned long basek, unsigned long sizek) { @@ -468,12 +449,6 @@ assign_resources(&dev->link[0]); } -static unsigned int pci_domain_scan_bus(device_t dev, unsigned int max) -{ - max = pci_scan_bus(&dev->link[0], PCI_DEVFN(0, 0), 0xff, max); - return max; -} - static struct device_operations pci_domain_ops = { .read_resources = pci_domain_read_resources, .set_resources = pci_domain_set_resources, Modified: trunk/coreboot-v2/src/northbridge/amd/lx/northbridge.c =================================================================== --- trunk/coreboot-v2/src/northbridge/amd/lx/northbridge.c 2009-07-02 18:27:02 UTC (rev 4393) +++ trunk/coreboot-v2/src/northbridge/amd/lx/northbridge.c 2009-07-02 18:56:24 UTC (rev 4394) @@ -74,8 +74,6 @@ #define IOD_BM(msr, pdid1, bizarro, ibase, imask) {msr, {.hi=(pdid1<<29)|(bizarro<<28)|(ibase>>12), .lo=(ibase<<20)|imask}} #define IOD_SC(msr, pdid1, bizarro, en, wen, ren, ibase) {msr, {.hi=(pdid1<<29)|(bizarro<<28), .lo=(en<<24)|(wen<<21)|(ren<<20)|(ibase<<3)}} -#define BRIDGE_IO_MASK (IORESOURCE_IO | IORESOURCE_MEM) - extern void graphics_init(void); extern void cpubug(void); extern void chipsetinit(void); @@ -382,24 +380,6 @@ .device = PCI_DEVICE_ID_AMD_LXBRIDGE, }; -static void pci_domain_read_resources(device_t dev) -{ - struct resource *resource; - printk_spew(">> Entering northbridge.c: %s\n", __func__); - - /* Initialize the system wide io space constraints */ - resource = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0)); - resource->limit = 0xffffUL; - resource->flags = - IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED; - - /* Initialize the system wide memory resources constraints */ - resource = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0)); - resource->limit = 0xffffffffULL; - resource->flags = - IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED; -} - static void ram_resource(device_t dev, unsigned long index, unsigned long basek, unsigned long sizek) { @@ -470,14 +450,6 @@ pci_set_method(dev); } -static unsigned int pci_domain_scan_bus(device_t dev, unsigned int max) -{ - printk_spew(">> Entering northbridge.c: %s\n", __func__); - - max = pci_scan_bus(&dev->link[0], PCI_DEVFN(0, 0), 0xff, max); - return max; -} - static struct device_operations pci_domain_ops = { .read_resources = pci_domain_read_resources, .set_resources = pci_domain_set_resources, Modified: trunk/coreboot-v2/src/northbridge/ibm/cpc710/cpc710_northbridge.c =================================================================== --- trunk/coreboot-v2/src/northbridge/ibm/cpc710/cpc710_northbridge.c 2009-07-02 18:27:02 UTC (rev 4393) +++ trunk/coreboot-v2/src/northbridge/ibm/cpc710/cpc710_northbridge.c 2009-07-02 18:56:24 UTC (rev 4394) @@ -9,23 +9,6 @@ #include <cpu/cpu.h> #include "chip.h" -static void pci_domain_read_resources(device_t dev) -{ - struct resource *resource; - - /* Initialize the system wide io space constraints */ - resource = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0)); - resource->base = 0; - resource->limit = 0xffffUL; - resource->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED; - - /* Initialize the system wide memory resources constraints */ - resource = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0)); - resource->base = 0x80000000ULL; - resource->limit = 0xfeffffffULL; /* We can put pci resources in the system controll area */ - resource->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED; -} - static void ram_resource(device_t dev, unsigned long index, unsigned long basek, unsigned long sizek) { @@ -53,13 +36,6 @@ assign_resources(&dev->link[0]); } - -static unsigned int pci_domain_scan_bus(device_t dev, unsigned int max) -{ - max = pci_scan_bus(&dev->link[0], PCI_DEVFN(0, 0), 0xff, max); - return max; -} - static struct device_operations pci_domain_ops = { .read_resources = pci_domain_read_resources, .set_resources = pci_domain_set_resources, Modified: trunk/coreboot-v2/src/northbridge/ibm/cpc925/cpc925_northbridge.c =================================================================== --- trunk/coreboot-v2/src/northbridge/ibm/cpc925/cpc925_northbridge.c 2009-07-02 18:27:02 UTC (rev 4393) +++ trunk/coreboot-v2/src/northbridge/ibm/cpc925/cpc925_northbridge.c 2009-07-02 18:56:24 UTC (rev 4394) @@ -9,23 +9,6 @@ #include <cpu/cpu.h> #include "chip.h" -static void pci_domain_read_resources(device_t dev) -{ - struct resource *resource; - - /* Initialize the system wide io space constraints */ - resource = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0)); - resource->base = 0; - resource->limit = 0xffffUL; - resource->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED; - - /* Initialize the system wide memory resources constraints */ - resource = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0)); - resource->base = 0x80000000ULL; - resource->limit = 0xfeffffffULL; /* We can put pci resources in the system controll area */ - resource->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED; -} - static void ram_resource(device_t dev, unsigned long index, unsigned long basek, unsigned long sizek) { @@ -53,13 +36,6 @@ assign_resources(&dev->link[0]); } - -static unsigned int pci_domain_scan_bus(device_t dev, unsigned int max) -{ - max = pci_scan_bus(&dev->link[0], PCI_DEVFN(0, 0), 0xff, max); - return max; -} - static struct device_operations pci_domain_ops = { .read_resources = pci_domain_read_resources, .set_resources = pci_domain_set_resources, Modified: trunk/coreboot-v2/src/northbridge/intel/e7501/northbridge.c =================================================================== --- trunk/coreboot-v2/src/northbridge/intel/e7501/northbridge.c 2009-07-02 18:27:02 UTC (rev 4393) +++ trunk/coreboot-v2/src/northbridge/intel/e7501/northbridge.c 2009-07-02 18:56:24 UTC (rev 4394) @@ -9,23 +9,6 @@ #include <bitops.h> #include "chip.h" -static void pci_domain_read_resources(device_t dev) -{ - struct resource *resource; - unsigned reg; - - /* Initialize the system wide io space constraints */ - resource = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0)); - resource->base = 0x400; //yhlu - resource->limit = 0xffffUL; - resource->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED; - - /* Initialize the system wide memory resources constraints */ - resource = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0)); - resource->limit = 0xffffffffULL; - resource->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED; -} - static void ram_resource(device_t dev, unsigned long index, unsigned long basek, unsigned long sizek) { @@ -155,12 +138,6 @@ assign_resources(&dev->link[0]); } -static unsigned int pci_domain_scan_bus(device_t dev, unsigned int max) -{ - max = pci_scan_bus(&dev->link[0], PCI_DEVFN(0, 0), 0xff, max); - return max; -} - static struct device_operations pci_domain_ops = { .read_resources = pci_domain_read_resources, .set_resources = pci_domain_set_resources, Modified: trunk/coreboot-v2/src/northbridge/intel/e7520/northbridge.c =================================================================== --- trunk/coreboot-v2/src/northbridge/intel/e7520/northbridge.c 2009-07-02 18:27:02 UTC (rev 4393) +++ trunk/coreboot-v2/src/northbridge/intel/e7520/northbridge.c 2009-07-02 18:56:24 UTC (rev 4394) @@ -28,30 +28,6 @@ IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; } - -static void pci_domain_read_resources(device_t dev) -{ - struct resource *resource; - - /* Initialize the system wide io space constraints */ - resource = new_resource(dev, IOINDEX_SUBTRACTIVE(0,0)); - resource->base = 0; - resource->size = 0; - resource->align = 0; - resource->gran = 0; - resource->limit = 0xffffUL; - resource->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED; - - /* Initialize the system wide memory resources constraints */ - resource = new_resource(dev, IOINDEX_SUBTRACTIVE(1,0)); - resource->base = 0; - resource->size = 0; - resource->align = 0; - resource->gran = 0; - resource->limit = 0xffffffffUL; - resource->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED; -} - static void tolm_test(void *gp, struct device *dev, struct resource *new) { struct resource **best_p = gp; @@ -90,7 +66,7 @@ #if 1 printk_debug("PCI mem marker = %x\n", pci_tolm); -#endif +#endif /* FIXME Me temporary hack */ if(pci_tolm > 0xe0000000) pci_tolm = 0xe0000000; @@ -122,7 +98,7 @@ remapbasek = 0x3ff << 16; remaplimitk = 0 << 16; remapoffsetk = 0 << 16; - } + } else { /* The PCI memory hole overlaps memory * setup the remap window. @@ -165,7 +141,7 @@ ram_resource(dev, 5, 4096*1024, tomk - 4*1024*1024); } if (remaplimitk >= remapbasek) { - ram_resource(dev, 6, remapbasek, + ram_resource(dev, 6, remapbasek, (remaplimitk + 64*1024) - remapbasek); } @@ -178,13 +154,10 @@ assign_resources(&dev->link[0]); } -static unsigned int pci_domain_scan_bus(device_t dev, unsigned int max) +static u32 e7520_domain_scan_bus(device_t dev, u32 max) { - max = pci_scan_bus(&dev->link[0], 0, 0xff, max); - if (max > max_bus) { - max_bus = max; - } - return max; + max_bus = pci_domain_scan_bus(dev, max); + return max_bus; } static struct device_operations pci_domain_ops = { @@ -192,7 +165,7 @@ .set_resources = pci_domain_set_resources, .enable_resources = enable_childrens_resources, .init = 0, - .scan_bus = pci_domain_scan_bus, + .scan_bus = e7520_domain_scan_bus, .ops_pci_bus = &pci_cf8_conf1, /* Do we want to use the memory mapped space here? */ }; Modified: trunk/coreboot-v2/src/northbridge/intel/e7525/northbridge.c =================================================================== --- trunk/coreboot-v2/src/northbridge/intel/e7525/northbridge.c 2009-07-02 18:27:02 UTC (rev 4393) +++ trunk/coreboot-v2/src/northbridge/intel/e7525/northbridge.c 2009-07-02 18:56:24 UTC (rev 4394) @@ -28,30 +28,6 @@ IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; } - -static void pci_domain_read_resources(device_t dev) -{ - struct resource *resource; - - /* Initialize the system wide io space constraints */ - resource = new_resource(dev, IOINDEX_SUBTRACTIVE(0,0)); - resource->base = 0; - resource->size = 0; - resource->align = 0; - resource->gran = 0; - resource->limit = 0xffffUL; - resource->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED; - - /* Initialize the system wide memory resources constraints */ - resource = new_resource(dev, IOINDEX_SUBTRACTIVE(1,0)); - resource->base = 0; - resource->size = 0; - resource->align = 0; - resource->gran = 0; - resource->limit = 0xffffffffUL; - resource->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED; -} - static void tolm_test(void *gp, struct device *dev, struct resource *new) { struct resource **best_p = gp; @@ -90,7 +66,7 @@ #if 1 printk_debug("PCI mem marker = %x\n", pci_tolm); -#endif +#endif /* FIXME Me temporary hack */ if(pci_tolm > 0xe0000000) pci_tolm = 0xe0000000; @@ -122,7 +98,7 @@ remapbasek = 0x3ff << 16; remaplimitk = 0 << 16; remapoffsetk = 0 << 16; - } + } else { /* The PCI memory hole overlaps memory * setup the remap window. @@ -160,12 +136,12 @@ /* Report the memory regions */ ram_resource(dev, 3, 0, 640); - ram_resource(dev, 4, 768, tolmk - 768); + ram_resource(dev, 4, 768, (tolmk - 768)); if (tomk > 4*1024*1024) { ram_resource(dev, 5, 4096*1024, tomk - 4*1024*1024); } if (remaplimitk >= remapbasek) { - ram_resource(dev, 6, remapbasek, + ram_resource(dev, 6, remapbasek, (remaplimitk + 64*1024) - remapbasek); } @@ -178,13 +154,10 @@ assign_resources(&dev->link[0]); } -static unsigned int pci_domain_scan_bus(device_t dev, unsigned int max) +static u32 e7525_domain_scan_bus(device_t dev, u32 max) { - max = pci_scan_bus(&dev->link[0], 0, 0xff, max); - if (max > max_bus) { - max_bus = max; - } - return max; + max_bus = pci_domain_scan_bus(dev, max); + return max_bus; } static struct device_operations pci_domain_ops = { @@ -192,7 +165,7 @@ .set_resources = pci_domain_set_resources, .enable_resources = enable_childrens_resources, .init = 0, - .scan_bus = pci_domain_scan_bus, + .scan_bus = e7525_domain_scan_bus, .ops_pci_bus = &pci_cf8_conf1, /* Do we want to use the memory mapped space here? */ }; Modified: trunk/coreboot-v2/src/northbridge/intel/i3100/northbridge.c =================================================================== --- trunk/coreboot-v2/src/northbridge/intel/i3100/northbridge.c 2009-07-02 18:27:02 UTC (rev 4393) +++ trunk/coreboot-v2/src/northbridge/intel/i3100/northbridge.c 2009-07-02 18:56:24 UTC (rev 4394) @@ -49,30 +49,6 @@ IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; } - -static void pci_domain_read_resources(device_t dev) -{ - struct resource *resource; - - /* Initialize the system wide io space constraints */ - resource = new_resource(dev, IOINDEX_SUBTRACTIVE(0,0)); - resource->base = 0; - resource->size = 0; - resource->align = 0; - resource->gran = 0; - resource->limit = 0xffffUL; - resource->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED; - - /* Initialize the system wide memory resources constraints */ - resource = new_resource(dev, IOINDEX_SUBTRACTIVE(1,0)); - resource->base = 0; - resource->size = 0; - resource->align = 0; - resource->gran = 0; - resource->limit = 0xffffffffUL; - resource->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED; -} - static void tolm_test(void *gp, struct device *dev, struct resource *new) { struct resource **best_p = gp; @@ -199,13 +175,10 @@ assign_resources(&dev->link[0]); } -static u32 pci_domain_scan_bus(device_t dev, u32 max) +static u32 i3100_domain_scan_bus(device_t dev, u32 max) { - max = pci_scan_bus(&dev->link[0], 0, 0xff, max); - if (max > max_bus) { - max_bus = max; - } - return max; + max_bus = pci_domain_scan_bus(dev, max); + return max_bus; } static struct device_operations pci_domain_ops = { @@ -213,7 +186,7 @@ .set_resources = pci_domain_set_resources, .enable_resources = enable_childrens_resources, .init = 0, - .scan_bus = pci_domain_scan_bus, + .scan_bus = i3100_domain_scan_bus, .ops_pci_bus = &pci_cf8_conf1, /* Do we want to use the memory mapped space here? */ }; Modified: trunk/coreboot-v2/src/northbridge/intel/i440bx/northbridge.c =================================================================== --- trunk/coreboot-v2/src/northbridge/intel/i440bx/northbridge.c 2009-07-02 18:27:02 UTC (rev 4393) +++ trunk/coreboot-v2/src/northbridge/intel/i440bx/northbridge.c 2009-07-02 18:56:24 UTC (rev 4394) @@ -33,24 +33,6 @@ .device = 0x7190, }; - -#define BRIDGE_IO_MASK (IORESOURCE_IO | IORESOURCE_MEM) - -static void pci_domain_read_resources(device_t dev) -{ - struct resource *resource; - - /* Initialize the system wide io space constraints */ - resource = new_resource(dev, IOINDEX_SUBTRACTIVE(0,0)); - resource->limit = 0xffffUL; - resource->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED; - - /* Initialize the system wide memory resources constraints */ - resource = new_resource(dev, IOINDEX_SUBTRACTIVE(1,0)); - resource->limit = 0xffffffffULL; - resource->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED; -} - static void ram_resource(device_t dev, unsigned long index, unsigned long basek, unsigned long sizek) { @@ -95,7 +77,7 @@ extern uint64_t high_tables_base, high_tables_size; #endif -static void pci_domain_set_resources(device_t dev) +static void i440bx_domain_set_resources(device_t dev) { device_t mc_dev; uint32_t pci_tolm; @@ -140,15 +122,9 @@ assign_resources(&dev->link[0]); } -static unsigned int pci_domain_scan_bus(device_t dev, unsigned int max) -{ - max = pci_scan_bus(&dev->link[0], PCI_DEVFN(0, 0), 0xff, max); - return max; -} - static struct device_operations pci_domain_ops = { .read_resources = pci_domain_read_resources, - .set_resources = pci_domain_set_resources, + .set_resources = i440bx_domain_set_resources, .enable_resources = enable_childrens_resources, .init = 0, .scan_bus = pci_domain_scan_bus, Modified: trunk/coreboot-v2/src/northbridge/intel/i82810/northbridge.c =================================================================== --- trunk/coreboot-v2/src/northbridge/intel/i82810/northbridge.c 2009-07-02 18:27:02 UTC (rev 4393) +++ trunk/coreboot-v2/src/northbridge/intel/i82810/northbridge.c 2009-07-02 18:56:24 UTC (rev 4394) @@ -52,27 +52,6 @@ .device = 0x7120, }; -#define BRIDGE_IO_MASK (IORESOURCE_IO | IORESOURCE_MEM) - -static void pci_domain_read_resources(device_t dev) -{ - struct resource *resource; - unsigned reg; - - /* Initialize the system wide io space constraints */ - resource = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0)); - resource->base = 0x400; - resource->limit = 0xffffUL; - resource->flags = - IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED; - - /* Initialize the system wide memory resources constraints */ - resource = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0)); - resource->limit = 0xffffffffULL; - resource->flags = - IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED; -} - static void ram_resource(device_t dev, unsigned long index, unsigned long basek, unsigned long sizek) { @@ -181,12 +160,6 @@ assign_resources(&dev->link[0]); } -static unsigned int pci_domain_scan_bus(device_t dev, unsigned int max) -{ - max = pci_scan_bus(&dev->link[0], PCI_DEVFN(0, 0), 0xff, max); - return max; -} - static struct device_operations pci_domain_ops = { .read_resources = pci_domain_read_resources, .set_resources = pci_domain_set_resources, Modified: trunk/coreboot-v2/src/northbridge/intel/i82830/northbridge.c =================================================================== --- trunk/coreboot-v2/src/northbridge/intel/i82830/northbridge.c 2009-07-02 18:27:02 UTC (rev 4393) +++ trunk/coreboot-v2/src/northbridge/intel/i82830/northbridge.c 2009-07-02 18:56:24 UTC (rev 4394) @@ -51,25 +51,6 @@ .device = 0x3575, }; -#define BRIDGE_IO_MASK (IORESOURCE_IO | IORESOURCE_MEM) - -static void pci_domain_read_resources(device_t dev) -{ - struct resource *resource; - - /* Initialize the system wide I/O space constraints. */ - resource = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0)); - resource->limit = 0xffffUL; - resource->flags = - IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED; - - /* Initialize the system wide memory resources constraints. */ - resource = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0)); - resource->limit = 0xffffffffULL; - resource->flags = - IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED; -} - static void ram_resource(device_t dev, unsigned long index, unsigned long basek, unsigned long sizek) { @@ -158,12 +139,6 @@ assign_resources(&dev->link[0]); } -static unsigned int pci_domain_scan_bus(device_t dev, unsigned int max) -{ - max = pci_scan_bus(&dev->link[0], PCI_DEVFN(0, 0), 0xff, max); - return max; -} - static struct device_operations pci_domain_ops = { .read_resources = pci_domain_read_resources, .set_resources = pci_domain_set_resources, Modified: trunk/coreboot-v2/src/northbridge/intel/i855gme/northbridge.c =================================================================== --- trunk/coreboot-v2/src/northbridge/intel/i855gme/northbridge.c 2009-07-02 18:27:02 UTC (rev 4393) +++ trunk/coreboot-v2/src/northbridge/intel/i855gme/northbridge.c 2009-07-02 18:56:24 UTC (rev 4394) @@ -31,24 +31,6 @@ #include <cpu/x86/cache.h> #include "chip.h" -#define BRIDGE_IO_MASK (IORESOURCE_IO | IORESOURCE_MEM) - -static void pci_domain_read_resources(device_t dev) -{ - struct resource *resource; - unsigned reg; - - /* Initialize the system wide io space constraints */ - resource = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0)); - resource->limit = 0xffffUL; - resource->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED; - - /* Initialize the system wide memory resources constraints */ - resource = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0)); - resource->limit = 0xffffffffULL; - resource->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED; -} - static void ram_resource(device_t dev, unsigned long index, unsigned long basek, unsigned long sizek) { @@ -156,12 +138,6 @@ assign_resources(&dev->link[0]); } -static unsigned int pci_domain_scan_bus(device_t dev, unsigned int max) -{ - max = pci_scan_bus(&dev->link[0], PCI_DEVFN(0, 0), 0xff, max); - return max; -} - static struct device_operations pci_domain_ops = { .read_resources = pci_domain_read_resources, .set_resources = pci_domain_set_resources, Modified: trunk/coreboot-v2/src/northbridge/intel/i855pm/northbridge.c =================================================================== --- trunk/coreboot-v2/src/northbridge/intel/i855pm/northbridge.c 2009-07-02 18:27:02 UTC (rev 4393) +++ trunk/coreboot-v2/src/northbridge/intel/i855pm/northbridge.c 2009-07-02 18:56:24 UTC (rev 4394) @@ -10,23 +10,6 @@ #include <bitops.h> #include "chip.h" -#define BRIDGE_IO_MASK (IORESOURCE_IO | IORESOURCE_MEM) - -static void pci_domain_read_resources(device_t dev) -{ - struct resource *resource; - - /* Initialize the system wide io space constraints */ - resource = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0)); - resource->limit = 0xffffUL; - resource->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED; - - /* Initialize the system wide memory resources constraints */ - resource = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0)); - resource->limit = 0xffffffffULL; - resource->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED; -} - static void ram_resource(device_t dev, unsigned long index, unsigned long basek, unsigned long sizek) { @@ -123,12 +106,6 @@ assign_resources(&dev->link[0]); } -static unsigned int pci_domain_scan_bus(device_t dev, unsigned int max) -{ - max = pci_scan_bus(&dev->link[0], PCI_DEVFN(0, 0), 0xff, max); - return max; -} - static struct device_operations pci_domain_ops = { .read_resources = pci_domain_read_resources, .set_resources = pci_domain_set_resources, Modified: trunk/coreboot-v2/src/northbridge/intel/i945/northbridge.c =================================================================== --- trunk/coreboot-v2/src/northbridge/intel/i945/northbridge.c 2009-07-02 18:27:02 UTC (rev 4393) +++ trunk/coreboot-v2/src/northbridge/intel/i945/northbridge.c 2009-07-02 18:56:24 UTC (rev 4394) @@ -43,31 +43,6 @@ IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; } -static void pci_domain_read_resources(device_t dev) -{ - struct resource *resource; - - /* Initialize the system wide io space constraints */ - resource = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0)); - resource->base = 0; - resource->size = 0; - resource->align = 0; - resource->gran = 0; - resource->limit = 0xffffUL; - resource->flags = - IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED; - - /* Initialize the system wide memory resources constraints */ - resource = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0)); - resource->base = 0; - resource->size = 0; - resource->align = 0; - resource->gran = 0; - resource->limit = 0xffffffffUL; - resource->flags = - IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED; -} - static void tolm_test(void *gp, struct device *dev, struct resource *new) { struct resource **best_p = gp; @@ -184,15 +159,10 @@ #endif } -static unsigned int pci_domain_scan_bus(device_t dev, unsigned int max) -{ - max = pci_scan_bus(&dev->link[0], 0, 0xff, max); /* TODO We could determine how many PCIe busses we need in * the bar. For now that number is hardcoded to a max of 64. + * See e7525/northbridge.c for an example. */ - return max; -} - static struct device_operations pci_domain_ops = { .read_resources = pci_domain_read_resources, .set_resources = pci_domain_set_resources, Modified: trunk/coreboot-v2/src/northbridge/motorola/mpc107/mpc107_northbridge.c =================================================================== --- trunk/coreboot-v2/src/northbridge/motorola/mpc107/mpc107_northbridge.c 2009-07-02 18:27:02 UTC (rev 4393) +++ trunk/coreboot-v2/src/northbridge/motorola/mpc107/mpc107_northbridge.c 2009-07-02 18:56:24 UTC (rev 4394) @@ -16,7 +16,7 @@ * be large enough to hold all expected resources for all PCI * devices. */ -static void pci_domain_read_resources(device_t dev) +static void mpc107_domain_read_resources(device_t dev) { struct resource *resource; @@ -101,15 +101,8 @@ assign_resources(&dev->link[0]); } - -static unsigned int pci_domain_scan_bus(device_t dev, unsigned int max) -{ - max = pci_scan_bus(&dev->link[0], PCI_DEVFN(0, 0), 0xff, max); - return max; -} - static struct device_operations pci_domain_ops = { - .read_resources = pci_domain_read_resources, + .read_resources = mpc107_domain_read_resources, .set_resources = pci_domain_set_resources, .enable_resources = enable_childrens_resources, .init = 0, Modified: trunk/coreboot-v2/src/northbridge/via/cn400/northbridge.c =================================================================== --- trunk/coreboot-v2/src/northbridge/via/cn400/northbridge.c 2009-07-02 18:27:02 UTC (rev 4393) +++ trunk/coreboot-v2/src/northbridge/via/cn400/northbridge.c 2009-07-02 18:56:24 UTC (rev 4394) @@ -101,11 +101,11 @@ .device = PCI_DEVICE_ID_VIA_CN400_MEMCTRL, }; -static void pci_domain_read_resources(device_t dev) +static void cn400_domain_read_resources(device_t dev) { struct resource *resource; - printk_spew("Entering cn400 pci_domain_read_resources.\n"); + printk_spew("Entering %s.\n", __func__); /* Initialize the system wide I/O space constraints. */ resource = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0)); @@ -119,7 +119,7 @@ resource->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED; - printk_spew("Leaving cn400 pci_domain_read_resources.\n"); + printk_spew("Leaving %s.\n", __func__); } static void ram_resource(device_t dev, unsigned long index, @@ -173,14 +173,14 @@ extern uint64_t high_tables_base, high_tables_size; #endif -static void pci_domain_set_resources(device_t dev) +static void cn400_domain_set_resources(device_t dev) { /* The order is important to find the correct RAM size. */ static const u8 ramregs[] = { 0x43, 0x42, 0x41, 0x40 }; device_t mc_dev; u32 pci_tolm; - printk_spew("Entering cn400 pci_domain_set_resources.\n"); + printk_spew("Entering %s.\n", __func__); pci_tolm = find_pci_tolm(&dev->link[0]); mc_dev = dev_find_device(PCI_VENDOR_ID_VIA, @@ -226,23 +226,23 @@ } assign_resources(&dev->link[0]); - printk_spew("Leaving cn400 pci_domain_set_resources.\n"); + printk_spew("Leaving %s.\n", __func__); } -static unsigned int pci_domain_scan_bus(device_t dev, unsigned int max) +static unsigned int cn400_domain_scan_bus(device_t dev, unsigned int max) { - printk_debug("Entering cn400 pci_domain_scan_bus.\n"); + printk_debug("Entering %s.\n", __func__); max = pci_scan_bus(&dev->link[0], PCI_DEVFN(0, 0), 0xff, max); return max; } static const struct device_operations pci_domain_ops = { - .read_resources = pci_domain_read_resources, - .set_resources = pci_domain_set_resources, + .read_resources = cn400_domain_read_resources, + .set_resources = cn400_domain_set_resources, .enable_resources = enable_childrens_resources, .init = 0, - .scan_bus = pci_domain_scan_bus, + .scan_bus = cn400_domain_scan_bus, }; static void cpu_bus_init(device_t dev) Modified: trunk/coreboot-v2/src/northbridge/via/cn700/northbridge.c =================================================================== --- trunk/coreboot-v2/src/northbridge/via/cn700/northbridge.c 2009-07-02 18:27:02 UTC (rev 4393) +++ trunk/coreboot-v2/src/northbridge/via/cn700/northbridge.c 2009-07-02 18:56:24 UTC (rev 4394) @@ -97,27 +97,6 @@ .device = PCI_DEVICE_ID_VIA_CN700_MEMCTRL, }; -static void pci_domain_read_resources(device_t dev) -{ - struct resource *resource; - - printk_spew("Entering cn700 pci_domain_read_resources.\n"); - - /* Initialize the system wide I/O space constraints. */ - resource = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0)); - resource->limit = 0xffffUL; - resource->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | - IORESOURCE_ASSIGNED; - - /* Initialize the system wide memory resources constraints. */ - resource = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0)); - resource->limit = 0xffffffffULL; - resource->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | - IORESOURCE_ASSIGNED; - - printk_spew("Leaving cn700 pci_domain_read_resources.\n"); -} - static void ram_resource(device_t dev, unsigned long index, unsigned long basek, unsigned long sizek) { @@ -223,14 +202,6 @@ assign_resources(&dev->link[0]); } -static unsigned int pci_domain_scan_bus(device_t dev, unsigned int max) -{ - printk_debug("Entering cn700 pci_domain_scan_bus.\n"); - - max = pci_scan_bus(&dev->link[0], PCI_DEVFN(0, 0), 0xff, max); - return max; -} - static const struct device_operations pci_domain_ops = { .read_resources = pci_domain_read_resources, .set_resources = pci_domain_set_resources, Modified: trunk/coreboot-v2/src/northbridge/via/cx700/cx700_lpc.c =================================================================== --- trunk/coreboot-v2/src/northbridge/via/cx700/cx700_lpc.c 2009-07-02 18:27:02 UTC (rev 4393) +++ trunk/coreboot-v2/src/northbridge/via/cx700/cx700_lpc.c 2009-07-02 18:56:24 UTC (rev 4394) @@ -329,7 +329,7 @@ void cx700_read_resources(device_t dev) { - struct resource *resource; + struct resource *res; /* Make sure we call our childrens set/enable functions - these * are not called unless this device has a resource to set. @@ -337,11 +337,16 @@ pci_dev_read_resources(dev); - resource = new_resource(dev, 1); - resource->flags |= - IORESOURCE_FIXED | IORESOURCE_ASSIGNED | IORESOURCE_IO | IORESOURCE_STORED; - resource->size = 2; - resource->base = 0x2e; + res = new_resource(dev, 1); + res->base = 0x0UL; + res->size = 0x400UL; + res->limit = 0xffffUL; + res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; + + res = new_resource(dev, 3); /* IOAPIC */ + res->base = 0xfec00000; + res->size = 0x00001000; + res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; } void cx700_set_resources(device_t dev) Modified: trunk/coreboot-v2/src/northbridge/via/cx700/northbridge.c =================================================================== --- trunk/coreboot-v2/src/northbridge/via/cx700/northbridge.c 2009-07-02 18:27:02 UTC (rev 4393) +++ trunk/coreboot-v2/src/northbridge/via/cx700/northbridge.c 2009-07-02 18:56:24 UTC (rev 4394) @@ -32,21 +32,6 @@ #include "chip.h" #include "northbridge.h" -static void pci_domain_read_resources(device_t dev) -{ - struct resource *resource; - - /* Initialize the system wide io space constraints */ - resource = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0)); - resource->limit = 0xffffUL; - resource->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED; - - /* Initialize the system wide memory resources constraints */ - resource = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0)); - resource->limit = 0xffffffffULL; - resource->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED; -} - static void ram_resource(device_t dev, unsigned long index, unsigned long basek, unsigned long sizek) { @@ -146,12 +131,6 @@ assign_resources(&dev->link[0]); } -static unsigned int pci_domain_scan_bus(device_t dev, unsigned int max) -{ - max = pci_scan_bus(&dev->link[0], PCI_DEVFN(0, 0), 0xff, max); - return max; -} - static struct device_operations pci_domain_ops = { .read_resources = pci_domain_read_resources, .set_resources = pci_domain_set_resources, Modified: trunk/coreboot-v2/src/northbridge/via/vt8601/northbridge.c =================================================================== --- trunk/coreboot-v2/src/northbridge/via/vt8601/northbridge.c 2009-07-02 18:27:02 UTC (rev 4393) +++ trunk/coreboot-v2/src/northbridge/via/vt8601/northbridge.c 2009-07-02 18:56:24 UTC (rev 4394) @@ -45,23 +45,6 @@ .device = 0x0601, /* 0x8601 is the AGP bridge? */ }; -#define BRIDGE_IO_MASK (IORESOURCE_IO | IORESOURCE_MEM) - -static void pci_domain_read_resources(device_t dev) -{ - struct resource *resource; - - /* Initialize the system wide io space constraints */ - resource = new_resource(dev, IOINDEX_SUBTRACTIVE(0,0)); - resource->limit = 0xffffUL; - resource->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED; - - /* Initialize the system wide memory resources constraints */ - resource = new_resource(dev, IOINDEX_SUBTRACTIVE(1,0)); - resource->limit = 0xffffffffULL; - resource->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED; -} - static void ram_resource(device_t dev, unsigned long index, unsigned long basek, unsigned long sizek) { @@ -160,12 +143,6 @@ assign_resources(&dev->link[0]); } -static unsigned int pci_domain_scan_bus(device_t dev, unsigned int max) -{ - max = pci_scan_bus(&dev->link[0], PCI_DEVFN(0, 0), 0xff, max); - return max; -} - static struct device_operations pci_domain_ops = { .read_resources = pci_domain_read_resources, .set_resources = pci_domain_set_resources, Modified: trunk/coreboot-v2/src/northbridge/via/vt8623/northbridge.c =================================================================== --- trunk/coreboot-v2/src/northbridge/via/vt8623/northbridge.c 2009-07-02 18:27:02 UTC (rev 4393) +++ trunk/coreboot-v2/src/northbridge/via/vt8623/northbridge.c 2009-07-02 18:56:24 UTC (rev 4394) @@ -190,30 +190,6 @@ .device = 0x3122, }; - -#define BRIDGE_IO_MASK (IORESOURCE_IO | IORESOURCE_MEM) - -static void pci_domain_read_resources(device_t dev) -{ - struct resource *resource; - - printk_spew("Entering vt8623 pci_domain_read_resources.\n"); - - /* Initialize the system wide io space constraints */ - resource = new_resource(dev, IOINDEX_SUBTRACTIVE(0,0)); - resource->limit = 0xffffUL; - resource->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | - IORESOURCE_ASSIGNED; - - /* Initialize the system wide memory resources constraints */ - resource = new_resource(dev, IOINDEX_SUBTRACTIVE(1,0)); - resource->limit = 0xffffffffULL; - resource->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | - IORESOURCE_ASSIGNED; - - printk_spew("Leaving vt8623 pci_domain_read_resources.\n"); -} - static void ram_resource(device_t dev, unsigned long index, unsigned long basek, unsigned long sizek) { @@ -313,14 +289,6 @@ assign_resources(&dev->link[0]); } -static unsigned int pci_domain_scan_bus(device_t dev, unsigned int max) -{ - printk_spew("Entering vt8623 pci_domain_scan_bus.\n"); - - max = pci_scan_bus(&dev->link[0], PCI_DEVFN(0, 0), 0xff, max); - return max; -} - static struct device_operations pci_domain_ops = { .read_resources = pci_domain_read_resources, .set_resources = pci_domain_set_resources, Modified: trunk/coreboot-v2/src/northbridge/via/vx800/northbridge.c =================================================================== --- trunk/coreboot-v2/src/northbridge/via/vx800/northbridge.c 2009-07-02 18:27:02 UTC (rev 4393) +++ trunk/coreboot-v2/src/northbridge/via/vx800/northbridge.c 2009-07-02 18:56:24 UTC (rev 4394) @@ -69,27 +69,6 @@ .device = PCI_DEVICE_ID_VIA_VX855_MEMCTRL, }; -static void pci_domain_read_resources(device_t dev) -{ - struct resource *resource; - - printk_spew("Entering vx800 pci_domain_read_resources.\n"); - - /* Initialize the system wide io space constraints */ - resource = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0)); - resource->limit = 0xffffUL; - resource->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | - IORESOURCE_ASSIGNED; - - /* Initialize the system wide memory resources constraints */ - resource = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0)); - resource->limit = 0xffffffffULL; - resource->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | - IORESOURCE_ASSIGNED; - - printk_spew("Leaving vx800 pci_domain_read_resources.\n"); -} - static void ram_resource(device_t dev, unsigned long index, unsigned long basek, unsigned long sizek) { @@ -195,14 +174,6 @@ assign_resources(&dev->link[0]); } -static unsigned int pci_domain_scan_bus(device_t dev, unsigned int max) -{ - printk_debug("Entering vx800 pci_domain_scan_bus.\n"); - - max = pci_scan_bus(&dev->link[0], PCI_DEVFN(0, 0), 0xff, max); - return max; -} - static const struct device_operations pci_domain_ops = { .read_resources = pci_domain_read_resources, .set_resources = pci_domain_set_resources, Modified: trunk/coreboot-v2/src/southbridge/amd/amd8111/amd8111_lpc.c =================================================================== --- trunk/coreboot-v2/src/southbridge/amd/amd8111/amd8111_lpc.c 2009-07-02 18:27:02 UTC (rev 4393) +++ trunk/coreboot-v2/src/southbridge/amd/amd8111/amd8111_lpc.c 2009-07-02 18:56:24 UTC (rev 4394) @@ -162,15 +162,26 @@ { struct resource *res; - /* Get the normal pci resources of this device */ + /* Get the normal PCI resources of this device. */ pci_dev_read_resources(dev); - /* Add an extra subtractive resource for both memory and I/O */ + /* Add an extra subtractive resource for both memory and I/O. */ res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0)); - res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED; - + res->base = 0; + res->size = 0x1000; + res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | + IORESOURCE_ASSIGNED | IORESOURCE_FIXED; + res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0)); - res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED; + res->base = 0xff800000; + res->size = 0x00800000; /* 8 MB for flash */ + res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | + IORESOURCE_ASSIGNED | IORESOURCE_FIXED; + + res = new_resource(dev, 3); /* IOAPIC */ + res->base = 0xfec00000; + res->size = 0x00001000; + res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; } static void amd8111_lpc_enable_resources(device_t dev) Modified: trunk/coreboot-v2/src/southbridge/amd/amd8131/amd8131_bridge.c =================================================================== --- trunk/coreboot-v2/src/southbridge/amd/amd8131/amd8131_bridge.c 2009-07-02 18:27:02 UTC (rev 4393) +++ trunk/coreboot-v2/src/southbridge/amd/amd8131/amd8131_bridge.c 2009-07-02 18:56:24 UTC (rev 4394) @@ -364,9 +364,6 @@ /* set the memory range */ dev->command |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER; res->flags |= IORESOURCE_STORED; - compute_allocate_resource(&dev->link[0], res, - IORESOURCE_MEM | IORESOURCE_PREFETCH, - IORESOURCE_MEM); base = res->base; end = resource_end(res); pci_write_config16(dev, PCI_MEMORY_BASE, base >> 16); Modified: trunk/coreboot-v2/src/southbridge/amd/amd8132/amd8132_bridge.c =================================================================== --- trunk/coreboot-v2/src/southbridge/amd/amd8132/amd8132_bridge.c 2009-07-02 18:27:02 UTC (rev 4393) +++ trunk/coreboot-v2/src/southbridge/amd/amd8132/amd8132_bridge.c 2009-07-02 18:56:24 UTC (rev 4394) @@ -350,9 +350,6 @@ /* set the memory range */ dev->command |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER; res->flags |= IORESOURCE_STORED; - compute_allocate_resource(&dev->link[0], res, - IORESOURCE_MEM | IORESOURCE_PREFETCH, - IORESOURCE_MEM); base = res->base; end = resource_end(res); pci_write_config16(dev, PCI_MEMORY_BASE, base >> 16); Modified: trunk/coreboot-v2/src/southbridge/amd/cs5530/cs5530_isa.c =================================================================== --- trunk/coreboot-v2/src/southbridge/amd/cs5530/cs5530_isa.c 2009-07-02 18:27:02 UTC (rev 4393) +++ trunk/coreboot-v2/src/southbridge/amd/cs5530/cs5530_isa.c 2009-07-02 18:56:24 UTC (rev 4394) @@ -25,6 +25,24 @@ #include <device/pci_ids.h> #include "cs5530.h" +static void cs5530_read_resources(device_t dev) +{ + struct resource* res; + + pci_dev_read_resources(dev); + + res = new_resource(dev, 1); + res->base = 0x0UL; + res->size = 0x400UL; + res->limit = 0xffffUL; + res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; + + res = new_resource(dev, 3); /* IOAPIC */ + res->base = 0xfec00000; + res->size = 0x00001000; + res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; +} + static void isa_init(struct device *dev) { uint8_t reg8; @@ -45,7 +63,7 @@ } static struct device_operations isa_ops = { - .read_resources = pci_dev_read_resources, + .read_resources = cs5530_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = cs5530_pci_dev_enable_resources, .init = isa_init, Modified: trunk/coreboot-v2/src/southbridge/amd/cs5535/cs5535.c =================================================================== --- trunk/coreboot-v2/src/southbridge/amd/cs5535/cs5535.c 2009-07-02 18:27:02 UTC (rev 4393) +++ trunk/coreboot-v2/src/southbridge/amd/cs5535/cs5535.c 2009-07-02 18:56:24 UTC (rev 4394) @@ -69,6 +69,24 @@ printk_spew("%s: dev is %p\n", __func__, dev); } +static void cs5535_read_resources(device_t dev) +{ + struct resource* res; + + pci_dev_read_resources(dev); + + res = new_resource(dev, 1); + res->base = 0x0UL; + res->size = 0x400UL; + res->limit = 0xffffUL; + res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; + + res = new_resource(dev, 3); /* IOAPIC */ + res->base = 0xfec00000; + res->size = 0x00001000; + res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; +} + static void cs5535_pci_dev_enable_resources(device_t dev) { printk_spew("cs5535.c: %s()\n", __func__); @@ -77,7 +95,7 @@ } static struct device_operations southbridge_ops = { - .read_resources = pci_dev_read_resources, + .read_resources = cs5535_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = cs5535_pci_dev_enable_resources, .init = southbridge_init, Modified: trunk/coreboot-v2/src/southbridge/amd/cs5536/cs5536.c =================================================================== --- trunk/coreboot-v2/src/southbridge/amd/cs5536/cs5536.c 2009-07-02 18:27:02 UTC (rev 4393) +++ trunk/coreboot-v2/src/southbridge/amd/cs5536/cs5536.c 2009-07-02 18:56:24 UTC (rev 4394) @@ -607,6 +607,25 @@ } } +static void cs5536_read_resources(device_t dev) +{ + struct resource *res; + + pci_dev_read_resources(dev); + + res = new_resource(dev, 1); + res->base = 0x0UL; + res->size = 0x400UL; + res->limit = 0xffffUL; + res->flags = IORESOURCE_IO | + IORESOURCE_ASSIGNED | IORESOURCE_FIXED; + + res = new_resource(dev, 3); /* IOAPIC */ + res->base = 0xfec00000; + res->size = 0x00001000; + res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; +} + static void southbridge_enable(struct device *dev) { printk_err("cs5536: %s: dev is %p\n", __func__, dev); @@ -621,7 +640,7 @@ } static struct device_operations southbridge_ops = { - .read_resources = pci_dev_read_resources, + .read_resources = cs5536_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = cs5536_pci_dev_enable_resources, .init = southbridge_init, Modified: trunk/coreboot-v2/src/southbridge/amd/sb600/sb600_lpc.c =================================================================== --- trunk/coreboot-v2/src/southbridge/amd/sb600/sb600_lpc.c 2009-07-02 18:27:02 UTC (rev 4393) +++ trunk/coreboot-v2/src/southbridge/amd/sb600/sb600_lpc.c 2009-07-02 18:56:24 UTC (rev 4394) @@ -70,15 +70,24 @@ pci_get_resource(dev, 0xA0); /* SPI ROM base address */ - /* Add an extra subtractive resource for both memory and I/O */ + /* Add an extra subtractive resource for both memory and I/O. */ res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0)); - res->flags = - IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED; + res->base = 0; + res->size = 0x1000; + res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | + IORESOURCE_ASSIGNED | IORESOURCE_FIXED; res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0)); - res->flags = - IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED; + res->base = 0xff800000; + res->size = 0x00800000; /* 8 MB for flash */ + res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | + IORESOURCE_ASSIGNED | IORESOURCE_FIXED; + res = new_resource(dev, 3); /* IOAPIC */ + res->base = 0xfec00000; + res->size = 0x00001000; + res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; + compact_resources(dev); } @@ -111,7 +120,7 @@ for (child = dev->link[link].children; child; child = child->sibling) { enable_resources(child); - if (child->have_resources + if (child->enabled && (child->path.type == DEVICE_PATH_PNP)) { for (i = 0; i < child->resources; i++) { struct resource *res; Modified: trunk/coreboot-v2/src/southbridge/broadcom/bcm5785/bcm5785_lpc.c =================================================================== --- trunk/coreboot-v2/src/southbridge/broadcom/bcm5785/bcm5785_lpc.c 2009-07-02 18:27:02 UTC (rev 4393) +++ trunk/coreboot-v2/src/southbridge/broadcom/bcm5785/bcm5785_lpc.c 2009-07-02 18:56:24 UTC (rev 4394) @@ -29,18 +29,27 @@ static void bcm5785_lpc_read_resources(device_t dev) { struct resource *res; - unsigned long index; /* Get the normal pci resources of this device */ - pci_dev_read_resources(dev); - - /* Add an extra subtractive resource for both memory and I/O */ - res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0)); - res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED; - - res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0)); - res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED; + pci_dev_read_resources(dev); + /* Add an extra subtractive resource for both memory and I/O. */ + res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0)); + res->base = 0; + res->size = 0x1000; + res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | + IORESOURCE_ASSIGNED | IORESOURCE_FIXED; + + res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0)); + res->base = 0xff800000; + res->size = 0x00800000; /* 8 MB for flash */ + res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | + IORESOURCE_ASSIGNED | IORESOURCE_FIXED; + + res = new_resource(dev, 3); /* IOAPIC */ + res->base = 0xfec00000; + res->size = 0x00001000; + res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; } /** @@ -69,7 +78,7 @@ device_t child; for (child = dev->link[link].children; child; child = child->sibling) { enable_resources(child); - if(child->have_resources && (child->path.type == DEVICE_PATH_PNP)) { + if(child->enabled && (child->path.type == DEVICE_PATH_PNP)) { for(i=0;i<child->resources;i++) { struct resource *res; unsigned long base, end; // don't need long long Modified: trunk/coreboot-v2/src/southbridge/broadcom/bcm5785/bcm5785_sb_pci_main.c =================================================================== --- trunk/coreboot-v2/src/southbridge/broadcom/bcm5785/bcm5785_sb_pci_main.c 2009-07-02 18:27:02 UTC (rev 4393) +++ trunk/coreboot-v2/src/southbridge/broadcom/bcm5785/bcm5785_sb_pci_main.c 2009-07-02 18:56:24 UTC (rev 4394) @@ -51,7 +51,6 @@ /* Get the normal pci resources of this device */ pci_dev_read_resources(dev); - /* Get Resource for SMBUS */ pci_get_resource(dev, 0x90); Modified: trunk/coreboot-v2/src/southbridge/intel/esb6300/esb6300_lpc.c =================================================================== --- trunk/coreboot-v2/src/southbridge/intel/esb6300/esb6300_lpc.c 2009-07-02 18:27:02 UTC (rev 4393) +++ trunk/coreboot-v2/src/southbridge/intel/esb6300/esb6300_lpc.c 2009-07-02 18:56:24 UTC (rev 4394) @@ -361,12 +361,23 @@ /* Add the GPIO BAR */ res = pci_get_resource(dev, GPIO_BAR); - /* Add an extra subtractive resource for both memory and I/O */ + /* Add an extra subtractive resource for both memory and I/O. */ res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0)); - res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED; + res->base = 0; + res->size = 0x1000; + res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | + IORESOURCE_ASSIGNED | IORESOURCE_FIXED; res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0)); - res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED; + res->base = 0xff800000; + res->size = 0x00800000; /* 8 MB for flash */ + res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | + IORESOURCE_ASSIGNED | IORESOURCE_FIXED; + + res = new_resource(dev, 3); /* IOAPIC */ + res->base = 0xfec00000; + res->size = 0x00001000; + res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; } static void esb6300_lpc_enable_resources(device_t dev) Modified: trunk/coreboot-v2/src/southbridge/intel/i3100/i3100_lpc.c =================================================================== --- trunk/coreboot-v2/src/southbridge/intel/i3100/i3100_lpc.c 2009-07-02 18:27:02 UTC (rev 4393) +++ trunk/coreboot-v2/src/southbridge/intel/i3100/i3100_lpc.c 2009-07-02 18:56:24 UTC (rev 4394) @@ -399,13 +399,24 @@ /* Add the GPIO BAR */ res = pci_get_resource(dev, GPIO_BAR); - /* Add an extra subtractive resource for both memory and I/O */ + /* Add an extra subtractive resource for both memory and I/O. */ res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0)); - res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED; + res->base = 0; + res->size = 0x1000; + res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | + IORESOURCE_ASSIGNED | IORESOURCE_FIXED; res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0)); - res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED; + res->base = 0xff800000; + res->size = 0x00800000; /* 8 MB for flash */ + res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | + IORESOURCE_ASSIGNED | IORESOURCE_FIXED; + res = new_resource(dev, 3); /* IOAPIC */ + res->base = 0xfec00000; + res->size = 0x00001000; + res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; + /* Add resource for RCBA */ res = new_resource(dev, RCBA); res->size = 0x4000; Modified: trunk/coreboot-v2/src/southbridge/intel/i82371eb/i82371eb_isa.c =================================================================== --- trunk/coreboot-v2/src/southbridge/intel/i82371eb/i82371eb_isa.c 2009-07-02 18:27:02 UTC (rev 4393) +++ trunk/coreboot-v2/src/southbridge/intel/i82371eb/i82371eb_isa.c 2009-07-02 18:56:24 UTC (rev 4394) @@ -55,8 +55,31 @@ isa_dma_init(); } -static const struct device_operations isa_ops = { - .read_resources = pci_dev_read_resources, +static void sb_read_resources(struct device *dev) +{ + struct resource *res; + + pci_dev_read_resources(dev); + + res = new_resource(dev, 1); + res->base = 0x0UL; + res->size = 0x1000UL; + res->limit = 0xffffUL; + res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; + + res = new_resource(dev, 2); + res->base = 0xff800000UL; + res->size = 0x00800000UL; /* 8 MB for flash */ + res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; + + res = new_resource(dev, 3); /* IOAPIC */ + res->base = 0xfec00000; + res->size = 0x00001000; + res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; +} + +const struct device_operations isa_ops = { + .read_resources = sb_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = isa_init, Modified: trunk/coreboot-v2/src/southbridge/intel/i82801ca/i82801ca_lpc.c =================================================================== --- trunk/coreboot-v2/src/southbridge/intel/i82801ca/i82801ca_lpc.c 2009-07-02 18:27:02 UTC (rev 4393) +++ trunk/coreboot-v2/src/southbridge/intel/i82801ca/i82801ca_lpc.c 2009-07-02 18:56:24 UTC (rev 4394) @@ -207,15 +207,26 @@ { struct resource *res; - /* Get the normal pci resources of this device */ + /* Get the normal PCI resources of this device. */ pci_dev_read_resources(dev); - /* Add an extra subtractive resource for both memory and I/O */ + /* Add an extra subtractive resource for both memory and I/O. */ res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0)); - res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED; + res->base = 0; + res->size = 0x1000; + res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | + IORESOURCE_ASSIGNED | IORESOURCE_FIXED; res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0)); - res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED; + res->base = 0xff800000; + res->size = 0x00800000; /* 8 MB for flash */ + res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | + IORESOURCE_ASSIGNED | IORESOURCE_FIXED; + + res = new_resource(dev, 3); /* IOAPIC */ + res->base = 0xfec00000; + res->size = 0x00001000; + res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; } static void i82801ca_lpc_enable_resources(device_t dev) Modified: trunk/coreboot-v2/src/southbridge/intel/i82801dbm/i82801dbm_lpc.c =================================================================== --- trunk/coreboot-v2/src/southbridge/intel/i82801dbm/i82801dbm_lpc.c 2009-07-02 18:27:02 UTC (rev 4393) +++ trunk/coreboot-v2/src/southbridge/intel/i82801dbm/i82801dbm_lpc.c 2009-07-02 18:56:24 UTC (rev 4394) @@ -182,15 +182,26 @@ { struct resource *res; - /* Get the normal pci resources of this device */ + /* Get the normal PCI resources of this device. */ pci_dev_read_resources(dev); - /* Add an extra subtractive resource for both memory and I/O */ + /* Add an extra subtractive resource for both memory and I/O. */ res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0)); - res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED; + res->base = 0; + res->size = 0x1000; + res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | + IORESOURCE_ASSIGNED | IORESOURCE_FIXED; res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0)); - res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED; + res->base = 0xff800000; + res->size = 0x00800000; /* 8 MB for flash */ + res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | + IORESOURCE_ASSIGNED | IORESOURCE_FIXED; + + res = new_resource(dev, 3); /* IOAPIC */ + res->base = 0xfec00000; + res->size = 0x00001000; + res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; } static void i82801dbm_lpc_enable_resources(device_t dev) Modified: trunk/coreboot-v2/src/southbridge/intel/i82801er/i82801er_lpc.c =================================================================== --- trunk/coreboot-v2/src/southbridge/intel/i82801er/i82801er_lpc.c 2009-07-02 18:27:02 UTC (rev 4393) +++ trunk/coreboot-v2/src/southbridge/intel/i82801er/i82801er_lpc.c 2009-07-02 18:56:24 UTC (rev 4394) @@ -334,7 +334,7 @@ { struct resource *res; - /* Get the normal pci resources of this device */ + /* Get the normal PCI resources of this device. */ pci_dev_read_resources(dev); /* Add the ACPI BAR */ @@ -343,12 +343,23 @@ /* Add the GPIO BAR */ res = pci_get_resource(dev, GPIO_BAR); - /* Add an extra subtractive resource for both memory and I/O */ + /* Add an extra subtractive resource for both memory and I/O. */ res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0)); - res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED; + res->base = 0; + res->size = 0x1000; + res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | + IORESOURCE_ASSIGNED | IORESOURCE_FIXED; res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0)); - res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED; + res->base = 0xff800000; + res->size = 0x00800000; /* 8 MB for flash */ + res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | + IORESOURCE_ASSIGNED | IORESOURCE_FIXED; + + res = new_resource(dev, 3); /* IOAPIC */ + res->base = 0xfec00000; + res->size = 0x00001000; + res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; } static void i82801er_lpc_enable_resources(device_t dev) Modified: trunk/coreboot-v2/src/southbridge/intel/i82801gx/i82801gx_lpc.c =================================================================== --- trunk/coreboot-v2/src/southbridge/intel/i82801gx/i82801gx_lpc.c 2009-07-02 18:27:02 UTC (rev 4393) +++ trunk/coreboot-v2/src/southbridge/intel/i82801gx/i82801gx_lpc.c 2009-07-02 18:56:24 UTC (rev 4394) @@ -419,12 +419,21 @@ /* Add an extra subtractive resource for both memory and I/O. */ res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0)); - res->flags = - IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED; + res->base = 0; + res->size = 0x1000; + res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | + IORESOURCE_ASSIGNED | IORESOURCE_FIXED; res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0)); - res->flags = - IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED; + res->base = 0xff800000; + res->size = 0x00800000; /* 8 MB for flash */ + res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | + IORESOURCE_ASSIGNED | IORESOURCE_FIXED; + + res = new_resource(dev, 3); /* IOAPIC */ + res->base = 0xfec00000; + res->size = 0x00001000; + res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; } static void i82801gx_lpc_enable_resources(device_t dev) Modified: trunk/coreboot-v2/src/southbridge/intel/i82801xx/i82801xx_lpc.c =================================================================== --- trunk/coreboot-v2/src/southbridge/intel/i82801xx/i82801xx_lpc.c 2009-07-02 18:27:02 UTC (rev 4393) +++ trunk/coreboot-v2/src/southbridge/intel/i82801xx/i82801xx_lpc.c 2009-07-02 18:56:24 UTC (rev 4394) @@ -340,12 +340,21 @@ /* Add an extra subtractive resource for both memory and I/O. */ res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0)); - res->flags = - IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED; + res->base = 0; + res->size = 0x1000; + res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | + IORESOURCE_ASSIGNED | IORESOURCE_FIXED; res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0)); - res->flags = - IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED; + res->base = 0xff800000; + res->size = 0x00800000; /* 8 MB for flash */ + res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | + IORESOURCE_ASSIGNED | IORESOURCE_FIXED; + + res = new_resource(dev, 3); /* IOAPIC */ + res->base = 0xfec00000; + res->size = 0x00001000; + res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; } static void i82801xx_lpc_enable_resources(device_t dev) Modified: trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_lpc.c =================================================================== --- trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_lpc.c 2009-07-02 18:27:02 UTC (rev 4393) +++ trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_lpc.c 2009-07-02 18:56:24 UTC (rev 4394) @@ -275,12 +275,21 @@ /* Add an extra subtractive resource for both memory and I/O. */ res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0)); - res->flags = - IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED; + res->base = 0; + res->size = 0x1000; + res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | + IORESOURCE_ASSIGNED | IORESOURCE_FIXED; res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0)); - res->flags = - IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED; + res->base = 0xff800000; + res->size = 0x00800000; /* 8 MB for flash */ + res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | + IORESOURCE_ASSIGNED | IORESOURCE_FIXED; + + res = new_resource(dev, 3); /* IOAPIC */ + res->base = 0xfec00000; + res->size = 0x00001000; + res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; } /** @@ -308,7 +317,7 @@ device_t child; for (child = dev->link[link].children; child; child = child->sibling) { enable_resources(child); - if (child->have_resources && (child->path.type == DEVICE_PATH_PNP)) { + if (child->enabled && (child->path.type == DEVICE_PATH_PNP)) { for (i = 0; i < child->resources; i++) { struct resource *res; unsigned long base, end; // don't need long long Modified: trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_pci.c =================================================================== --- trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_pci.c 2009-07-02 18:27:02 UTC (rev 4393) +++ trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_pci.c 2009-07-02 18:56:24 UTC (rev 4394) @@ -5,6 +5,7 @@ #include <console/console.h> #include <device/device.h> +#include <device/resource.h> #include <device/pci.h> #include <device/pci_ids.h> #include <device/pci_ops.h> @@ -13,10 +14,8 @@ static void pci_init(struct device *dev) { uint32_t dword; -#if CONFIG_PCI_64BIT_PREF_MEM == 1 device_t pci_domain_dev; - struct resource *mem1, *mem2; -#endif + struct resource *mem, *pref; dword = pci_read_config32(dev, 0x04); dword |= (1 << 8); /* System error enable */ @@ -36,7 +35,6 @@ pci_write_config32(dev, 0x4c, dword); #endif -#if CONFIG_PCI_64BIT_PREF_MEM == 1 pci_domain_dev = dev->bus->dev; while (pci_domain_dev) { if (pci_domain_dev->path.type == DEVICE_PATH_PCI_DOMAIN) @@ -47,21 +45,19 @@ if (!pci_domain_dev) return; /* Impossible */ - mem1 = find_resource(pci_domain_dev, 1); // prefmem, it could be 64bit - mem2 = find_resource(pci_domain_dev, 2); // mem - if (mem1->base > mem2->base) { - dword = mem2->base & (0xffff0000UL); - printk_debug("PCI DOMAIN mem2 base = 0x%010Lx\n", mem2->base); + pref = probe_resource(pci_domain_dev, IOINDEX_SUBTRACTIVE(2,0)); + mem = probe_resource(pci_domain_dev, IOINDEX_SUBTRACTIVE(1,0)); + + if (!mem) + return; /* Impossible */ + + if (!pref || pref->base > mem->base) { + dword = mem->base & (0xffff0000UL); + printk_debug("PCI DOMAIN mem base = 0x%010Lx\n", mem->base); } else { - dword = mem1->base & (0xffff0000UL); - printk_debug("PCI DOMAIN mem1 (prefmem) base = 0x%010Lx\n", - mem1->base); + dword = pref->base & (0xffff0000UL); + printk_debug("PCI DOMAIN pref base = 0x%010Lx\n", pref->base); } -#else - dword = dev_root.resource[1].base & (0xffff0000UL); - printk_debug("dev_root mem base = 0x%010Lx\n", - dev_root.resource[1].base); -#endif printk_debug("[0x50] <-- 0x%08x\n", dword); pci_write_config32(dev, 0x50, dword); /* TOM */ Modified: trunk/coreboot-v2/src/southbridge/nvidia/mcp55/mcp55_lpc.c =================================================================== --- trunk/coreboot-v2/src/southbridge/nvidia/mcp55/mcp55_lpc.c 2009-07-02 18:27:02 UTC (rev 4393) +++ trunk/coreboot-v2/src/southbridge/nvidia/mcp55/mcp55_lpc.c 2009-07-02 18:56:24 UTC (rev 4394) @@ -248,16 +248,27 @@ { struct resource *res; - /* Get the normal pci resources of this device */ - pci_dev_read_resources(dev); // We got one for APIC, or one more for TRAP + /* Get the normal PCI resources of this device. */ + /* We got one for APIC, or one more for TRAP. */ + pci_dev_read_resources(dev); - /* Add an extra subtractive resource for both memory and I/O */ + /* Add an extra subtractive resource for both memory and I/O. */ res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0)); - res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED; + res->base = 0; + res->size = 0x1000; + res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | + IORESOURCE_ASSIGNED | IORESOURCE_FIXED; res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0)); - res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED; + res->base = 0xff800000; + res->size = 0x00800000; /* 8 MB for flash */ + res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | + IORESOURCE_ASSIGNED | IORESOURCE_FIXED; + res = new_resource(dev, 3); /* IOAPIC */ + res->base = 0xfec00000; + res->size = 0x00001000; + res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; } /** @@ -265,7 +276,7 @@ * * @param dev the device whos children's resources are to be enabled * - * This function is call by the global enable_resources() indirectly via the + * This function is called by the global enable_resources() indirectly via the * device_operation::enable_resources() method of devices. * * Indirect mutual recursion: @@ -286,7 +297,7 @@ device_t child; for (child = dev->link[link].children; child; child = child->sibling) { enable_resources(child); - if(child->have_resources && (child->path.type == DEVICE_PATH_PNP)) { + if(child->enabled && (child->path.type == DEVICE_PATH_PNP)) { for(i=0;i<child->resources;i++) { struct resource *res; unsigned long base, end; // don't need long long Modified: trunk/coreboot-v2/src/southbridge/nvidia/mcp55/mcp55_pci.c =================================================================== --- trunk/coreboot-v2/src/southbridge/nvidia/mcp55/mcp55_pci.c 2009-07-02 18:27:02 UTC (rev 4393) +++ trunk/coreboot-v2/src/southbridge/nvidia/mcp55/mcp55_pci.c 2009-07-02 18:56:24 UTC (rev 4394) @@ -23,6 +23,7 @@ #include <console/console.h> #include <device/device.h> +#include <device/resource.h> #include <device/pci.h> #include <device/pci_ids.h> #include <device/pci_ops.h> @@ -33,10 +34,8 @@ uint32_t dword; uint16_t word; -#if CONFIG_PCI_64BIT_PREF_MEM == 1 device_t pci_domain_dev; - struct resource *mem1, *mem2; -#endif + struct resource *mem, *pref; /* System error enable */ dword = pci_read_config32(dev, 0x04); @@ -58,30 +57,32 @@ pci_write_config32(dev, 0x4c, dword); #endif -#if CONFIG_PCI_64BIT_PREF_MEM == 1 pci_domain_dev = dev->bus->dev; - while(pci_domain_dev) { - if(pci_domain_dev->path.type == DEVICE_PATH_PCI_DOMAIN) break; + while (pci_domain_dev) { + if (pci_domain_dev->path.type == DEVICE_PATH_PCI_DOMAIN) + break; pci_domain_dev = pci_domain_dev->bus->dev; } - if(!pci_domain_dev) return; // impossiable - mem1 = find_resource(pci_domain_dev, 1); // prefmem, it could be 64bit - mem2 = find_resource(pci_domain_dev, 2); // mem - if(mem1->base > mem2->base) { - dword = mem2->base & (0xffff0000UL); - printk_debug("PCI DOMAIN mem2 base = 0x%010Lx\n", mem2->base); + if (!pci_domain_dev) + return; /* Impossible */ + + pref = probe_resource(pci_domain_dev, IOINDEX_SUBTRACTIVE(2,0)); + mem = probe_resource(pci_domain_dev, IOINDEX_SUBTRACTIVE(1,0)); + + if (!mem) + return; /* Impossible */ + + if (!pref || pref->base > mem->base) { + dword = mem->base & (0xffff0000UL); + printk_debug("PCI DOMAIN mem base = 0x%010Lx\n", mem->base); } else { - dword = mem1->base & (0xffff0000UL); - printk_debug("PCI DOMAIN mem1 (prefmem) base = 0x%010Lx\n", mem1->base); + dword = pref->base & (0xffff0000UL); + printk_debug("PCI DOMAIN pref base = 0x%010Lx\n", pref->base); } -#else - dword = dev_root.resource[1].base & (0xffff0000UL); - printk_debug("dev_root mem base = 0x%010Lx\n", dev_root.resource[1].base); -#endif + printk_debug("[0x50] <-- 0x%08x\n", dword); - pci_write_config32(dev, 0x50, dword); //TOM - + pci_write_config32(dev, 0x50, dword); /* TOM */ } static struct pci_operations lops_pci = { Modified: trunk/coreboot-v2/src/southbridge/ricoh/rl5c476/rl5c476.c =================================================================== --- trunk/coreboot-v2/src/southbridge/ricoh/rl5c476/rl5c476.c 2009-07-02 18:27:02 UTC (rev 4393) +++ trunk/coreboot-v2/src/southbridge/ricoh/rl5c476/rl5c476.c 2009-07-02 18:56:24 UTC (rev 4394) @@ -172,7 +172,6 @@ resource = find_resource(dev,1); if( !(resource->flags & IORESOURCE_STORED) ){ resource->flags |= IORESOURCE_STORED ; - compute_allocate_resource(&dev->link[0],resource,resource->flags,resourc e->flags); printk_debug("%s 1 ==> %x\n",dev_path(dev),resource->base); cf_base = resource->base; } Modified: trunk/coreboot-v2/src/southbridge/sis/sis966/sis966_lpc.c =================================================================== --- trunk/coreboot-v2/src/southbridge/sis/sis966/sis966_lpc.c 2009-07-02 18:27:02 UTC (rev 4393) +++ trunk/coreboot-v2/src/southbridge/sis/sis966/sis966_lpc.c 2009-07-02 18:56:24 UTC (rev 4394) @@ -239,13 +239,23 @@ /* Get the normal pci resources of this device */ pci_dev_read_resources(dev); // We got one for APIC, or one more for TRAP - /* Add an extra subtractive resource for both memory and I/O */ + /* Add an extra subtractive resource for both memory and I/O. */ res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0)); - res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED; + res->base = 0; + res->size = 0x1000; + res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | + IORESOURCE_ASSIGNED | IORESOURCE_FIXED; res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0)); - res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED; + res->base = 0xff800000; + res->size = 0x00800000; /* 8 MB for flash */ + res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | + IORESOURCE_ASSIGNED | IORESOURCE_FIXED; + res = new_resource(dev, 3); /* IOAPIC */ + res->base = 0xfec00000; + res->size = 0x00001000; + res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; } /** @@ -274,7 +284,7 @@ device_t child; for (child = dev->link[link].children; child; child = child->sibling) { enable_resources(child); - if(child->have_resources && (child->path.type == DEVICE_PATH_PNP)) { + if(child->enabled && (child->path.type == DEVICE_PATH_PNP)) { for(i=0;i<child->resources;i++) { struct resource *res; unsigned long base, end; // don't need long long Modified: trunk/coreboot-v2/src/southbridge/via/vt8231/vt8231_lpc.c =================================================================== --- trunk/coreboot-v2/src/southbridge/via/vt8231/vt8231_lpc.c 2009-07-02 18:27:02 UTC (rev 4393) +++ trunk/coreboot-v2/src/southbridge/via/vt8231/vt8231_lpc.c 2009-07-02 18:56:24 UTC (rev 4394) @@ -131,6 +131,24 @@ rtc_init(0); } +void vt8231_read_resources(device_t dev) +{ + struct resource *res; + + pci_dev_read_resources(dev); + + res = new_resource(dev, 1); + res->base = 0x0UL; + res->size = 0x400UL; + res->limit = 0xffffUL; + res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; + + res = new_resource(dev, 3); /* IOAPIC */ + res->base = 0xfec00000; + res->size = 0x00001000; + res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; +} + static void southbridge_init(struct device *dev) { vt8231_init(dev); @@ -138,7 +156,7 @@ } static struct device_operations vt8231_lpc_ops = { - .read_resources = pci_dev_read_resources, + .read_resources = vt8231_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = &southbridge_init, Modified: trunk/coreboot-v2/src/southbridge/via/vt8235/vt8235_lpc.c =================================================================== --- trunk/coreboot-v2/src/southbridge/via/vt8235/vt8235_lpc.c 2009-07-02 18:27:02 UTC (rev 4393) +++ trunk/coreboot-v2/src/southbridge/via/vt8235/vt8235_lpc.c 2009-07-02 18:56:24 UTC (rev 4394) @@ -219,15 +219,22 @@ device has a resource to set - so set a dummy one */ void vt8235_read_resources(device_t dev) { + struct resource *res; - struct resource *resource; pci_dev_read_resources(dev); - resource = new_resource(dev, 1); - resource->flags |= IORESOURCE_FIXED | IORESOURCE_ASSIGNED | IORESOURCE_IO | IORESOURCE_STORED; - resource->size = 2; - resource->base = 0x2e; + res = new_resource(dev, 1); + res->base = 0x0UL; + res->size = 0x400UL; + res->limit = 0xffffUL; + res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; + + res = new_resource(dev, 3); /* IOAPIC */ + res->base = 0xfec00000; + res->size = 0x00001000; + res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; } + void vt8235_set_resources(device_t dev) { struct resource *resource; Modified: trunk/coreboot-v2/src/southbridge/winbond/w83c553/w83c553f.c =================================================================== --- trunk/coreboot-v2/src/southbridge/winbond/w83c553/w83c553f.c 2009-07-02 18:27:02 UTC (rev 4393) +++ trunk/coreboot-v2/src/southbridge/winbond/w83c553/w83c553f.c 2009-07-02 18:56:24 UTC (rev 4394) @@ -188,8 +188,26 @@ enable_childrens_resources(dev); } +static void w83c553_read_resources(device_t dev) +{ + struct resource* res; + + pci_dev_read_resources(dev); + + res = new_resource(dev, 1); + res->base = 0x0UL; + res->size = 0x400UL; + res->limit = 0xffffUL; + res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; + + res = new_resource(dev, 3); /* IOAPIC */ + res->base = 0xfec00000; + res->size = 0x00001000; + res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; +} + static struct device_operations w83c553_ops = { - .read_resources = pci_dev_read_resources, + .read_resources = w83c553_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = w83c553_enable_resources, .init = w83c553_init, -- coreboot mailing list: coreboot(a)coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

7 13

CAR vs. non-CAR ck804 bringup
by Myles Watson 09 Jul '09

09 Jul '09

I'd like to unify the ck804_early_setup[_car].c files. The differences are very minor, as you can see from ck804. This patch applies after removing the CK804B defines since they are copies of other defines (with the same values) car_white.diff. Questions: 1. What is PANTA, and why is it commented out in CAR but enabled in the other? 2. Why was SATA on dev 7 enabled in non-CAR but not CAR? I've tried it out on the s2892, but since I don't know exactly what to test... Signed-off-by: Myles Watson <mylesgw(a)gmail.com> Thanks, Myles

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coreboot July 2009