coreboot July 2009

coreboot@coreboot.org

75 participants
304 discussions

[v2] r4425 - trunk/coreboot-v2/src/southbridge/amd/sb600
by svn＠coreboot.org 14 Jul '09

14 Jul '09

Author: stepan Date: 2009-07-14 21:10:10 +0200 (Tue, 14 Jul 2009) New Revision: 4425 Modified: trunk/coreboot-v2/src/southbridge/amd/sb600/sb600_early_setup.c Log: trivial fixes to function declarations (and build system test) Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/coreboot-v2/src/southbridge/amd/sb600/sb600_early_setup.c =================================================================== --- trunk/coreboot-v2/src/southbridge/amd/sb600/sb600_early_setup.c 2009-07-12 14:24:06 UTC (rev 4424) +++ trunk/coreboot-v2/src/southbridge/amd/sb600/sb600_early_setup.c 2009-07-14 19:10:10 UTC (rev 4425) @@ -38,7 +38,7 @@ } /* Get SB ASIC Revision.*/ -static u8 get_sb600_revision() +static u8 get_sb600_revision(void) { device_t dev; dev = pci_locate_device(PCI_ID(0x1002, 0x4385), 0); @@ -123,7 +123,7 @@ } -static u8 dual_core() +static u8 dual_core(void) { return (pci_read_config32(PCI_DEV(0, 0x18, 3), 0xE8) & (0x3<<12)) != 0; } @@ -205,7 +205,7 @@ } -static void sb600_pci_port80() +static void sb600_pci_port80(void) { u8 byte; device_t dev; @@ -271,7 +271,7 @@ /* sbDevicesPorInitTable */ -static void sb600_devices_por_init() +static void sb600_devices_por_init(void) { device_t dev; u8 byte; @@ -467,7 +467,7 @@ * The index address is first programmed into IO reg 0xcd6. * Read or write values are accessed through IO reg 0xcd7. */ -static void sb600_pmio_por_init() +static void sb600_pmio_por_init(void) { u8 byte; @@ -556,7 +556,7 @@ * Compliant with CIM_48's sbPciCfg. * Add any south bridge setting. */ -static void sb600_pci_cfg() +static void sb600_pci_cfg(void) { device_t dev; u8 byte; @@ -645,7 +645,7 @@ /* * Compliant with CIM_48's ATSBPowerOnResetInitJSP */ -static void sb600_por_init() +static void sb600_por_init(void) { /* sbDevicesPorInitTable + sbK8PorInitTable */ sb600_devices_por_init(); @@ -658,7 +658,7 @@ * Compliant with CIM_48's AtiSbBeforePciInit * It should be called during early POST after memory detection and BIOS shadowing but before PCI bus enumeration. */ -static void sb600_before_pci_init() +static void sb600_before_pci_init(void) { sb600_pci_cfg(); }

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Re: [coreboot] [FILO] EPIA-NL/CN400 Port.... FILO Booting kernel, init probs
by Peter Stuge 14 Jul '09

14 Jul '09

Harrison, Jon (SELEX GALILEO, UK) wrote: > I'd appreciate any pointers as to what's going on, It seems that interrupts aren't working correctly. //Peter

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[FILO] EPIA-NL/CN400 Port.... FILO Booting kernel, init probs
by Harrison, Jon (SELEX GALILEO, UK) 14 Jul '09

14 Jul '09

Hi Folks, I've added initial ACPI support to my EPIA-NL/CN400 Port. This has allowed me to get to the point where I can run FILO and start to boot a kernel from SATA. FILO is finding the kernel and initrd image and kicks off the boot process, the kernel is picking up the ACPI tables and starts PCI init (note use of ACPI=force to get around lack of DMI support). I think the issues are concerned with the South Bridge Init (VT8237R), There a bunch of USB UHCI problems reported and then the boot hangs configuring/mounting sda1 Below is the coreboot spew level output, FILO startup and then linux init. I'd appreciate any pointers as to what's going on, particularly the later FILO/Linux init stages. Thanks, Jon ****************************************************************** coreboot-2.0.0-r1M-epia_n-fallback Tue Jul 14 15:52:50 BST 2009 starting... In auto.c:main() Enabling mainboard devices Enable F-ROM Shadow RAM Setup CPU Interface CN400 RAM init starting Setting Burst Length 8 Low Bond 41 High Bond 79 Setting DQS delay66 CN400 Init done doing early_mtrr Leaving auto.c:main() Uncompressing coreboot to RAM. src=fffe0000 dst=00004000 Uncompressing image to RAM. image length = 00018058 Jumping to image. coreboot-2.0.0-r1M-epia_n-fallback Tue Jul 14 15:52:50 BST 2009 booting... Calibrating delay loop... end 99fe9ba6, start 2ca09f0e 32-bit delta 1749 calibrate_tsc 32-bit result is 1749 clocks_per_usec: 1749 Enumerating buses... Show all devs...Before Device Enumeration. Root Device: enabled 1, 0 resources PCI_DOMAIN: 0000: enabled 1, 0 resources PCI: 00:00.0: enabled 1, 0 resources PCI: 00:00.1: enabled 1, 0 resources PCI: 00:00.2: enabled 1, 0 resources PCI: 00:00.3: enabled 1, 0 resources PCI: 00:00.4: enabled 1, 0 resources PCI: 00:00.7: enabled 1, 0 resources PCI: 00:01.0: enabled 1, 0 resources PCI: 00:0f.0: enabled 1, 0 resources PCI: 00:0f.1: enabled 1, 0 resources PCI: 00:10.0: enabled 1, 0 resources PCI: 00:10.1: enabled 1, 0 resources PCI: 00:10.2: enabled 1, 0 resources PCI: 00:10.3: enabled 1, 0 resources PCI: 00:10.4: enabled 1, 0 resources PCI: 00:11.0: enabled 1, 0 resources PNP: 002e.0: enabled 0, 3 resources PNP: 002e.1: enabled 0, 3 resources PNP: 002e.2: enabled 1, 2 resources PNP: 002e.3: enabled 0, 2 resources PNP: 002e.6: enabled 0, 1 resources PNP: 002e.7: enabled 0, 1 resources PNP: 002e.8: enabled 0, 1 resources PNP: 002e.9: enabled 0, 1 resources PNP: 002e.a: enabled 0, 1 resources PNP: 002e.b: enabled 1, 2 resources PCI: 00:11.5: enabled 0, 0 resources PCI: 00:11.6: enabled 0, 0 resources PCI: 00:12.0: enabled 1, 0 resources APIC_CLUSTER: 0: enabled 1, 0 resources APIC: 00: enabled 1, 0 resources Compare with tree... Root Device: enabled 1, 0 resources PCI_DOMAIN: 0000: enabled 1, 0 resources PCI: 00:00.0: enabled 1, 0 resources PCI: 00:00.1: enabled 1, 0 resources PCI: 00:00.2: enabled 1, 0 resources PCI: 00:00.3: enabled 1, 0 resources PCI: 00:00.4: enabled 1, 0 resources PCI: 00:00.7: enabled 1, 0 resources PCI: 00:01.0: enabled 1, 0 resources PCI: 00:0f.0: enabled 1, 0 resources PCI: 00:0f.1: enabled 1, 0 resources PCI: 00:10.0: enabled 1, 0 resources PCI: 00:10.1: enabled 1, 0 resources PCI: 00:10.2: enabled 1, 0 resources PCI: 00:10.3: enabled 1, 0 resources PCI: 00:10.4: enabled 1, 0 resources PCI: 00:11.0: enabled 1, 0 resources PNP: 002e.0: enabled 0, 3 resources PNP: 002e.1: enabled 0, 3 resources PNP: 002e.2: enabled 1, 2 resources PNP: 002e.3: enabled 0, 2 resources PNP: 002e.6: enabled 0, 1 resources PNP: 002e.7: enabled 0, 1 resources PNP: 002e.8: enabled 0, 1 resources PNP: 002e.9: enabled 0, 1 resources PNP: 002e.a: enabled 0, 1 resources PNP: 002e.b: enabled 1, 2 resources PCI: 00:11.5: enabled 0, 0 resources PCI: 00:11.6: enabled 0, 0 resources PCI: 00:12.0: enabled 1, 0 resources APIC_CLUSTER: 0: enabled 1, 0 resources APIC: 00: enabled 1, 0 resources scan_static_bus for Root Device In cn400 enable_dev for device PCI_DOMAIN: 0000. Finding PCI configuration type. PCI: Using configuration type 1 PCI_DOMAIN: 0000 enabled In cn400 enable_dev for device APIC_CLUSTER: 0. APIC_CLUSTER: 0 enabled PCI_DOMAIN: 0000 scanning... Entering cn400_domain_scan_bus. PCI: pci_scan_bus for bus 00 In cn400 enable_dev for device PCI: 00:00.0. PCI: 00:00.0 [1106/0259] ops PCI: 00:00.0 [1106/0259] enabled In cn400 enable_dev for device PCI: 00:00.1. PCI: 00:00.1 [1106/1259] enabled In cn400 enable_dev for device PCI: 00:00.2. PCI: 00:00.2 [1106/2259] enabled In cn400 enable_dev for device PCI: 00:00.3. PCI: 00:00.3 [1106/3259] ops PCI: 00:00.3 [1106/3259] enabled In cn400 enable_dev for device PCI: 00:00.4. PCI: 00:00.4 [1106/4259] enabled PCI: 00:00.5, bad id 0xffffffff PCI: 00:00.6, bad id 0xffffffff In cn400 enable_dev for device PCI: 00:00.7. PCI: 00:00.7 [1106/7259] enabled In cn400 enable_dev for device PCI: 00:01.0. PCI: 00:01.0 [1106/b198] bus ops PCI: 00:01.0 [1106/b198] enabled PCI: 00:02.0, bad id 0xffffffff PCI: 00:03.0, bad id 0xffffffff PCI: 00:04.0, bad id 0xffffffff PCI: 00:05.0, bad id 0xffffffff PCI: 00:06.0, bad id 0xffffffff PCI: 00:07.0, bad id 0xffffffff PCI: 00:08.0, bad id 0xffffffff PCI: 00:09.0, bad id 0xffffffff PCI: 00:0a.0, bad id 0xffffffff PCI: 00:0b.0, bad id 0xffffffff PCI: 00:0c.0, bad id 0xffffffff PCI: 00:0d.0, bad id 0xffffffff PCI: 00:0e.0, bad id 0xffffffff PCI: 00:0f.0 [1106/3149] ops PCI: 00:0f.0 [1106/3149] enabled PCI: 00:0f.1 [1106/0571] ops PCI: 00:0f.1 [1106/0571] enabled PCI: 00:0f.2, bad id 0xffffffff PCI: 00:0f.3, bad id 0xffffffff PCI: 00:0f.4, bad id 0xffffffff PCI: 00:0f.5, bad id 0xffffffff PCI: 00:0f.6, bad id 0xffffffff PCI: 00:0f.7, bad id 0xffffffff PCI: 00:10.0 [1106/3038] enabled PCI: 00:10.1 [1106/3038] enabled PCI: 00:10.2 [1106/3038] enabled PCI: 00:10.3 [1106/3038] enabled PCI: 00:10.4 [1106/3104] enabled malloc Enter, size 1100, free_mem_ptr 00022000 malloc 00022000 PCI: 00:10.5 [1106/d104] enabled PCI: 00:10.6, bad id 0xffffffff PCI: 00:10.7, bad id 0xffffffff PCI: 00:11.0 [1106/3227] bus ops PCI: 00:11.0 [1106/3227] enabled PCI: 00:11.1, bad id 0xffffffff PCI: 00:11.2, bad id 0xffffffff PCI: 00:11.3, bad id 0xffffffff PCI: 00:11.4, bad id 0xffffffff PCI: 00:11.5 [1106/3059] disabled PCI: 00:11.7, bad id 0xffffffff PCI: 00:12.0 [1106/3065] enabled PCI: 00:13.0, bad id 0xffffffff PCI: 00:14.0, bad id 0xffffffff PCI: 00:15.0, bad id 0xffffffff PCI: 00:16.0, bad id 0xffffffff PCI: 00:17.0, bad id 0xffffffff PCI: 00:18.0, bad id 0xffffffff PCI: 00:19.0, bad id 0xffffffff PCI: 00:1a.0, bad id 0xffffffff PCI: 00:1b.0, bad id 0xffffffff PCI: 00:1c.0, bad id 0xffffffff PCI: 00:1d.0, bad id 0xffffffff PCI: 00:1e.0, bad id 0xffffffff PCI: 00:1f.0, bad id 0xffffffff do_pci_scan_bridge for PCI: 00:01.0 PCI: pci_scan_bus for bus 01 malloc Enter, size 1100, free_mem_ptr 0002244c malloc 0002244c PCI: 01:00.0 [1106/3118] ops PCI: 01:00.0 [1106/3118] enabled PCI: 01:01.0, bad id 0xffffffff PCI: 01:02.0, bad id 0xffffffff PCI: 01:03.0, bad id 0xffffffff PCI: 01:04.0, bad id 0xffffffff PCI: 01:05.0, bad id 0xffffffff PCI: 01:06.0, bad id 0xffffffff PCI: 01:07.0, bad id 0xffffffff PCI: 01:08.0, bad id 0xffffffff PCI: 01:09.0, bad id 0xffffffff PCI: 01:0a.0, bad id 0xffffffff PCI: 01:0b.0, bad id 0xffffffff PCI: 01:0c.0, bad id 0xffffffff PCI: 01:0d.0, bad id 0xffffffff PCI: 01:0e.0, bad id 0xffffffff PCI: 01:0f.0, bad id 0xffffffff PCI: 01:10.0, bad id 0xffffffff PCI: 01:11.0, bad id 0xffffffff PCI: 01:12.0, bad id 0xffffffff PCI: 01:13.0, bad id 0xffffffff PCI: 01:14.0, bad id 0xffffffff PCI: 01:15.0, bad id 0xffffffff PCI: 01:16.0, bad id 0xffffffff PCI: 01:17.0, bad id 0xffffffff PCI: 01:18.0, bad id 0xffffffff PCI: 01:19.0, bad id 0xffffffff PCI: 01:1a.0, bad id 0xffffffff PCI: 01:1b.0, bad id 0xffffffff PCI: 01:1c.0, bad id 0xffffffff PCI: 01:1d.0, bad id 0xffffffff PCI: 01:1e.0, bad id 0xffffffff PCI: 01:1f.0, bad id 0xffffffff PCI: pci_scan_bus returning with max=001 do_pci_scan_bridge returns max 1 scan_static_bus for PCI: 00:11.0 PNP: 002e.0 disabled PNP: 002e.1 disabled PNP: 002e.2 enabled PNP: 002e.3 disabled PNP: 002e.6 disabled PNP: 002e.7 disabled PNP: 002e.8 disabled PNP: 002e.9 disabled PNP: 002e.a disabled PNP: 002e.b enabled scan_static_bus for PCI: 00:11.0 done PCI: pci_scan_bus returning with max=001 scan_static_bus for Root Device done done Allocating resources... Reading resources... Root Device read_resources bus 0 link: 0 Entering cn400_domain_read_resources. Leaving cn400_domain_read_resources. PCI_DOMAIN: 0000 read_resources bus 0 link: 0 PCI: 00:01.0 read_resources bus 1 link: 0 PCI: 00:01.0 read_resources bus 1 link: 0 done PCI: 00:11.0 read_resources bus 0 link: 0 PCI: 00:11.0 read_resources bus 0 link: 0 done PCI_DOMAIN: 0000 read_resources bus 0 link: 0 done APIC_CLUSTER: 0 read_resources bus 0 link: 0 APIC: 00 missing read_resources APIC_CLUSTER: 0 read_resources bus 0 link: 0 done Root Device read_resources bus 0 link: 0 done Done reading resources. Show resources in subtree (Root Device)...After reading. Root Device links 1 child on link 0 Root Device PCI_DOMAIN: 0000 links 1 child on link 0 PCI_DOMAIN: 0000 PCI_DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffff flags 40040100 index 10000000 PCI_DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffffffff flags 40040200 index 10000100 PCI: 00:00.0 links 0 child on link 0 NULL PCI: 00:00.1 links 0 child on link 0 NULL PCI: 00:00.2 links 0 child on link 0 NULL PCI: 00:00.3 links 0 child on link 0 NULL PCI: 00:00.4 links 0 child on link 0 NULL PCI: 00:00.7 links 0 child on link 0 NULL PCI: 00:01.0 links 1 child on link 0 PCI: 00:01.0 PCI: 01:00.0 links 0 child on link 0 NULL PCI: 01:00.0 resource base 0 size 4000000 align 26 gran 26 limit ffffffff flags 1200 index 10 PCI: 01:00.0 resource base 0 size 1000000 align 24 gran 24 limit ffffffff flags 200 index 14 PCI: 01:00.0 resource base fff80000 size 10000 align 16 gran 16 limit ffffffff flags c0002200 index 30 PCI: 00:0f.0 links 0 child on link 0 NULL PCI: 00:0f.0 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 10 PCI: 00:0f.0 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 14 PCI: 00:0f.0 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 18 PCI: 00:0f.0 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 1c PCI: 00:0f.0 resource base 0 size 10 align 4 gran 4 limit ffff flags 100 index 20 PCI: 00:0f.0 resource base 0 size 100 align 8 gran 8 limit ffff flags 100 index 24 PCI: 00:0f.1 links 0 child on link 0 NULL PCI: 00:0f.1 resource base 0 size 10 align 4 gran 4 limit ffff flags 100 index 20 PCI: 00:10.0 links 0 child on link 0 NULL PCI: 00:10.0 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 index 20 PCI: 00:10.1 links 0 child on link 0 NULL PCI: 00:10.1 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 index 20 PCI: 00:10.2 links 0 child on link 0 NULL PCI: 00:10.2 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 index 20 PCI: 00:10.3 links 0 child on link 0 NULL PCI: 00:10.3 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 index 20 PCI: 00:10.4 links 0 child on link 0 NULL PCI: 00:10.4 resource base 0 size 100 align 8 gran 8 limit ffffffff flags 200 index 10 PCI: 00:10.5 links 0 child on link 0 NULL PCI: 00:10.5 resource base 0 size 100 align 8 gran 8 limit ffffffff flags 200 index 10 PCI: 00:11.0 links 1 child on link 0 PCI: 00:11.0 PCI: 00:11.0 resource base fec00000 size 100 align 8 gran 8 limit fec000ff flags e0000200 index 44 PNP: 002e.0 links 0 child on link 0 NULL PNP: 002e.0 resource base 3f0 size 8 align 3 gran 3 limit 7ff flags c0000100 index 60 PNP: 002e.0 resource base 6 size 1 align 0 gran 0 limit 0 flags c0000400 index 70 PNP: 002e.0 resource base 2 size 1 align 0 gran 0 limit 0 flags c0000800 index 74 PNP: 002e.1 links 0 child on link 0 NULL PNP: 002e.1 resource base 378 size 8 align 3 gran 3 limit 7ff flags c0000100 index 60 PNP: 002e.1 resource base 7 size 1 align 0 gran 0 limit 0 flags c0000400 index 70 PNP: 002e.1 resource base 3 size 1 align 0 gran 0 limit 0 flags c0000800 index 74 PNP: 002e.2 links 0 child on link 0 NULL PNP: 002e.2 resource base 3f8 size 8 align 3 gran 3 limit 7ff flags c0000100 index 60 PNP: 002e.2 resource base 4 size 1 align 0 gran 0 limit 0 flags c0000400 index 70 PNP: 002e.3 links 0 child on link 0 NULL PNP: 002e.3 resource base 2f8 size 8 align 3 gran 3 limit 7ff flags c0000100 index 60 PNP: 002e.3 resource base 3 size 1 align 0 gran 0 limit 0 flags c0000400 index 70 PNP: 002e.6 links 0 child on link 0 NULL PNP: 002e.6 resource base 0 size 8 align 3 gran 3 limit 7ff flags c0000100 index 60 PNP: 002e.6 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 PNP: 002e.7 links 0 child on link 0 NULL PNP: 002e.7 resource base 201 size 1 align 0 gran 0 limit ffffffff flags c0000100 index 60 PNP: 002e.7 resource base 0 size 2 align 1 gran 1 limit 7ff flags 100 index 62 PNP: 002e.7 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 PNP: 002e.8 links 0 child on link 0 NULL PNP: 002e.8 resource base 330 size 0 align 0 gran 0 limit 0 flags c0000100 index 60 PNP: 002e.9 links 0 child on link 0 NULL PNP: 002e.9 resource base 0 size 0 align 0 gran 0 limit 0 flags c0000100 index 60 PNP: 002e.a links 0 child on link 0 NULL PNP: 002e.a resource base 0 size 0 align 0 gran 0 limit 0 flags c0000100 index 60 PNP: 002e.b links 0 child on link 0 NULL PNP: 002e.b resource base 290 size 8 align 3 gran 3 limit fff flags c0000100 index 60 PNP: 002e.b resource base 0 size 1 align 0 gran 0 limit 0 flags c0000400 index 70 PCI: 00:11.5 links 0 child on link 0 NULL PCI: 00:11.6 links 0 child on link 0 NULL PCI: 00:12.0 links 0 child on link 0 NULL PCI: 00:12.0 resource base 0 size 100 align 8 gran 8 limit ffff flags 100 index 10 PCI: 00:12.0 resource base 0 size 100 align 8 gran 8 limit ffffffff flags 200 index 14 APIC_CLUSTER: 0 links 1 child on link 0 APIC_CLUSTER: 0 APIC: 00 links 0 child on link 0 NULL PCI_DOMAIN: 0000 compute_resources_io: base: 0 size: 0 align: 0 gran: 0 limit: ffff PCI: 00:0f.0 24 * [0x0 - 0xff] io PCI: 00:12.0 10 * [0x400 - 0x4ff] io PCI: 00:10.0 20 * [0x800 - 0x81f] io PCI: 00:10.1 20 * [0x820 - 0x83f] io PCI: 00:10.2 20 * [0x840 - 0x85f] io PCI: 00:10.3 20 * [0x860 - 0x87f] io PCI: 00:0f.0 20 * [0x880 - 0x88f] io PCI: 00:0f.1 20 * [0x890 - 0x89f] io PCI: 00:0f.0 10 * [0x8a0 - 0x8a7] io PCI: 00:0f.0 18 * [0x8a8 - 0x8af] io PCI: 00:0f.0 14 * [0x8b0 - 0x8b3] io PCI: 00:0f.0 1c * [0x8b4 - 0x8b7] io PCI_DOMAIN: 0000 compute_resources_io: base: 8b8 size: 8b8 align: 8 gran: 0 limit: ffff done PCI_DOMAIN: 0000 compute_resources_mem: base: 0 size: 0 align: 0 gran: 0 limit: ffffffff PCI: 00:10.4 10 * [0x0 - 0xff] mem PCI: 00:10.5 10 * [0x100 - 0x1ff] mem PCI: 00:12.0 14 * [0x200 - 0x2ff] mem PCI_DOMAIN: 0000 compute_resources_mem: base: 300 size: 300 align: 8 gran: 0 limit: ffffffff done avoid_fixed_resources: PCI_DOMAIN: 0000 avoid_fixed_resources:@PCI_DOMAIN: 0000 10000000 limit 0000ffff avoid_fixed_resources:@PCI_DOMAIN: 0000 10000100 limit ffffffff constrain_resources: PCI_DOMAIN: 0000 constrain_resources: PCI: 00:00.0 constrain_resources: PCI: 00:00.1 constrain_resources: PCI: 00:00.2 constrain_resources: PCI: 00:00.3 constrain_resources: PCI: 00:00.4 constrain_resources: PCI: 00:00.7 constrain_resources: PCI: 00:01.0 constrain_resources: PCI: 01:00.0 constrain_resources: PCI: 00:0f.0 constrain_resources: PCI: 00:0f.1 constrain_resources: PCI: 00:10.0 constrain_resources: PCI: 00:10.1 constrain_resources: PCI: 00:10.2 constrain_resources: PCI: 00:10.3 constrain_resources: PCI: 00:10.4 constrain_resources: PCI: 00:10.5 constrain_resources: PCI: 00:11.0 constrain_resources: PNP: 002e.2 constrain_resources: PNP: 002e.b constrain_resources: PCI: 00:12.0 avoid_fixed_resources2: PCI_DOMAIN: 0000@10000000 limit 0000ffff lim->base 00000400 lim->limit 0000ffff avoid_fixed_resources2: PCI_DOMAIN: 0000@10000100 limit ffffffff lim->base 00000000 lim->limit febfffff Setting resources... PCI_DOMAIN: 0000 allocate_resources_io: base:400 size:8b8 align:8 gran:0 limit:ffff Assigned: PCI: 00:0f.0 24 * [0x400 - 0x4ff] io Assigned: PCI: 00:12.0 10 * [0x800 - 0x8ff] io Assigned: PCI: 00:10.0 20 * [0xc00 - 0xc1f] io Assigned: PCI: 00:10.1 20 * [0xc20 - 0xc3f] io Assigned: PCI: 00:10.2 20 * [0xc40 - 0xc5f] io Assigned: PCI: 00:10.3 20 * [0xc60 - 0xc7f] io Assigned: PCI: 00:0f.0 20 * [0xc80 - 0xc8f] io Assigned: PCI: 00:0f.1 20 * [0xc90 - 0xc9f] io Assigned: PCI: 00:0f.0 10 * [0xca0 - 0xca7] io Assigned: PCI: 00:0f.0 18 * [0xca8 - 0xcaf] io Assigned: PCI: 00:0f.0 14 * [0xcb0 - 0xcb3] io Assigned: PCI: 00:0f.0 1c * [0xcb4 - 0xcb7] io PCI_DOMAIN: 0000 allocate_resources_io: next_base: cb8 size: 8b8 align: 8 gran: 0 done PCI_DOMAIN: 0000 allocate_resources_mem: base:febffd00 size:300 align:8 gran:0 limit:febfffff Assigned: PCI: 00:10.4 10 * [0xfebffd00 - 0xfebffdff] mem Assigned: PCI: 00:10.5 10 * [0xfebffe00 - 0xfebffeff] mem Assigned: PCI: 00:12.0 14 * [0xfebfff00 - 0xfebfffff] mem PCI_DOMAIN: 0000 allocate_resources_mem: next_base: fec00000 size: 300 align: 8 gran: 0 done Root Device assign_resources, bus 0 link: 0 Entering cn400_domain_set_resources. Entering CN400 find_pci_tolm Leaving CN400 find_pci_tolm tomk is 0x100000, tolmk is 0x003FAFFF tom: 40000000, high_tables_base: 3bff0000, high_tables_size: 10000 PCI_DOMAIN: 0000 assign_resources, bus 0 link: 0 PCI: 00:0f.0 10 <- [0x0000000ca0 - 0x0000000ca7] size 0x00000008 gran 0x03 io PCI: 00:0f.0 14 <- [0x0000000cb0 - 0x0000000cb3] size 0x00000004 gran 0x02 io PCI: 00:0f.0 18 <- [0x0000000ca8 - 0x0000000caf] size 0x00000008 gran 0x03 io PCI: 00:0f.0 1c <- [0x0000000cb4 - 0x0000000cb7] size 0x00000004 gran 0x02 io PCI: 00:0f.0 20 <- [0x0000000c80 - 0x0000000c8f] size 0x00000010 gran 0x04 io PCI: 00:0f.0 24 <- [0x0000000400 - 0x00000004ff] size 0x00000100 gran 0x08 io PCI: 00:0f.1 20 <- [0x0000000c90 - 0x0000000c9f] size 0x00000010 gran 0x04 io PCI: 00:10.0 20 <- [0x0000000c00 - 0x0000000c1f] size 0x00000020 gran 0x05 io PCI: 00:10.1 20 <- [0x0000000c20 - 0x0000000c3f] size 0x00000020 gran 0x05 io PCI: 00:10.2 20 <- [0x0000000c40 - 0x0000000c5f] size 0x00000020 gran 0x05 io PCI: 00:10.3 20 <- [0x0000000c60 - 0x0000000c7f] size 0x00000020 gran 0x05 io PCI: 00:10.4 10 <- [0x00febffd00 - 0x00febffdff] size 0x00000100 gran 0x08 mem PCI: 00:10.5 10 <- [0x00febffe00 - 0x00febffeff] size 0x00000100 gran 0x08 mem PCI: 00:11.0 assign_resources, bus 0 link: 0 PNP: 002e.2 60 <- [0x00000003f8 - 0x00000003ff] size 0x00000008 gran 0x03 io PNP: 002e.2 70 <- [0x0000000004 - 0x0000000004] size 0x00000001 gran 0x00 irq PNP: 002e.b 60 <- [0x0000000290 - 0x0000000297] size 0x00000008 gran 0x03 io PNP: 002e.b 70 <- [0x0000000000 - 0x0000000000] size 0x00000001 gran 0x00 irq PCI: 00:11.0 assign_resources, bus 0 link: 0 PCI: 00:12.0 10 <- [0x0000000800 - 0x00000008ff] size 0x00000100 gran 0x08 io PCI: 00:12.0 14 <- [0x00febfff00 - 0x00febfffff] size 0x00000100 gran 0x08 mem PCI_DOMAIN: 0000 assign_resources, bus 0 link: 0 Leaving cn400_domain_set_resources. Root Device assign_resources, bus 0 link: 0 Done setting resources. Show resources in subtree (Root Device)...After assigning values. Root Device links 1 child on link 0 Root Device PCI_DOMAIN: 0000 links 1 child on link 0 PCI_DOMAIN: 0000 PCI_DOMAIN: 0000 resource base 400 size 8b8 align 8 gran 0 limit ffff flags 40040100 index 10000000 PCI_DOMAIN: 0000 resource base febffd00 size 300 align 8 gran 0 limit febfffff flags 40040200 index 10000100 PCI_DOMAIN: 0000 resource base 0 size a0000 align 0 gran 0 limit 0 flags e0004200 index a PCI_DOMAIN: 0000 resource base c0000 size 3bf40000 align 0 gran 0 limit 0 flags e0004200 index b PCI: 00:00.0 links 0 child on link 0 NULL PCI: 00:00.1 links 0 child on link 0 NULL PCI: 00:00.2 links 0 child on link 0 NULL PCI: 00:00.3 links 0 child on link 0 NULL PCI: 00:00.4 links 0 child on link 0 NULL PCI: 00:00.7 links 0 child on link 0 NULL PCI: 00:01.0 links 1 child on link 0 PCI: 00:01.0 PCI: 01:00.0 links 0 child on link 0 NULL PCI: 01:00.0 resource base 0 size 4000000 align 26 gran 26 limit ffffffff flags 1200 index 10 PCI: 01:00.0 resource base 0 size 1000000 align 24 gran 24 limit ffffffff flags 200 index 14 PCI: 01:00.0 resource base fff80000 size 10000 align 16 gran 16 limit ffffffff flags c0002200 index 30 PCI: 00:0f.0 links 0 child on link 0 NULL PCI: 00:0f.0 resource base ca0 size 8 align 3 gran 3 limit ffff flags 60000100 index 10 PCI: 00:0f.0 resource base cb0 size 4 align 2 gran 2 limit ffff flags 60000100 index 14 PCI: 00:0f.0 resource base ca8 size 8 align 3 gran 3 limit ffff flags 60000100 index 18 PCI: 00:0f.0 resource base cb4 size 4 align 2 gran 2 limit ffff flags 60000100 index 1c PCI: 00:0f.0 resource base c80 size 10 align 4 gran 4 limit ffff flags 60000100 index 20 PCI: 00:0f.0 resource base 400 size 100 align 8 gran 8 limit ffff flags 60000100 index 24 PCI: 00:0f.1 links 0 child on link 0 NULL PCI: 00:0f.1 resource base c90 size 10 align 4 gran 4 limit ffff flags 60000100 index 20 PCI: 00:10.0 links 0 child on link 0 NULL PCI: 00:10.0 resource base c00 size 20 align 5 gran 5 limit ffff flags 60000100 index 20 PCI: 00:10.1 links 0 child on link 0 NULL PCI: 00:10.1 resource base c20 size 20 align 5 gran 5 limit ffff flags 60000100 index 20 PCI: 00:10.2 links 0 child on link 0 NULL PCI: 00:10.2 resource base c40 size 20 align 5 gran 5 limit ffff flags 60000100 index 20 PCI: 00:10.3 links 0 child on link 0 NULL PCI: 00:10.3 resource base c60 size 20 align 5 gran 5 limit ffff flags 60000100 index 20 PCI: 00:10.4 links 0 child on link 0 NULL PCI: 00:10.4 resource base febffd00 size 100 align 8 gran 8 limit febfffff flags 60000200 index 10 PCI: 00:10.5 links 0 child on link 0 NULL PCI: 00:10.5 resource base febffe00 size 100 align 8 gran 8 limit febfffff flags 60000200 index 10 PCI: 00:11.0 links 1 child on link 0 PCI: 00:11.0 PCI: 00:11.0 resource base fec00000 size 100 align 8 gran 8 limit fec000ff flags e0000200 index 44 PNP: 002e.0 links 0 child on link 0 NULL PNP: 002e.0 resource base 3f0 size 8 align 3 gran 3 limit 7ff flags c0000100 index 60 PNP: 002e.0 resource base 6 size 1 align 0 gran 0 limit 0 flags c0000400 index 70 PNP: 002e.0 resource base 2 size 1 align 0 gran 0 limit 0 flags c0000800 index 74 PNP: 002e.1 links 0 child on link 0 NULL PNP: 002e.1 resource base 378 size 8 align 3 gran 3 limit 7ff flags c0000100 index 60 PNP: 002e.1 resource base 7 size 1 align 0 gran 0 limit 0 flags c0000400 index 70 PNP: 002e.1 resource base 3 size 1 align 0 gran 0 limit 0 flags c0000800 index 74 PNP: 002e.2 links 0 child on link 0 NULL PNP: 002e.2 resource base 3f8 size 8 align 3 gran 3 limit 7ff flags e0000100 index 60 PNP: 002e.2 resource base 4 size 1 align 0 gran 0 limit 0 flags e0000400 index 70 PNP: 002e.3 links 0 child on link 0 NULL PNP: 002e.3 resource base 2f8 size 8 align 3 gran 3 limit 7ff flags c0000100 index 60 PNP: 002e.3 resource base 3 size 1 align 0 gran 0 limit 0 flags c0000400 index 70 PNP: 002e.6 links 0 child on link 0 NULL PNP: 002e.6 resource base 0 size 8 align 3 gran 3 limit 7ff flags c0000100 index 60 PNP: 002e.6 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 PNP: 002e.7 links 0 child on link 0 NULL PNP: 002e.7 resource base 201 size 1 align 0 gran 0 limit ffffffff flags c0000100 index 60 PNP: 002e.7 resource base 0 size 2 align 1 gran 1 limit 7ff flags 100 index 62 PNP: 002e.7 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 PNP: 002e.8 links 0 child on link 0 NULL PNP: 002e.8 resource base 330 size 0 align 0 gran 0 limit 0 flags c0000100 index 60 PNP: 002e.9 links 0 child on link 0 NULL PNP: 002e.9 resource base 0 size 0 align 0 gran 0 limit 0 flags c0000100 index 60 PNP: 002e.a links 0 child on link 0 NULL PNP: 002e.a resource base 0 size 0 align 0 gran 0 limit 0 flags c0000100 index 60 PNP: 002e.b links 0 child on link 0 NULL PNP: 002e.b resource base 290 size 8 align 3 gran 3 limit fff flags e0000100 index 60 PNP: 002e.b resource base 0 size 1 align 0 gran 0 limit 0 flags e0000400 index 70 PCI: 00:11.5 links 0 child on link 0 NULL PCI: 00:11.6 links 0 child on link 0 NULL PCI: 00:12.0 links 0 child on link 0 NULL PCI: 00:12.0 resource base 800 size 100 align 8 gran 8 limit ffff flags 60000100 index 10 PCI: 00:12.0 resource base febfff00 size 100 align 8 gran 8 limit febfffff flags 60000200 index 14 APIC_CLUSTER: 0 links 1 child on link 0 APIC_CLUSTER: 0 APIC: 00 links 0 child on link 0 NULL Done allocating resources. Enabling resources... PCI: 00:00.0 cmd <- 06 PCI: 00:00.1 subsystem <- 00/00 PCI: 00:00.1 cmd <- 06 PCI: 00:00.2 subsystem <- 00/00 PCI: 00:00.2 cmd <- 06 PCI: 00:00.4 subsystem <- 00/00 PCI: 00:00.4 cmd <- 06 PCI: 00:00.7 subsystem <- 00/00 PCI: 00:00.7 cmd <- 06 PCI: 00:01.0 bridge ctrl <- 0003 PCI: 00:01.0 cmd <- 07 PCI: 01:00.0 cmd <- 00 PCI: 00:0f.0 cmd <- 01 PCI: 00:0f.1 cmd <- 81 PCI: 00:10.0 subsystem <- 00/00 PCI: 00:10.0 cmd <- 01 PCI: 00:10.1 subsystem <- 00/00 PCI: 00:10.1 cmd <- 01 PCI: 00:10.2 subsystem <- 00/00 PCI: 00:10.2 cmd <- 01 PCI: 00:10.3 subsystem <- 00/00 PCI: 00:10.3 cmd <- 01 PCI: 00:10.4 subsystem <- 00/00 PCI: 00:10.4 cmd <- 02 PCI: 00:10.5 cmd <- 02 PCI: 00:11.0 cmd <- 07 PCI: 00:12.0 subsystem <- 00/00 PCI: 00:12.0 cmd <- 83 done. Initializing devices... Root Device init PCI: 00:00.0 init Enabling AGP. PCI: 00:00.1 init PCI: 00:00.2 init PCI: 00:00.3 init Entering cn400 memctrl_init. Low Top Address = 0x03F0 Leaving cn400 memctrl_init. PCI: 00:00.4 init PCI: 00:00.7 init PCI: 00:01.0 init Setting up AGP bridge device PCI: 00:0f.0 init Configuring VIA SATA controller PCI: 00:0f.1 init Primary IDE interface enabled Secondary IDE interface enabled Enables in reg 0x40 read back as 0x4f Enables in reg 0x42 read back as 0x9 PCI: 00:10.0 init PCI: 00:10.1 init PCI: 00:10.2 init PCI: 00:10.3 init PCI: 00:10.4 init PCI: 00:11.0 init Entering vt8237r_init. vt8237r_init SATA LED. vt8237r_init PCI Req. vt8237r_init CPU Rst. vt8237r_init Read Pass Write Ctrl. vt8237r_init calling southbridge_init_common. RTC Init RTC: Checksum invalid zeroing cmos Invalid CMOS LB checksum Keyboard init... Keyboard selftest failed ACK: 0xfe Leaving vt8237r_init. PNP: 002e.2 init PNP: 002e.b init PCI: 00:12.0 init APIC_CLUSTER: 0 init malloc Enter, size 1100, free_mem_ptr 00022898 malloc 00022898 Initializing CPU #0 CPU: vendor Centaur device 69a CPU: family 06, model 09, stepping 0a Using generic cpu ops (good) Enabling cache Setting fixed MTRRs(0-88) Type: UC Setting fixed MTRRs(0-16) Type: WB Setting fixed MTRRs(24-88) Type: WB DONE fixed MTRRs call enable_fixed_mtrr() Setting variable MTRR 0, base: 0MB, range: 512MB, type WB ADDRESS_MASK_HIGH=0xf Setting variable MTRR 1, base: 512MB, range: 256MB, type WB ADDRESS_MASK_HIGH=0xf Setting variable MTRR 2, base: 768MB, range: 128MB, type WB ADDRESS_MASK_HIGH=0xf Setting variable MTRR 3, base: 896MB, range: 64MB, type WB ADDRESS_MASK_HIGH=0xf Zero-sized MTRR range @0KB DONE variable MTRRs Clear out the extra MTRR's call enable_var_mtrr() Leave x86_setup_var_mtrrs MTRR check Fixed MTRRs : Enabled Variable MTRRs: Enabled Disabling local apic...done. CPU #0 initialized PCI: 00:10.5 init PCI: 01:00.0 init Copying BOCHS BIOS from 0xFFF90000 to 0xf000 Initializing VGA INSTALL REAL-MODE IDT DO THE VGA BIOS found VGA: vid=1106, did=3118 VGA BIOS ROM base address: fff80000 bus/devfn = 0x100 biosint: INT# 0x1a biosint: eax 0xb108 ebx 0x6b0100 ecx 0x301 edx 0x3000115 biosint: ebp 0x20fd2 esp 0xf7c edi 0x10008 esi 0x4677 biosint: ip 0xcbdc cs 0xc000 flags 0x46 0xb108: bus 1 devfn 0x0 reg 0x8 val 0x2 Devices initialized Show all devs...After init. Root Device: enabled 1, 0 resources PCI_DOMAIN: 0000: enabled 1, 4 resources PCI: 00:00.0: enabled 1, 0 resources PCI: 00:00.1: enabled 1, 0 resources PCI: 00:00.2: enabled 1, 0 resources PCI: 00:00.3: enabled 1, 0 resources PCI: 00:00.4: enabled 1, 0 resources PCI: 00:00.7: enabled 1, 0 resources PCI: 00:01.0: enabled 1, 0 resources PCI: 00:0f.0: enabled 1, 6 resources PCI: 00:0f.1: enabled 1, 1 resources PCI: 00:10.0: enabled 1, 1 resources PCI: 00:10.1: enabled 1, 1 resources PCI: 00:10.2: enabled 1, 1 resources PCI: 00:10.3: enabled 1, 1 resources PCI: 00:10.4: enabled 1, 1 resources PCI: 00:11.0: enabled 1, 1 resources PNP: 002e.0: enabled 0, 3 resources PNP: 002e.1: enabled 0, 3 resources PNP: 002e.2: enabled 1, 2 resources PNP: 002e.3: enabled 0, 2 resources PNP: 002e.6: enabled 0, 2 resources PNP: 002e.7: enabled 0, 3 resources PNP: 002e.8: enabled 0, 1 resources PNP: 002e.9: enabled 0, 1 resources PNP: 002e.a: enabled 0, 1 resources PNP: 002e.b: enabled 1, 2 resources PCI: 00:11.5: enabled 0, 0 resources PCI: 00:11.6: enabled 0, 0 resources PCI: 00:12.0: enabled 1, 2 resources APIC_CLUSTER: 0: enabled 1, 0 resources APIC: 00: enabled 1, 0 resources PCI: 00:10.5: enabled 1, 1 resources PCI: 01:00.0: enabled 1, 3 resources CPU: 00: enabled 1, 0 resources High Tables Base is 3bff0000. Copying Interrupt Routing Table to 0x000f0000... done. Copying Interrupt Routing Table to 0x3bff0000... done. ACPI: Writing ACPI tables at 3bff0400... ACPI: * FACS ACPI: * DSDT @ 3bff04a8 Length 3b8 ACPI: * FADT ACPI: added table 1/8 Length now 40 ACPI: done. Moving GDT to 0x3bff0c00...ok Multiboot Information structure has been written. Writing high table forward entry at 0x00000500 Wrote coreboot table at: 00000500 - 00000518 checksum b3df New low_table_end: 0x00000518 Now going to write high coreboot table at 0x3bff1000 rom_table_end = 0x3bff1000 Adjust low_table_end from 0x00000518 to 0x00001000 Adjust rom_table_end from 0x3bff1000 to 0x3c000000 Adding high table area Wrote coreboot table at: 3bff1000 - 3bff1698 checksum f4ab elfboot: Attempting to load payload. rom_stream: 0xfffa0000 - 0xfffdffff Found ELF candidate at offset 0 header_offset is 0 Try to load at offset 0x0 malloc Enter, size 32, free_mem_ptr 00022ce4 malloc 00022ce4 New segment addr 0x100000 size 0x3a2410 offset 0xe0 filesize 0x1ac00 (cleaned up) New segment addr 0x100000 size 0x3a2410 offset 0xe0 filesize 0x1ac00 lb: [0x0000000000004000, 0x0000000000026000) malloc Enter, size 32, free_mem_ptr 00022d04 malloc 00022d04 New segment addr 0x4a2420 size 0x48 offset 0x1ace0 filesize 0x48 (cleaned up) New segment addr 0x4a2420 size 0x48 offset 0x1ace0 filesize 0x48 lb: [0x0000000000004000, 0x0000000000026000) Dropping non PT_LOAD segment Dropping non PT_LOAD segment Dropping non PT_LOAD segment Loading Segment: addr: 0x0000000000100000 memsz: 0x00000000003a2410 filesz: 0x000000000001ac00 [ 0x0000000000100000, 000000000011ac00, 0x00000000004a2410) <- 00000000000000e0 Clearing Segment: addr: 0x000000000011ac00 memsz: 0x0000000000387810 Loading Segment: addr: 0x00000000004a2420 memsz: 0x0000000000000048 filesz: 0x0000000000000048 [ 0x00000000004a2420, 00000000004a2468, 0x00000000004a2468) <- 000000000001ace0 Loaded segments verified segments closed down stream Jumping to boot code at 00100088 entry = 0x00100088 lb_start = 0x00004000 lb_size = 0x00022000 adjust = 0x3bfca000 buffer = 0x3bfac000 elf_boot_notes = 0x0001c000 adjusted_boot_notes = 0x3bfe6000 FILO version 0.6.0 (jon(a)localhost.localdomain) Tue Jul 14 16:23:39 BST 2009 ERROR: No such CMOS option (boot_devices) menu: hda1:/filo/menu.lst Booting 'hda1:/vmlinuz-2.6.25-14.fc9.i686 ro root=/dev/sda5 acpi=force console= ttyS0,115200n8 initrd=hda1:/initrd-2.6.25-14.fc9.i686.img' Found Linux version 2.6.25-14.fc9.i686 (mockbuild@) #1 SMP Thu May 1 06:28:41 E DT 2008 (protocol 0x207) (loadflags 0x1) bzImage. Setting up paramters at 0x90000 %016Lx - %016Lx (0) %016Lx - %016Lx (4096) %016Lx - %016Lx (786432) %016Lx - %016Lx (1006567424) ramtop=0x3c000000 ext_mem_k=64512, alt_mem_k=982016 original command line: "ro root=/dev/sda5 acpi=force console=ttyS0,115200n8 ini trd=hda1:/initrd-2.6.25-14.fc9.i686.img" kernel command line at 0x91000 initrd=hda1:/initrd-2.6.25-14.fc9.i686.img kernel command line (51 bytes): "ro root=/dev/sda5 acpi=force console=ttyS0,115 200n8" offset=0x3200 addr=0x100000 size=0x1fab60 Loading kernel... ok start=0x3b9c7000 end=0x3bc4cc24 Loading initrd... ok eip=0x100000 Jumping to entry point... Initializing cgroup subsys cpuset Initializing cgroup subsys cpu Linux version 2.6.25-14.fc9.i686 (mockbuild@) (gcc version 4.3.0 20080428 (Red Hat 4.3.0-8) (GCC) ) #1 SMP Thu May 1 06:28:41 EDT 20 08 BIOS-provided physical RAM map: BIOS-e820: 0000000000000000 - 0000000000001000 type 16 BIOS-e820: 0000000000001000 - 00000000000a0000 (usable) BIOS-e820: 0000000000100000 - 000000003bff0000 (usable) BIOS-e820: 000000003bff0000 - 000000003c000000 type 16 63MB HIGHMEM available. 896MB LOWMEM available. Scan SMP from c0000000 for 1024 bytes. Scan SMP from c009fc00 for 1024 bytes. Scan SMP from c00f0000 for 65536 bytes. Using x86 segment limits to approximate NX protection Zone PFN ranges: DMA 0 -> 4096 Normal 4096 -> 229376 HighMem 229376 -> 245744 Movable zone start PFN for each node early_node_map[1] active PFN ranges 0: 0 -> 245744 DMI not present or invalid. Using APIC driver default ACPI: RSDP 000F0400, 0024 (r2 CORE ) ACPI: RSDT 3BFF0424, 0028 (r1 CORE RSDT 0 CORE 0) ACPI: FACP 3BFF0860, 00F4 (r4 COREBO COREBOOT 0 CORE 2A) ACPI: DSDT 3BFF04A8, 03B8 (r1 CBT-V2 CBT-DSDT 1 INTL 20061109) ACPI: FACS 3BFF0468, 0040 ACPI: no DMI BIOS year, acpi=force is required to enable ACPI ACPI: acpi=force override ACPI: PM-Timer IO Port: 0x508 Allocating PCI resources starting at 40000000 (gap: 3c000000:c4000000) PM: Registered nosave memory: 00000000000a0000 - 0000000000100000 Built 1 zonelists in Zone order, mobility grouping on. Total pages: 243825 Kernel command line: ro root=/dev/sda5 acpi=force console=ttyS0,115200n8 No local APIC present or hardware disabled Enabling fast FPU save and restore... done. Enabling unmasked SIMD FPU exception support... done. Initializing CPU#0 CPU 0 irqstacks, hard=c07b9000 soft=c0799000 PID hash table entries: 4096 (order: 12, 16384 bytes) Detected 800.075 MHz processor. Console: colour VGA+ 80x25 console [ttyS0] enabled Dentry cache hash table entries: 131072 (order: 7, 524288 bytes) Inode-cache hash table entries: 65536 (order: 6, 262144 bytes) Memory: 966672k/982976k available (2236k kernel code, 15644k reserved, 1121k data, 284k init, 65472k highmem) virtual kernel memory layout: fixmap : 0xffc53000 - 0xfffff000 (3760 kB) pkmap : 0xff400000 - 0xff800000 (4096 kB) vmalloc : 0xf8800000 - 0xff3fe000 ( 107 MB) lowmem : 0xc0000000 - 0xf8000000 ( 896 MB) .init : 0xc074f000 - 0xc0796000 ( 284 kB) .data : 0xc062f37d - 0xc0747800 (1121 kB) .text : 0xc0400000 - 0xc062f37d (2236 kB) Checking if this processor honours the WP bit even in supervisor mode...Ok. SLUB: Genslabs=12, HWalign=32, Order=0-1, MinObjects=4, CPUs=1, Nodes=1 Calibrating delay using timer specific routine.. 1602.22 BogoMIPS (lpj=801113) Security Framework initialized SELinux: Initializing. selinux_register_security: Registering secondary module capability Capability LSM initialized as secondary Mount-cache hash table entries: 512 Initializing cgroup subsys ns Initializing cgroup subsys cpuacct CPU: L1 I Cache: 64K (32 bytes/line), D cache 64K (32 bytes/line) CPU: L2 Cache: 64K (32 bytes/line) Compat vDSO mapped to ffffe000. Checking 'hlt' instruction... OK. SMP alternatives: switching to UP code Freeing SMP alternatives: 20k freed ACPI: Core revision 20070126 ACPI: setting ELCR to 0200 (from 0000) CPU0: Centaur VIA Nehemiah stepping 0a SMP motherboard not detected. Local APIC not detected. Using dummy APIC emulation. Brought up 1 CPUs net_namespace: 548 bytes Booting paravirtualized kernel on bare hardware Time: 16:28:00 Date: 07/14/09 NET: Registered protocol family 16 No dock devices found. ACPI FADT declares the system doesn't support MSI, so disable it ACPI: bus type pci registered PCI: Using configuration type 1 Setting up standard PCI resources ACPI: Interpreter enabled ACPI: (supports S0 S5) ACPI: Using PIC for interrupt routing ACPI: PCI Root Bridge [PCI0] (0000:00) ACPI: PCI Interrupt Link [LNKA] (IRQs 3 4 6 7 *10 11 12) ACPI: PCI Interrupt Link [LNKB] (IRQs 3 4 6 7 10 *11 12) ACPI: PCI Interrupt Link [LNKC] (IRQs 3 4 6 7 10 11 *12) ACPI: PCI Interrupt Link [LNKD] (IRQs 3 4 6 7 *10 11 12) Linux Plug and Play Support v0.97 (c) Adam Belay pnp: PnP ACPI init ACPI: bus type pnp registered pnp: PnP ACPI: found 0 devices ACPI: ACPI bus type pnp unregistered usbcore: registered new interface driver usbfs usbcore: registered new interface driver hub usbcore: registered new device driver usb PCI: Using ACPI for IRQ routing PCI: If a device doesn't work, try "pci=routeirq". If it helps, post a report NetLabel: Initializing NetLabel: domain hash size = 128 NetLabel: protocols = UNLABELED CIPSOv4 NetLabel: unlabeled traffic allowed by default PCI: Bridge: 0000:00:01.0 IO window: d000-dfff MEM window: 0xfb000000-0xfcffffff PREFETCH window: 0x00000000f4000000-0x00000000f7ffffff NET: Registered protocol family 2 IP route cache hash table entries: 32768 (order: 5, 131072 bytes) TCP established hash table entries: 131072 (order: 8, 1048576 bytes) TCP bind hash table entries: 65536 (order: 7, 524288 bytes) TCP: Hash tables configured (established 131072 bind 65536) TCP reno registered checking if image is initramfs... it is Freeing initrd memory: 2583k freed apm: BIOS not found. audit: initializing netlink socket (disabled) type=2000 audit(1247588880.216:1): initialized highmem bounce pool size: 64 pages Total HugeTLB memory allocated, 0 VFS: Disk quotas dquot_6.5.1 Dquot-cache hash table entries: 1024 (order 0, 4096 bytes) Block layer SCSI generic (bsg) driver version 0.4 loaded (major 252) io scheduler noop registered io scheduler anticipatory registered io scheduler deadline registered io scheduler cfq registered (default) PCI: VIA PCI bridge detected. Disabling DAC. pci_hotplug: PCI Hot Plug PCI Core version: 0.5 ACPI: ACPI0007:00 is registered as cooling_device0 isapnp: Scanning for PnP cards... isapnp: No Plug & Play device found Non-volatile memory driver v1.2 Linux agpgart interface v0.103 agpgart: Detected VIA PM800/PN800/PM880/PN880 chipset agpgart: AGP aperture is 32M @ 0xf8000000 Serial: 8250/16550 driver $Revision: 1.90 $ 4 ports, IRQ sharing enabled ÿserial8250: ttyS0 at I/O 0x3f8 (irq = 4) is a 16550A brd: module loaded input: Macintosh mouse button emulation as /devices/virtual/input/input0 PNP: No PS/2 controller found. Probing ports directly. serio: i8042 KBD port at 0x60,0x64 irq 1 serio: i8042 AUX port at 0x60,0x64 irq 12 mice: PS/2 mouse device common for all mice cpuidle: using governor ladder cpuidle: using governor menu usbcore: registered new interface driver hiddev usbcore: registered new interface driver usbhid drivers/hid/usbhid/hid-core.c: v2.6:USB HID core driver TCP cubic registered Initializing XFRM netlink socket NET: Registered protocol family 1 NET: Registered protocol family 17 Using IPI No-Shortcut mode registered taskstats version 1 Magic number: 1:680:489 Freeing unused kernel memory: 284k freed Write protecting the kernel read-only data: 908k Red Hat nash version 6.0.52 starting Mounting proc filesystem Mounting sysfs filesystem Creating /dev Creating initial device nodes Setting up hotplug. Creating block device nodes. Loading ehci-hcd module ACPI: PCI Interrupt Link [LNKC] enabled at IRQ 12 ACPI: PCI Interrupt 0000:00:10.4[C] -> <3>irq 12: nobody cared (try booting with the "irqpoll" option) Pid: 345, comm: modprobe Not tainted 2.6.25-14.fc9.i686 #1 [<c045ccd8>] __report_bad_irq+0x2e/0x6f [<c045cedb>] note_interrupt+0x1c2/0x21b [<c045c574>] ? handle_IRQ_event+0x2a/0x5a [<c045d53c>] handle_level_irq+0x8e/0xbe [<c045d4ae>] ? handle_level_irq+0x0/0xbe [<c0407eb4>] do_IRQ+0x98/0xc4 [<c04065e7>] common_interrupt+0x23/0x28 [<c042bfb7>] ? __do_softirq+0x5b/0xe7 [<c0407ddb>] do_softirq+0x74/0xb5 [<c045d4ae>] ? handle_level_irq+0x0/0xbe [<c042bddd>] irq_exit+0x38/0x6b [<c0407ec8>] do_IRQ+0xac/0xc4 [<c04065e7>] common_interrupt+0x23/0x28 [<c04282b7>] ? vprintk+0x2fc/0x330 [<c0531d5f>] ? acpi_pci_link_allocate_irq+0x199/0x1d6 [<c05adc9c>] ? eisa_set_level_irq+0x4c/0x66 [<c05320f6>] ? acpi_pci_irq_enable+0x165/0x1c4 [<c05ae897>] ? pcibios_enable_device+0x22/0x27 [<c04fdb84>] ? do_pci_enable_device+0x22/0x38 [<c04fdc01>] ? __pci_enable_device_flags+0x67/0x84 [<c04fdc2d>] ? pci_enable_device+0xf/0x11 [<c057e593>] ? usb_hcd_pci_probe+0x39/0x316 [<c04fea0f>] ? pci_match_device+0x8f/0x95 [<c04feac9>] ? pci_device_probe+0x39/0x59 [<c0562826>] ? driver_probe_device+0xa0/0x136 [<c0562935>] ? __driver_attach+0x79/0xaf [<c05621d3>] ? bus_for_each_dev+0x3b/0x63 [<c05626cb>] ? driver_attach+0x14/0x16 [<c05628bc>] ? __driver_attach+0x0/0xaf [<c0561ba4>] ? bus_add_driver+0x9d/0x1ba [<c0562ab8>] ? driver_register+0x47/0xa7 [<c047592d>] ? __vunmap+0x93/0x9b [<c04fec75>] ? __pci_register_driver+0x35/0x64 [<f882b025>] ? ehci_hcd_init+0x25/0x2b [ehci_hcd] [<c0446f93>] ? sys_init_module+0x17be/0x18f6 [<c04d3577>] ? selinux_file_permission+0x100/0x106 [<c0571957>] ? usb_root_hub_lost_power+0x0/0x2f [<c04cc41c>] ? security_file_permission+0xf/0x11 [<c04835e1>] ? sys_read+0x3b/0x60 [<c0405bf2>] ? syscall_call+0x7/0xb ======================= handlers: [<c0583513>] (i8042_interrupt+0x0/0x1e7) Disabling IRQ #12 Link [LNKC] -> GSI 12 (level, low) -> IRQ 12 ehci_hcd 0000:00:10.4: VIA VLink IRQ fixup, from 0 to 12 ehci_hcd 0000:00:10.4: EHCI Host Controller ehci_hcd 0000:00:10.4: new USB bus registered, assigned bus number 1 ehci_hcd 0000:00:10.4: irq 12, io mem 0xfebffd00 ehci_hcd 0000:00:10.4: USB 2.0 started, EHCI 1.00, driver 10 Dec 2004 usb usb1: configuration #1 chosen from 1 choice hub 1-0:1.0: USB hub found hub 1-0:1.0: 8 ports detected usb usb1: New USB device found, idVendor=1d6b, idProduct=0002 usb usb1: New USB device strings: Mfr=3, Product=2, SerialNumber=1 usb usb1: Product: EHCI Host Controller usb usb1: Manufacturer: Linux 2.6.25-14.fc9.i686 ehci_hcd usb usb1: SerialNumber: 0000:00:10.4 Loading ohci-hcd module Loading uhci-hcd module USB Universal Host Controller Interface driver v3.0 ACPI: PCI Interrupt Link [LNKA] enabled at IRQ 10 ACPI: PCI Interrupt 0000:00:10.0[A] -> Link [LNKA] -> GSI 10 (level, low) -> IRQ 10 uhci_hcd 0000:00:10.0: VIA VLink IRQ fixup, from 0 to 10 uhci_hcd 0000:00:10.0: UHCI Host Controller uhci_hcd 0000:00:10.0: new USB bus registered, assigned bus number 2 uhci_hcd 0000:00:10.0: irq 10, io base 0x00000c00 uhci_hcd 0000:00:10.0: host system error, PCI problems? uhci_hcd 0000:00:10.0: host controller halted, very bad! uhci_hcd 0000:00:10.0: HC died; cleaning up uhci_hcd 0000:00:10.0: USB bus 2 deregistered ACPI: PCI interrupt for device 0000:00:10.0 disabled uhci_hcd 0000:00:10.0: init 0000:00:10.0 fail, -108 uhci_hcd: probe of 0000:00:10.0 failed with error -108 ACPI: PCI Interrupt 0000:00:10.1[A] -> Link [LNKA] -> GSI 10 (level, low) -> IRQ 10 uhci_hcd 0000:00:10.1: VIA VLink IRQ fixup, from 0 to 10 uhci_hcd 0000:00:10.1: UHCI Host Controller uhci_hcd 0000:00:10.1: new USB bus registered, assigned bus number 2 uhci_hcd 0000:00:10.1: irq 10, io base 0x00000c20 uhci_hcd 0000:00:10.1: host system error, PCI problems? uhci_hcd 0000:00:10.1: host controller halted, very bad! uhci_hcd 0000:00:10.1: HC died; cleaning up uhci_hcd 0000:00:10.1: USB bus 2 deregistered ACPI: PCI interrupt for device 0000:00:10.1 disabled uhci_hcd 0000:00:10.1: init 0000:00:10.1 fail, -108 uhci_hcd: probe of 0000:00:10.1 failed with error -108 ACPI: PCI Interrupt Link [LNKB] enabled at IRQ 11 ACPI: PCI Interrupt 0000:00:10.2[B] -> Link [LNKB] -> GSI 11 (level, low) -> IRQ 11 uhci_hcd 0000:00:10.2: VIA VLink IRQ fixup, from 0 to 11 uhci_hcd 0000:00:10.2: UHCI Host Controller uhci_hcd 0000:00:10.2: new USB bus registered, assigned bus number 2 uhci_hcd 0000:00:10.2: irq 11, io base 0x00000c40 uhci_hcd 0000:00:10.2: host system error, PCI problems? uhci_hcd 0000:00:10.2: host controller halted, very bad! uhci_hcd 0000:00:10.2: HC died; cleaning up uhci_hcd 0000:00:10.2: USB bus 2 deregistered ACPI: PCI interrupt for device 0000:00:10.2 disabled uhci_hcd 0000:00:10.2: init 0000:00:10.2 fail, -108 uhci_hcd: probe of 0000:00:10.2 failed with error -108 ACPI: PCI Interrupt 0000:00:10.3[B] -> Link [LNKB] -> GSI 11 (level, low) -> IRQ 11 uhci_hcd 0000:00:10.3: VIA VLink IRQ fixup, from 0 to 11 uhci_hcd 0000:00:10.3: UHCI Host Controller uhci_hcd 0000:00:10.3: new USB bus registered, assigned bus number 2 uhci_hcd 0000:00:10.3: irq 11, io base 0x00000c60 uhci_hcd 0000:00:10.3: host system error, PCI problems? uhci_hcd 0000:00:10.3: host controller halted, very bad! uhci_hcd 0000:00:10.3: HC died; cleaning up uhci_hcd 0000:00:10.3: USB bus 2 deregistered ACPI: PCI interrupt for device 0000:00:10.3 disabled uhci_hcd 0000:00:10.3: init 0000:00:10.3 fail, -108 uhci_hcd: probe of 0000:00:10.3 failed with error -108 Loading ext2 module Loading scsi_mod module SCSI subsystem initialized Loading sd_mod module Driver 'sd' needs updating - please use bus_type methods Loading libata module Loading sata_via module ACPI: PCI Interrupt 0000:00:0f.0[B] -> Link [LNKB] -> GSI 11 (level, low) -> IRQ 11 sata_via 0000:00:0f.0: VIA VLink IRQ fixup, from 0 to 11 sata_via 0000:00:0f.0: routed to hard irq line 11 scsi0 : sata_via scsi1 : sata_via ata1: SATA max UDMA/133 cmd 0xca0 ctl 0xcb0 bmdma 0xc80 irq 11 ata2: SATA max UDMA/133 cmd 0xca8 ctl 0xcb4 bmdma 0xc88 irq 11 ata1: SATA link up 1.5 Gbps (SStatus 113 SControl 300) ata1.00: ATA-7: ST9120822AS, 3.ALC, max UDMA/133 ata1.00: 234441648 sectors, multi 0: LBA48 NCQ (depth 0/32) ata1.00: configured for UDMA/133 ata2: SATA link down 1.5 Gbps (SStatus 0 SControl 300) scsi 0:0:0:0: Direct-Access ATA ST9120822AS 3.AL PQ: 0 ANSI: 5 sd 0:0:0:0: [sda] 234441648 512-byte hardware sectors (120034 MB) sd 0:0:0:0: [sda] Write Protect is off sd 0:0:0:0: [sda] Write cache: enabled, read cache: enabled, doesn't support DPO or FUA sd 0:0:0:0: [sda] 234441648 512-byte hardware sectors (120034 MB) sd 0:0:0:0: [sda] Write Protect is off sd 0:0:0:0: [sda] Write cache: enabled, read cache: enabled, doesn't support DPO or FUA sda: SELEX Sensors and Airborne Systems Limited Registered Office: Sigma House, Christopher Martin Road, Basildon, Essex SS14 3EL A company registered in England & Wales. Company no. 02426132 ******************************************************************** This email and any attachments are confidential to the intended recipient and may also be privileged. If you are not the intended recipient please delete it from your system and notify the sender. You should not copy it or use it for any purpose nor disclose or distribute its contents to any other person. ********************************************************************

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Re: [coreboot] [PATCH] CN400 / EPIA-NL [v2] patch
by Harrison, Jon (SELEX GALILEO, UK) 14 Jul '09

14 Jul '09

Peter, See below. If this patch can't go in as it is then it'll have to wait until I've got the time to break the patches up, I have another patch coming soon to add initial ACPI support, which seems to be just about working. Jon -----Original Message----- From: coreboot-bounces(a)coreboot.org [mailto:coreboot-bounces@coreboot.org] On Behalf Of coreboot-request(a)coreboot.org Sent: 13 July 2009 19:57 To: coreboot(a)coreboot.org Subject: coreboot Digest, Vol 53, Issue 56 ------------------------------ Message: 3 Date: Mon, 13 Jul 2009 14:02:29 +0200 From: Peter Stuge <peter(a)stuge.se> To: coreboot(a)coreboot.org Subject: Re: [coreboot] [PATCH] CN400 / EPIA-NL [v2] patch Message-ID: <20090713120229.9595.qmail(a)stuge.se> Content-Type: text/plain; charset=us-ascii Hi Jon, I did have a look but didn't send out comments. I still have a few thoughts.. Content-Description: cn400-patch-v6.patch > Index: src/mainboard/via/epia-n/Config.lb .. > -chip northbridge/via/cn400 # Northbridge > - > - device apic_cluster 0 on # APIC cluster > - chip cpu/via/model_c3 # VIA C3 > - device apic 0 on end # APIC > - end > - end >This apic_cluster block is moved to be last within the cn400 block, >does it matter if it comes first or last? I don't know. It works this way round and it's now consistent with the epia-cn > +chip northbridge/via/cn400 # Northbridge .. > - device pci_domain 0 on # PCI domain > + device pci_domain 0 on # PCI domain >The patch still has some whitespace changes in Config.lb. >I know how things move around while working, but it would be so nice >to not have whitespace changes in patches that are sent for review. >Everyone, please review your patches yourself before sending out. These whitespace fixes come for free with the re-jig of the Config.lb order > Index: src/northbridge/via/cn400/raminit.c .. > - //print_val("\r\nBank 0 (*32 Mb) ",c); > - .. > - //print_val("\r\nTotal Memory (*32 Mb) ",c); .. > - /* Graphics Control Basic Init. */ > - //pci_write_config8(ctrl.d0f3, 0xb0, 0xFf); > - //pci_write_config8(ctrl.d0f3, 0xb1, 0xAA); > - //pci_write_config8(ctrl.d0f3, 0xb2, 0xAA); > - //pci_write_config8(ctrl.d0f3, 0xb3, 0x5A); > - //pci_write_config8(ctrl.d0f3, 0xb4, 0x0f); > - > - /* AGP Controller Interface Basic Init */ > - //pci_write_config8(ctrl.d0f3, 0xc0, 0x3b); > - > - /* VGA device, Basic frame Buffer Init. */ > - //pci_write_config8(ctrl.d0f3, 0xa0, 0x01); > - /* Bit 7 = Enable VGA When Set to 1 */ > - //pci_write_config8(ctrl.d0f3, 0xa1, 0xef); > - //pci_write_config8(ctrl.d0f3, 0xa4, 0x00); >Should these and all other removed comments be a separate patch? Are >they related to the other changes in this patch? Just part of the general tidy up before moving on. > Index: src/northbridge/via/cn400/northbridge.c .. > static u32 find_pci_tolm(struct bus *bus) > { > - struct resource *min; > + struct resource *min = NULL; > u32 tolm; > > - print_debug("Entering CN400 find_pci_tolm\n"); > + printk_spew("Entering CN400 find_pci_tolm\n"); > > - min = 0; > search_bus_resources(bus, IORESOURCE_MEM, IORESOURCE_MEM, > tolm_test, &min); > tolm = 0xffffffffUL; > if (min && tolm > min->base) > tolm = min->base; > > - print_debug("Leaving find_pci_tolm\n"); > + printk_spew("Leaving CN400 find_pci_tolm\n"); > > return tolm; > } >This hunk doesn't change functionality much, it seems to only change >debugging, but if you prefer this way then I think that's fine. Again this is just for consistency with the rest of the code. >Thanks >//Peter SELEX Sensors and Airborne Systems Limited Registered Office: Sigma House, Christopher Martin Road, Basildon, Essex SS14 3EL A company registered in England & Wales. Company no. 02426132 ******************************************************************** This email and any attachments are confidential to the intended recipient and may also be privileged. If you are not the intended recipient please delete it from your system and notify the sender. You should not copy it or use it for any purpose nor disclose or distribute its contents to any other person. ********************************************************************

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coreboot on Intel GM45 and ICH9M-E ?
by Stephan Raue 14 Jul '09

14 Jul '09

Is it possible to run coreoot on a Gigabyte GA-6QPCV-RH with Intel GM45 and ICH9M-E and ITE IT8718F Super I/O ? http://www.gigabyte.com.tw/Products/Networking/Products_Spec.aspx?ProductID… Details: Processor Supported * Intel® Celeron M585/M575 series processor * Socket P with 667/800/1066MHz Chipset Description * Intel® GM45 * Intel® ICH9M-E System Memory * 2 x DDR2 SO-DIMM sockets * Up to 4GB 667/800 memory System BIOS * PhoenixBIOS on 8Mb flash ROM Integrated Super I/O Controller * ITE IT8718F Super I/O Integrated SATA Controller * Intel®ICH9M-E with RAID 0,1 * 4 SATA connectors Integrated Network * Intel® 82567LM and 82574L GbE controllers * Supports iAMT function (Only 82567LM) Expansion Slot * 1 PCI slots 32-Bit/33MHz * 1 mini card slot (PCI-E x1/ USB 2.0) Integrated Video Controller * Intel® GMA 4500AHD 3D Graphic Engine * Shared system memory up to 256MB On Board Connectors * 1 x 24bit LVDS connector * 1 x 19V_IN DC power connector * 4 x SATA connectors * 2 x Serial connectors (COM) * 1 x front audio connector * 3 x USB 2.0 connectors for additional 6 ports by cable * 1 x front panel connecctor * 1 x System fan cable connector * 1 x CPU fan cable connector Rear I/O Connectors * 1 x SPDIF Out (Optical + Coaxial) * 1 x YPbPr prot (HDTV out ) * 1 x HDMI port * 1 x VGA port * 4 x USB 2.0 ports * 2 x LAN RJ45 ports * 1 HD Audio jacks (Line-out / MIC-in / Line-in/Cen/SURR) can configure 7.1 channel output by utility Board Dimension * Mini ITX form factor * 170mmx170mm -- ### OpenELEC.tv ### The free and open Mediacenter Distribution 4 you http://www.openelec.tv

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[PATCH] Fix out{b,l} buglets
by Ed Swierk 13 Jul '09

13 Jul '09

Apparently I'm not the only one who forgets which way the outb and outl arguments go. Signed-off-by: Ed Swierk <eswierk(a)aristanetworks.com> --- Index: coreboot-v2/src/southbridge/broadcom/bcm5785/bcm5785_sb_pci_main.c =================================================================== --- coreboot-v2/src/southbridge/broadcom/bcm5785/bcm5785_sb_pci_main.c (revision 4415) +++ coreboot-v2/src/southbridge/broadcom/bcm5785/bcm5785_sb_pci_main.c (working copy) @@ -38,7 +38,7 @@ byte |= ( 1 << 7); // Can not mask NMI from PCI-E and NMI_NOW } if( byte != byte_old) { - outb(0x70, byte); + outb(byte, 0x70); } Index: coreboot-v2/src/southbridge/nvidia/ck804/ck804_lpc.c =================================================================== --- coreboot-v2/src/southbridge/nvidia/ck804/ck804_lpc.c (revision 4415) +++ coreboot-v2/src/southbridge/nvidia/ck804/ck804_lpc.c (working copy) @@ -245,7 +245,7 @@ byte |= (1 << 7); /* Can't mask NMI from PCI-E and NMI_NOW. */ } if (byte != byte_old) - outb(0x70, byte); + outb(byte, 0x70); /* Initialize the real time clock (RTC). */ rtc_init(0); Index: coreboot-v2/src/southbridge/nvidia/mcp55/mcp55_lpc.c =================================================================== --- coreboot-v2/src/southbridge/nvidia/mcp55/mcp55_lpc.c (revision 4415) +++ coreboot-v2/src/southbridge/nvidia/mcp55/mcp55_lpc.c (working copy) @@ -230,7 +230,7 @@ byte |= ( 1 << 7); // Can not mask NMI from PCI-E and NMI_NOW } if( byte != byte_old) { - outb(0x70, byte); + outb(byte, 0x70); } /* Initialize the real time clock */ Index: coreboot-v2/src/southbridge/sis/sis966/sis966_lpc.c =================================================================== --- coreboot-v2/src/southbridge/sis/sis966/sis966_lpc.c (revision 4415) +++ coreboot-v2/src/southbridge/sis/sis966/sis966_lpc.c (working copy) @@ -220,7 +220,7 @@ byte |= ( 1 << 7); // Can not mask NMI from PCI-E and NMI_NOW } if( byte != byte_old) { - outb(0x70, byte); + outb(byte, 0x70); } /* Initialize the real time clock */ Index: coreboot-v2/src/cpu/amd/sc520/raminit.c =================================================================== --- coreboot-v2/src/cpu/amd/sc520/raminit.c (revision 4415) +++ coreboot-v2/src/cpu/amd/sc520/raminit.c (working copy) @@ -183,16 +183,16 @@ /* Stepan says: This needs to go to the msm586seg code */ /* "enumerate" the PCI. Mainly set the interrupt bits on the PCnetFast. */ - outl(0xcf8, 0x08000683c); - outl(0xcfc, 0xc); /* set the interrupt line */ + outl(0x08000683c, 0xcf8); + outl(0xc, 0xcfc); /* set the interrupt line */ /* Set the SC520 PCI host bridge to target mode to * allow external bus mastering events */ /* index the status command register on device 0*/ - outl(0x0cf8,0x080000004); - outl(0xcfc, 0x2); /*set the memory access enable bit*/ + outl(0x080000004, 0x0cf8); + outl(0x2, 0xcfc); /*set the memory access enable bit*/ OUTC(0x0fffef072, 1); /* enable req bits in SYSARBMENB */ }

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ACPI on m57sli v1.0
by Andreas B. Mundt 13 Jul '09

13 Jul '09

Hi everybody, with the help of Harald's seaBIOS-payload I managed to run the latest coreboot (revision 4387) on my v1.0 m57sli-board. From a first look everything seems to work: kvm, sound, power-now frequency scaling. dmesg is attached for proprietary and free bios. Minor issues: coreboot ACPI: hda: host side 80-wire cable detection failed, limiting max speed to UDMA33 hda: UDMA/33 mode selected [...] powernow-k8: Found 1 AMD Athlon(tm) 64 X2 Dual Core Processor 4800+ processors (2 cpu cores) (version 2.20.00) powernow-k8: 0 : fid 0x11 (2500 MHz), vid 0x9 powernow-k8: 1 : fid 0x10 (2400 MHz), vid 0xa powernow-k8: 2 : fid 0xe (2200 MHz), vid 0xc powernow-k8: 3 : fid 0xc (2000 MHz), vid 0xe powernow-k8: 4 : fid 0x2 (1000 MHz), vid 0x12 powernow-k8: ph2 null fid transition 0x11 proprietary: hda: UDMA/66 mode selected [...] powernow-k8: Found 1 AMD Athlon(tm) 64 X2 Dual Core Processor 4800+ processors (2 cpu cores) (version 2.20.00) powernow-k8: 0 : fid 0x11 (2500 MHz), vid 0x9 powernow-k8: 1 : fid 0x10 (2400 MHz), vid 0xa powernow-k8: 2 : fid 0xe (2200 MHz), vid 0xc powernow-k8: 3 : fid 0xc (2000 MHz), vid 0xe powernow-k8: 4 : fid 0xa (1800 MHz), vid 0x10 powernow-k8: 5 : fid 0x2 (1000 MHz), vid 0x12 Many thanks to everybody involved! I'll run my board now fulltime coreboot! Regards Andi

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Re: [coreboot] [PATCH] CN400 / EPIA-NL [v2] patch
by Peter Stuge 13 Jul '09

13 Jul '09

Hi Jon, I did have a look but didn't send out comments. I still have a few thoughts.. Harrison, Jon (SELEX GALILEO, UK) wrote: > ******************************************************************** > This email and any attachments are confidential to the intended > recipient and may also be privileged. If you are not the intended > recipient please delete it from your system and notify the sender. > You should not copy it or use it for any purpose nor disclose or > distribute its contents to any other person. > ******************************************************************** Unrelated, but maybe talk to your systems administrator about this, it doesn't make much sense on a public mailing list - and who sends confidential email without encryption anyway? ;) Content-Description: cn400-patch-v6.patch > Index: src/mainboard/via/epia-n/Config.lb .. > -chip northbridge/via/cn400 # Northbridge > - > - device apic_cluster 0 on # APIC cluster > - chip cpu/via/model_c3 # VIA C3 > - device apic 0 on end # APIC > - end > - end This apic_cluster block is moved to be last within the cn400 block, does it matter if it comes first or last? > +chip northbridge/via/cn400 # Northbridge .. > - device pci_domain 0 on # PCI domain > + device pci_domain 0 on # PCI domain The patch still has some whitespace changes in Config.lb. I know how things move around while working, but it would be so nice to not have whitespace changes in patches that are sent for review. Everyone, please review your patches yourself before sending out. > Index: src/northbridge/via/cn400/raminit.c .. > - //print_val("\r\nBank 0 (*32 Mb) ",c); > - .. > - //print_val("\r\nTotal Memory (*32 Mb) ",c); .. > - /* Graphics Control Basic Init. */ > - //pci_write_config8(ctrl.d0f3, 0xb0, 0xFf); > - //pci_write_config8(ctrl.d0f3, 0xb1, 0xAA); > - //pci_write_config8(ctrl.d0f3, 0xb2, 0xAA); > - //pci_write_config8(ctrl.d0f3, 0xb3, 0x5A); > - //pci_write_config8(ctrl.d0f3, 0xb4, 0x0f); > - > - /* AGP Controller Interface Basic Init */ > - //pci_write_config8(ctrl.d0f3, 0xc0, 0x3b); > - > - /* VGA device, Basic frame Buffer Init. */ > - //pci_write_config8(ctrl.d0f3, 0xa0, 0x01); > - /* Bit 7 = Enable VGA When Set to 1 */ > - //pci_write_config8(ctrl.d0f3, 0xa1, 0xef); > - //pci_write_config8(ctrl.d0f3, 0xa4, 0x00); Should these and all other removed comments be a separate patch? Are they related to the other changes in this patch? > Index: src/northbridge/via/cn400/northbridge.c .. > static u32 find_pci_tolm(struct bus *bus) > { > - struct resource *min; > + struct resource *min = NULL; > u32 tolm; > > - print_debug("Entering CN400 find_pci_tolm\n"); > + printk_spew("Entering CN400 find_pci_tolm\n"); > > - min = 0; > search_bus_resources(bus, IORESOURCE_MEM, IORESOURCE_MEM, > tolm_test, &min); > tolm = 0xffffffffUL; > if (min && tolm > min->base) > tolm = min->base; > > - print_debug("Leaving find_pci_tolm\n"); > + printk_spew("Leaving CN400 find_pci_tolm\n"); > > return tolm; > } This hunk doesn't change functionality much, it seems to only change debugging, but if you prefer this way then I think that's fine. Thanks //Peter

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Re: [coreboot] [PATCH] CN400 / EPIA-NL [v2] patch
by Harrison, Jon (SELEX GALILEO, UK) 13 Jul '09

13 Jul '09

Hi Peter, Don't think I saw an Ack to this patch, is there anything else you would like done with the patch? Thanks, Jon -----Original Message----- From: coreboot-bounces(a)coreboot.org [mailto:coreboot-bounces@coreboot.org] On Behalf Of coreboot-request(a)coreboot.org Sent: 08 July 2009 10:58 To: coreboot(a)coreboot.org Subject: coreboot Digest, Vol 53, Issue 43 ------------------------------ Message: 7 Date: Wed, 8 Jul 2009 10:57:58 +0100 From: "Harrison, Jon (SELEX GALILEO, UK)" <jon.harrison(a)selexgalileo.com> To: <coreboot(a)coreboot.org>, <peter(a)stuge.se> Subject: Re: [coreboot] [PATCH] CN400 / EPIA-NL [v2] patch Message-ID: <8E520A5E7FB8D647BFDA039F6031C1C60586D903(a)desmdswms201.des.grplnk.net> Content-Type: text/plain; charset="us-ascii" Peter, Attached is v6 of the CN400/EPIA-N(L) patch for Coreboot V2, addressing your earlier comments on v5 of the patch. This has been built and tested against R4407 on an EPIA-NL 8000, fitted with 1GB DDR400 SDRAM. The status as follows: 1/ Board sucessfully boots and launches FILO 0.6.0 payload. 2/ VGA framebuffer seems to work OK. (with factory VGA BIOS and BOCHS helpers) TODO:: 1/ ACPI to be integrated with build 2/ Fix file headers for accuracy 3/ Tidy up comments/whitespace stuff 4/ Get FILO to actually start a kernel from SATA Signed-off-by: Jon Harrison <bothyln(a)blueyonder.co.uk> SELEX Sensors and Airborne Systems Limited Registered Office: Sigma House, Christopher Martin Road, Basildon, Essex SS14 3EL A company registered in England & Wales. Company no. 02426132 ******************************************************************** This email and any attachments are confidential to the intended recipient and may also be privileged. If you are not the intended recipient please delete it from your system and notify the sender. You should not copy it or use it for any purpose nor disclose or distribute its contents to any other person. ********************************************************************

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bios_extract.
by Luc Verhaegen 13 Jul '09

13 Jul '09

As many probably know already, i have been poking on cleaning up some code that has been floating around the web to extract individual modules out of common legacy bios images. It's called bios_extract and it should be able to extract award, standard phoenix and ami bioses. It contains code and information retrieved from code of both Anton Borisov and Veit Kannegieser, and the lh5 extraction routine was stripped out of lha. The tree can be found here, the git-uri is also available from this page: http://cgit.freedesktop.org/~libv/bios_extract/ Simply point it to a bios image, and watch it clutter up your working directory. If it doesn't work for you, you know where to find me :) Enjoy, Luc Verhaegen.

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coreboot July 2009