coreboot July 2009

coreboot@coreboot.org

75 participants
304 discussions

GPLv2 vs GPLv3
by Joseph Smith 08 Jul '09

08 Jul '09

Hello, This has probably been discussed before but what are the pros and cons of GPLv2 and GPLv3? -- Thanks, Joseph Smith Set-Top-Linux www.settoplinux.org

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Re: [coreboot] error in Building coreboot: Corrupt rom -- found no header at 2031584
by Myles Watson 08 Jul '09

08 Jul '09

> I used the following command to build the coreboot payload: > mkelfImage --append="console=ttyS0" --initrd=/boot/initrd.img-2.6.27-7- > generic /boot/vmlinuz-2.6.27-7-generic linux.elf > > and when i executed the 'make' command from the targets/emulation/qemu- > x86/qemu-x86 directory i got the error message as: > Corrupt rom -- found no header at 2031584 How big is your payload. It looks like it is too big to fit in the space that's left. Thanks, Myles

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Re: [coreboot] error in Building coreboot: Corrupt rom -- found no header at 2031584
by ron minnich 08 Jul '09

08 Jul '09

2097152 any reason for that size? I have had this problem but I think only when I somehow misconfigured the ROM sizes. What parts of coreboot have you changed? ron

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Holding the s2895 in reset powers off the machine
by Myles Watson 08 Jul '09

08 Jul '09

I have two boards, the s2892 and the s2895. I can power on the s2892 while holding in reset, but the s2895 powers off after a second. Any guesses where I'd look for the solution? SuperIO or Southbridge? The factory BIOS has the same behavior. Thanks, Myles

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Re: [coreboot] [PATCH] CN400 / EPIA-NL [v2] patch
by Harrison, Jon (SELEX GALILEO, UK) 08 Jul '09

08 Jul '09

Peter, Attached is v6 of the CN400/EPIA-N(L) patch for Coreboot V2, addressing your earlier comments on v5 of the patch. This has been built and tested against R4407 on an EPIA-NL 8000, fitted with 1GB DDR400 SDRAM. The status as follows: 1/ Board sucessfully boots and launches FILO 0.6.0 payload. 2/ VGA framebuffer seems to work OK. (with factory VGA BIOS and BOCHS helpers) TODO:: 1/ ACPI to be integrated with build 2/ Fix file headers for accuracy 3/ Tidy up comments/whitespace stuff 4/ Get FILO to actually start a kernel from SATA Signed-off-by: Jon Harrison <bothyln(a)blueyonder.co.uk> SELEX Sensors and Airborne Systems Limited Registered Office: Sigma House, Christopher Martin Road, Basildon, Essex SS14 3EL A company registered in England & Wales. Company no. 02426132 ******************************************************************** This email and any attachments are confidential to the intended recipient and may also be privileged. If you are not the intended recipient please delete it from your system and notify the sender. You should not copy it or use it for any purpose nor disclose or distribute its contents to any other person. ********************************************************************

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Re: [coreboot] [PATCH] CN400 / EPIA-NL [v2] patch
by Harrison, Jon (SELEX GALILEO, UK) 08 Jul '09

08 Jul '09

Hi Peter, I'll rework the patch a bit then. Thanks for the spot on the second part, I thought I'd taken that out already. Ta, Jon ------------------------------ Message: 4 Date: Tue, 7 Jul 2009 18:30:55 +0200 From: Peter Stuge <peter(a)stuge.se> To: coreboot(a)coreboot.org Subject: Re: [coreboot] [PATCH] CN400 / EPIA-NL [v2] patch Message-ID: <20090707163055.13999.qmail(a)stuge.se> Content-Type: text/plain; charset=us-ascii Hey Jon, Harrison, Jon (SELEX GALILEO, UK) wrote: > Attached is v5 of the CN400/EPIA-NL patch for Coreboot V2. > > This has been built and tested against R4404. > > The status as follows: > 1/ Board sucessfully boots and launches FILO 0.6.0 payload. > 2/ VGA framebuffer seems to work OK. (with factory VGA BIOS and BOCHS > helpers) Nice progress! Other than my few concerns, I think this is a good patch. Content-Description: cn400-patch-v5.patch > Index: src/mainboard/via/epia-n/Config.lb .. > -chip northbridge/via/cn400 # Northbridge .. > +chip northbridge/via/cn400 # Northbridge It seems that there are quite a few whitespace only changes in this patch. It would be very helpful if you could split up the patch into several parts; one for functional changes and one for whitespace corrections. > Index: src/northbridge/via/cn400/northbridge.c .. > @@ -193,27 +202,29 @@ > > /* > * Once the register value is not zero, the RAM size is > - * this register's value multiply 64 * 1024 * 1024. > - */ > + * this register's value multiply 32 * 1024 * 1024. > + * > for (rambits = 0, i = 0; i < ARRAY_SIZE(ramregs); i++) { > rambits = pci_read_config8(mc_dev, ramregs[i]); > if (rambits != 0) > break; > } > - > - tomk = rambits * 64 * 1024; > - printk_spew("tomk is 0x%x\n", tomk); > + */ > + rambits = pci_read_config8(mc_dev, 0x47); > + tomk = rambits * 32 * 1024; This hunk is really too tricky. Please remove the lines if they should not be in there. Thanks! //Peter SELEX Sensors and Airborne Systems Limited Registered Office: Sigma House, Christopher Martin Road, Basildon, Essex SS14 3EL A company registered in England & Wales. Company no. 02426132 ******************************************************************** This email and any attachments are confidential to the intended recipient and may also be privileged. If you are not the intended recipient please delete it from your system and notify the sender. You should not copy it or use it for any purpose nor disclose or distribute its contents to any other person. ********************************************************************

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error in Building coreboot: Corrupt rom -- found no header at 2031584
by Anurag_Vashisth 08 Jul '09

08 Jul '09

Hi All, I am trying to build the coreboot-v2-4304 following the link on the page: http://www.coreboot.org/QEMU_Build_Tutorial I've installed mkelfImage 2.7 I used the following command to build the coreboot payload: mkelfImage --append="console=ttyS0" --initrd=/boot/initrd.img-2.6.27-7-generic /boot/vmlinuz-2.6.27-7-generic linux.elf and when i executed the 'make' command from the targets/emulation/qemu-x86/qemu-x86 directory i got the error message as: Corrupt rom -- found no header at 2031584 make: *** [coreboot.rom] Error 1 fro more details see the attachment of the output of make command. i used gcc version 4.3.2 Please suggest the solution. Thanks Anurag Vashisth +919739278384 DISCLAIMER: This email (including any attachments) is intended for the sole use of the intended recipient/s and may contain material that is CONFIDENTIAL AND PRIVATE COMPANY INFORMATION. Any review or reliance by others or copying or distribution or forwarding of any or all of the contents in this message is STRICTLY PROHIBITED. If you are not the intended recipient, please contact the sender by email and delete all copies; your cooperation in this regard is appreciated.

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Dell XS11-VX8 AKA Fortuna
by Peter Stuge 08 Jul '09

08 Jul '09

Ron, I think they saw your minicluster and wanted one of their own. http://www.youtube.com/watch?v=QT8wEgjwr7k Pretty interesting coreboot prospect too. //Peter

2 1

Interesting device enumeration problem
by Myles Watson 08 Jul '09

08 Jul '09

I tried to disable the onboard graphics on my s2892: device pci 6.0 off end But that made it probe 6.1 - 6.7. Since the code only checks for multifunction devices at function 0, all of those responded. So now instead of disabling my card, it had 7 instances of it. I realize that the card probably shouldn't have responded to all of those functions, but it probably doesn't bother checking which function is addressed. device pci 6.0 off end device pci 6.1 off end device pci 6.2 off end device pci 6.3 off end device pci 6.4 off end device pci 6.5 off end device pci 6.6 off end device pci 6.7 off end This worked, but it is non-obvious. I wonder what the "right" way would be to handle this. Is there any time when you want to disable function 0 but still have all the other functions enabled/probed? Thanks, Myles

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Trac email interface?
by Peter Stuge 07 Jul '09

07 Jul '09

Could this be a viable interface for those who would like to use Trac more, but prefer to work mainly in an email application? https://subtrac.sara.nl/oss/email2trac/wiki/Email2tracParse //Peter

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coreboot July 2009