coreboot July 2009

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build service results for r4385
by coreboot information 01 Jul '09

01 Jul '09

Dear coreboot readers! This is the automatic build system of coreboot. The developer "zbao" checked in revision 4385 to the coreboot repository. This caused the following changes: Change Log: Add AMD family 10 AM2r2 support. Coreboot used to take SYSTEM_TYPE as a lable to tell what the socket is. This patch replaces (some of, not all) CONFIG_SYSTEM_TYPE with CONFIG_SOCKET_TYPE. It also fix some compiling error in src/northbridge/amd/amdmct/mct/mctardk4.c Signed-off-by: Zheng Bao <zheng.bao(a)amd.com> Acked-by: Marc Jones <marcj303(a)gmail.com> Build Log: Compilation of motorola:sandpointx3_altimus_mpc7410 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4385&device=sandpointx3_al… Compilation of via:epia-m700 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4385&device=epia-m700&vend… If something broke during this checkin please be a pain in zbao's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

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[v2] r4385 - in trunk/coreboot-v2/src: cpu/amd cpu/amd/socket_AM2r2 northbridge/amd/amdfam10 northbridge/amd/amdmct/mct northbridge/amd/amdmct/wrappers
by svn＠coreboot.org 01 Jul '09

01 Jul '09

Author: zbao Date: 2009-07-01 09:01:32 +0200 (Wed, 01 Jul 2009) New Revision: 4385 Added: trunk/coreboot-v2/src/cpu/amd/socket_AM2r2/ trunk/coreboot-v2/src/cpu/amd/socket_AM2r2/Config.lb trunk/coreboot-v2/src/cpu/amd/socket_AM2r2/chip.h trunk/coreboot-v2/src/cpu/amd/socket_AM2r2/socket_AM2r2.c Modified: trunk/coreboot-v2/src/northbridge/amd/amdfam10/raminit_amdmct.c trunk/coreboot-v2/src/northbridge/amd/amdmct/mct/mctardk4.c trunk/coreboot-v2/src/northbridge/amd/amdmct/wrappers/mcti_d.c Log: Add AMD family 10 AM2r2 support. Coreboot used to take SYSTEM_TYPE as a lable to tell what the socket is. This patch replaces (some of, not all) CONFIG_SYSTEM_TYPE with CONFIG_SOCKET_TYPE. It also fix some compiling error in src/northbridge/amd/amdmct/mct/mctardk4.c Signed-off-by: Zheng Bao <zheng.bao(a)amd.com> Acked-by: Marc Jones <marcj303(a)gmail.com> Added: trunk/coreboot-v2/src/cpu/amd/socket_AM2r2/Config.lb =================================================================== --- trunk/coreboot-v2/src/cpu/amd/socket_AM2r2/Config.lb (rev 0) +++ trunk/coreboot-v2/src/cpu/amd/socket_AM2r2/Config.lb 2009-07-01 07:01:32 UTC (rev 4385) @@ -0,0 +1,54 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2007 Advanced Micro Devices, Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +# + +uses CONFIG_PCI_IO_CFG_EXT +uses CONFIG_MMCONF_SUPPORT +uses CONFIG_HT3_SUPPORT +uses CONFIG_EXT_RT_TBL_SUPPORT +uses CONFIG_EXT_CONF_SUPPORT +uses CONFIG_DIMM_SUPPORT +uses CONFIG_CPU_SOCKET_TYPE +uses CONFIG_CBB +uses CONFIG_CDB +uses CONFIG_PCI_BUS_SEGN_BITS +uses CONFIG_CAR_FAM10 + +config chip.h + +default CONFIG_PCI_IO_CFG_EXT=1 + +default CONFIG_HT3_SUPPORT=1 +default CONFIG_EXT_RT_TBL_SUPPORT=0 +default CONFIG_EXT_CONF_SUPPORT=0 +default CONFIG_DIMM_SUPPORT=0x0104 #DDR2 and REG +default CONFIG_CPU_SOCKET_TYPE=0x11 + +default CONFIG_CAR_FAM10=1 + +if CONFIG_EXT_RT_TBL_SUPPORT + default CONFIG_CBB=0xff + default CONFIG_CDB=0 +end + +#default CONFIG_MMCONF_SUPPORT=1 +#default CONFIG_MMCONF_SUPPORT_DEFAULT=1 + +object socket_AM2r2.o + +dir /cpu/amd/model_10xxx Added: trunk/coreboot-v2/src/cpu/amd/socket_AM2r2/chip.h =================================================================== --- trunk/coreboot-v2/src/cpu/amd/socket_AM2r2/chip.h (rev 0) +++ trunk/coreboot-v2/src/cpu/amd/socket_AM2r2/chip.h 2009-07-01 07:01:32 UTC (rev 4385) @@ -0,0 +1,23 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +extern struct chip_operations cpu_amd_socket_AM2r2_ops; + +struct cpu_amd_socket_AM2r2_config { +}; Added: trunk/coreboot-v2/src/cpu/amd/socket_AM2r2/socket_AM2r2.c =================================================================== --- trunk/coreboot-v2/src/cpu/amd/socket_AM2r2/socket_AM2r2.c (rev 0) +++ trunk/coreboot-v2/src/cpu/amd/socket_AM2r2/socket_AM2r2.c 2009-07-01 07:01:32 UTC (rev 4385) @@ -0,0 +1,25 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <device/device.h> +#include "chip.h" + +struct chip_operations cpu_amd_socket_AM2r2_ops = { + CHIP_NAME("socket AM2r2") +}; Modified: trunk/coreboot-v2/src/northbridge/amd/amdfam10/raminit_amdmct.c =================================================================== --- trunk/coreboot-v2/src/northbridge/amd/amdfam10/raminit_amdmct.c 2009-06-30 17:13:58 UTC (rev 4384) +++ trunk/coreboot-v2/src/northbridge/amd/amdfam10/raminit_amdmct.c 2009-07-01 07:01:32 UTC (rev 4385) @@ -63,10 +63,10 @@ #include "../amdmct/mct/mctndi_d.c" #include "../amdmct/mct/mctchi_d.c" -#if SYSTEM_TYPE == SERVER +#if CONFIG_CPU_SOCKET_TYPE == 0x10 //L1 #include "../amdmct/mct/mctardk3.c" -#elif SYSTEM_TYPE == DESKTOP +#elif CONFIG_CPU_SOCKET_TYPE == 0x11 //AM2 #include "../amdmct/mct/mctardk4.c" //#elif SYSTEM_TYPE == MOBILE Modified: trunk/coreboot-v2/src/northbridge/amd/amdmct/mct/mctardk4.c =================================================================== --- trunk/coreboot-v2/src/northbridge/amd/amdmct/mct/mctardk4.c 2009-06-30 17:13:58 UTC (rev 4384) +++ trunk/coreboot-v2/src/northbridge/amd/amdmct/mct/mctardk4.c 2009-07-01 07:01:32 UTC (rev 4385) @@ -25,7 +25,7 @@ void mctGet_PS_Cfg_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, u32 dct) - +{ print_tx("dct: ", dct); print_tx("Speed: ", pDCTstat->Speed); @@ -66,42 +66,43 @@ */ static const u8 Table_ATC_ODC_D_Bx[] = { - 1, 0xFF, 0x00, 0x2F, 0x2F, 0x0, 0x22, 0x13, 0x11, 0x0 - 2, 12, 0x00, 0x2F, 0x2F, 0x0, 0x22, 0x13, 0x11, 0x0 - 2, 16, 0x00, 0x2F, 0x00, 0x0, 0x22, 0x13, 0x11, 0x0 - 2, 20, 0x00, 0x2F, 0x38, 0x0, 0x22, 0x13, 0x11, 0x0 - 2, 24, 0x00, 0x2F, 0x37, 0x0, 0x22, 0x13, 0x11, 0x0 - 2, 32, 0x00, 0x2F, 0x34, 0x0, 0x22, 0x13, 0x11, 0x0 - 3, 12, 0x20, 0x22, 0x20, 0x0, 0x22, 0x13, 0x11, 0x0 - 3, 16, 0x20, 0x22, 0x30, 0x0, 0x22, 0x13, 0x11, 0x0 - 3, 20, 0x20, 0x22, 0x2C, 0x0, 0x22, 0x13, 0x11, 0x0 - 3, 24, 0x20, 0x22, 0x2A, 0x0, 0x22, 0x13, 0x11, 0x0 - 3, 32, 0x20, 0x22, 0x2B, 0x0, 0x22, 0x13, 0x11, 0x0 - 4, 0xFF, 0x20, 0x25, 0x20, 0x0, 0x22, 0x33, 0x11, 0x0 - 5, 0xFF, 0x20, 0x20, 0x2F, 0x0, 0x22, 0x32, 0x11, 0x0 - 0FFh + 1, 0xFF, 0x00, 0x2F, 0x2F, 0x0, 0x22, 0x13, 0x11, 0x0, + 2, 12, 0x00, 0x2F, 0x2F, 0x0, 0x22, 0x13, 0x11, 0x0, + 2, 16, 0x00, 0x2F, 0x00, 0x0, 0x22, 0x13, 0x11, 0x0, + 2, 20, 0x00, 0x2F, 0x38, 0x0, 0x22, 0x13, 0x11, 0x0, + 2, 24, 0x00, 0x2F, 0x37, 0x0, 0x22, 0x13, 0x11, 0x0, + 2, 32, 0x00, 0x2F, 0x34, 0x0, 0x22, 0x13, 0x11, 0x0, + 3, 12, 0x20, 0x22, 0x20, 0x0, 0x22, 0x13, 0x11, 0x0, + 3, 16, 0x20, 0x22, 0x30, 0x0, 0x22, 0x13, 0x11, 0x0, + 3, 20, 0x20, 0x22, 0x2C, 0x0, 0x22, 0x13, 0x11, 0x0, + 3, 24, 0x20, 0x22, 0x2A, 0x0, 0x22, 0x13, 0x11, 0x0, + 3, 32, 0x20, 0x22, 0x2B, 0x0, 0x22, 0x13, 0x11, 0x0, + 4, 0xFF, 0x20, 0x25, 0x20, 0x0, 0x22, 0x33, 0x11, 0x0, + 5, 0xFF, 0x20, 0x20, 0x2F, 0x0, 0x22, 0x32, 0x11, 0x0, + 0xFF +}; static const u8 Table_ATC_ODC_D_Ax[] = { - 1, 0xFF, 0x00, 0x2F, 0x2F, 0x0, 0x22, 0x13, 0x11, 0x0 - 2, 12, 0x00, 0x2F, 0x2F, 0x0, 0x22, 0x13, 0x11, 0x0 - 2, 16, 0x00, 0x2F, 0x00, 0x0, 0x22, 0x13, 0x11, 0x0 - 2, 20, 0x00, 0x2F, 0x38, 0x0, 0x22, 0x13, 0x11, 0x0 - 2, 24, 0x00, 0x2F, 0x37, 0x0, 0x22, 0x13, 0x11, 0x0 - 2, 32, 0x00, 0x2F, 0x34, 0x0, 0x22, 0x13, 0x11, 0x0 - 3, 12, 0x20, 0x22, 0x20, 0x0, 0x22, 0x13, 0x11, 0x0 - 3, 16, 0x20, 0x22, 0x30, 0x0, 0x22, 0x13, 0x11, 0x0 - 3, 20, 0x20, 0x22, 0x2C, 0x0, 0x22, 0x13, 0x11, 0x0 - 3, 24, 0x20, 0x22, 0x2A, 0x0, 0x22, 0x13, 0x11, 0x0 - 3, 32, 0x20, 0x22, 0x2B, 0x0, 0x22, 0x13, 0x11, 0x0 - 4, 0xFF, 0x20, 0x25, 0x20, 0x0, 0x22, 0x33, 0x11, 0x0 - 5, 0xFF, 0x20, 0x20, 0x2F, 0x0, 0x22, 0x32, 0x11, 0x0 + 1, 0xFF, 0x00, 0x2F, 0x2F, 0x0, 0x22, 0x13, 0x11, 0x0, + 2, 12, 0x00, 0x2F, 0x2F, 0x0, 0x22, 0x13, 0x11, 0x0, + 2, 16, 0x00, 0x2F, 0x00, 0x0, 0x22, 0x13, 0x11, 0x0, + 2, 20, 0x00, 0x2F, 0x38, 0x0, 0x22, 0x13, 0x11, 0x0, + 2, 24, 0x00, 0x2F, 0x37, 0x0, 0x22, 0x13, 0x11, 0x0, + 2, 32, 0x00, 0x2F, 0x34, 0x0, 0x22, 0x13, 0x11, 0x0, + 3, 12, 0x20, 0x22, 0x20, 0x0, 0x22, 0x13, 0x11, 0x0, + 3, 16, 0x20, 0x22, 0x30, 0x0, 0x22, 0x13, 0x11, 0x0, + 3, 20, 0x20, 0x22, 0x2C, 0x0, 0x22, 0x13, 0x11, 0x0, + 3, 24, 0x20, 0x22, 0x2A, 0x0, 0x22, 0x13, 0x11, 0x0, + 3, 32, 0x20, 0x22, 0x2B, 0x0, 0x22, 0x13, 0x11, 0x0, + 4, 0xFF, 0x20, 0x25, 0x20, 0x0, 0x22, 0x33, 0x11, 0x0, + 5, 0xFF, 0x20, 0x20, 0x2F, 0x0, 0x22, 0x32, 0x11, 0x0, 0xFF }; static void Get_ChannelPS_Cfg0_D( u8 MAAdimms, u8 Speed, u8 MAAload, u8 DATAAload, u32 *AddrTmgCTL, u32 *ODC_CTL, - u32 *CMDmode); + u32 *CMDmode) { u8 *p; @@ -168,5 +169,5 @@ } p+=10; } while (0xFF == *p); - + } } Modified: trunk/coreboot-v2/src/northbridge/amd/amdmct/wrappers/mcti_d.c =================================================================== --- trunk/coreboot-v2/src/northbridge/amd/amdmct/wrappers/mcti_d.c 2009-06-30 17:13:58 UTC (rev 4384) +++ trunk/coreboot-v2/src/northbridge/amd/amdmct/wrappers/mcti_d.c 2009-07-01 07:01:32 UTC (rev 4385) @@ -25,9 +25,9 @@ switch (index) { case NV_PACK_TYPE: -#if SYSTEM_TYPE == SERVER +#if CONFIG_CPU_SOCKET_TYPE == 0x10 /* Socket F */ val = 0; -#elif SYSTEM_TYPE == DESKTOP +#elif CONFIG_CPU_SOCKET_TYPE == 0x11 /* AM2r2 */ val = 1; //#elif SYSTEM_TYPE == MOBILE // val = 2;

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[RFC] Mailing list and IRC split
by Carl-Daniel Hailfinger 30 Jun '09

30 Jun '09

Hi, AFAICS the time has come to give flashrom its own mailing list (maybe flashrom(a)coreboot.org) and IRC channel (irc.freenode.net/#flashrom). I do realize this has been brought up in the past, but while I was sceptical back then, I realized that the times have changed in the last few months. The release of flashrom 0.9.0 has increased both visiblity and user base, resulting in a sizable portion of list and chat traffic to be related to flashrom. Some of us are only interested in coreboot, while others are only interested in flashrom. Since filtering mails according to subject can introduce lots of errors, having two separate lists would make watching one one of flashrom/coreboot easier. List traffic over the last few years: 2007: 29 mails/day 2008: 41 mails/day 2009: 36 mails/day Although the list traffic has not yet reached linux-kernel levels, it is already too much to read in full. I hope splitting the lists will allow people to concentrate on their personal area of interest and also encourage more reviews. After all, if you have to read less mails, you can respond to more of them. One issue to solve is how we want to handle flashrom success/failure reports sent to flashrom(a)coreboot.org. Right now they end up on an unmoderated private list. After the change, they'd get a message that the list is moderated. This might discourage users, so we have to think of a nice moderation message, possibly mentioning that emergency help for broken flash is available on IRC. The suggested way forward is outlined below: 1. Register #flashrom on irc.freenode.net (done) 2. Invite parties interested in flashrom to join #flashrom besides #coreboot. 3. Pre-Announce the mailing list split with the following text: "coreboot(a)coreboot.org will be split in two lists. flashrom(a)coreboot.org is where flashrom development and usage will be discussed. coreboot(a)coreboot.org will carry all traffic not related to flashrom. coreboot(a)coreboot.org list members will be subscribed automatically to flashrom(a)coreboot.org. If you are only interested in either coreboot or flashrom, feel free to unsubscribe from either list once the split is done." 4. Wait a week for protests etc. 5. Create a new mailing list flashrom(a)coreboot.org with the same subscribers as coreboot(a)coreboot.org. 6. Announce the mailing list split with the following text: "coreboot(a)coreboot.org has been split in two lists. flashrom(a)coreboot.org is where flashrom development and usage are discussed from now own. coreboot(a)coreboot.org carries all traffic not related to flashrom. coreboot(a)coreboot.org list members have been subscribed automatically to flashrom(a)coreboot.org. If you are only interested in either coreboot or flashrom, feel free to unsubscribe from either list." Thoughts? Flames? Regards, Carl-Daniel

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[PATCH] Changes for DLP 1232H external programer to Flashrom
by Jakob Bornecrantz 30 Jun '09

30 Jun '09

Hi all. These are the changes I had to do the flashrom to get my in circuit programer working. Not much as you can see. Unfortunately it seems to have problems writing to the chip. The first time I tried it it worked well. Writing random data to the chip. But when I then tried to write the bios image. After several tries, adding more capacitors, increasing the bus speed (yes increasing not decreasing) and always erasing the chip before doing a write I got good write. There where a couple of write runs that seems to be get partial success, parts of the bios looked okay while parts where still all FF. Increasing the bus speed seemed to make it write more data. I have some pictures of the programer here: http://irc.walkyrie.se/coreboot/pictures/ Signed-off-by: Jakob Bornecrantz <wallbraker(a)gmail.com> Cheers Jakob.

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coreboot July 2009