Dear coreboot readers!
This is the automatic build system of coreboot.
The developer "ward" checked in revision 4393 to
the coreboot repository. This caused the following
Convert Supermicro H8DMR to CBFS. Also clean up some whitespace in
targets/supermicro/h8dmr/Config.lb and Config-abuild.lb.
Importantly, this also sets
which is required to make this box boot since the changes that went in in
At Myles' suggestion, this patch also sets
in src/mainboard/supermicro/h8dmr/Options.lb to simplify
targets/supermicro/h8dmr/Config.lb a bit further.
Build tested with abuild, boot tested on physical hardware.
Signed-off-by: Ward Vandewege <ward(a)gnu.org>
Acked-by: Myles Watson <mylesgw(a)gmail.com>
Compilation of motorola:sandpointx3_altimus_mpc7410 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4393&device=sandpointx3_al…
Compilation of via:epia-m700 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4393&device=epia-m700&vend…
If something broke during this checkin please be a pain
in ward's neck until the issue is fixed.
If this issue is not fixed within 24h the revision should
be backed out.
coreboot automatic build system
Add support to flashrom for Hyundai HY29F002T on the assumption it is
the same as other *29F002T chips. Running 'flashrom -r' finds the chip
and reads what looks like a BIOS image, other than that it is un-tested.
Signed-off-by: Andrew Morgan <ziltro(a)ziltro.com>
Once I de-solder these chips and get some sockets fitted I can do some
proper testing! Gigabyte GA-7ZXR has two of them for its DualBIOS™.
Switching between chips seems to be done in software... Very useful.
Can libpayload based binaries be launched by grub instead of a Linux kernel?
I would like to write something that does something similar to lspci
from the bare metal instead of within Linux.
> +++ trunk/coreboot-v2/src/southbridge/via/vt8237r/vt8237r_lpc.c 2009-07-01 13:19:25 UTC (rev 4389)
> +#ifdef CONFIG_EPIA_VT8237R_INIT
Is this absolutely neccessary? We really want any board specific code
only in the src/mainboard directory.
> + * Setup to match EPIA default
> + * PCS0# on Pin U1
Yeah, again, I would like this to be improved, so that the
southbridge code is general.
Some pin muxing would have to become structured information so
southbridge code can do the right thing at runtime, I guess..
Harrison, Jon (SELEX GALILEO, UK) wrote:
> This version now boots all of the way through to attempting to
> launch a payload (I'm trying FILO right now), where it falls over
> with exception 6 (invalid opcode)
Please start with memtest86 or memtest86+ as payload, and let it run
a few days.