coreboot July 2009

coreboot@coreboot.org

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build service results for r4393
by coreboot information 02 Jul '09

02 Jul '09

Dear coreboot readers! This is the automatic build system of coreboot. The developer "ward" checked in revision 4393 to the coreboot repository. This caused the following changes: Change Log: Convert Supermicro H8DMR to CBFS. Also clean up some whitespace in targets/supermicro/h8dmr/Config.lb and Config-abuild.lb. Importantly, this also sets default CONFIG_AP_CODE_IN_CAR=0 in src/mainboard/supermicro/h8dmr/Options.lb which is required to make this box boot since the changes that went in in r4315. At Myles' suggestion, this patch also sets default CONFIG_USE_FAILOVER_IMAGE=0 default CONFIG_USE_FALLBACK_IMAGE=0 default CONFIG_XIP_ROM_SIZE=CONFIG_FAILOVER_SIZE in src/mainboard/supermicro/h8dmr/Options.lb to simplify targets/supermicro/h8dmr/Config.lb a bit further. Build tested with abuild, boot tested on physical hardware. Signed-off-by: Ward Vandewege <ward(a)gnu.org> Acked-by: Myles Watson <mylesgw(a)gmail.com> Build Log: Compilation of motorola:sandpointx3_altimus_mpc7410 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4393&device=sandpointx3_al… Compilation of via:epia-m700 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4393&device=epia-m700&vend… If something broke during this checkin please be a pain in ward's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

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[PATCH] convert h8dmr to CBFS
by Ward Vandewege 02 Jul '09

02 Jul '09

The patch comment says it all... Thanks, Ward. -- Ward Vandewege <ward(a)fsf.org> Free Software Foundation - Senior Systems Administrator

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[v2] r4393 - in trunk/coreboot-v2: src/mainboard/supermicro/h8dmr targets/supermicro/h8dmr
by svn＠coreboot.org 02 Jul '09

02 Jul '09

Author: ward Date: 2009-07-02 20:27:02 +0200 (Thu, 02 Jul 2009) New Revision: 4393 Modified: trunk/coreboot-v2/src/mainboard/supermicro/h8dmr/Config.lb trunk/coreboot-v2/src/mainboard/supermicro/h8dmr/Options.lb trunk/coreboot-v2/targets/supermicro/h8dmr/Config-abuild.lb trunk/coreboot-v2/targets/supermicro/h8dmr/Config.lb Log: Convert Supermicro H8DMR to CBFS. Also clean up some whitespace in targets/supermicro/h8dmr/Config.lb and Config-abuild.lb. Importantly, this also sets default CONFIG_AP_CODE_IN_CAR=0 in src/mainboard/supermicro/h8dmr/Options.lb which is required to make this box boot since the changes that went in in r4315. At Myles' suggestion, this patch also sets default CONFIG_USE_FAILOVER_IMAGE=0 default CONFIG_USE_FALLBACK_IMAGE=0 default CONFIG_XIP_ROM_SIZE=CONFIG_FAILOVER_SIZE in src/mainboard/supermicro/h8dmr/Options.lb to simplify targets/supermicro/h8dmr/Config.lb a bit further. Build tested with abuild, boot tested on physical hardware. Signed-off-by: Ward Vandewege <ward(a)gnu.org> Acked-by: Myles Watson <mylesgw(a)gmail.com> Modified: trunk/coreboot-v2/src/mainboard/supermicro/h8dmr/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/supermicro/h8dmr/Config.lb 2009-07-01 17:01:17 UTC (rev 4392) +++ trunk/coreboot-v2/src/mainboard/supermicro/h8dmr/Config.lb 2009-07-02 18:27:02 UTC (rev 4393) @@ -58,7 +58,6 @@ depends "$(CONFIG_MAINBOARD)/apc_auto.c option_table.h" action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/apc_auto.c -o $@" end - ldscript /arch/i386/init/ldscript_apc.lb end end Modified: trunk/coreboot-v2/src/mainboard/supermicro/h8dmr/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/supermicro/h8dmr/Options.lb 2009-07-01 17:01:17 UTC (rev 4392) +++ trunk/coreboot-v2/src/mainboard/supermicro/h8dmr/Options.lb 2009-07-02 18:27:02 UTC (rev 4393) @@ -126,13 +126,9 @@ default CONFIG_ROM_SIZE=0x100000 ## -## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use +## CONFIG_FALLBACK_SIZE is the amount of the ROM the ROM part of the fallback image will use ## -#default CONFIG_FALLBACK_SIZE=131072 -#default CONFIG_FALLBACK_SIZE=0x40000 - -#FALLBACK: 256K-4K -default CONFIG_FALLBACK_SIZE=0x3f000 +default CONFIG_FALLBACK_SIZE=CONFIG_ROM_IMAGE_SIZE #FAILOVER: 4K default CONFIG_FAILOVER_SIZE=0x01000 @@ -234,7 +230,7 @@ default CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE=0x01000 default CONFIG_USE_INIT=0 -default CONFIG_AP_CODE_IN_CAR=1 +default CONFIG_AP_CODE_IN_CAR=0 default CONFIG_MEM_TRAIN_SEQ=1 default CONFIG_WAIT_BEFORE_CPUS_INIT=1 @@ -256,8 +252,9 @@ ### ## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. -default CONFIG_ROM_IMAGE_SIZE = 65536 +default CONFIG_ROM_IMAGE_SIZE = 0xf000 + ## ## Use a small 8K stack ## @@ -347,10 +344,15 @@ ## Select power on after power fail setting default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON" -### End Options.lb +default CONFIG_USE_FAILOVER_IMAGE=0 +default CONFIG_USE_FALLBACK_IMAGE=0 +default CONFIG_XIP_ROM_SIZE=CONFIG_FAILOVER_SIZE + # # CBFS # # -default CONFIG_CBFS=0 +default CONFIG_CBFS=1 + +### End Options.lb end Modified: trunk/coreboot-v2/targets/supermicro/h8dmr/Config-abuild.lb =================================================================== --- trunk/coreboot-v2/targets/supermicro/h8dmr/Config-abuild.lb 2009-07-01 17:01:17 UTC (rev 4392) +++ trunk/coreboot-v2/targets/supermicro/h8dmr/Config-abuild.lb 2009-07-02 18:27:02 UTC (rev 4393) @@ -11,27 +11,20 @@ __LOGLEVEL__ romimage "normal" - option CONFIG_USE_FAILOVER_IMAGE=0 - option CONFIG_USE_FALLBACK_IMAGE=0 - option CONFIG_ROM_IMAGE_SIZE=0x20000 option COREBOOT_EXTRA_VERSION=".0-normal" payload __PAYLOAD__ end romimage "fallback" - option CONFIG_USE_FAILOVER_IMAGE=0 option CONFIG_USE_FALLBACK_IMAGE=1 - option CONFIG_ROM_IMAGE_SIZE=0x20000 option COREBOOT_EXTRA_VERSION=".0-fallback" payload __PAYLOAD__ end romimage "failover" - option CONFIG_USE_FAILOVER_IMAGE=1 - option CONFIG_USE_FALLBACK_IMAGE=0 - option CONFIG_ROM_IMAGE_SIZE=CONFIG_FAILOVER_SIZE - option CONFIG_XIP_ROM_SIZE=CONFIG_FAILOVER_SIZE - option COREBOOT_EXTRA_VERSION=".0-failover" + option CONFIG_USE_FAILOVER_IMAGE=1 + option CONFIG_ROM_IMAGE_SIZE=CONFIG_FAILOVER_SIZE + option COREBOOT_EXTRA_VERSION=".0-failover" end buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback" "failover" Modified: trunk/coreboot-v2/targets/supermicro/h8dmr/Config.lb =================================================================== --- trunk/coreboot-v2/targets/supermicro/h8dmr/Config.lb 2009-07-01 17:01:17 UTC (rev 4392) +++ trunk/coreboot-v2/targets/supermicro/h8dmr/Config.lb 2009-07-02 18:27:02 UTC (rev 4393) @@ -23,44 +23,20 @@ mainboard supermicro/h8dmr romimage "normal" -# 48K for SCSI FW -# option CONFIG_ROM_SIZE = 475136 -# 48K for SCSI FW and 48K for ATI ROM -# option CONFIG_ROM_SIZE = 425984 -# 64K for Etherboot -# option CONFIG_ROM_SIZE = 458752 -# 44k for atixx.rom -# option CONFIG_ROM_SIZE = 479232 - option CONFIG_USE_FAILOVER_IMAGE=0 - option CONFIG_USE_FALLBACK_IMAGE=0 -# option CONFIG_ROM_IMAGE_SIZE=0x13800 -# option CONFIG_ROM_IMAGE_SIZE=0x18800 - option CONFIG_ROM_IMAGE_SIZE=0x20000 -# option CONFIG_ROM_IMAGE_SIZE=0x15800 - option CONFIG_XIP_ROM_SIZE=0x40000 - option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Normal" - payload ../payload.elf + option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Normal" + payload ../payload.elf end romimage "fallback" - option CONFIG_USE_FAILOVER_IMAGE=0 - option CONFIG_USE_FALLBACK_IMAGE=1 -# option CONFIG_ROM_IMAGE_SIZE=0x13800 -# option CONFIG_ROM_IMAGE_SIZE=0x19800 - option CONFIG_ROM_IMAGE_SIZE=0x20000 -# option CONFIG_ROM_IMAGE_SIZE=0x15800 - option CONFIG_XIP_ROM_SIZE=0x40000 - option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback" - payload ../payload.elf + option CONFIG_USE_FALLBACK_IMAGE=1 + option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback" + payload ../payload.elf end romimage "failover" - option CONFIG_USE_FAILOVER_IMAGE=1 - option CONFIG_USE_FALLBACK_IMAGE=0 - option CONFIG_ROM_IMAGE_SIZE=CONFIG_FAILOVER_SIZE - option CONFIG_XIP_ROM_SIZE=CONFIG_FAILOVER_SIZE - option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Failover" + option CONFIG_USE_FAILOVER_IMAGE=1 + option CONFIG_ROM_IMAGE_SIZE=CONFIG_FAILOVER_SIZE + option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Failover" end -#buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback" buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback" "failover"

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[PATCH] flashrom: Add support for Hyundai HY29F002T
by Andrew Morgan 01 Jul '09

01 Jul '09

Add support to flashrom for Hyundai HY29F002T on the assumption it is the same as other *29F002T chips. Running 'flashrom -r' finds the chip and reads what looks like a BIOS image, other than that it is un-tested. Signed-off-by: Andrew Morgan <ziltro(a)ziltro.com> --- Once I de-solder these chips and get some sockets fitted I can do some proper testing! Gigabyte GA-7ZXR has two of them for its DualBIOS™. Switching between chips seems to be done in software... Very useful. -- Andrew.

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libpayload question
by Warren Turkal 01 Jul '09

01 Jul '09

Can libpayload based binaries be launched by grub instead of a Linux kernel? I would like to write something that does something similar to lspci from the bare metal instead of within Linux. Thanks, wt

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Info for EPIA m700 and EPIA n700
by Jakob Bornecrantz 01 Jul '09

01 Jul '09

Hi all Here is some info on two Via EPIA boards, you can find them here: http://irc.walkyrie.se/coreboot/EPIA_m700/ http://irc.walkyrie.se/coreboot/EPIA_n700/ and some pictures of the boards, which I release to public domain: http://irc.walkyrie.se/coreboot/pictures/ Cheers Jakob.

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[patch][v2]:fam10 microcode
by Bao, Zheng 01 Jul '09

01 Jul '09

Attached are the latest ucode patches for Family 10h: 9fh for RB/BL/DA Rev C; 96h for DR Rev B. Signed-off-by: <zheng.bao(a)amd.com> Zheng

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Re: [coreboot] [v2] r4389 - in trunk/coreboot-v2/src: include/device mainboard/via/epia-n southbridge/via/vt8237r
by Peter Stuge 01 Jul '09

01 Jul '09

svn(a)coreboot.org wrote: > +++ trunk/coreboot-v2/src/southbridge/via/vt8237r/vt8237r_lpc.c 2009-07-01 13:19:25 UTC (rev 4389) .. > + > +#ifdef CONFIG_EPIA_VT8237R_INIT Is this absolutely neccessary? We really want any board specific code only in the src/mainboard directory. > + * Setup to match EPIA default > + * PCS0# on Pin U1 Yeah, again, I would like this to be improved, so that the southbridge code is general. Some pin muxing would have to become structured information so southbridge code can do the right thing at runtime, I guess.. //Peter

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Re: [coreboot] C3/CN400 Support - coreboot_tables
by Peter Stuge 01 Jul '09

01 Jul '09

Harrison, Jon (SELEX GALILEO, UK) wrote: > This version now boots all of the way through to attempting to > launch a payload (I'm trying FILO right now), where it falls over > with exception 6 (invalid opcode) Please start with memtest86 or memtest86+ as payload, and let it run a few days. //Peter

1 0

[PATCH]:AMD family 10 AM2r2 support
by Bao, Zheng 01 Jul '09

01 Jul '09

Add AMD family 10 AM2r2 support. Coreboot used to take SYSTEM_TYPE as a label to tell what the socket is. The patch replaces (some of, not all) SYSTEM_TYPE with CPU_SOCKET_TYPE. Signed-off-by: Zheng Bao <zheng.bao(a)amd.com> Index: src/cpu/amd/socket_AM2r2/Config.lb =================================================================== --- src/cpu/amd/socket_AM2r2/Config.lb (revision 0) +++ src/cpu/amd/socket_AM2r2/Config.lb (revision 0) @@ -0,0 +1,54 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2007 Advanced Micro Devices, Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +# + +uses PCI_IO_CFG_EXT +uses MMCONF_SUPPORT +uses HT3_SUPPORT +uses EXT_RT_TBL_SUPPORT +uses EXT_CONF_SUPPORT +uses DIMM_SUPPORT +uses CPU_SOCKET_TYPE +uses CBB +uses CDB +uses PCI_BUS_SEGN_BITS +uses CAR_FAM10 + +config chip.h + +default PCI_IO_CFG_EXT=1 + +default HT3_SUPPORT=1 +default EXT_RT_TBL_SUPPORT=0 +default EXT_CONF_SUPPORT=0 +default DIMM_SUPPORT=0x0104 #DDR2 and REG +default CPU_SOCKET_TYPE=0x11 + +default CAR_FAM10=1 + +if EXT_RT_TBL_SUPPORT + default CBB=0xff + default CDB=0 +end + +#default MMCONF_SUPPORT=1 +#default MMCONF_SUPPORT_DEFAULT=1 + +object socket_AM2r2.o + +dir /cpu/amd/model_10xxx Index: src/cpu/amd/socket_AM2r2/chip.h =================================================================== --- src/cpu/amd/socket_AM2r2/chip.h (revision 0) +++ src/cpu/amd/socket_AM2r2/chip.h (revision 0) @@ -0,0 +1,23 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +extern struct chip_operations cpu_amd_socket_AM2r2_ops; + +struct cpu_amd_socket_AM2r2_config { +}; Index: src/cpu/amd/socket_AM2r2/socket_AM2r2.c =================================================================== --- src/cpu/amd/socket_AM2r2/socket_AM2r2.c (revision 0) +++ src/cpu/amd/socket_AM2r2/socket_AM2r2.c (revision 0) @@ -0,0 +1,25 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <device/device.h> +#include "chip.h" + +struct chip_operations cpu_amd_socket_AM2r2_ops = { + CHIP_NAME("socket AM2r2") +}; Index: src/northbridge/amd/amdmct/mct/mctardk4.c =================================================================== --- src/northbridge/amd/amdmct/mct/mctardk4.c (revision 4379) +++ src/northbridge/amd/amdmct/mct/mctardk4.c (working copy) @@ -25,7 +25,7 @@ void mctGet_PS_Cfg_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, u32 dct) - +{ print_tx("dct: ", dct); print_tx("Speed: ", pDCTstat->Speed); @@ -66,42 +66,43 @@ */ static const u8 Table_ATC_ODC_D_Bx[] = { - 1, 0xFF, 0x00, 0x2F, 0x2F, 0x0, 0x22, 0x13, 0x11, 0x0 - 2, 12, 0x00, 0x2F, 0x2F, 0x0, 0x22, 0x13, 0x11, 0x0 - 2, 16, 0x00, 0x2F, 0x00, 0x0, 0x22, 0x13, 0x11, 0x0 - 2, 20, 0x00, 0x2F, 0x38, 0x0, 0x22, 0x13, 0x11, 0x0 - 2, 24, 0x00, 0x2F, 0x37, 0x0, 0x22, 0x13, 0x11, 0x0 - 2, 32, 0x00, 0x2F, 0x34, 0x0, 0x22, 0x13, 0x11, 0x0 - 3, 12, 0x20, 0x22, 0x20, 0x0, 0x22, 0x13, 0x11, 0x0 - 3, 16, 0x20, 0x22, 0x30, 0x0, 0x22, 0x13, 0x11, 0x0 - 3, 20, 0x20, 0x22, 0x2C, 0x0, 0x22, 0x13, 0x11, 0x0 - 3, 24, 0x20, 0x22, 0x2A, 0x0, 0x22, 0x13, 0x11, 0x0 - 3, 32, 0x20, 0x22, 0x2B, 0x0, 0x22, 0x13, 0x11, 0x0 - 4, 0xFF, 0x20, 0x25, 0x20, 0x0, 0x22, 0x33, 0x11, 0x0 - 5, 0xFF, 0x20, 0x20, 0x2F, 0x0, 0x22, 0x32, 0x11, 0x0 - 0FFh + 1, 0xFF, 0x00, 0x2F, 0x2F, 0x0, 0x22, 0x13, 0x11, 0x0, + 2, 12, 0x00, 0x2F, 0x2F, 0x0, 0x22, 0x13, 0x11, 0x0, + 2, 16, 0x00, 0x2F, 0x00, 0x0, 0x22, 0x13, 0x11, 0x0, + 2, 20, 0x00, 0x2F, 0x38, 0x0, 0x22, 0x13, 0x11, 0x0, + 2, 24, 0x00, 0x2F, 0x37, 0x0, 0x22, 0x13, 0x11, 0x0, + 2, 32, 0x00, 0x2F, 0x34, 0x0, 0x22, 0x13, 0x11, 0x0, + 3, 12, 0x20, 0x22, 0x20, 0x0, 0x22, 0x13, 0x11, 0x0, + 3, 16, 0x20, 0x22, 0x30, 0x0, 0x22, 0x13, 0x11, 0x0, + 3, 20, 0x20, 0x22, 0x2C, 0x0, 0x22, 0x13, 0x11, 0x0, + 3, 24, 0x20, 0x22, 0x2A, 0x0, 0x22, 0x13, 0x11, 0x0, + 3, 32, 0x20, 0x22, 0x2B, 0x0, 0x22, 0x13, 0x11, 0x0, + 4, 0xFF, 0x20, 0x25, 0x20, 0x0, 0x22, 0x33, 0x11, 0x0, + 5, 0xFF, 0x20, 0x20, 0x2F, 0x0, 0x22, 0x32, 0x11, 0x0, + 0xFF +}; static const u8 Table_ATC_ODC_D_Ax[] = { - 1, 0xFF, 0x00, 0x2F, 0x2F, 0x0, 0x22, 0x13, 0x11, 0x0 - 2, 12, 0x00, 0x2F, 0x2F, 0x0, 0x22, 0x13, 0x11, 0x0 - 2, 16, 0x00, 0x2F, 0x00, 0x0, 0x22, 0x13, 0x11, 0x0 - 2, 20, 0x00, 0x2F, 0x38, 0x0, 0x22, 0x13, 0x11, 0x0 - 2, 24, 0x00, 0x2F, 0x37, 0x0, 0x22, 0x13, 0x11, 0x0 - 2, 32, 0x00, 0x2F, 0x34, 0x0, 0x22, 0x13, 0x11, 0x0 - 3, 12, 0x20, 0x22, 0x20, 0x0, 0x22, 0x13, 0x11, 0x0 - 3, 16, 0x20, 0x22, 0x30, 0x0, 0x22, 0x13, 0x11, 0x0 - 3, 20, 0x20, 0x22, 0x2C, 0x0, 0x22, 0x13, 0x11, 0x0 - 3, 24, 0x20, 0x22, 0x2A, 0x0, 0x22, 0x13, 0x11, 0x0 - 3, 32, 0x20, 0x22, 0x2B, 0x0, 0x22, 0x13, 0x11, 0x0 - 4, 0xFF, 0x20, 0x25, 0x20, 0x0, 0x22, 0x33, 0x11, 0x0 - 5, 0xFF, 0x20, 0x20, 0x2F, 0x0, 0x22, 0x32, 0x11, 0x0 + 1, 0xFF, 0x00, 0x2F, 0x2F, 0x0, 0x22, 0x13, 0x11, 0x0, + 2, 12, 0x00, 0x2F, 0x2F, 0x0, 0x22, 0x13, 0x11, 0x0, + 2, 16, 0x00, 0x2F, 0x00, 0x0, 0x22, 0x13, 0x11, 0x0, + 2, 20, 0x00, 0x2F, 0x38, 0x0, 0x22, 0x13, 0x11, 0x0, + 2, 24, 0x00, 0x2F, 0x37, 0x0, 0x22, 0x13, 0x11, 0x0, + 2, 32, 0x00, 0x2F, 0x34, 0x0, 0x22, 0x13, 0x11, 0x0, + 3, 12, 0x20, 0x22, 0x20, 0x0, 0x22, 0x13, 0x11, 0x0, + 3, 16, 0x20, 0x22, 0x30, 0x0, 0x22, 0x13, 0x11, 0x0, + 3, 20, 0x20, 0x22, 0x2C, 0x0, 0x22, 0x13, 0x11, 0x0, + 3, 24, 0x20, 0x22, 0x2A, 0x0, 0x22, 0x13, 0x11, 0x0, + 3, 32, 0x20, 0x22, 0x2B, 0x0, 0x22, 0x13, 0x11, 0x0, + 4, 0xFF, 0x20, 0x25, 0x20, 0x0, 0x22, 0x33, 0x11, 0x0, + 5, 0xFF, 0x20, 0x20, 0x2F, 0x0, 0x22, 0x32, 0x11, 0x0, 0xFF }; static void Get_ChannelPS_Cfg0_D( u8 MAAdimms, u8 Speed, u8 MAAload, u8 DATAAload, u32 *AddrTmgCTL, u32 *ODC_CTL, - u32 *CMDmode); + u32 *CMDmode) { u8 *p; @@ -168,5 +169,5 @@ } p+=10; } while (0xFF == *p); - + } } Index: src/northbridge/amd/amdmct/wrappers/mcti_d.c =================================================================== --- src/northbridge/amd/amdmct/wrappers/mcti_d.c (revision 4379) +++ src/northbridge/amd/amdmct/wrappers/mcti_d.c (working copy) @@ -25,9 +25,9 @@ switch (index) { case NV_PACK_TYPE: -#if SYSTEM_TYPE == SERVER +#if CPU_SOCKET_TYPE == 0x10 /* Socket F */ val = 0; -#elif SYSTEM_TYPE == DESKTOP +#elif CPU_SOCKET_TYPE == 0x11 /* AM2r2 */ val = 1; //#elif SYSTEM_TYPE == MOBILE // val = 2; Index: src/northbridge/amd/amdfam10/raminit_amdmct.c =================================================================== --- src/northbridge/amd/amdfam10/raminit_amdmct.c (revision 4379) +++ src/northbridge/amd/amdfam10/raminit_amdmct.c (working copy) @@ -63,10 +63,10 @@ #include "../amdmct/mct/mctndi_d.c" #include "../amdmct/mct/mctchi_d.c" -#if SYSTEM_TYPE == SERVER +#if CPU_SOCKET_TYPE == 0x10 //L1 #include "../amdmct/mct/mctardk3.c" -#elif SYSTEM_TYPE == DESKTOP +#elif CPU_SOCKET_TYPE == 0x11 //AM2 #include "../amdmct/mct/mctardk4.c" //#elif SYSTEM_TYPE == MOBILE

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coreboot July 2009