coreboot July 2009

coreboot@coreboot.org

75 participants
304 discussions

s2891
by Myles Watson 16 Jul '09

16 Jul '09

Ward, I remember you saying that your SATA performance was low on this board. Have you ever tried uncommenting the soft_reset in cache_as_ram_auto.c? That makes it so that the HyperTransport links all run at 200 MHz 8-bit instead of 1 GHz 16-bit (factor of 10 difference in bandwidth) The unfortunate thing about HyperTransport is that you can't tell if it's running at speed from the lspci. The new values are there, but only take effect at the next soft reset. Thanks, Myles

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jetwaynf94-270-lf: ATOM-n270+i945 triplefault if activate the variable mtrr.
by Urbez Santana Roma 15 Jul '09

15 Jul '09

Hi, i'm working with these mainboard fanless: Jetway NF94-270-LF The bios chip is one Winbond W25X80, i have released a simple circuit with one transistor BC547, and the rest connected directly to the paralel port in mode ECP, data buses are 3.3V Also i have release a simple program to erase, test and program it. If one are interesed in this, tell-me. The flashprogram not works correctly with this chip, but i can try to solve. The CPU is the Atom N270, normally i used VIA's but, i will test my aplications with it, with VIA i cannot use my SSE2 optimizations, they are more slow that direct use of 32bit assembler code. This have a Fintek SuperIO F71862FG that is similar to the F71805F. The base is the ich7m and i945GSE. I have tested and make that it works, except the VGA and the Audio, i have solved the problems with acpi, and linux kernel boots normally with the SATA. I have only one problem, with the variable MTRR if i activate variable MTRR's for have cache, the kernel immediately makes a triple fault. I not known if in the moment of activate MTRR this chip generates a spurious interrupt or similar, and when the kernel creates the IDT table, hangs. Have one show this problem in the past? I have send to local APIC's the EOI, but the problem continues...

2 1

Only UDMA/33 PATA on m57sli, UDMA/66 with factory BIOS
by Peter Stuge 15 Jul '09

15 Jul '09

Harald Gutmann wrote: > > * hda: UDMA/33 compared to UDMA/66 with prop. BIOS > > My suggestion would be to open up a new ML-thread according to this > problem. Good idea. > It should be "easy" to fix, and I think that it has nothing to do > with the DMA modes itself, but with the "88pin-wire-cable-bit" Yep. > (but I don't know if it's for real a bit which needs to be set). Usually there is. > I also tried to investigate that problem, but ran out of time the > evening I started. (check kernel ide-drivers amd7xxx.c (or similar) > to find out what's going on there). I hope the bit we want isn't hidden in a chipset doc which we can't find. :\ //Peter

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Re: [coreboot] [FILO] EPIA-NL/CN400 Port.... FILO Booting kernel, init probs
by Rudolf Marek 15 Jul '09

15 Jul '09

-----BEGIN PGP SIGNED MESSAGE----- Hash: SHA1 Harrison, Jon (SELEX GALILEO, UK) wrote: > Hi Folks, > > I've added initial ACPI support to my EPIA-NL/CN400 Port. Hmm pity is that it is not here so mine help is limited. > I think the issues are concerned with the South Bridge Init (VT8237R), There > a bunch of USB UHCI problems reported and then the boot hangs > configuring/mounting sda1 Perhaps it seems that PCI routing does not work. Does the CPU lacks APIC? I think PIC only mode needs some tuning to PCI router. I dont know how you have done the LNKA etc devices in ACPI but you need to change the 0x55-0x57 in SB to reflect current settings. You will need to implement _CRS and _SRS for that. Also there is some in kernel quirk that IRQ routing (non APIC) works only if the 0x3c is written with right value. Kernel will fix that. OperationRegion (SREG, PCI_Config, Zero, ... Field (SREG, ByteAcc, NoLock, Preserve) { Offset (0x55),. , 4,. PIRA, 4,. PIRB, 4,. PIRC, 4,. and then for LNKA for example: _SRS will need to parse the the IRQ resource from OS, which is stored as bitmap. Using findsetright bit/dec create a IRQ nr and store it in the PIRA ;) Something could be taken from amd8111_pic.asl Second possibility would be to create a PIR table and store the right routing values in the SB init code + ECLR should be modified. I never finished this code for VT8237R. Check VT8235 vt8235_lpc.c for details pci_routing_fixup. Rudolf -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.9 (GNU/Linux) Comment: Using GnuPG with Mozilla - http://enigmail.mozdev.org iEYEARECAAYFAkpc+T8ACgkQ3J9wPJqZRNWbbQCfe1Ap+C9XfR1tHsSGSfnw2uO0 dt4An0H9c7TfPhlxC5TkYWXdhVSnpJ3x =NWPg -----END PGP SIGNATURE-----

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#137: S2895 no function after coreboot 2 flash
by coreboot 15 Jul '09

15 Jul '09

#137: S2895 no function after coreboot 2 flash --------------------------+------------------------------------------------- Reporter: anonymous | Type: defect Status: new | Priority: major Milestone: | Component: buildrom Version: v2 | Keywords: Dependencies: | Patchstatus: there is no patch --------------------------+------------------------------------------------- Hi Guys, I am not sure whether i am correct here with you guys. But i have some troubles after flashing the tyan-s2895.rom that has been generated with seabios as payload by the buildrom tool. There are no logs in the log folders and everything worked fine. But after flashing the coreboot bios to the board using "flashrom -v -w tyan-s2895.rom" and i "halt" the system, it will come up for a second and switches off immediately. I tried clearing the CMOS, but this did not solve the problem. Any idea what i am doing wrong? -- Ticket URL: <http://tracker.coreboot.org/trac/coreboot/ticket/137> coreboot <http://www.coreboot.org/>

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Trac reminder: list of new ticket(s)
by coreboot tracker 15 Jul '09

15 Jul '09

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Fwd: 1sec linux boot
by ron minnich 15 Jul '09

15 Jul '09

---------- Forwarded message ---------- From: Date: Tue, Jul 14, 2009 at 7:46 PM Subject: 1sec linux boot To: cool demo: http://www.youtube.com/watch?v=-l_DSZe8_F8

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[PATCH] Fix VIA EPIA-M700 so it gets a first serial boot log
by Uwe Hermann 15 Jul '09

15 Jul '09

See patch. Thanks everyone on IRC helping get this stuff debugged this far, and especially Jakob Bornecrantz <wallbraker(a)gmail.com> for testing on his VIA EPIA-M700! Uwe. -- http://www.hermann-uwe.de | http://www.holsham-traders.de http://www.crazy-hacks.org | http://www.unmaintained-free-software.org

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[v2] r4426 - trunk/coreboot-v2/src/mainboard/via/epia-m700
by svn＠coreboot.org 15 Jul '09

15 Jul '09

Author: uwe Date: 2009-07-15 02:03:28 +0200 (Wed, 15 Jul 2009) New Revision: 4426 Modified: trunk/coreboot-v2/src/mainboard/via/epia-m700/Config.lb trunk/coreboot-v2/src/mainboard/via/epia-m700/Options.lb trunk/coreboot-v2/src/mainboard/via/epia-m700/cache_as_ram_auto.c trunk/coreboot-v2/src/mainboard/via/epia-m700/irq_tables.c Log: Fix VIA EPIA-M700 target enough for a first serial boot log. Add the respective Super I/O config in Config.lb (Winbond W83697HG), enable COM1 on the board, fix irq_table.c, as well as the PCI devices listed in Config.lb (based on lspci output). This has been tested by Jakob Bornecrantz <wallbraker(a)gmail.com> on hardware, i.e. there is serial output. It does not yet boot to a Linux console successfully, more fixing will be needed. Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Jakob Bornecrantz <wallbraker(a)gmail.com> Modified: trunk/coreboot-v2/src/mainboard/via/epia-m700/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/via/epia-m700/Config.lb 2009-07-14 19:10:10 UTC (rev 4425) +++ trunk/coreboot-v2/src/mainboard/via/epia-m700/Config.lb 2009-07-15 00:03:28 UTC (rev 4426) @@ -109,21 +109,54 @@ chip northbridge/via/vx800 # Northbridge device pci_domain 0 on - device pci 0.0 on end # AGP Bridge + device pci 0.0 on end # Host Bridge device pci 0.1 on end # Error Reporting device pci 0.2 on end # Host Bus Control - device pci 0.3 on end # Memory Controller + device pci 0.3 on end # PCI to PCI Bridge device pci 0.4 on end # Power Management - device pci 0.7 on end # V-Link Controller + device pci 0.5 on end # APIC and Central Traffic Control + device pci 0.6 on end # Scratch Registers + device pci 0.7 on end # North-South Module Interface Control device pci 1.0 on end # PCI Bridge - # device pci f.0 on end # IDE/SATA + device pci f.0 on end # IDE/SATA # device pci f.1 on end # IDE - # device pci 10.0 on end # USB 1.1 - # device pci 10.1 on end # USB 1.1 - # device pci 10.2 on end # USB 1.1 - # device pci 10.4 on end # USB 2.0 - # device pci 11.0 on # Southbridge LPC - # end + device pci 10.0 on end # USB 1.1 + device pci 10.1 on end # USB 1.1 + device pci 10.2 on end # USB 1.1 + device pci 10.4 on end # USB 2.0 + device pci 11.0 on # Bus Control and Power Management (SB, LPC) + chip superio/winbond/w83697hf + # TODO: Check all devices, this may need some more work. + device pnp 2e.0 off # Floppy (N/A?) + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 2e.1 off # Parallel Port (N/A?) + io 0x60 = 0x378 + irq 0x70 = 7 + drq 0x74 = 4 + end + device pnp 2e.2 on # COM1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.3 on # COM2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.6 off end # Consumer IR + device pnp 2e.7 off end # Game port, GPIO 1 + device pnp 2e.8 off end # MIDI port, GPIO 5 + device pnp 2e.9 off end # GPIO 2-4 + device pnp 2e.a off end # ACPI + device pnp 2e.b on # HWM + io 0x60 = 0x290 + end + end + end + device pci 11.7 on end # North-South Module Interface Control + device pci 14.0 on end # HD Audio (Azalia) end device apic_cluster 0 on # APIC cluster chip cpu/via/model_c7 # VIA C7 Modified: trunk/coreboot-v2/src/mainboard/via/epia-m700/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/via/epia-m700/Options.lb 2009-07-14 19:10:10 UTC (rev 4425) +++ trunk/coreboot-v2/src/mainboard/via/epia-m700/Options.lb 2009-07-15 00:03:28 UTC (rev 4426) @@ -120,7 +120,7 @@ default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1 default CONFIG_HAVE_HARD_RESET = 0 default CONFIG_HAVE_PIRQ_TABLE = 0 -default CONFIG_IRQ_SLOT_COUNT = 14 +default CONFIG_IRQ_SLOT_COUNT = 13 default CONFIG_HAVE_ACPI_TABLES = 1 default CONFIG_HAVE_OPTION_TABLE = 1 default CONFIG_ROM_IMAGE_SIZE = 128 * 1024 @@ -135,6 +135,8 @@ default CONFIG_CROSS_COMPILE = "" default CC = "$(CONFIG_CROSS_COMPILE)gcc -m32" default HOSTCC = "gcc" +default CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 9 +default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9 default CONFIG_CBFS = 0 ## Modified: trunk/coreboot-v2/src/mainboard/via/epia-m700/cache_as_ram_auto.c =================================================================== --- trunk/coreboot-v2/src/mainboard/via/epia-m700/cache_as_ram_auto.c 2009-07-14 19:10:10 UTC (rev 4425) +++ trunk/coreboot-v2/src/mainboard/via/epia-m700/cache_as_ram_auto.c 2009-07-15 00:03:28 UTC (rev 4426) @@ -55,6 +55,10 @@ #include "cpu/x86/car/copy_and_run.c" #include "wakeup.h" +#include "superio/winbond/w83697hf/w83697hf_early_serial.c" + +#define SERIAL_DEV PNP_DEV(0x2e, W83697HF_SP1) + /* * This acpi_is_wakeup_early_via_VX800 is from Rudolf's patch on the list: * http://www.coreboot.org/pipermail/coreboot/2008-January/028787.html. @@ -407,7 +411,10 @@ * console_init()) are the same with epia-cn port. */ pci_write_config8(PCI_DEV(0, 0, 0), 0x4f, 0x01); - EmbedComInit(); + /* EmbedComInit(); */ + w83697hf_set_clksel_48(SERIAL_DEV); + w83697hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + uart_init(); /* enable_vx800_serial(); */ /* uart_init(); */ Modified: trunk/coreboot-v2/src/mainboard/via/epia-m700/irq_tables.c =================================================================== --- trunk/coreboot-v2/src/mainboard/via/epia-m700/irq_tables.c 2009-07-14 19:10:10 UTC (rev 4425) +++ trunk/coreboot-v2/src/mainboard/via/epia-m700/irq_tables.c 2009-07-15 00:03:28 UTC (rev 4426) @@ -26,23 +26,27 @@ 32 + 16 * CONFIG_IRQ_SLOT_COUNT,/* Max. number of devices on the bus */ 0x00, /* Where the interrupt router lies (bus) */ (0x11 << 3) | 0x0, /* Where the interrupt router lies (dev) */ - 0xc20, /* IRQs devoted exclusively to PCI usage */ + 0xca0, /* IRQs devoted exclusively to PCI usage */ 0x1106, /* Vendor */ - 0x8409, /* Device */ + 0x596, /* Device */ 0, /* Miniport */ {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, /* u8 rfu[11] */ - 0xc6, /* Checksum. 0xa0? */ + 0xdb, /* Checksum. 0xa0? */ { /* bus, dev | fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ - {0x00, (0x01 << 3) | 0x0, {{0x01, 0xdeb8}, {0x00, 0xdeb8}, {0x00, 0xdeb8}, {0x00, 0x0deb8}}, 0x0, 0x0}, - {0x00, (0x08 << 3) | 0x0, {{0x01, 0xdeb8}, {0x01, 0xdeb8}, {0x01, 0xdeb8}, {0x01, 0x0deb8}}, 0x1, 0x0}, - {0x00, (0x0b << 3) | 0x0, {{0x01, 0xdeb8}, {0x00, 0xdeb8}, {0x00, 0xdeb8}, {0x00, 0x0deb8}}, 0x0, 0x0}, - {0x00, (0x0c << 3) | 0x0, {{0x01, 0xdeb8}, {0x00, 0xdeb8}, {0x00, 0xdeb8}, {0x00, 0x0deb8}}, 0x0, 0x0}, - {0x00, (0x0d << 3) | 0x0, {{0x02, 0xdeb8}, {0x00, 0xdeb8}, {0x00, 0xdeb8}, {0x00, 0x0deb8}}, 0x0, 0x0}, - {0x00, (0x0e << 3) | 0x0, {{0x03, 0xdeb8}, {0x00, 0xdeb8}, {0x00, 0xdeb8}, {0x00, 0x0deb8}}, 0x0, 0x0}, - {0x00, (0x0f << 3) | 0x0, {{0x02, 0xdeb8}, {0x00, 0xdeb8}, {0x00, 0xdeb8}, {0x00, 0x0deb8}}, 0x0, 0x0}, - {0x00, (0x10 << 3) | 0x0, {{0x01, 0xdeb8}, {0x02, 0xdeb8}, {0x03, 0xdeb8}, {0x04, 0x0deb8}}, 0x0, 0x0}, - {0x00, (0x14 << 3) | 0x0, {{0x02, 0xdeb8}, {0x00, 0xdeb8}, {0x00, 0xdeb8}, {0x00, 0x0deb8}}, 0x0, 0x0}, + {0x00, (0x02 << 3) | 0x0, {{0x09, 0xdeb8}, {0x09, 0xdeb8}, {0x09, 0xdeb8}, {0x09, 0xdeb8}}, 0x1, 0x0}, + {0x00, (0x03 << 3) | 0x0, {{0x09, 0xdeb8}, {0x09, 0xdeb8}, {0x09, 0xdeb8}, {0x09, 0xdeb8}}, 0x2, 0x0}, + {0x00, (0x03 << 3) | 0x1, {{0x09, 0xdeb8}, {0x09, 0xdeb8}, {0x09, 0xdeb8}, {0x09, 0xdeb8}}, 0x3, 0x0}, + {0x04, (0x04 << 3) | 0x0, {{0x02, 0xdeb8}, {0x03, 0xdeb8}, {0x05, 0xdeb8}, {0x01, 0xdeb8}}, 0x4, 0x0}, + {0x04, (0x0e << 3) | 0x0, {{0x01, 0xdeb8}, {0x02, 0xdeb8}, {0x03, 0xdeb8}, {0x05, 0xdeb8}}, 0x5, 0x0}, + {0x00, (0x11 << 3) | 0x0, {{0x00, 0xdeb8}, {0x00, 0xdeb8}, {0x03, 0xdeb8}, {0x05, 0xdeb8}}, 0x0, 0x0}, + {0x00, (0x0f << 3) | 0x0, {{0x01, 0xdeb8}, {0x02, 0xdeb8}, {0x03, 0xdeb8}, {0x05, 0xdeb8}}, 0x0, 0x0}, + {0x00, (0x01 << 3) | 0x0, {{0x01, 0xdeb8}, {0x02, 0xdeb8}, {0x03, 0xdeb8}, {0x05, 0xdeb8}}, 0x0, 0x0}, + {0x00, (0x10 << 3) | 0x0, {{0x01, 0xdeb8}, {0x02, 0xdeb8}, {0x03, 0xdeb8}, {0x05, 0xdeb8}}, 0x0, 0x0}, + {0x00, (0x02 << 3) | 0x0, {{0x09, 0xdeb8}, {0x09, 0xdeb8}, {0x09, 0xdeb8}, {0x09, 0xdeb8}}, 0x0, 0x0}, + {0x00, (0x03 << 3) | 0x0, {{0x09, 0xdeb8}, {0x09, 0xdeb8}, {0x09, 0xdeb8}, {0x09, 0xdeb8}}, 0x0, 0x0}, + {0x00, (0x03 << 3) | 0x1, {{0x09, 0xdeb8}, {0x09, 0xdeb8}, {0x09, 0xdeb8}, {0x09, 0xdeb8}}, 0x0, 0x0}, + {0x00, (0x14 << 3) | 0x0, {{0x01, 0xdeb8}, {0x02, 0xdeb8}, {0x03, 0xdeb8}, {0x05, 0xdeb8}}, 0x0, 0x0}, } };

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[PATCH] xcshell: serial shell for early debugging
by Michael Gold 15 Jul '09

15 Jul '09

I've been working on some code to ensure I can debug a system even if coreboot fails to boot an OS. The attached patch adds this code to the tree: - serialprobe watches the serial port for about a second, and boots the system normally unless 32 consecutive null bytes are seen. - xcshell allows the CPU to be controlled via the serial port, using a binary protocol. The code assembles to about 1 KB, so it can be left in an image for emergency use. It's also modular in case someone wants to use it with something other than a serial port. xcsinterp.inc describes the protocol, and xccmd.inc describes the command set. Signed-off-by: Michael Gold <mgold(a)ncf.ca> --- It should possible to jump to the 'xcshell' or 'serialprobe' symbol (with the return address in ESP) as soon as the serial port is configured and the CPU is executing 32-bit code (e.g., after console_init in auto.c). I'm using these lines in my mainboard's Config.lb to include the code: mainboardinit arch/i386/xcshell/jmp_xccmd_end.inc mainboardinit arch/i386/xcshell/serialprobe.inc mainboardinit arch/i386/xcshell/io_serial.inc mainboardinit arch/i386/xcshell/xcsinterp.inc mainboardinit arch/i386/xcshell/xccmd.inc I'm not sure whether there's anything that needs to be added, but suggestions are welcome. I'm hoping the command set is sufficient to initialise RAM, though so far I've only tested cache-as-RAM mode (which just seems to work for data, not code). -- Michael

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coreboot July 2009