coreboot June 2009

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[Patch] flashrom: board enable for shuttle ak31.
by Luc Verhaegen 06 Jul '09

06 Jul '09

2 2

[patch] fix intel 82810 onboard VGA and SDRAM functions
by Elia Yehuda 05 Jul '09

05 Jul '09

This patch enables the onboard VGA found on 82810 boards and fixes the memory procedures to support different kinds of DIMMs. also, support for 82810e board had been added. The only drawback from this patch is the HAVE_HIGH_TABLES being disabled since it disables (for unknown reason) the onboard VGA. Signed-off-by: Elia Yehuda <z4ziggy(a)gmail.com>

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FlashROM on VIA EPIA EN12000EG
by Sebastian Schuberth 03 Jul '09

03 Jul '09

Hi, this is just to report that I succeeded reading the BIOS using FlashROM 0.9.0 from my VIA EPIA EN12000EG motherboard. I haven't tried writing the BIOS yet. The only small issue I had was that my motherboard is reported to be from the "CN" rather than the "EN" series: Calibrating delay loop... OK. No coreboot table found. Found chipset "VIA VT8237", enabling flash write... OK. Found board "VIA EPIA-CN", enabling flash write... OK. Found chip "SST SST49LF004A/B" (512 KB) at physical address 0xfff80000. Reading flash... done. I don't know if it's even technically possible to distinguish the CN and EN series, or if they are simply too close / almost identical from a chipset etc. view, but I'd be happy to help out improving this, if I can. -- Sebastian Schuberth

3 3

coreinfo compilation problem
by Warren Turkal 03 Jul '09

03 Jul '09

The following is the output I get when trying to compile coreinfo. wt@mediakitchen:~/projects/coreboot/coreinfo$ make CC build/cpuinfo_module.o AS build/cpuid.S.o CC build/pci_module.o CC build/coreboot_module.o CC build/nvram_module.o CC build/bootlog_module.o CC build/ramdump_module.o CC build/lar_module.o CC build/multiboot_module.o CC build/coreinfo.o LD build/coreinfo.elf /home/wt/projects/coreboot/coreinfo/build/cpuinfo_module.o: In function `cpuinfo_module_init': cpuinfo_module.c:(.text+0x469): undefined reference to `__udivdi3' ../libpayload/bin/../lib/libpayload.a(timer.o): In function `get_cpu_speed': timer.c:(.text+0xe8): undefined reference to `__udivdi3' ../libpayload/bin/../lib/libpayload.a(printf.o): In function `print_number': printf.c:(.text+0x344): undefined reference to `__umoddi3' printf.c:(.text+0x379): undefined reference to `__udivdi3' collect2: ld returned 1 exit status make: *** [/home/wt/projects/coreboot/coreinfo/build/coreinfo.elf] Error 1 Is there something I am not doing that I should be doing? Also, I had to manually symlink libpayload.config to .config in my libpayload directory so that lpgcc would work. This should probably be automated. Thanks, wt

2 1

Simple Firmware Interface?
by Robinson Tryon 02 Jul '09

02 Jul '09

I just found a story in the Slashdot queue about a new Intel project called the "Simple Firmware Interface" (http://simplefirmware.org/). According to the project website, SFI is "a method for platform firmware to export static tables to the operating system (OS)" and looks to be a lightweight replacement for ACPI. I haven't found any mention of SFI on either Wikipedia or on the coreboot wiki. Does anyone have further information on the project? Thanks, --R Here's the story in the /. queue: http://slashdot.org/firehose.pl?op=view&id=4979253 Here's the link to the announcement: http://www.h-online.com/open/Intel-develops-simpler-alternative-to-ACPI-for… Looks someone from Intel will be giving a talk at Linux Symposium 2009: http://www.linuxsymposium.org/2009/view_abstract.php?content_key=82

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K8 resource allocation cleanup
by Myles Watson 02 Jul '09

02 Jul '09

These patches depend on the new resource allocator. Abuild tested and boot tested on SimNow, qemu, s2892, and s2895. k8_north.diff: change FX_DEVS to MAX_FX_DEVS introduce fx_devs for the number of nodes only call get_fx_devs if fx_devs == 0 change i to node_id and ii to i remove shadowed variables take out continue statements in loops go to fx_devs k8_resources.diff: combine find_iopair and find_mempair return the register number instead of a resource don't allocate resources until the allocate stage simplify amdk8_create_vga_resource and move it to read resources (It could be moved above read resources, but I was minimizing changes) allocate resources in amdk8_set_resources For each resource: See if there's already a resource for that link and node Use it if there is Otherwise allocate a new one Compact resources to get rid of extra ones in amdk8_domain_read_resources, store the base and limit in the temporary resources so it's easier to debug. tolm_test needed to be changed so it didn't find the VGA resource It could probably be changed to be > 0x100000 since any system should have 1M of RAM and this is trying to find the bottom of PCI space. tolm_test should be factored out of all northbridges In device.c, rename allocate_vga_resource to set_vga_bridge_bits and move it to the beginning of resource allocation. Signed-off-by: Myles Watson <mylesgw(a)gmail.com> Thanks, Myles

2 2

[PATCH] flashrom: Add support for Hyundai HY29F002T
by Andrew Morgan 02 Jul '09

02 Jul '09

Add support to flashrom for Hyundai HY29F002T on the assumption it is the same as other *29F002T chips. Running 'flashrom -r' finds the chip and reads what looks like a BIOS image, other than that it is un-tested. Signed-off-by: Andrew Morgan <ziltro(a)ziltro.com> --- Once I de-solder these chips and get some sockets fitted I can do some proper testing! Gigabyte GA-7ZXR has two of them for its DualBIOS™. Switching between chips seems to be done in software... Very useful. -- Andrew.

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libpayload question
by Warren Turkal 02 Jul '09

02 Jul '09

Can libpayload based binaries be launched by grub instead of a Linux kernel? I would like to write something that does something similar to lspci from the bare metal instead of within Linux. Thanks, wt

2 2

[patch][v2]:fam10 microcode
by Bao, Zheng 02 Jul '09

02 Jul '09

Attached are the latest ucode patches for Family 10h: 9fh for RB/BL/DA Rev C; 96h for DR Rev B. Signed-off-by: <zheng.bao(a)amd.com> Zheng

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[PATCH]:AMD family 10 AM2r2 support
by Bao, Zheng 02 Jul '09

02 Jul '09

Add AMD family 10 AM2r2 support. Coreboot used to take SYSTEM_TYPE as a label to tell what the socket is. The patch replaces (some of, not all) SYSTEM_TYPE with CPU_SOCKET_TYPE. Signed-off-by: Zheng Bao <zheng.bao(a)amd.com> Index: src/cpu/amd/socket_AM2r2/Config.lb =================================================================== --- src/cpu/amd/socket_AM2r2/Config.lb (revision 0) +++ src/cpu/amd/socket_AM2r2/Config.lb (revision 0) @@ -0,0 +1,54 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2007 Advanced Micro Devices, Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +# + +uses PCI_IO_CFG_EXT +uses MMCONF_SUPPORT +uses HT3_SUPPORT +uses EXT_RT_TBL_SUPPORT +uses EXT_CONF_SUPPORT +uses DIMM_SUPPORT +uses CPU_SOCKET_TYPE +uses CBB +uses CDB +uses PCI_BUS_SEGN_BITS +uses CAR_FAM10 + +config chip.h + +default PCI_IO_CFG_EXT=1 + +default HT3_SUPPORT=1 +default EXT_RT_TBL_SUPPORT=0 +default EXT_CONF_SUPPORT=0 +default DIMM_SUPPORT=0x0104 #DDR2 and REG +default CPU_SOCKET_TYPE=0x11 + +default CAR_FAM10=1 + +if EXT_RT_TBL_SUPPORT + default CBB=0xff + default CDB=0 +end + +#default MMCONF_SUPPORT=1 +#default MMCONF_SUPPORT_DEFAULT=1 + +object socket_AM2r2.o + +dir /cpu/amd/model_10xxx Index: src/cpu/amd/socket_AM2r2/chip.h =================================================================== --- src/cpu/amd/socket_AM2r2/chip.h (revision 0) +++ src/cpu/amd/socket_AM2r2/chip.h (revision 0) @@ -0,0 +1,23 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +extern struct chip_operations cpu_amd_socket_AM2r2_ops; + +struct cpu_amd_socket_AM2r2_config { +}; Index: src/cpu/amd/socket_AM2r2/socket_AM2r2.c =================================================================== --- src/cpu/amd/socket_AM2r2/socket_AM2r2.c (revision 0) +++ src/cpu/amd/socket_AM2r2/socket_AM2r2.c (revision 0) @@ -0,0 +1,25 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <device/device.h> +#include "chip.h" + +struct chip_operations cpu_amd_socket_AM2r2_ops = { + CHIP_NAME("socket AM2r2") +}; Index: src/northbridge/amd/amdmct/mct/mctardk4.c =================================================================== --- src/northbridge/amd/amdmct/mct/mctardk4.c (revision 4379) +++ src/northbridge/amd/amdmct/mct/mctardk4.c (working copy) @@ -25,7 +25,7 @@ void mctGet_PS_Cfg_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, u32 dct) - +{ print_tx("dct: ", dct); print_tx("Speed: ", pDCTstat->Speed); @@ -66,42 +66,43 @@ */ static const u8 Table_ATC_ODC_D_Bx[] = { - 1, 0xFF, 0x00, 0x2F, 0x2F, 0x0, 0x22, 0x13, 0x11, 0x0 - 2, 12, 0x00, 0x2F, 0x2F, 0x0, 0x22, 0x13, 0x11, 0x0 - 2, 16, 0x00, 0x2F, 0x00, 0x0, 0x22, 0x13, 0x11, 0x0 - 2, 20, 0x00, 0x2F, 0x38, 0x0, 0x22, 0x13, 0x11, 0x0 - 2, 24, 0x00, 0x2F, 0x37, 0x0, 0x22, 0x13, 0x11, 0x0 - 2, 32, 0x00, 0x2F, 0x34, 0x0, 0x22, 0x13, 0x11, 0x0 - 3, 12, 0x20, 0x22, 0x20, 0x0, 0x22, 0x13, 0x11, 0x0 - 3, 16, 0x20, 0x22, 0x30, 0x0, 0x22, 0x13, 0x11, 0x0 - 3, 20, 0x20, 0x22, 0x2C, 0x0, 0x22, 0x13, 0x11, 0x0 - 3, 24, 0x20, 0x22, 0x2A, 0x0, 0x22, 0x13, 0x11, 0x0 - 3, 32, 0x20, 0x22, 0x2B, 0x0, 0x22, 0x13, 0x11, 0x0 - 4, 0xFF, 0x20, 0x25, 0x20, 0x0, 0x22, 0x33, 0x11, 0x0 - 5, 0xFF, 0x20, 0x20, 0x2F, 0x0, 0x22, 0x32, 0x11, 0x0 - 0FFh + 1, 0xFF, 0x00, 0x2F, 0x2F, 0x0, 0x22, 0x13, 0x11, 0x0, + 2, 12, 0x00, 0x2F, 0x2F, 0x0, 0x22, 0x13, 0x11, 0x0, + 2, 16, 0x00, 0x2F, 0x00, 0x0, 0x22, 0x13, 0x11, 0x0, + 2, 20, 0x00, 0x2F, 0x38, 0x0, 0x22, 0x13, 0x11, 0x0, + 2, 24, 0x00, 0x2F, 0x37, 0x0, 0x22, 0x13, 0x11, 0x0, + 2, 32, 0x00, 0x2F, 0x34, 0x0, 0x22, 0x13, 0x11, 0x0, + 3, 12, 0x20, 0x22, 0x20, 0x0, 0x22, 0x13, 0x11, 0x0, + 3, 16, 0x20, 0x22, 0x30, 0x0, 0x22, 0x13, 0x11, 0x0, + 3, 20, 0x20, 0x22, 0x2C, 0x0, 0x22, 0x13, 0x11, 0x0, + 3, 24, 0x20, 0x22, 0x2A, 0x0, 0x22, 0x13, 0x11, 0x0, + 3, 32, 0x20, 0x22, 0x2B, 0x0, 0x22, 0x13, 0x11, 0x0, + 4, 0xFF, 0x20, 0x25, 0x20, 0x0, 0x22, 0x33, 0x11, 0x0, + 5, 0xFF, 0x20, 0x20, 0x2F, 0x0, 0x22, 0x32, 0x11, 0x0, + 0xFF +}; static const u8 Table_ATC_ODC_D_Ax[] = { - 1, 0xFF, 0x00, 0x2F, 0x2F, 0x0, 0x22, 0x13, 0x11, 0x0 - 2, 12, 0x00, 0x2F, 0x2F, 0x0, 0x22, 0x13, 0x11, 0x0 - 2, 16, 0x00, 0x2F, 0x00, 0x0, 0x22, 0x13, 0x11, 0x0 - 2, 20, 0x00, 0x2F, 0x38, 0x0, 0x22, 0x13, 0x11, 0x0 - 2, 24, 0x00, 0x2F, 0x37, 0x0, 0x22, 0x13, 0x11, 0x0 - 2, 32, 0x00, 0x2F, 0x34, 0x0, 0x22, 0x13, 0x11, 0x0 - 3, 12, 0x20, 0x22, 0x20, 0x0, 0x22, 0x13, 0x11, 0x0 - 3, 16, 0x20, 0x22, 0x30, 0x0, 0x22, 0x13, 0x11, 0x0 - 3, 20, 0x20, 0x22, 0x2C, 0x0, 0x22, 0x13, 0x11, 0x0 - 3, 24, 0x20, 0x22, 0x2A, 0x0, 0x22, 0x13, 0x11, 0x0 - 3, 32, 0x20, 0x22, 0x2B, 0x0, 0x22, 0x13, 0x11, 0x0 - 4, 0xFF, 0x20, 0x25, 0x20, 0x0, 0x22, 0x33, 0x11, 0x0 - 5, 0xFF, 0x20, 0x20, 0x2F, 0x0, 0x22, 0x32, 0x11, 0x0 + 1, 0xFF, 0x00, 0x2F, 0x2F, 0x0, 0x22, 0x13, 0x11, 0x0, + 2, 12, 0x00, 0x2F, 0x2F, 0x0, 0x22, 0x13, 0x11, 0x0, + 2, 16, 0x00, 0x2F, 0x00, 0x0, 0x22, 0x13, 0x11, 0x0, + 2, 20, 0x00, 0x2F, 0x38, 0x0, 0x22, 0x13, 0x11, 0x0, + 2, 24, 0x00, 0x2F, 0x37, 0x0, 0x22, 0x13, 0x11, 0x0, + 2, 32, 0x00, 0x2F, 0x34, 0x0, 0x22, 0x13, 0x11, 0x0, + 3, 12, 0x20, 0x22, 0x20, 0x0, 0x22, 0x13, 0x11, 0x0, + 3, 16, 0x20, 0x22, 0x30, 0x0, 0x22, 0x13, 0x11, 0x0, + 3, 20, 0x20, 0x22, 0x2C, 0x0, 0x22, 0x13, 0x11, 0x0, + 3, 24, 0x20, 0x22, 0x2A, 0x0, 0x22, 0x13, 0x11, 0x0, + 3, 32, 0x20, 0x22, 0x2B, 0x0, 0x22, 0x13, 0x11, 0x0, + 4, 0xFF, 0x20, 0x25, 0x20, 0x0, 0x22, 0x33, 0x11, 0x0, + 5, 0xFF, 0x20, 0x20, 0x2F, 0x0, 0x22, 0x32, 0x11, 0x0, 0xFF }; static void Get_ChannelPS_Cfg0_D( u8 MAAdimms, u8 Speed, u8 MAAload, u8 DATAAload, u32 *AddrTmgCTL, u32 *ODC_CTL, - u32 *CMDmode); + u32 *CMDmode) { u8 *p; @@ -168,5 +169,5 @@ } p+=10; } while (0xFF == *p); - + } } Index: src/northbridge/amd/amdmct/wrappers/mcti_d.c =================================================================== --- src/northbridge/amd/amdmct/wrappers/mcti_d.c (revision 4379) +++ src/northbridge/amd/amdmct/wrappers/mcti_d.c (working copy) @@ -25,9 +25,9 @@ switch (index) { case NV_PACK_TYPE: -#if SYSTEM_TYPE == SERVER +#if CPU_SOCKET_TYPE == 0x10 /* Socket F */ val = 0; -#elif SYSTEM_TYPE == DESKTOP +#elif CPU_SOCKET_TYPE == 0x11 /* AM2r2 */ val = 1; //#elif SYSTEM_TYPE == MOBILE // val = 2; Index: src/northbridge/amd/amdfam10/raminit_amdmct.c =================================================================== --- src/northbridge/amd/amdfam10/raminit_amdmct.c (revision 4379) +++ src/northbridge/amd/amdfam10/raminit_amdmct.c (working copy) @@ -63,10 +63,10 @@ #include "../amdmct/mct/mctndi_d.c" #include "../amdmct/mct/mctchi_d.c" -#if SYSTEM_TYPE == SERVER +#if CPU_SOCKET_TYPE == 0x10 //L1 #include "../amdmct/mct/mctardk3.c" -#elif SYSTEM_TYPE == DESKTOP +#elif CPU_SOCKET_TYPE == 0x11 //AM2 #include "../amdmct/mct/mctardk4.c" //#elif SYSTEM_TYPE == MOBILE

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coreboot June 2009