coreboot June 2009

coreboot@coreboot.org

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500 discussions

Re: [coreboot] SeaBIOS and hp dl145g3
by Kevin O'Connor 26 May '10

26 May '10

On Wed, Apr 29, 2009 at 04:53:13PM +0200, samuel wrote: > Hi Kevin, > > I have tried Seabios on my hp dl145 g3 (the patches from mondrian) and > it works really well now > I was able to load the vga rom and i have output on the screen. Great! > One single problem... It doesn't seem to find the sata controller... > > bootlog with coreboot and seabios: > http://merlin.ugent.be/~samuel/dl145g3/corebootwithseabios.log There isn't much SeaBIOS info in that log - can you recompile with CONFIG_DEBUG_LEVEL set to 6? > > lspci -vnn : http://merlin.ugent.be/~samuel/dl145g3/info/lspci-vnn.txt > > and the original patch from mondrian to add support for the dl145g3 to filo: > http://merlin.ugent.be/~samuel/dl145g3/patch/filo_dl145_sata.patch > > It looks rather simple but I don't see what i have to change in > seabios to support the device. > > The pci id (0x104 is already in pci_ids.h of seabios) so i would think > it should just work. Myles thought it could be related to the fact > that his sata interface of this mainboard does not support a legacy > IDE interface mode. > > You have any ideas how i could quickly add support for the hp dl145 g3 > to SeaBIOS?? The equivalent patch in SeaBIOS would look like: --- a/src/ata.c +++ b/src/ata.c @@ -841,7 +845,8 @@ ata_init() int count=0; int bdf, max; foreachpci(bdf, max) { - if (pci_config_readw(bdf, PCI_CLASS_DEVICE) != PCI_CLASS_STORAGE_IDE) + u16 class = pci_config_readw(bdf, PCI_CLASS_DEVICE); + if (class != PCI_CLASS_STORAGE_IDE && class != PCI_CLASS_STORAGE_RAID) continue; if (count >= ARRAY_SIZE(ATA.channels)) break; -Kevin

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#142: remove #warnings in the code
by coreboot 03 May '10

03 May '10

#142: remove #warnings in the code ---------------------------------+------------------------------------------ Reporter: myles | Owner: somebody Type: defect | Status: new Priority: major | Milestone: Component: coreboot | Version: v2 Keywords: | Dependencies: Patchstatus: there is no patch | ---------------------------------+------------------------------------------ #warnings in the code should be converted to tickets in trac, or fixed. Compiler warnings don't seem to be useful to get things fixed. They also obscure real warnings. The medium-term goal would be to have warning-free compilation. After that -Werror would be nice. It seems like a small thing to ask that code compile without warnings. -- Ticket URL: <http://tracker.coreboot.org/trac/coreboot/ticket/142> coreboot <http://www.coreboot.org/>

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#108: Add int 10 VESA video driver to libpayload
by coreboot 15 Apr '10

15 Apr '10

#108: Add int 10 VESA video driver to libpayload ---------------------------------+------------------------------------------ Reporter: stuge | Owner: somebody Type: enhancement | Status: new Priority: major | Milestone: Component: libpayload | Version: Keywords: video | Dependencies: Patchstatus: there is no patch | ---------------------------------+------------------------------------------ -- Ticket URL: <http://tracker.coreboot.org/trac/coreboot/ticket/108> coreboot <http://www.coreboot.org/>

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#129: Add support for high_tables_base for all chipsets that don't support it yet.
by coreboot 15 Apr '10

15 Apr '10

#129: Add support for high_tables_base for all chipsets that don't support it yet. ---------------------------------+------------------------------------------ Reporter: oxygene | Owner: somebody Type: defect | Status: new Priority: critical | Milestone: Component: coreboot | Version: v2 Keywords: | Dependencies: Patchstatus: there is no patch | ---------------------------------+------------------------------------------ Without tables in high memory, seabios won't run on your chipset properly. it overwrites your tables in the F segment, as seabios itself lives there. Also, once there is support for high_tables_base everywhere, the code in src/arch/i386/boot/tables.c can be cleaned up and simplified considerably. -- Ticket URL: <http://tracker.coreboot.org/trac/coreboot/ticket/129> coreboot <http://www.coreboot.org/>

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#139: flashrom: -c option should be case insensitive
by coreboot 15 Apr '10

15 Apr '10

#139: flashrom: -c option should be case insensitive ---------------------------------+------------------------------------------ Reporter: uwe | Owner: somebody Type: enhancement | Status: new Priority: minor | Milestone: Component: flashrom | Version: Keywords: | Dependencies: Patchstatus: there is no patch | ---------------------------------+------------------------------------------ flashrom's -c option requires you to enter extact chip names. It should probably be case insensitive for easier usage. -- Ticket URL: <http://tracker.coreboot.org/trac/coreboot/ticket/139> coreboot <http://www.coreboot.org/>

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#103: flashrom: Don't exit() after successful erase operation
by coreboot 12 Apr '10

12 Apr '10

#103: flashrom: Don't exit() after successful erase operation ---------------------------------+------------------------------------------ Reporter: stuge | Owner: somebody Type: defect | Status: new Priority: major | Milestone: flashrom v1.0 Component: flashrom | Version: Keywords: erase exit | Dependencies: Patchstatus: there is no patch | ---------------------------------+------------------------------------------ -- Ticket URL: <http://tracker.coreboot.org/trac/coreboot/ticket/103> coreboot <http://www.coreboot.org/>

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#119: Winbond W39V040FBPZ is not written correctly by flashrom
by coreboot 12 Apr '10

12 Apr '10

#119: Winbond W39V040FBPZ is not written correctly by flashrom -----------------------------------------+---------------------------------- Reporter: charles.herndon@… | Owner: somebody Type: enhancement | Status: new Priority: minor | Milestone: Component: flashrom | Version: v2 Keywords: W39V040FBPZ | Dependencies: Patchstatus: there is no patch | -----------------------------------------+---------------------------------- Flash device is detected as a Winbond W39V040B device. Flashrom attempts to flash device, but verification fails. No actual writing to the chip appears to be done. Tried changing write and erase in flashchips.c to: jedec, winbond_fwhub and 49lfxxxc. ./flashrom -wv xxxx.bin Calibrating delay loop... OK. No coreboot table found. Found chipset "Intel ICH7/ICH7R", enabling flash write... OK. Found chip "Winbond W39V040B" (512 KB) at physical address 0xfff80000. Flash image seems to be a legacy BIOS. Disabling checks. Programming page: 0007 at address: 0x00070000 Verifying flash... FAILED! Expected=0xc7, Read=0x49 -- Ticket URL: <http://tracker.coreboot.org/trac/coreboot/ticket/119> coreboot <http://www.coreboot.org/>

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#104: flashrom: Change flash drivers to never erase data before writing
by coreboot 16 Jan '10

16 Jan '10

#104: flashrom: Change flash drivers to never erase data before writing ---------------------------------+------------------------------------------ Reporter: stuge | Owner: somebody Type: defect | Status: new Priority: major | Milestone: flashrom v1.0 Component: flashrom | Version: Keywords: erase write | Dependencies: #103 Patchstatus: there is no patch | ---------------------------------+------------------------------------------ The user should be responsible for ensuring that the flash chip has been erased where new data should be written. At the moment, flashrom will erase at least one full page and then rewrite it, when the user asks to only write a few bytes using -l/-i/-s/-e. -- Ticket URL: <http://tracker.coreboot.org/trac/coreboot/ticket/104> coreboot <http://www.coreboot.org/>

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#101: flashrom: Remove pciutils check from Makefile
by coreboot 16 Jan '10

16 Jan '10

#101: flashrom: Remove pciutils check from Makefile ---------------------------------------------+------------------------------ Reporter: stuge | Owner: somebody Type: defect | Status: new Priority: major | Milestone: flashrom v1.0 Component: flashrom | Version: Keywords: pciutils libpci build ldflags | Dependencies: Patchstatus: patch needs review | ---------------------------------------------+------------------------------ The check belongs in a configure script or similar, the check also claims that packages can not be found for any build error, which is not good enough. Has confused more than one user already. -- Ticket URL: <http://tracker.coreboot.org/trac/coreboot/ticket/101> coreboot <http://www.coreboot.org/>

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#120: flashrom failure to read
by coreboot 16 Jan '10

16 Jan '10

#120: flashrom failure to read ---------------------------------+------------------------------------------ Reporter: toc@… | Owner: somebody Type: defect | Status: new Priority: major | Milestone: Component: flashrom | Version: v2 Keywords: | Dependencies: Patchstatus: there is no patch | ---------------------------------+------------------------------------------ Running flashrom -r rom.file results in an output file of all null bytes. Standard output: {{{ Calibrating delay loop... OK. No coreboot table found. Found chipset "Intel ICH9R", enabling flash write... tried to set 0xdc to 0x3 on Intel ICH9R failed (WARNING ONLY) FAILED! Found chip "Macronix MX25L8005" (1024 KB) at physical address 0xfff00000. Reading flash... done. }}} Verbose output indicates failure of opcode 0x03. {{{ Reading flash... ich_spi_read_page: offset=0, number=256, buf=0xb7cf0008 Opcode 3 not found. run OPCODE 0x03 failed Error readingdone. }}} Full verbose output attached -- Ticket URL: <http://tracker.coreboot.org/trac/coreboot/ticket/120> coreboot <http://www.coreboot.org/>

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coreboot June 2009