coreboot June 2009

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Re: [coreboot] Flashrom support for EPIA-N(L) - patch for review
by Luc Verhaegen 18 Jun '09

18 Jun '09

On Thu, Jun 18, 2009 at 11:36:49AM +0100, Harrison, Jon (SELEX GALILEO, UK) wrote: > > Auto detection doesn't seem to be working properly and at this stage I'm > breaking things so much that the -m switch is necessary for reliable > operation. Why doesn't it seem to work properly? Luc Verhaegen.

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Re: [coreboot] Flashrom support for EPIA-N(L) - patch for review
by Carl-Daniel Hailfinger 18 Jun '09

18 Jun '09

Hi Jon, could you please resend the patch as attachment? It seems your mailer mangled long lines. Thanks. On 18.06.2009 12:36, Harrison, Jon (SELEX GALILEO, UK) wrote: > I've incorporated mods as suggested except for removing the coreboot ids > and updated for r602. > > Re-tested erase, read, verify, write, read, verify. > > Auto detection doesn't seem to be working properly and at this stage I'm > breaking things so much that the -m switch is necessary for reliable > operation. > Regards, Carl-Daniel -- http://www.hailfinger.org/

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Re: [coreboot] Flashrom support for EPIA-N(L) - patch for review
by Luc Verhaegen 18 Jun '09

18 Jun '09

On Wed, Jun 17, 2009 at 12:36:41PM +0100, Harrison, Jon (SELEX GALILEO, UK) wrote: > Hi Guys, > > See below patch for flashrom to add support for EPIA-N(L) Programming. > > This has been built against R599 and tested for read, write and verify > on an EPIA-NL 800 > > Seems to work for me! > > Regards, > Jon > > > Index: util/flashrom/board_enable.c > =================================================================== > --- util/flashrom/board_enable.c (revision 599) > +++ util/flashrom/board_enable.c (working copy) > @@ -270,6 +270,44 @@ > } > > /** > + * Suited for VIAs EPIA N & NL. > + */ > +static int board_via_epia_n(const char *name) > +{ > + struct pci_dev *dev; > + uint16_t base; > + uint8_t val; > + > + dev = pci_dev_find(0x1106, 0x3227); /* VT8237R ISA bridge */ > + if (!dev) { > + fprintf(stderr, "\nERROR: VT8237R ISA bridge not > found.\n"); > + return -1; > + } > + > + /* All memory cycles, not just ROM ones, go to LPC */ > + val = pci_read_byte(dev, 0x59); > + val &= ~0x80; > + pci_write_byte(dev, 0x59, val); > + > + /* GPIO9 -> output */ > + val = pci_read_byte(dev, 0xE4); > + //printf("GPO Pin Select Reg = 0x%02X\n", val); > + val |= 0x20; > + pci_write_byte(dev, 0xE4, val); > + > + /* Get Power Management IO address. */ > + base = pci_read_word(dev, 0x88) & 0xFF80; > + > + /* Enable GPIO9 which is connected to write protect. */ > + val = INB(base + 0x4D); > + //printf("PMM GPIO = 0x%02X\n", val); > + val |= 0x02; > + OUTB(val, base + 0x4D); > + > + return 0; > +} > + Please use vt823x_set_all_writes_to_lpc and vt823x_gpio_set I will verify and fix gpio_set for setting other gpio lines than 12-15, in the next hour or so. Remove the //printf. > + {0x1106, 0x0259, 0x1106, 0xaa08, 0x1106, 0x3227, 0x1106, > 0xAA08, "via", "epia-n", "VIA", "EPIA-N/NL", > board_via_epia_n}, Please remove the coreboot ids. This hardware can be autodetected, and you should not disable rom access in your upcoming coreboot support, and therefor will not need this board enable. So NACK on this first pass, but will ack once issues are addressed, and once vt823x_gpio_set is fixed. Luc Verhaegen.

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build service results for r4362
by coreboot information 18 Jun '09

18 Jun '09

Dear coreboot readers! This is the automatic build system of coreboot. The developer "hargut" checked in revision 4362 to the coreboot repository. This caused the following changes: Change Log: Change Log: Fix interrupt handling in mptable.c on M57SLI. Signed-off-by: Harald Gutmann <harald.gutmann(a)gmx.net> Acked-by: Luc Verhaegen <libv(a)skynet.be> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Build Log: Compilation of embeddedplanet:ep405pc is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4362&device=ep405pc&vendor… Compilation of motorola:sandpointx3_altimus_mpc7410 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4362&device=sandpointx3_al… Compilation of totalimpact:briq is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4362&device=briq&vendor=to… Compilation of via:epia-m700 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4362&device=epia-m700&vend… If something broke during this checkin please be a pain in hargut's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

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Gigabyte M57SLI-S4 Interrupt Fix
by Harald Gutmann 18 Jun '09

18 Jun '09

Hello, after a few tries of me to fix the interrupt problems which occurred on the M57SLI here is the final patch from me. The Patch fixes the following issues on M57SLI: * Interrupt routing in the MPTable which affects the following hardware parts: * PCI-E 16x Slots (blue and black) - both are working now like a charm * PCI-E 1x Slots - all three should be fine, but I have no card to test. (untested) * PCI Slots - both work fine now. This is the first and (hopefully) the last patch on this issue which gets a Signed-off-by: Harald Gutmann <harald.gutmann(a)gmx.net> from me. I'm really looking forward to commit this patch (which is my first one) and mark the interrupt issues on the wiki page to the M57SLI as solved. :) Kind regards, Harald Gutmann

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build service results for r4361
by coreboot information 18 Jun '09

18 Jun '09

Dear coreboot readers! This is the automatic build system of coreboot. The developer "hargut" checked in revision 4361 to the coreboot repository. This caused the following changes: Change Log: Change Log: Activate HIGH_TABES on M57SLI Signed-off-by: Harald Gutmann <harald.gutmann(a)gmx.net> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Build Log: Compilation of embeddedplanet:ep405pc is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4361&device=ep405pc&vendor… Compilation of motorola:sandpointx3_altimus_mpc7410 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4361&device=sandpointx3_al… Compilation of totalimpact:briq is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4361&device=briq&vendor=to… Compilation of via:epia-m700 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4361&device=epia-m700&vend… If something broke during this checkin please be a pain in hargut's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

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[v2] r4362 - trunk/coreboot-v2/src/mainboard/gigabyte/m57sli
by svn＠coreboot.org 18 Jun '09

18 Jun '09

Author: hargut Date: 2009-06-18 12:05:41 +0200 (Thu, 18 Jun 2009) New Revision: 4362 Modified: trunk/coreboot-v2/src/mainboard/gigabyte/m57sli/mptable.c Log: Change Log: Fix interrupt handling in mptable.c on M57SLI. Signed-off-by: Harald Gutmann <harald.gutmann(a)gmx.net> Acked-by: Luc Verhaegen <libv(a)skynet.be> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Modified: trunk/coreboot-v2/src/mainboard/gigabyte/m57sli/mptable.c =================================================================== --- trunk/coreboot-v2/src/mainboard/gigabyte/m57sli/mptable.c 2009-06-18 09:46:11 UTC (rev 4361) +++ trunk/coreboot-v2/src/mainboard/gigabyte/m57sli/mptable.c 2009-06-18 10:05:41 UTC (rev 4362) @@ -3,6 +3,7 @@ * * Copyright (C) 2007 AMD * Written by Yinghai Lu <yinghailu(a)amd.com> for AMD. + * Copyright (C) 2009 Harald Gutmann <harald.gutmann(a)gmx.net> * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -43,7 +44,7 @@ struct mp_config_table *mc; unsigned sbdn; - int i,j; + int i,j,k; mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); memset(mc, 0, sizeof(*mc)); @@ -79,7 +80,6 @@ { device_t dev; struct resource *res; - uint32_t dword; dev = dev_find_slot(bus_mcp55[0], PCI_DEVFN(sbdn+ 0x1,0)); if (dev) { @@ -87,19 +87,13 @@ if (res) { smp_write_ioapic(mc, apicid_mcp55, 0x11, res->base); } - - dword = 0x43c6c643; - pci_write_config32(dev, 0x7c, dword); - - dword = 0x81001a00; - pci_write_config32(dev, 0x80, dword); - - dword = 0xd0001202; - pci_write_config32(dev, 0x84, dword); - + /* set up the interrupt registers of mcp55 */ + pci_write_config32(dev, 0x7c, 0xc643c643); + pci_write_config32(dev, 0x80, 0x8da01009); + pci_write_config32(dev, 0x84, 0x200018d2); } } - + /*I/O Ints: Type Trigger Polarity Bus ID IRQ APIC ID PIN# */ smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, apicid_mcp55, 0x0); @@ -128,31 +122,39 @@ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,\ bus_mcp55[bus], (((dev)<<2)|(fn)), apicid_mcp55, (pin)) - PCI_INT(0,sbdn+1,1, 10); /* SMBus */ - PCI_INT(0,sbdn+2,0, 22); /* USB */ - PCI_INT(0,sbdn+2,1, 23); /* USB */ - PCI_INT(0,sbdn+6,1, 23); /* HD Audio */ - PCI_INT(0,sbdn+5,0, 20); /* SATA */ - PCI_INT(0,sbdn+5,1, 23); /* SATA */ - PCI_INT(0,sbdn+5,2, 21); /* SATA */ + PCI_INT(0,sbdn+1,1, 10); /* SMBus */ + PCI_INT(0,sbdn+2,0, 22); /* USB */ + PCI_INT(0,sbdn+2,1, 23); /* USB */ + PCI_INT(0,sbdn+4,0, 21); /* IDE */ + PCI_INT(0,sbdn+5,0, 20); /* SATA */ + PCI_INT(0,sbdn+5,1, 21); /* SATA */ + PCI_INT(0,sbdn+5,2, 22); /* SATA */ + PCI_INT(0,sbdn+6,1, 23); /* HD Audio */ + PCI_INT(0,sbdn+8,0, 20); /* GBit Ethernet */ - PCI_INT(0,sbdn+8,0, 22); /* GBit Ether */ - /* The PCIe slots, each on its own bus */ - for(j=7; j>=2; j--) { - if(!bus_mcp55[j]) continue; - for(i=0;i<4;i++) { /* map all functions */ - PCI_INT(j,0,i, 16+(1+j+i)%4); - } - } + k = 1; + for(i=0; i<4; i++){ + for(j=7; j>1; j--){ + if(k>3) k=0; + PCI_INT(j,0,i, 16+k); + k++; + } + k--; + } - /* On bus 1: the physical PCI bus slots... */ - for(j=0; j<2; j++) /* on a Rev 1.x board, they are devs 7 and 8 */ - for(i=0;i<4;i++) { /* map all functions */ - PCI_INT(1,7+j,i, 16+(3+i+j)%4); - } - /* ... and OB FireWire */ - PCI_INT(1,0x0a,0, 18); + /* On bus 1: the PCI bus slots... + pyhsical PCI slots are j = 7,8 + FireWire is j = 10 + */ + k=2; + for(i=0; i<4; i++){ + for(j=6; j<11; j++){ + if(k>3) k=0; + PCI_INT(1,j,i, 16+k); + k++; + } + } /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/ smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x0);

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Activate HIGH_TABES on M57SLI
by Harald Gutmann 18 Jun '09

18 Jun '09

Hello! This little patch activates HIGH_TABLES on M57SLI. I tested it with a recent SeaBios version, and it works. Signed-off-by: Harald Gutmann <harald.gutmann(a)gmx.net> Kind regards, Harald

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[v2] r4361 - trunk/coreboot-v2/src/mainboard/gigabyte/m57sli
by svn＠coreboot.org 18 Jun '09

18 Jun '09

Author: hargut Date: 2009-06-18 11:46:11 +0200 (Thu, 18 Jun 2009) New Revision: 4361 Modified: trunk/coreboot-v2/src/mainboard/gigabyte/m57sli/Options.lb Log: Change Log: Activate HIGH_TABES on M57SLI Signed-off-by: Harald Gutmann <harald.gutmann(a)gmx.net> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Modified: trunk/coreboot-v2/src/mainboard/gigabyte/m57sli/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/gigabyte/m57sli/Options.lb 2009-06-17 16:38:43 UTC (rev 4360) +++ trunk/coreboot-v2/src/mainboard/gigabyte/m57sli/Options.lb 2009-06-18 09:46:11 UTC (rev 4361) @@ -87,6 +87,8 @@ uses HW_MEM_HOLE_SIZE_AUTO_INC uses K8_HT_FREQ_1G_SUPPORT +uses HAVE_HIGH_TABLES + uses HT_CHAIN_UNITID_BASE uses HT_CHAIN_END_UNITID_BASE uses SB_HT_CHAIN_ON_BUS0 @@ -169,6 +171,9 @@ ## default HAVE_MP_TABLE=1 +## HIGH tables support +default HAVE_HIGH_TABLES=1 + ## ACPI tables will be included default HAVE_ACPI_TABLES=0 @@ -356,10 +361,10 @@ ## Select power on after power fail setting default MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON" -### End Options.lb # # CBFS # # default CONFIG_CBFS=0 +### End Options.lb end

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Re: [coreboot] Via EPIA-N(L) C3/CN400 Support - Initial Patch for V2
by ron minnich 18 Jun '09

18 Jun '09

Hi, I notice you have an ACPI blob in there. Where did that come from? thanks ron

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coreboot June 2009