coreboot June 2009

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[PATCH] flashrom: Remove duplicated [file] from usage help
by Carl-Daniel Hailfinger 24 Jun '09

24 Jun '09

Remove duplicated [file] from usage help. A file is already specified directly in conjunction for -r/-w/-v. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: flashrom-fix_duplicated_file_in_usage_message/flashrom.8 =================================================================== --- flashrom-fix_duplicated_file_in_usage_message/flashrom.8 (Revision 607) +++ flashrom-fix_duplicated_file_in_usage_message/flashrom.8 (Arbeitskopie) @@ -4,7 +4,7 @@ .SH SYNOPSIS .B flashrom \fR[\fB\-VfLzhR\fR] [\fB\-E\fR|\fB\-r\fR file|\fB\-w\fR file|\fB\-v\fR file] [\fB\-c\fR chipname] [\fB\-s\fR addr] [\fB\-e\fR addr] [\fB\-m\fR [vendor:]part] - [\fB\-l\fR file] [\fB\-i\fR image] [\fB\-p\fR programmer] [file] + [\fB\-l\fR file] [\fB\-i\fR image] [\fB\-p\fR programmer] .SH DESCRIPTION .B flashrom is a utility for detecting, reading, writing, verifying and erasing flash Index: flashrom-fix_duplicated_file_in_usage_message/flashrom.c =================================================================== --- flashrom-fix_duplicated_file_in_usage_message/flashrom.c (Revision 607) +++ flashrom-fix_duplicated_file_in_usage_message/flashrom.c (Arbeitskopie) @@ -483,7 +483,7 @@ void usage(const char *name) { printf("usage: %s [-VfLzhR] [-E|-r file|-w file|-v file] [-c chipname] [-s addr]\n" - " [-e addr] [-m [vendor:]part] [-l file] [-i image] [-p programmer] [file]\n\n", name); + " [-e addr] [-m [vendor:]part] [-l file] [-i image] [-p programmer]\n\n", name); printf("Please note that the command line interface for flashrom will " "change before\nflashrom 1.0. Do not use flashrom in scripts " @@ -510,9 +510,8 @@ " it87spi, ft2232spi)\n" " -h | --help: print this help text\n" " -R | --version: print the version (release)\n" - "\nYou can specify one of -E, -r, -w, -v or no operation. " - "If no operation is\nspecified, then all that happens" - " is that flash info is dumped.\n\n"); + "\nYou can specify one of -E, -r, -w, -v or no operation. If no operation is\n" + "specified, then all that happens is that flash info is dumped.\n\n"); exit(1); } -- http://www.hailfinger.org/ Index: flashrom-fix_duplicated_file_in_usage_message/flashrom.8 =================================================================== --- flashrom-fix_duplicated_file_in_usage_message/flashrom.8 (Revision 607) +++ flashrom-fix_duplicated_file_in_usage_message/flashrom.8 (Arbeitskopie) @@ -4,7 +4,7 @@ .SH SYNOPSIS .B flashrom \fR[\fB\-VfLzhR\fR] [\fB\-E\fR|\fB\-r\fR file|\fB\-w\fR file|\fB\-v\fR file] [\fB\-c\fR chipname] [\fB\-s\fR addr] [\fB\-e\fR addr] [\fB\-m\fR [vendor:]part] - [\fB\-l\fR file] [\fB\-i\fR image] [\fB\-p\fR programmer] [file] + [\fB\-l\fR file] [\fB\-i\fR image] [\fB\-p\fR programmer] .SH DESCRIPTION .B flashrom is a utility for detecting, reading, writing, verifying and erasing flash Index: flashrom-fix_duplicated_file_in_usage_message/flashrom.c =================================================================== --- flashrom-fix_duplicated_file_in_usage_message/flashrom.c (Revision 607) +++ flashrom-fix_duplicated_file_in_usage_message/flashrom.c (Arbeitskopie) @@ -483,7 +483,7 @@ void usage(const char *name) { printf("usage: %s [-VfLzhR] [-E|-r file|-w file|-v file] [-c chipname] [-s addr]\n" - " [-e addr] [-m [vendor:]part] [-l file] [-i image] [-p programmer] [file]\n\n", name); + " [-e addr] [-m [vendor:]part] [-l file] [-i image] [-p programmer]\n\n", name); printf("Please note that the command line interface for flashrom will " "change before\nflashrom 1.0. Do not use flashrom in scripts " @@ -510,9 +510,8 @@ " it87spi, ft2232spi)\n" " -h | --help: print this help text\n" " -R | --version: print the version (release)\n" - "\nYou can specify one of -E, -r, -w, -v or no operation. " - "If no operation is\nspecified, then all that happens" - " is that flash info is dumped.\n\n"); + "\nYou can specify one of -E, -r, -w, -v or no operation. If no operation is\n" + "specified, then all that happens is that flash info is dumped.\n\n"); exit(1); }

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[flashrom] r628 - trunk
by svn＠coreboot.org 24 Jun '09

24 Jun '09

Author: hailfinger Date: 2009-06-24 10:18:38 +0200 (Wed, 24 Jun 2009) New Revision: 628 Modified: trunk/flashrom.8 trunk/flashrom.c Log: Remove duplicated [file] from usage help. A file is already specified directly in conjunction for -r/-w/-v. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Modified: trunk/flashrom.8 =================================================================== --- trunk/flashrom.8 2009-06-23 20:27:33 UTC (rev 627) +++ trunk/flashrom.8 2009-06-24 08:18:38 UTC (rev 628) @@ -4,7 +4,7 @@ .SH SYNOPSIS .B flashrom \fR[\fB\-VfLzhR\fR] [\fB\-E\fR|\fB\-r\fR file|\fB\-w\fR file|\fB\-v\fR file] [\fB\-c\fR chipname] [\fB\-m\fR [vendor:]part] - [\fB\-l\fR file] [\fB\-i\fR image] [\fB\-p\fR programmer] [file] + [\fB\-l\fR file] [\fB\-i\fR image] [\fB\-p\fR programmer] .SH DESCRIPTION .B flashrom is a utility for detecting, reading, writing, verifying and erasing flash Modified: trunk/flashrom.c =================================================================== --- trunk/flashrom.c 2009-06-23 20:27:33 UTC (rev 627) +++ trunk/flashrom.c 2009-06-24 08:18:38 UTC (rev 628) @@ -493,7 +493,7 @@ void usage(const char *name) { printf("usage: %s [-VfLzhR] [-E|-r file|-w file|-v file] [-c chipname]\n" - " [-m [vendor:]part] [-l file] [-i image] [-p programmer] [file]\n\n", name); + " [-m [vendor:]part] [-l file] [-i image] [-p programmer]\n\n", name); printf("Please note that the command line interface for flashrom will " "change before\nflashrom 1.0. Do not use flashrom in scripts " @@ -518,9 +518,8 @@ " it87spi, ft2232spi, serprog)\n" " -h | --help: print this help text\n" " -R | --version: print the version (release)\n" - "\nYou can specify one of -E, -r, -w, -v or no operation. " - "If no operation is\nspecified, then all that happens" - " is that flash info is dumped.\n\n"); + "\nYou can specify one of -E, -r, -w, -v or no operation. If no operation is\n" + "specified, then all that happens is that flash info is dumped.\n\n"); exit(1); }

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Which file should I burn?
by Rick Ant 24 Jun '09

24 Jun '09

I got this message : ================= boot: hda:/boot/vmlinuz root=/dev/hda initrd=/boot/initrd console=ttyS0 hda: LBA48 524MB: QEMU HARDDISK Mounted ext2fs Found Linux version 2.6.16.5 (root@e-smith) #2 PREEMPT Sat Sep 22 00:14:46 Local time zone must be set--see bzImage. Loading kernel... ok Loading initrd... ok Jumping to entry point... ============== Is the coreboot working fine ? or not yet ? Can I write it to Compact flash for real boot ? How ? Which file should I burn ? the bios.bin? Thanks

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Re: [coreboot] Which file should I burn?
by Rick Ant 24 Jun '09

24 Jun '09

Hello, then I will burn the bios.bin into the flash ROM chip 49LF004, the original BIOS system will be removed ? and disk.img into Compact flash... Am I right in this point ? Thanks --- On Tue, 6/23/09, David Hendricks <david.hendricks(a)gmail.com> wrote: From: David Hendricks <david.hendricks(a)gmail.com> Subject: Re: [coreboot] Which file should I burn? To: "Rick Ant" <rick_077(a)yahoo.com> Cc: coreboot(a)coreboot.org Date: Tuesday, June 23, 2009, 7:49 PM On Tue, Jun 23, 2009 at 7:06 PM, Rick Ant <rick_077(a)yahoo.com> wrote: I got this message : ================= boot: hda:/boot/vmlinuz root=/dev/hda initrd=/boot/initrd console=ttyS0 hda: LBA48 524MB: QEMU HARDDISK Mounted ext2fs Found Linux version 2.6.16.5 (root@e-smith) #2 PREEMPT Sat Sep 22 00:14:46 Local time zone must be set--see bzImage. Loading kernel... ok Loading initrd... ok Jumping to entry point... ============== Is the coreboot working fine ? or not yet ? Can I write it to Compact flash for real boot ? How ? Which file should I burn ? the bios.bin? Thanks Yep, Coreboot is working fine and you're squarely in kernel mode at this point. Make sure you have all the requisite serial driver support compiled statically into your kernel (Device Drivers --> Character Devices --> Serial Drivers) so you can see the kernel messages. Copy your system image to your storage media (compact flash?) as you normally would and try it out with the vendor BIOS first to verify that the system image + kernel work fine on real hardware. If you're comfortable with the QEMU trial results, and you have a sane way of recovering the vendor BIOS, use flashrom to burn the new Coreboot image to the firmware ROM.

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build service results for r4369
by coreboot information 24 Jun '09

24 Jun '09

Dear coreboot readers! This is the automatic build system of coreboot. The developer "uwe" checked in revision 4369 to the coreboot repository. This caused the following changes: Change Log: Add support for the Soyo SY-6BA+ III board. Tested on hardware by Andrew Morgan <ziltro(a)ziltro.com>, boots Linux fine. Detailed status at: http://www.coreboot.org/Soyo_SY-6BA_Plus_III Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Andrew Morgan <ziltro(a)ziltro.com> Build Log: Compilation of motorola:sandpointx3_altimus_mpc7410 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4369&device=sandpointx3_al… Compilation of via:epia-m700 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4369&device=epia-m700&vend… If something broke during this checkin please be a pain in uwe's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

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Soyo SY-6BA+ III
by Andrew Morgan 24 Jun '09

24 Jun '09

Hi, Here is the output of 'lspci -tvnn', 'superiotool -dV', 'getpir', and 'mptable' run on the (beautifully named) Soyo SY-6BA+ III motherboard. -- Andrew. -[0000:00]-+-00.0 Intel Corporation 440BX/ZX/DX - 82443BX/ZX/DX Host bridge [8086:7190] +-01.0-[0000:01]----00.0 S3 Inc. 86c368 [Trio 3D/2X] [5333:8a13] +-07.0 Intel Corporation 82371AB/EB/MB PIIX4 ISA [8086:7110] +-07.1 Intel Corporation 82371AB/EB/MB PIIX4 IDE [8086:7111] +-07.2 Intel Corporation 82371AB/EB/MB PIIX4 USB [8086:7112] +-07.3 Intel Corporation 82371AB/EB/MB PIIX4 ACPI [8086:7113] \-0f.0 Realtek Semiconductor Co., Ltd. RTL-8139/8139C/8139C+ [10ec:8139] MP FPS NOT found, suggest trying -grope option!!! /* generated by MPTable, version 2.0.15*/ /* as modified by RGM for coreboot */ #include <console/console.h> #include <arch/smp/mpspec.h> #include <device/pci.h> #include <string.h> #include <stdint.h> void *smp_write_config_table(void *v) { static const char sig[4] = "PCMP"; static const char oem[8] = "LNXI "; static const char productid[12] = "P4DPE "; struct mp_config_table *mc; mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); memset(mc, 0, sizeof(*mc)); memcpy(mc->mpc_signature, sig, sizeof(sig)); mc->mpc_length = sizeof(*mc); /* initially just the header */ mc->mpc_spec = 0x04; mc->mpc_checksum = 0; /* not yet computed */ memcpy(mc->mpc_oem, oem, sizeof(oem)); memcpy(mc->mpc_productid, productid, sizeof(productid)); mc->mpc_oemptr = 0; mc->mpc_oemsize = 0; mc->mpc_entry_count = 0; /* No entries yet... */ mc->mpc_lapic = LAPIC_ADDR; mc->mpe_length = 0; mc->mpe_checksum = 0; mc->reserved = 0; smp_write_processors(mc); superiotool r4356 Probing for ALi Super I/O at 0x3f0... Failed. Returned data: id=0xffff, rev=0xff Probing for ALi Super I/O at 0x370... Failed. Returned data: id=0xffff, rev=0xff Probing for Fintek Super I/O at 0x2e... Failed. Returned data: vid=0xffff, id=0xffff Probing for Fintek Super I/O at 0x4e... Failed. Returned data: vid=0xffff, id=0xffff Probing for ITE Super I/O (init=standard) at 0x2e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=it8761e) at 0x2e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=it8228e) at 0x2e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=0x87,0x87) at 0x2e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=standard) at 0x4e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=it8761e) at 0x4e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=it8228e) at 0x4e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=0x87,0x87) at 0x4e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=legacy/it8661f) at 0x370... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=legacy/it8671f) at 0x370... Found ITE IT8671F/IT8687R (id=0x8681, rev=0x1) at 0x370 No dump available for this Super I/O Probing for NSC Super I/O at 0x2e... Failed. Returned data: port=0xff, port+1=0xff Probing for NSC Super I/O at 0x4e... Failed. Returned data: port=0xff, port+1=0xff Probing for NSC Super I/O at 0x15c... Failed. Returned data: port=0xff, port+1=0xff Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x2e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x2e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x4e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x4e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x162e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x162e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x164e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x164e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x3f0... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x3f0... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x370... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x370... Failed. Returned data: id=0xff, rev=0xff Probing for Winbond Super I/O (init=0x88) at 0x2e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x89) at 0x2e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x86,0x86) at 0x2e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x87,0x87) at 0x2e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x88) at 0x4e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x89) at 0x4e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x86,0x86) at 0x4e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x87,0x87) at 0x4e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x88) at 0x3f0... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x89) at 0x3f0... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x86,0x86) at 0x3f0... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x87,0x87) at 0x3f0... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x88) at 0x370... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x89) at 0x370... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x86,0x86) at 0x370... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x87,0x87) at 0x370... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x88) at 0x250... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x89) at 0x250... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x86,0x86) at 0x250... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x87,0x87) at 0x250... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff

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[v2] r4369 - in trunk/coreboot-v2: src/mainboard src/mainboard/soyo src/mainboard/soyo/sy-6ba-plus-iii targets targets/soyo targets/soyo/sy-6ba-plus-iii
by svn＠coreboot.org 24 Jun '09

24 Jun '09

Author: uwe Date: 2009-06-24 02:35:07 +0200 (Wed, 24 Jun 2009) New Revision: 4369 Added: trunk/coreboot-v2/src/mainboard/soyo/ trunk/coreboot-v2/src/mainboard/soyo/sy-6ba-plus-iii/ trunk/coreboot-v2/src/mainboard/soyo/sy-6ba-plus-iii/Config.lb trunk/coreboot-v2/src/mainboard/soyo/sy-6ba-plus-iii/Options.lb trunk/coreboot-v2/src/mainboard/soyo/sy-6ba-plus-iii/auto.c trunk/coreboot-v2/src/mainboard/soyo/sy-6ba-plus-iii/chip.h trunk/coreboot-v2/src/mainboard/soyo/sy-6ba-plus-iii/irq_tables.c trunk/coreboot-v2/src/mainboard/soyo/sy-6ba-plus-iii/mainboard.c trunk/coreboot-v2/targets/soyo/ trunk/coreboot-v2/targets/soyo/sy-6ba-plus-iii/ trunk/coreboot-v2/targets/soyo/sy-6ba-plus-iii/Config.lb Log: Add support for the Soyo SY-6BA+ III board. Tested on hardware by Andrew Morgan <ziltro(a)ziltro.com>, boots Linux fine. Detailed status at: http://www.coreboot.org/Soyo_SY-6BA_Plus_III Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Andrew Morgan <ziltro(a)ziltro.com> Added: trunk/coreboot-v2/src/mainboard/soyo/sy-6ba-plus-iii/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/soyo/sy-6ba-plus-iii/Config.lb (rev 0) +++ trunk/coreboot-v2/src/mainboard/soyo/sy-6ba-plus-iii/Config.lb 2009-06-24 00:35:07 UTC (rev 4369) @@ -0,0 +1,126 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2009 Uwe Hermann <uwe(a)hermann-uwe.de> +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +## XIP_ROM_SIZE must be a power of 2. +default XIP_ROM_SIZE = 64 * 1024 +include /config/nofailovercalculation.lb + +arch i386 end +driver mainboard.o +if HAVE_PIRQ_TABLE + object irq_tables.o +end +makerule ./failover.E + depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" + action "../romcc -E -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" +end +makerule ./failover.inc + depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" + action "../romcc -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" +end +makerule ./auto.E + # depends "$(MAINBOARD)/auto.c option_table.h ../romcc" + depends "$(MAINBOARD)/auto.c ../romcc" + action "../romcc -E -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" +end +makerule ./auto.inc + # depends "$(MAINBOARD)/auto.c option_table.h ../romcc" + depends "$(MAINBOARD)/auto.c ../romcc" + action "../romcc -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" +end +mainboardinit cpu/x86/16bit/entry16.inc +mainboardinit cpu/x86/32bit/entry32.inc +ldscript /cpu/x86/16bit/entry16.lds +ldscript /cpu/x86/32bit/entry32.lds +if USE_FALLBACK_IMAGE + mainboardinit cpu/x86/16bit/reset16.inc + ldscript /cpu/x86/16bit/reset16.lds +else + mainboardinit cpu/x86/32bit/reset32.inc + ldscript /cpu/x86/32bit/reset32.lds +end +mainboardinit arch/i386/lib/cpu_reset.inc +mainboardinit arch/i386/lib/id.inc +ldscript /arch/i386/lib/id.lds +if USE_FALLBACK_IMAGE + ldscript /arch/i386/lib/failover.lds + mainboardinit ./failover.inc +end +mainboardinit cpu/x86/fpu/enable_fpu.inc +mainboardinit cpu/x86/mmx/enable_mmx.inc +mainboardinit ./auto.inc +mainboardinit cpu/x86/mmx/disable_mmx.inc + +dir /pc80 +config chip.h + +chip northbridge/intel/i440bx # Northbridge + device apic_cluster 0 on # APIC cluster + chip cpu/intel/slot_2 # CPU (FIXME: It's slot 1, actually) + device apic 0 on end # APIC + end + end + device pci_domain 0 on # PCI domain + device pci 0.0 on end # Host bridge + device pci 1.0 on end # PCI/AGP bridge + chip southbridge/intel/i82371eb # Southbridge + device pci 7.0 on # ISA bridge + chip superio/ite/it8671f # Super I/O + device pnp 370.0 on # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 370.1 on # COM1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 370.2 on # COM2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 370.3 on # Parallel port + io 0x60 = 0x378 + irq 0x70 = 7 + end + device pnp 370.5 on # PS/2 keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + end + device pnp 370.6 on # PS/2 mouse + irq 0x70 = 12 + end + end + end + device pci 7.1 on end # IDE + device pci 7.2 on end # USB + device pci 7.3 on end # ACPI + register "ide0_enable" = "1" + register "ide1_enable" = "1" + register "ide_legacy_enable" = "1" + # Enable UDMA/33 for higher speed if your IDE device(s) support it. + register "ide0_drive0_udma33_enable" = "0" + register "ide0_drive1_udma33_enable" = "0" + register "ide1_drive0_udma33_enable" = "0" + register "ide1_drive1_udma33_enable" = "0" + end + end +end Added: trunk/coreboot-v2/src/mainboard/soyo/sy-6ba-plus-iii/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/soyo/sy-6ba-plus-iii/Options.lb (rev 0) +++ trunk/coreboot-v2/src/mainboard/soyo/sy-6ba-plus-iii/Options.lb 2009-06-24 00:35:07 UTC (rev 4369) @@ -0,0 +1,100 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2009 Uwe Hermann <uwe(a)hermann-uwe.de> +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +uses HAVE_MP_TABLE +uses CONFIG_CBFS +uses HAVE_PIRQ_TABLE +uses USE_FALLBACK_IMAGE +uses HAVE_FALLBACK_BOOT +uses HAVE_HARD_RESET +uses HAVE_OPTION_TABLE +uses USE_OPTION_TABLE +uses CONFIG_ROM_PAYLOAD +uses IRQ_SLOT_COUNT +uses MAINBOARD +uses MAINBOARD_VENDOR +uses MAINBOARD_PART_NUMBER +uses COREBOOT_EXTRA_VERSION +uses ARCH +uses FALLBACK_SIZE +uses STACK_SIZE +uses HEAP_SIZE +uses ROM_SIZE +uses ROM_SECTION_SIZE +uses ROM_IMAGE_SIZE +uses ROM_SECTION_SIZE +uses ROM_SECTION_OFFSET +uses CONFIG_ROM_PAYLOAD_START +uses CONFIG_COMPRESSED_PAYLOAD_LZMA +uses PAYLOAD_SIZE +uses _ROMBASE +uses _RAMBASE +uses XIP_ROM_SIZE +uses XIP_ROM_BASE +uses HAVE_MP_TABLE +uses CROSS_COMPILE +uses CC +uses HOSTCC +uses OBJCOPY +uses DEFAULT_CONSOLE_LOGLEVEL +uses MAXIMUM_CONSOLE_LOGLEVEL +uses CONFIG_CONSOLE_SERIAL8250 +uses TTYS0_BAUD +uses TTYS0_BASE +uses TTYS0_LCS +uses CONFIG_UDELAY_TSC +uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 +uses MAINBOARD_VENDOR +uses MAINBOARD_PART_NUMBER +uses CONFIG_CONSOLE_VGA +uses CONFIG_PCI_ROM_RUN + +default ROM_SIZE = 256 * 1024 +default HAVE_FALLBACK_BOOT = 1 +default HAVE_MP_TABLE = 0 +default HAVE_HARD_RESET = 0 +default CONFIG_UDELAY_TSC = 1 +default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1 +default HAVE_PIRQ_TABLE = 1 +default IRQ_SLOT_COUNT = 0 # Override this in targets/*/Config.lb. +default MAINBOARD_VENDOR = "N/A" # Override this in targets/*/Config.lb. +default MAINBOARD_PART_NUMBER = "N/A" # Override this in targets/*/Config.lb. +default ROM_IMAGE_SIZE = 64 * 1024 +default FALLBACK_SIZE = 128 * 1024 +default STACK_SIZE = 8 * 1024 +default HEAP_SIZE = 16 * 1024 +default HAVE_OPTION_TABLE = 0 +#default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE +default USE_OPTION_TABLE = 0 +default _RAMBASE = 0x00004000 +default CONFIG_ROM_PAYLOAD = 1 +default CROSS_COMPILE = "" +default CC = "$(CROSS_COMPILE)gcc -m32" +default HOSTCC = "gcc" +default CONFIG_CONSOLE_SERIAL8250 = 1 +default TTYS0_BAUD = 115200 +default TTYS0_BASE = 0x3f8 +default TTYS0_LCS = 0x3 # 8n1 +default DEFAULT_CONSOLE_LOGLEVEL = 9 +default MAXIMUM_CONSOLE_LOGLEVEL = 9 +default CONFIG_CONSOLE_VGA = 1 +default CONFIG_PCI_ROM_RUN = 1 +default CONFIG_CBFS = 0 +end Added: trunk/coreboot-v2/src/mainboard/soyo/sy-6ba-plus-iii/auto.c =================================================================== --- trunk/coreboot-v2/src/mainboard/soyo/sy-6ba-plus-iii/auto.c (rev 0) +++ trunk/coreboot-v2/src/mainboard/soyo/sy-6ba-plus-iii/auto.c 2009-06-24 00:35:07 UTC (rev 4369) @@ -0,0 +1,67 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2009 Uwe Hermann <uwe(a)hermann-uwe.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#define ASSEMBLY 1 + +#include <stdint.h> +#include <device/pci_def.h> +#include <arch/io.h> +#include <device/pnp_def.h> +#include <arch/romcc_io.h> +#include <arch/hlt.h> +#include <stdlib.h> +#include "pc80/serial.c" +#include "arch/i386/lib/console.c" +#include "ram/ramtest.c" +#include "southbridge/intel/i82371eb/i82371eb_early_smbus.c" +#include "northbridge/intel/i440bx/raminit.h" +#include "lib/debug.c" +#include "pc80/udelay_io.c" +#include "lib/delay.c" +#include "cpu/x86/mtrr/earlymtrr.c" +#include "cpu/x86/bist.h" +#include "superio/ite/it8671f/it8671f_early_serial.c" + +#define SERIAL_DEV PNP_DEV(0x370, IT8671F_SP1) + +static inline int spd_read_byte(unsigned int device, unsigned int address) +{ + return smbus_read_byte(device, address); +} + +#include "northbridge/intel/i440bx/raminit.c" +#include "northbridge/intel/i440bx/debug.c" + +static void main(unsigned long bist) +{ + if (bist == 0) + early_mtrr_init(); + + it8671f_enable_serial(SERIAL_DEV, TTYS0_BASE); + uart_init(); + console_init(); + report_bist_failure(bist); + enable_smbus(); + /* dump_spd_registers(); */ + sdram_set_registers(); + sdram_set_spd_registers(); + sdram_enable(); + /* ram_check(0, 640 * 1024); */ +} Added: trunk/coreboot-v2/src/mainboard/soyo/sy-6ba-plus-iii/chip.h =================================================================== --- trunk/coreboot-v2/src/mainboard/soyo/sy-6ba-plus-iii/chip.h (rev 0) +++ trunk/coreboot-v2/src/mainboard/soyo/sy-6ba-plus-iii/chip.h 2009-06-24 00:35:07 UTC (rev 4369) @@ -0,0 +1,22 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2009 Uwe Hermann <uwe(a)hermann-uwe.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +extern struct chip_operations mainboard_ops; +struct mainboard_config {}; Added: trunk/coreboot-v2/src/mainboard/soyo/sy-6ba-plus-iii/irq_tables.c =================================================================== --- trunk/coreboot-v2/src/mainboard/soyo/sy-6ba-plus-iii/irq_tables.c (rev 0) +++ trunk/coreboot-v2/src/mainboard/soyo/sy-6ba-plus-iii/irq_tables.c 2009-06-24 00:35:07 UTC (rev 4369) @@ -0,0 +1,53 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2009 Uwe Hermann <uwe(a)hermann-uwe.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/pirq_routing.h> + +const struct irq_routing_table intel_irq_routing_table = { + PIRQ_SIGNATURE, /* u32 signature */ + PIRQ_VERSION, /* u16 version */ + 32 + 16 * IRQ_SLOT_COUNT,/* Max. number of devices on the bus */ + 0x00, /* Interrupt router bus */ + (0x07 << 3) | 0x0, /* Interrupt router dev */ + 0xc00, /* IRQs devoted exclusively to PCI usage */ + 0x8086, /* Vendor */ + 0x7000, /* Device */ + 0, /* Miniport */ + { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */ + 0x9c, /* Checksum (has to be set to some value that + * would give 0 after the sum of all bytes + * for this structure (including checksum). + */ + { + /* bus, dev | fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ + {0x00, (0x0f << 3) | 0x0, {{0x60, 0xdeb8}, {0x61, 0xdeb8}, {0x62, 0xdeb8}, {0x63, 0xdeb8}}, 0x1, 0x0}, + {0x00, (0x10 << 3) | 0x0, {{0x61, 0xdeb8}, {0x62, 0xdeb8}, {0x63, 0xdeb8}, {0x60, 0xdeb8}}, 0x2, 0x0}, + {0x00, (0x11 << 3) | 0x0, {{0x62, 0xdeb8}, {0x63, 0xdeb8}, {0x60, 0xdeb8}, {0x61, 0xdeb8}}, 0x3, 0x0}, + {0x00, (0x12 << 3) | 0x0, {{0x63, 0xdeb8}, {0x60, 0xdeb8}, {0x61, 0xdeb8}, {0x62, 0xdeb8}}, 0x4, 0x0}, + {0x00, (0x13 << 3) | 0x0, {{0x60, 0xdeb8}, {0x61, 0xdeb8}, {0x62, 0xdeb8}, {0x63, 0xdeb8}}, 0x5, 0x0}, + {0x00, (0x07 << 3) | 0x1, {{0x60, 0xdeb8}, {0x61, 0xdeb8}, {0x62, 0xdeb8}, {0x63, 0xdeb8}}, 0x0, 0x0}, + {0x00, (0x01 << 3) | 0x0, {{0x60, 0xdeb8}, {0x61, 0xdeb8}, {0x62, 0xdeb8}, {0x63, 0xdeb8}}, 0x0, 0x0}, + } +}; + +unsigned long write_pirq_routing_table(unsigned long addr) +{ + return copy_pirq_routing_table(addr); +} Added: trunk/coreboot-v2/src/mainboard/soyo/sy-6ba-plus-iii/mainboard.c =================================================================== --- trunk/coreboot-v2/src/mainboard/soyo/sy-6ba-plus-iii/mainboard.c (rev 0) +++ trunk/coreboot-v2/src/mainboard/soyo/sy-6ba-plus-iii/mainboard.c 2009-06-24 00:35:07 UTC (rev 4369) @@ -0,0 +1,26 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2009 Uwe Hermann <uwe(a)hermann-uwe.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <device/device.h> +#include "chip.h" + +struct chip_operations mainboard_ops = { + CHIP_NAME("Soyo SY-6BA+ III Mainboard") +}; Added: trunk/coreboot-v2/targets/soyo/sy-6ba-plus-iii/Config.lb =================================================================== --- trunk/coreboot-v2/targets/soyo/sy-6ba-plus-iii/Config.lb (rev 0) +++ trunk/coreboot-v2/targets/soyo/sy-6ba-plus-iii/Config.lb 2009-06-24 00:35:07 UTC (rev 4369) @@ -0,0 +1,51 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2009 Uwe Hermann <uwe(a)hermann-uwe.de> +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +target sy-6ba-plus-iii +mainboard soyo/sy-6ba-plus-iii + +option ROM_SIZE = 256 * 1024 +# option FALLBACK_SIZE = ROM_SIZE + +option MAINBOARD_VENDOR = "Soyo" +option MAINBOARD_PART_NUMBER = "SY-6BA+ III" + +option IRQ_SLOT_COUNT = 7 + +option DEFAULT_CONSOLE_LOGLEVEL = 9 +option MAXIMUM_CONSOLE_LOGLEVEL = 9 + +option CONFIG_CONSOLE_VGA = 1 +option CONFIG_PCI_ROM_RUN = 1 + +romimage "normal" + option USE_FALLBACK_IMAGE = 0 + option COREBOOT_EXTRA_VERSION = ".0Normal" + payload ../payload.elf +end + +romimage "fallback" + option USE_FALLBACK_IMAGE = 1 + option COREBOOT_EXTRA_VERSION = ".0Fallback" + payload ../payload.elf +end + +# buildrom ./coreboot.rom ROM_SIZE "fallback" +buildrom ./coreboot.rom ROM_SIZE "normal" "fallback"

1 0

[flashrom] r627 - trunk
by svn＠coreboot.org 23 Jun '09

23 Jun '09

Author: uwe Date: 2009-06-23 22:27:33 +0200 (Tue, 23 Jun 2009) New Revision: 627 Modified: trunk/board_enable.c trunk/print.c Log: Mark the following boards as working OK: - ASUS P5KC (reported by Andrei Pavlov <pavlov.andrei(a)rambler.ru>) - GIGABYTE GA-EP35-DS3L (reported by Alexander Gordeev <lasaine(a)lvk.cs.msu.su>) Add a few more URLs. Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Modified: trunk/board_enable.c =================================================================== --- trunk/board_enable.c 2009-06-23 11:48:37 UTC (rev 626) +++ trunk/board_enable.c 2009-06-23 20:27:33 UTC (rev 627) @@ -901,6 +901,7 @@ { "ASUS", "P2B-F", }, { "ASUS", "P2L97-S", }, { "ASUS", "P5B-Deluxe", }, + { "ASUS", "P5KC", }, { "ASUS", "P6T Deluxe V2", }, { "A-Trend", "ATC-6220", }, { "BCOM", "WinNET100", }, @@ -908,6 +909,7 @@ { "GIGABYTE", "GA-6BXDU", }, { "GIGABYTE", "GA-6ZMA", }, { "GIGABYTE", "GA-7ZM", }, + { "GIGABYTE", "GA-EP35-DS3L", }, { "Intel", "EP80759", }, { "Jetway", "J7F4K1G5D-PB", }, { "MSI", "MS-6570 (K7N2)", }, Modified: trunk/print.c =================================================================== --- trunk/print.c 2009-06-23 11:48:37 UTC (rev 626) +++ trunk/print.c 2009-06-23 20:27:33 UTC (rev 627) @@ -300,7 +300,7 @@ { "Abit", "AX8", "http://www.abit.com.tw/page/en/motherboard/motherboard_detail.php?DEFTITLE=…" }, { "Advantech", "PCM-5820", "http://taiwan.advantech.com.tw/products/Model_Detail.asp?model_id=1-1TGZL8&…" }, { "ASI", "MB-5BLMP", "http://www.hojerteknik.com/winnet.htm" }, - { "ASRock", "A770CrossFire", NULL }, + { "ASRock", "A770CrossFire", "http://www.asrock.com/mb/overview.asp?Model=A770CrossFire&s=AM2\%2b" }, { "ASUS", "A7N8X Deluxe", "http://www.asus.com/Product.aspx?P_ID=wAsRYm41KTp78MFC" }, { "ASUS", "A7N8X-E Deluxe", "http://www.asus.com/products.aspx?l1=3&l2=13&l3=56&l4=0&model=217&modelmenu…" }, { "ASUS", "A7V400-MX", "http://www.asus.com.tw/products.aspx?l1=3&l2=13&l3=63&l4=0&model=228&modelm…" }, @@ -321,12 +321,14 @@ { "ASUS", "P2B-F", "http://www.motherboard.cz/mb/asus/P2B-F.htm" }, { "ASUS", "P2L97-S", "http://www.motherboard.cz/mb/asus/P2L97-S.htm" }, { "ASUS", "P5B-Deluxe", "ftp://ftp.asus.com.tw/pub/ASUS/mb/socket775/P5B-Deluxe/" }, + { "ASUS", "P5KC", "http://www.asus.com/product.aspx?P_ID=fFZ8oUIGmLpwNMjj" }, { "ASUS", "P6T Deluxe V2", "http://www.asus.com/product.aspx?P_ID=iRlP8RG9han6saZx" }, { "A-Trend", "ATC-6220", "http://www.motherboard.cz/mb/atrend/atc6220.htm" }, { "BCOM", "WinNET100", "http://www.coreboot.org/BCOM_WINNET100_Build_Tutorial" }, { "GIGABYTE", "GA-6BXC", "http://www.gigabyte.com.tw/Products/Motherboard/Products_Spec.aspx?ClassVal…" }, { "GIGABYTE", "GA-6BXDU", "http://www.gigabyte.com.tw/Products/Motherboard/Products_Spec.aspx?ProductI…" }, { "GIGABYTE", "GA-6ZMA", "http://www.gigabyte.de/Support/Motherboard/BIOS_Model.aspx?ProductID=3289" }, + { "GIGABYTE", "GA-EP35-DS3L", "http://www.gigabyte.com.tw/Products/Motherboard/Products_Overview.aspx?Prod…" }, { "Intel", "EP80759", NULL }, { "Jetway", "J7F4K1G5D-PB", "http://www.jetway.com.tw/jetway/system/productshow2.asp?id=389&proname=J7F4…" }, { "MSI", "MS-6570 (K7N2)", NULL }, @@ -376,33 +378,37 @@ { "Acorp", "6A815EPD", NULL }, { "agami", "Aruma", NULL }, { "Albatron", "PM266A", NULL }, - { "Artec Group", "DBE61", NULL }, - { "Artec Group", "DBE62", NULL }, + { "Artec Group", "DBE61", "http://wiki.thincan.org/DBE61" }, + { "Artec Group", "DBE62", "http://wiki.thincan.org/DBE62" }, { "ASUS", "A7V8-MX SE", NULL }, { "ASUS", "P4B266", "http://www.ciao.co.uk/ASUS_Intel_845D_Chipset_P4B266__5409807#productdetail" }, { "ASUS", "P5A", NULL }, { "BioStar", "P4M80-M4", NULL }, + { "Elitegroup", "K7VTA3", "http://www.ecs.com.tw/ECSWebSite/Products/ProductsDetail.aspx?detailid=264&…" }, { "EPoX", "EP-8K5A2", NULL }, { "EPoX", "EP-BX3", NULL }, { "GIGABYTE", "GA-2761GXDK", NULL }, { "GIGABYTE", "GA-7VT600", NULL }, - { "GIGABYTE", "GA-K8N-SLI", NULL }, - { "GIGABYTE", "GA-M57SLI-S4", NULL }, - { "GIGABYTE", "GA-M61P-S3", NULL }, + { "GIGABYTE", "GA-7ZM", "http://www.gigabyte.com.tw/Products/Motherboard/Products_Spec.aspx?ProductI…" }, + { "GIGABYTE", "GA-K8N-SLI", "http://www.gigabyte.com.tw/Products/Motherboard/Products_Spec.aspx?ProductI…" }, + { "GIGABYTE", "GA-M57SLI-S4", "http://www.gigabyte.com.tw/Products/Motherboard/Products_Overview.aspx?Prod…" }, + { "GIGABYTE", "GA-M61P-S3", "http://www.gigabyte.com.tw/Products/Motherboard/Products_Spec.aspx?ProductI…" }, { "GIGABYTE", "GA-MA78G-DS3H", NULL }, { "GIGABYTE", "GA-MA78GM-S2H", NULL }, - { "GIGABYTE", "GA-MA790FX-DQ6", NULL }, + { "GIGABYTE", "GA-MA790FX-DQ6", "http://www.gigabyte.com.tw/Products/Motherboard/Products_Spec.aspx?ProductI…" }, { "HP", "DL145 G3", NULL }, { "IBM", "x3455", NULL }, { "Intel", "D201GLY", NULL }, { "IWILL", "DK8-HTX", NULL }, - { "Kontron", "986LCD-M", NULL }, - { "MSI", "MS-7135 (K8N Neo3)", NULL }, + { "Kontron", "986LCD-M", "http://de.kontron.com/products/boards+and+mezzanines/embedded+motherboards/…" }, + { "Mitac", "6513WU", NULL }, + { "MSI", "MS-6590 (KT4 Ultra)", NULL }, { "MSI", "MS-6702E (K8T Neo2-F)",NULL }, { "MSI", "MS-6712 (KT4V)", NULL }, - { "MSI", "MS-6590 (KT4 Ultra)", NULL }, { "MSI", "MS-7046", NULL }, - { "Soyo", "SY-7VCA", NULL }, + { "MSI", "MS-7135 (K8N Neo3)", NULL }, + { "Shuttle", "AK38N", "http://eu.shuttle.com/en/desktopdefault.aspx/tabid-36/558_read-9889/" }, + { "Soyo", "SY-7VCA", "http://www.tomshardware.com/reviews/12-socket-370-motherboards,196-15.html" }, { "Tyan", "S2498 (Tomcat K7M)", "http://www.tyan.com/archive/products/html/tomcatk7m.html" }, { "VIA", "EPIA-CN", "http://www.via.com.tw/en/products/mainboards/motherboards.jsp?motherboard_i…" }, { "VIA", "EPIA M/MII/...", NULL }, @@ -411,7 +417,7 @@ /* Verified non-working boards (for now). */ { "Abit", "IS-10", "http://www.abit.com.tw/page/en/motherboard/motherboard_detail.php?pMODEL_NA…" }, - { "ASUS", "M3N78 Pro", NULL }, + { "ASUS", "M3N78 Pro", "http://www.asus.com/product.aspx?P_ID=DVvm9CU0G1bCC4gp" }, { "ASUS", "MEW-AM", "ftp://ftp.asus.com.tw/pub/ASUS/mb/sock370/810/mew-am/" }, { "ASUS", "MEW-VM", "http://www.elhvb.com/mboards/OEM/HP/manual/ASUS%20MEW-VM.htm" }, { "ASUS", "P3B-F", "ftp://ftp.asus.com.tw/pub/ASUS/mb/slot1/440bx/p3b-f/" }, @@ -420,9 +426,7 @@ { "Biostar", "M6TBA", "ftp://ftp.biostar-usa.com/manuals/M6TBA/" }, { "Boser", "HS-6637", "http://www.boser.com.tw/manual/HS-62376637v3.4.pdf" }, { "DFI", "855GME-MGF", NULL }, - { "Elitegroup", "K7VTA3", NULL }, { "FIC", "VA-502", "ftp://ftp.fic.com.tw/motherboard/manual/socket7/va-502/" }, - { "GIGABYTE", "GA-7ZM", NULL }, { "MSI", "MS-6178", NULL }, { "MSI", "MS-7260 (K9N Neo)", "http://global.msi.com.tw/index.php?func=proddesc&prod_no=255&maincat_no=1" }, { "PCCHIPS", "M537DMA33", "http://motherboards.mbarron.net/models/pcchips/m537dma.htm" },

1 0

[flashrom] pb flashing St M26P16
by stephan.guilloux＠free.fr 23 Jun '09

23 Jun '09

Hello all, I'm facing some issues, with some flash ST M25P16. When using flashrom (623), after programming, some bits are not programmed correctly. Each time, the same bits are wrong, making the BIOS unusable. In the file attached, the diff between what should be seen and and is really programmed. I'm still checking, but it seems that the same diffs are seen after each programmation of the flash. Note that I'm facing this on 3 boards. The 4th one is working properly. On each non working board, some bits are wrong, but they are not the same, on each board. Any hint ? Any idea ? Regards, Stephan.

3 5

Re: [coreboot] [flashrom] pb flashing St M25P16
by Myles Watson 23 Jun '09

23 Jun '09

> > > > Note that I'm facing this on 3 boards. The 4th one is working > properly. > > > > On each non working board, some bits are wrong, but they are not the > > > same, on > > > > each board. > > My best guess would be a timing issue. Is there a way that you can > lengthen > > the default delays to something safer but not too painful (2x or 3x) and > try > > again? > I can try, yes, but which timing to modify ? > What variable to update ? I don't know. I'm assuming that all 4 boards that you're talking about are the same, or at least have the same chipsets. Given that I would look at the actual flash routines that get used and see if there are timing parameters that you can play with. I'm just not that knowledgeable about flashrom. I was hoping I could point you in the right direction since you weren't getting other responses. Thanks, Myles

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coreboot June 2009