coreboot May 2009

coreboot@coreboot.org

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571 discussions

[flashrom][patch] enable/use flash chip read/erase return codes
by Stephan GUILLOUX 01 Jun '09

01 Jun '09

Hello, A last patch for tonight, to use chips read/erase return codes. erase() is not fully modified, though. flash_read() is unchanged, as I also have a patch pending in this area. Make good use of it ;-) Stephan. Signed-off-by: Stephan Guilloux <stephan.guilloux(a)free.fr> Index: flashrom-read-return-code/trunk/it87spi.c =================================================================== --- flashrom-read-return-code/trunk/it87spi.c (révision 547) +++ flashrom-read-return-code/trunk/it87spi.c (copie de travail) @@ -238,21 +238,22 @@ int it8716f_spi_chip_read(struct flashchip *flash, uint8_t *buf) { int total_size = 1024 * flash->total_size; + int rc = 0; int i; fast_spi = 0; if (total_size > 512 * 1024) { - for (i = 0; i < total_size; i += 3) { + for (i = 0; (i < total_size) && (rc == 0); i += 3) { int toread = 3; if (total_size - i < toread) toread = total_size - i; - spi_nbyte_read(i, buf + i, toread); + rc = spi_nbyte_read(i, buf + i, toread); } } else { memcpy(buf, (const char *)flash->virtual_memory, total_size); } - return 0; + return rc; } int it8716f_spi_chip_write_256(struct flashchip *flash, uint8_t *buf) Index: flashrom-read-return-code/trunk/sb600spi.c =================================================================== --- flashrom-read-return-code/trunk/sb600spi.c (révision 547) +++ flashrom-read-return-code/trunk/sb600spi.c (copie de travail) @@ -45,9 +45,9 @@ int total_size = flash->total_size * 1024; int page_size = 8; - for (i = 0; i < total_size / page_size; i++) - spi_nbyte_read(i * page_size, (void *)(buf + i * page_size), - page_size); + for (i = 0; (i < total_size / page_size) && (rc == 0); i++) + rc = spi_nbyte_read(i * page_size, (void *)(buf + i * page_size), + page_size); return rc; } Index: flashrom-read-return-code/trunk/flashrom.c =================================================================== --- flashrom-read-return-code/trunk/flashrom.c (révision 547) +++ flashrom-read-return-code/trunk/flashrom.c (copie de travail) @@ -208,12 +208,19 @@ int idx; int total_size = flash->total_size * 1024; uint8_t *buf2 = (uint8_t *) calloc(total_size, sizeof(char)); + + printf ("Reading flash... "); if (!flash->read) { printf("FAILED!\n"); fprintf(stderr, "ERROR: flashrom has no read function for this flash chip.\n"); return 1; - } else - flash->read(flash, buf2); + } + if (flash->read(flash, buf2)) { + printf("FAILED!\n"); + fprintf(stderr, "ERROR : flashrom cannot read this flash chip.\n"); + return 1; + } + printf ("passed\n"); printf("Verifying flash... "); @@ -286,15 +293,28 @@ fprintf(stderr, "ERROR: flashrom has no erase function for this flash chip.\n"); return 1; } - flash->erase(flash); + if (flash->erase(flash)) { + printf("FAILED!\n"); + fprintf(stderr, "ERROR: flashrom cannot erase this flash chip.\n"); + return 1; + } + printf ("passed.\n"); if (!flash->read) { printf("FAILED!\n"); fprintf(stderr, "ERROR: flashrom has no read function for this flash chip.\n"); return 1; - } else - flash->read(flash, buf); + } + printf ("Reading flash... "); + if (flash->read(flash, buf)) { + printf("FAILED!\n"); + fprintf(stderr, "ERROR: flashrom cannot read this flash chip.\n"); + return 1; + } + printf ("passed.\n"); + + printf ("Checking... "); for (erasedbytes = 0; erasedbytes < size; erasedbytes++) if (0xff != buf[erasedbytes]) { printf("FAILED!\n"); @@ -618,8 +638,12 @@ printf("FAILED!\n"); fprintf(stderr, "ERROR: flashrom has no read function for this flash chip.\n"); return 1; - } else - flashes[0]->read(flashes[0], buf); + } + if (flashes[0]->read(flashes[0], buf)) { + printf("FAILED!\n"); + fprintf(stderr, "ERROR : flashrom cannot read this flash chip.\n"); + return 1; + } if (exclude_end_position - exclude_start_position > 0) memset(buf + exclude_start_position, 0,

2 1

[flashrom] Patch to factorize read_flash() use
by Stephan GUILLOUX 01 Jun '09

01 Jun '09

Hello, A simple patch to use read_flash() when flash chip probe is probed. Unfortunatelly, I cannot test it... If anyone can do the job for me... Make good use of it ;-) Stephan. Signed-off-by: Stephan Guilloux <stephan.guilloux(a)free.fr> Index: flashrom-factorize-read/trunk/flashrom.c =================================================================== --- flashrom-factorize-read/trunk/flashrom.c (révision 546) +++ flashrom-factorize-read/trunk/flashrom.c (copie de travail) @@ -251,6 +251,12 @@ FILE *image; unsigned long size = flash->total_size * 1024; unsigned char *buf = calloc(size, sizeof(char)); + + if (! filename) { + printf("Error: No filename specified.\n"); + return 1; + } + if ((image = fopen(filename, "w")) == NULL) { perror(filename); exit(1); @@ -602,35 +608,10 @@ printf("Run flashrom -L to view the hardware supported in this flashrom version.\n"); exit(1); } - if (!filename) { - printf("Error: No filename specified.\n"); - exit(1); - } - size = flashes[0]->total_size * 1024; - buf = (uint8_t *) calloc(size, sizeof(char)); - - if ((image = fopen(filename, "w")) == NULL) { - perror(filename); - exit(1); - } - printf("Force reading flash... "); - if (!flashes[0]->read) { - printf("FAILED!\n"); - fprintf(stderr, "ERROR: flashrom has no read function for this flash chip.\n"); + if (read_flash(flashes[0], filename, exclude_start_position, exclude_end_position)) { return 1; - } else - flashes[0]->read(flashes[0], buf); - - if (exclude_end_position - exclude_start_position > 0) - memset(buf + exclude_start_position, 0, - exclude_end_position - - exclude_start_position); - - numbytes = fwrite(buf, 1, size, image); - fclose(image); - printf("%s.\n", numbytes == size ? "done" : "FAILED"); - free(buf); - return numbytes != size; + } + return 0; } // FIXME: flash writes stay enabled! exit(1);

2 1

[flashrom] Missing free() in read_flash (just for the form)
by Stephan GUILLOUX 01 Jun '09

01 Jun '09

Hello, Just a missing free() in read_flash(). Make good use of it ;-) Stephan. Signed-off-by: Stephan Guilloux <stephan.guilloux(a)free.fr> Index: flashrom-free/trunk/flashrom.c =================================================================== --- flashrom-free/trunk/flashrom.c (révision 547) +++ flashrom-free/trunk/flashrom.c (copie de travail) @@ -269,6 +269,7 @@ numbytes = fwrite(buf, 1, size, image); fclose(image); + free(buf); printf("%s.\n", numbytes == size ? "done" : "FAILED"); if (numbytes != size) return 1;

2 1

[PATCH] flashrom: Refactor HT-1000 GPIO setting
by Carl-Daniel Hailfinger 01 Jun '09

01 Jun '09

Refactor HT-1000 GPIO setting to use sio_mask. Although the HT-1000 GPIOs are not SuperIO related, the share the same index/data register access method. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: flashrom-ht1000_gpio_refactor/board_enable.c =================================================================== --- flashrom-ht1000_gpio_refactor/board_enable.c (Revision 547) +++ flashrom-ht1000_gpio_refactor/board_enable.c (Arbeitskopie) @@ -365,25 +365,20 @@ static int board_ibm_x3455(const char *name) { - uint8_t byte; - /* Set GPIO lines in the Broadcom HT-1000 southbridge. */ - OUTB(0x45, 0xcd6); - byte = INB(0xcd7); - OUTB(byte | 0x20, 0xcd7); + /* It's not a superio but it uses the same index/data port method. */ + sio_mask(0xcd6, 0x45, 0x20, 0x20); return 0; } static int board_hp_dl145_g3_enable(const char *name) { - uint8_t byte; - /* Set GPIO lines in the Broadcom HT-1000 southbridge. */ - OUTB(0x44, 0xcd6); /* GPIO 0 reg from PM regs */ - byte = INB(0xcd7); + /* GPIO 0 reg from PM regs */ /* Set GPIO 2 and 5 high, connected to flash WP# and TBL# pins. */ - OUTB(byte | 0x24, 0xcd7); + /* It's not a superio but it uses the same index/data port method. */ + sio_mask(0xcd6, 0x44, 0x24, 0x24); return 0; } -- http://www.hailfinger.org/ Index: flashrom-ht1000_gpio_refactor/board_enable.c =================================================================== --- flashrom-ht1000_gpio_refactor/board_enable.c (Revision 547) +++ flashrom-ht1000_gpio_refactor/board_enable.c (Arbeitskopie) @@ -365,25 +365,20 @@ static int board_ibm_x3455(const char *name) { - uint8_t byte; - /* Set GPIO lines in the Broadcom HT-1000 southbridge. */ - OUTB(0x45, 0xcd6); - byte = INB(0xcd7); - OUTB(byte | 0x20, 0xcd7); + /* It's not a superio but it uses the same index/data port method. */ + sio_mask(0xcd6, 0x45, 0x20, 0x20); return 0; } static int board_hp_dl145_g3_enable(const char *name) { - uint8_t byte; - /* Set GPIO lines in the Broadcom HT-1000 southbridge. */ - OUTB(0x44, 0xcd6); /* GPIO 0 reg from PM regs */ - byte = INB(0xcd7); + /* GPIO 0 reg from PM regs */ /* Set GPIO 2 and 5 high, connected to flash WP# and TBL# pins. */ - OUTB(byte | 0x24, 0xcd7); + /* It's not a superio but it uses the same index/data port method. */ + sio_mask(0xcd6, 0x44, 0x24, 0x24); return 0; }

3 3

Builing Coreboot
by audiossis＠netspace.net.au 01 Jun '09

01 Jun '09

Hi, I'm new to the Coreboot project. I am an experienced electronics technician, so desoldering and burning flash chips is second nature to me, but I'm not a programmer so please forgive me if this seems like a silly question. I've been poking around the Coreboot home pages for the last few days. I've downloaded all the required packages to my Gentoo box and had a good look at what is there. I've read through some of the various documents on the web site about how to build Coreboot and I think I now have a basic understanding of how it all works. My target system is a Clevo laptop with an Intel 82855PM/GM northbridge and an 82801DB(ICH-4m) south bridge. Both of these chips are listed on the supported chipsets page (albeit I understand that the 82855PM/GM is still a work in progress). My question is, do I have to set any build flags or edit any configuration files before building Coreboot, to support these chips? Or does Coreboot support every device on the supported chipsets page "out of the box" so to speak? I know that I have to edit a configuration file to specify the payload I wish to use, but I cannot find anything that tells me wether or not I have to configure Coreboot for the specific chipset on the target mainboard. Thanks for your time and keep up the good work. It's a very interesting project and I'm keen to help out even if only by testing on different platforms. Regards, Ben ------------------------------------------------------------ This email was sent from Netspace Webmail: http://www.netspace.net.au

4 3

[PATCH] use coreboot.rom for CBFS images, but default to smaller size
by Patrick Georgi 01 Jun '09

01 Jun '09

Hi, attached patch changes the bootblock generation for CBFS images. It uses coreboot.rom (padded and all), but defaults to smaller fallback/normal image sizes. It requires changes to each CBFS aware mainboard config (and requires adaption on conversion), but it fixes using normal image (as the offsets are calculated correctly). I tried to get rid of ROM_IMAGE_SIZE and friends, but that'll have to wait until non-CBFS images are gone - maintaining two separate build configurations in a single build system isn't fun. If this gets accepted, I'll propose a patch for the (few) CBFS boards, and commit them together. Signed-off-by: Patrick Georgi <patrick.georgi(a)coresystems.de> Patrick

3 8

[PATCH] flashrom: Only probe for chips with compatible bus protocols
by Carl-Daniel Hailfinger 31 May '09

31 May '09

Only probe for chips with compatible bus protocols. It doesn't make sense to probe for SPI chips on a LPC host, nor does it make sense to probe for LPC chips on a Parallel host. This change is backwards compatible, but adding host protocol info to chipset init functions will speed up probing. Once all chipset init functions are updated and the Winbond W29EE011 and AMIC A49LF040A chip definitions are updated, the W29EE011 workaround can be deleted as the W29/A49 conflict magically disappears. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: flashrom-chiptype_avoid_bus_mismatch/it87spi.c =================================================================== --- flashrom-chiptype_avoid_bus_mismatch/it87spi.c (Revision 557) +++ flashrom-chiptype_avoid_bus_mismatch/it87spi.c (Arbeitskopie) @@ -109,14 +109,23 @@ int it87spi_init(void) { + int ret; + get_io_perms(); - - return it87spi_common_init(); + ret = it87spi_common_init(); + if (!ret) + buses_supported = CHIP_BUSTYPE_SPI; + return ret; } int it87xx_probe_spi_flash(const char *name) { - return it87spi_common_init(); + int ret; + + ret = it87spi_common_init(); + if (!ret) + buses_supported |= CHIP_BUSTYPE_SPI; + return ret; } /* Index: flashrom-chiptype_avoid_bus_mismatch/nic3com.c =================================================================== --- flashrom-chiptype_avoid_bus_mismatch/nic3com.c (Revision 557) +++ flashrom-chiptype_avoid_bus_mismatch/nic3com.c (Arbeitskopie) @@ -81,6 +81,8 @@ */ OUTW(SELECT_REG_WINDOW + 0, io_base_addr + INT_STATUS); + buses_supported = CHIP_BUSTYPE_PARALLEL; + return 0; } Index: flashrom-chiptype_avoid_bus_mismatch/satasii.c =================================================================== --- flashrom-chiptype_avoid_bus_mismatch/satasii.c (Revision 557) +++ flashrom-chiptype_avoid_bus_mismatch/satasii.c (Arbeitskopie) @@ -67,6 +67,9 @@ if ((id != 0x0680) && (!(mmio_readl(sii_bar)) & (1 << 26))) printf("Warning: Flash seems unconnected.\n"); + /* Not sure if it only speaks Parallel. */ + buses_supported = CHIP_BUSTYPE_PARALLEL; + return 0; } Index: flashrom-chiptype_avoid_bus_mismatch/wbsio_spi.c =================================================================== --- flashrom-chiptype_avoid_bus_mismatch/wbsio_spi.c (Revision 557) +++ flashrom-chiptype_avoid_bus_mismatch/wbsio_spi.c (Arbeitskopie) @@ -63,6 +63,7 @@ return 1; printf_debug("\nwbsio_spibase = 0x%x\n", wbsio_spibase); + buses_supported |= CHIP_BUSTYPE_SPI; spi_controller = SPI_CONTROLLER_WBSIO; return 0; } Index: flashrom-chiptype_avoid_bus_mismatch/dummyflasher.c =================================================================== --- flashrom-chiptype_avoid_bus_mismatch/dummyflasher.c (Revision 557) +++ flashrom-chiptype_avoid_bus_mismatch/dummyflasher.c (Arbeitskopie) @@ -29,6 +29,8 @@ int dummy_init(void) { printf_debug("%s\n", __func__); + /* This depends on UNKNOWN having all bits set. */ + buses_supported = CHIP_BUSTYPE_UNKNOWN; spi_controller = SPI_CONTROLLER_DUMMY; return 0; } Index: flashrom-chiptype_avoid_bus_mismatch/chipset_enable.c =================================================================== --- flashrom-chiptype_avoid_bus_mismatch/chipset_enable.c (Revision 557) +++ flashrom-chiptype_avoid_bus_mismatch/chipset_enable.c (Arbeitskopie) @@ -36,13 +36,12 @@ unsigned long flashbase = 0; /** - * flashrom defaults to LPC flash devices. If a known SPI controller is found - * and the SPI strappings are set, this will be overwritten by the probing code. - * - * Eventually, this will become an array when multiple flash support works. + * flashrom defaults to Parallel/LPC/FWH flash devices. If a known host + * controller is found, the init routine sets the buses_supported bitfield to + * contain the supported buses for that controller. */ -enum chipbustype buses_supported = CHIP_BUSTYPE_UNKNOWN; +enum chipbustype buses_supported = CHIP_BUSTYPE_NONSPI; extern int ichspi_lock; @@ -217,6 +216,8 @@ printf_debug("0x6c: 0x%04x (CLOCK/DEBUG)\n", mmio_readw(spibar + 0x6c)); + /* Not sure if it speaks all these bus protocols. */ + buses_supported = CHIP_BUSTYPE_LPC | CHIP_BUSTYPE_FWH | CHIP_BUSTYPE_SPI; spi_controller = SPI_CONTROLLER_VIA; ich_init_opcodes(); @@ -262,22 +263,29 @@ */ if (ich_generation == 7 && bbs == ICH_STRAP_LPC) { + /* Not sure if it speaks LPC as well. */ + buses_supported = CHIP_BUSTYPE_LPC | CHIP_BUSTYPE_FWH; /* No further SPI initialization required */ return ret; } switch (ich_generation) { case 7: + buses_supported = CHIP_BUSTYPE_SPI; spi_controller = SPI_CONTROLLER_ICH7; spibar_offset = 0x3020; break; case 8: + /* Not sure if it speaks LPC as well. */ + buses_supported = CHIP_BUSTYPE_LPC | CHIP_BUSTYPE_FWH | CHIP_BUSTYPE_SPI; spi_controller = SPI_CONTROLLER_ICH9; spibar_offset = 0x3020; break; case 9: case 10: default: /* Future version might behave the same */ + /* Not sure if it speaks LPC as well. */ + buses_supported = CHIP_BUSTYPE_LPC | CHIP_BUSTYPE_FWH | CHIP_BUSTYPE_SPI; spi_controller = SPI_CONTROLLER_ICH9; spibar_offset = 0x3800; break; @@ -727,8 +735,11 @@ has_spi = 0; } - if (has_spi) + buses_supported = CHIP_BUSTYPE_LPC | CHIP_BUSTYPE_FWH; + if (has_spi) { + buses_supported |= CHIP_BUSTYPE_SPI; spi_controller = SPI_CONTROLLER_SB600; + } /* Read ROM strap override register. */ OUTB(0x8f, 0xcd6); Index: flashrom-chiptype_avoid_bus_mismatch/flashrom.c =================================================================== --- flashrom-chiptype_avoid_bus_mismatch/flashrom.c (Revision 557) +++ flashrom-chiptype_avoid_bus_mismatch/flashrom.c (Arbeitskopie) @@ -188,6 +188,10 @@ printf_debug("failed! flashrom has no probe function for this flash chip.\n"); continue; } + if (!(buses_supported & flash->bustype)) { + printf_debug("skipped. Host and chip bus type are incompatible.\n"); + continue; + } size = flash->total_size * 1024; -- http://www.hailfinger.org/ Index: flashrom-chiptype_avoid_bus_mismatch/it87spi.c =================================================================== --- flashrom-chiptype_avoid_bus_mismatch/it87spi.c (Revision 557) +++ flashrom-chiptype_avoid_bus_mismatch/it87spi.c (Arbeitskopie) @@ -109,14 +109,23 @@ int it87spi_init(void) { + int ret; + get_io_perms(); - - return it87spi_common_init(); + ret = it87spi_common_init(); + if (!ret) + buses_supported = CHIP_BUSTYPE_SPI; + return ret; } int it87xx_probe_spi_flash(const char *name) { - return it87spi_common_init(); + int ret; + + ret = it87spi_common_init(); + if (!ret) + buses_supported |= CHIP_BUSTYPE_SPI; + return ret; } /* Index: flashrom-chiptype_avoid_bus_mismatch/nic3com.c =================================================================== --- flashrom-chiptype_avoid_bus_mismatch/nic3com.c (Revision 557) +++ flashrom-chiptype_avoid_bus_mismatch/nic3com.c (Arbeitskopie) @@ -81,6 +81,8 @@ */ OUTW(SELECT_REG_WINDOW + 0, io_base_addr + INT_STATUS); + buses_supported = CHIP_BUSTYPE_PARALLEL; + return 0; } Index: flashrom-chiptype_avoid_bus_mismatch/satasii.c =================================================================== --- flashrom-chiptype_avoid_bus_mismatch/satasii.c (Revision 557) +++ flashrom-chiptype_avoid_bus_mismatch/satasii.c (Arbeitskopie) @@ -67,6 +67,9 @@ if ((id != 0x0680) && (!(mmio_readl(sii_bar)) & (1 << 26))) printf("Warning: Flash seems unconnected.\n"); + /* Not sure if it only speaks Parallel. */ + buses_supported = CHIP_BUSTYPE_PARALLEL; + return 0; } Index: flashrom-chiptype_avoid_bus_mismatch/wbsio_spi.c =================================================================== --- flashrom-chiptype_avoid_bus_mismatch/wbsio_spi.c (Revision 557) +++ flashrom-chiptype_avoid_bus_mismatch/wbsio_spi.c (Arbeitskopie) @@ -63,6 +63,7 @@ return 1; printf_debug("\nwbsio_spibase = 0x%x\n", wbsio_spibase); + buses_supported |= CHIP_BUSTYPE_SPI; spi_controller = SPI_CONTROLLER_WBSIO; return 0; } Index: flashrom-chiptype_avoid_bus_mismatch/dummyflasher.c =================================================================== --- flashrom-chiptype_avoid_bus_mismatch/dummyflasher.c (Revision 557) +++ flashrom-chiptype_avoid_bus_mismatch/dummyflasher.c (Arbeitskopie) @@ -29,6 +29,8 @@ int dummy_init(void) { printf_debug("%s\n", __func__); + /* This depends on UNKNOWN having all bits set. */ + buses_supported = CHIP_BUSTYPE_UNKNOWN; spi_controller = SPI_CONTROLLER_DUMMY; return 0; } Index: flashrom-chiptype_avoid_bus_mismatch/chipset_enable.c =================================================================== --- flashrom-chiptype_avoid_bus_mismatch/chipset_enable.c (Revision 557) +++ flashrom-chiptype_avoid_bus_mismatch/chipset_enable.c (Arbeitskopie) @@ -36,13 +36,12 @@ unsigned long flashbase = 0; /** - * flashrom defaults to LPC flash devices. If a known SPI controller is found - * and the SPI strappings are set, this will be overwritten by the probing code. - * - * Eventually, this will become an array when multiple flash support works. + * flashrom defaults to Parallel/LPC/FWH flash devices. If a known host + * controller is found, the init routine sets the buses_supported bitfield to + * contain the supported buses for that controller. */ -enum chipbustype buses_supported = CHIP_BUSTYPE_UNKNOWN; +enum chipbustype buses_supported = CHIP_BUSTYPE_NONSPI; extern int ichspi_lock; @@ -217,6 +216,8 @@ printf_debug("0x6c: 0x%04x (CLOCK/DEBUG)\n", mmio_readw(spibar + 0x6c)); + /* Not sure if it speaks all these bus protocols. */ + buses_supported = CHIP_BUSTYPE_LPC | CHIP_BUSTYPE_FWH | CHIP_BUSTYPE_SPI; spi_controller = SPI_CONTROLLER_VIA; ich_init_opcodes(); @@ -262,22 +263,29 @@ */ if (ich_generation == 7 && bbs == ICH_STRAP_LPC) { + /* Not sure if it speaks LPC as well. */ + buses_supported = CHIP_BUSTYPE_LPC | CHIP_BUSTYPE_FWH; /* No further SPI initialization required */ return ret; } switch (ich_generation) { case 7: + buses_supported = CHIP_BUSTYPE_SPI; spi_controller = SPI_CONTROLLER_ICH7; spibar_offset = 0x3020; break; case 8: + /* Not sure if it speaks LPC as well. */ + buses_supported = CHIP_BUSTYPE_LPC | CHIP_BUSTYPE_FWH | CHIP_BUSTYPE_SPI; spi_controller = SPI_CONTROLLER_ICH9; spibar_offset = 0x3020; break; case 9: case 10: default: /* Future version might behave the same */ + /* Not sure if it speaks LPC as well. */ + buses_supported = CHIP_BUSTYPE_LPC | CHIP_BUSTYPE_FWH | CHIP_BUSTYPE_SPI; spi_controller = SPI_CONTROLLER_ICH9; spibar_offset = 0x3800; break; @@ -727,8 +735,11 @@ has_spi = 0; } - if (has_spi) + buses_supported = CHIP_BUSTYPE_LPC | CHIP_BUSTYPE_FWH; + if (has_spi) { + buses_supported |= CHIP_BUSTYPE_SPI; spi_controller = SPI_CONTROLLER_SB600; + } /* Read ROM strap override register. */ OUTB(0x8f, 0xcd6); Index: flashrom-chiptype_avoid_bus_mismatch/flashrom.c =================================================================== --- flashrom-chiptype_avoid_bus_mismatch/flashrom.c (Revision 557) +++ flashrom-chiptype_avoid_bus_mismatch/flashrom.c (Arbeitskopie) @@ -188,6 +188,10 @@ printf_debug("failed! flashrom has no probe function for this flash chip.\n"); continue; } + if (!(buses_supported & flash->bustype)) { + printf_debug("skipped. Host and chip bus type are incompatible.\n"); + continue; + } size = flash->total_size * 1024;

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[flashrom] nic3com: address lines
by Mats Erik Andersson 31 May '09

31 May '09

Hello all, using a signal probe I can verify two facts: 1) 3c905B has address lines A0 -- A16 routed, but not A17. Thus 128 kB is the maximal capacity achievable. 2) 3c905 only routes the adress lines A0 -- A15, and therefore limits itself to only 64 kB. On the other hand, I have not succeeded in getting even read capabilities going in my own code (not your "flashrom"). As a side note, rtl8138C and via-rhine VT6102 are already a priory bounded by 64 kB. Both are easily usable by straight forward coding. In contrast, eepro100 seems to be usable by ctflasher only due to their repeated probing. One time probing, as in my efforts, have yet to prove successful. Best regards Mats Erik Andersson

2 1

[PATCH] flashrom: Add bus type support to -p dummy
by Carl-Daniel Hailfinger 31 May '09

31 May '09

Add bus type support to the dummy external programmer. The syntax is explained in the man page. Example: flashrom -p dummy=lpc,fwh Tested, works perfectly. ;-) As a nice benefit, it allows easy testing of the "probe only compatible flashes" patch. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: flashrom-dummy_bustype/flashrom.8 =================================================================== --- flashrom-dummy_bustype/flashrom.8 (Revision 557) +++ flashrom-dummy_bustype/flashrom.8 (Arbeitskopie) @@ -135,6 +135,18 @@ .sp .BR "* it87spi" " (for flash ROMs behind a IT87xx SuperI/O LPC/SPI translation unit)" .sp +The dummy programmer has an optional parameter specifying the bus types it +should support. For that you have to use the +.B "flashrom -p dummy=type" +syntax where +.B type +can be any comma-separated combination of +.B parallel lpc fwh spi all +in any order. +.sp +Example: +.B "flashrom -p dummy=lpc,fwh" +.sp If you have multiple supported PCI cards which can program flash chips (NICs, SATA/IDE controllers, etc.) in your system, you must use the .B "flashrom -p xxxx=bb:dd.f" Index: flashrom-dummy_bustype/flash.h =================================================================== --- flashrom-dummy_bustype/flash.h (Revision 557) +++ flashrom-dummy_bustype/flash.h (Arbeitskopie) @@ -122,6 +122,7 @@ #define ARRAY_SIZE(a) (sizeof(a) / sizeof((a)[0])) enum chipbustype { + CHIP_BUSTYPE_NONE = 0, CHIP_BUSTYPE_PARALLEL = 1 << 0, CHIP_BUSTYPE_LPC = 1 << 1, CHIP_BUSTYPE_FWH = 1 << 2, @@ -646,6 +647,7 @@ #endif /* dummyflasher.c */ +extern char *dummytype; int dummy_init(void); int dummy_shutdown(void); void *dummy_map(const char *descr, unsigned long phys_addr, size_t len); Index: flashrom-dummy_bustype/dummyflasher.c =================================================================== --- flashrom-dummy_bustype/dummyflasher.c (Revision 557) +++ flashrom-dummy_bustype/dummyflasher.c (Arbeitskopie) @@ -20,16 +20,51 @@ #include <string.h> #include <stdlib.h> +#include <ctype.h> #include <fcntl.h> #include <sys/types.h> #include <sys/stat.h> #include <errno.h> #include "flash.h" +char *dummytype = NULL; + int dummy_init(void) { + int i; printf_debug("%s\n", __func__); - spi_controller = SPI_CONTROLLER_DUMMY; + + /* "all" is equivalent to specifying no type. */ + if (!strcmp(dummytype, "all")) { + free(dummytype); + dummytype = NULL; + } + if (!dummytype) + dummytype = strdup("parallel,lpc,fwh,spi"); + for (i = 0; dummytype[i] != '\0'; i++) + dummytype[i] = (char)tolower(dummytype[i]); + + buses_supported = CHIP_BUSTYPE_NONE; + if (strstr(dummytype, "parallel")) { + buses_supported |= CHIP_BUSTYPE_PARALLEL; + printf_debug("Enabling support for parallel flash.\n"); + } + if (strstr(dummytype, "lpc")) { + buses_supported |= CHIP_BUSTYPE_LPC; + printf_debug("Enabling support for LPC flash.\n"); + } + if (strstr(dummytype, "fwh")) { + buses_supported |= CHIP_BUSTYPE_FWH; + printf_debug("Enabling support for FWH flash.\n"); + } + if (strstr(dummytype, "spi")) { + buses_supported |= CHIP_BUSTYPE_SPI; + spi_controller = SPI_CONTROLLER_DUMMY; + printf_debug("Enabling support for SPI flash.\n"); + } + if (buses_supported == CHIP_BUSTYPE_NONE) + printf_debug("Support for all flash bus types disabled.\n"); + free(dummytype); return 0; } Index: flashrom-dummy_bustype/flashrom.c =================================================================== --- flashrom-dummy_bustype/flashrom.c (Revision 557) +++ flashrom-dummy_bustype/flashrom.c (Arbeitskopie) @@ -537,6 +537,8 @@ programmer = PROGRAMMER_INTERNAL; } else if (strncmp(optarg, "dummy", 5) == 0) { programmer = PROGRAMMER_DUMMY; + if (optarg[5] == '=') + dummytype = strdup(optarg + 6); } else if (strncmp(optarg, "nic3com", 7) == 0) { programmer = PROGRAMMER_NIC3COM; if (optarg[7] == '=') -- http://www.hailfinger.org/ Index: flashrom-dummy_bustype/flashrom.8 =================================================================== --- flashrom-dummy_bustype/flashrom.8 (Revision 557) +++ flashrom-dummy_bustype/flashrom.8 (Arbeitskopie) @@ -135,6 +135,18 @@ .sp .BR "* it87spi" " (for flash ROMs behind a IT87xx SuperI/O LPC/SPI translation unit)" .sp +The dummy programmer has an optional parameter specifying the bus types it +should support. For that you have to use the +.B "flashrom -p dummy=type" +syntax where +.B type +can be any comma-separated combination of +.B parallel lpc fwh spi all +in any order. +.sp +Example: +.B "flashrom -p dummy=lpc,fwh" +.sp If you have multiple supported PCI cards which can program flash chips (NICs, SATA/IDE controllers, etc.) in your system, you must use the .B "flashrom -p xxxx=bb:dd.f" Index: flashrom-dummy_bustype/flash.h =================================================================== --- flashrom-dummy_bustype/flash.h (Revision 557) +++ flashrom-dummy_bustype/flash.h (Arbeitskopie) @@ -122,6 +122,7 @@ #define ARRAY_SIZE(a) (sizeof(a) / sizeof((a)[0])) enum chipbustype { + CHIP_BUSTYPE_NONE = 0, CHIP_BUSTYPE_PARALLEL = 1 << 0, CHIP_BUSTYPE_LPC = 1 << 1, CHIP_BUSTYPE_FWH = 1 << 2, @@ -646,6 +647,7 @@ #endif /* dummyflasher.c */ +extern char *dummytype; int dummy_init(void); int dummy_shutdown(void); void *dummy_map(const char *descr, unsigned long phys_addr, size_t len); Index: flashrom-dummy_bustype/dummyflasher.c =================================================================== --- flashrom-dummy_bustype/dummyflasher.c (Revision 557) +++ flashrom-dummy_bustype/dummyflasher.c (Arbeitskopie) @@ -20,16 +20,51 @@ #include <string.h> #include <stdlib.h> +#include <ctype.h> #include <fcntl.h> #include <sys/types.h> #include <sys/stat.h> #include <errno.h> #include "flash.h" +char *dummytype = NULL; + int dummy_init(void) { + int i; printf_debug("%s\n", __func__); - spi_controller = SPI_CONTROLLER_DUMMY; + + /* "all" is equivalent to specifying no type. */ + if (!strcmp(dummytype, "all")) { + free(dummytype); + dummytype = NULL; + } + if (!dummytype) + dummytype = strdup("parallel,lpc,fwh,spi"); + for (i = 0; dummytype[i] != '\0'; i++) + dummytype[i] = (char)tolower(dummytype[i]); + + buses_supported = CHIP_BUSTYPE_NONE; + if (strstr(dummytype, "parallel")) { + buses_supported |= CHIP_BUSTYPE_PARALLEL; + printf_debug("Enabling support for parallel flash.\n"); + } + if (strstr(dummytype, "lpc")) { + buses_supported |= CHIP_BUSTYPE_LPC; + printf_debug("Enabling support for LPC flash.\n"); + } + if (strstr(dummytype, "fwh")) { + buses_supported |= CHIP_BUSTYPE_FWH; + printf_debug("Enabling support for FWH flash.\n"); + } + if (strstr(dummytype, "spi")) { + buses_supported |= CHIP_BUSTYPE_SPI; + spi_controller = SPI_CONTROLLER_DUMMY; + printf_debug("Enabling support for SPI flash.\n"); + } + if (buses_supported == CHIP_BUSTYPE_NONE) + printf_debug("Support for all flash bus types disabled.\n"); + free(dummytype); return 0; } Index: flashrom-dummy_bustype/flashrom.c =================================================================== --- flashrom-dummy_bustype/flashrom.c (Revision 557) +++ flashrom-dummy_bustype/flashrom.c (Arbeitskopie) @@ -537,6 +537,8 @@ programmer = PROGRAMMER_INTERNAL; } else if (strncmp(optarg, "dummy", 5) == 0) { programmer = PROGRAMMER_DUMMY; + if (optarg[5] == '=') + dummytype = strdup(optarg + 6); } else if (strncmp(optarg, "nic3com", 7) == 0) { programmer = PROGRAMMER_NIC3COM; if (optarg[7] == '=')

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[flashrom] [patch] Warning in satasii.c with GCC 4.4.0
by Urja Rannikko 31 May '09

31 May '09

Hi all, log: Fix warning in satasii.c. This fix is simple as in i think it doesnt change the code logic at all and doesnt add a level of parentheses (ugly), but i can't test as i dont have the necessary hardware. Signed-off-by: Urja Rannikko <urjaman(a)gmail.com> I got this warning (as error) compiling flashrom with gcc 4.4.0: cc -Os -Wall -Werror -c -o satasii.o satasii.c cc1: warnings being treated as errors satasii.c: In function ‘satasii_init’: satasii.c:67: error: suggest parentheses around operand of ‘!’ or change ‘&’ to ‘&&’ or ‘!’ to ‘~’ Patch also inlined: Index: satasii.c =================================================================== --- satasii.c (revision 557) +++ satasii.c (working copy) @@ -64,7 +64,7 @@ sii_bar = physmap("SATA SIL registers", addr, 0x100) + reg_offset; /* Check if ROM cycle are OK. */ - if ((id != 0x0680) && (!(mmio_readl(sii_bar)) & (1 << 26))) + if ((id != 0x0680) && ((!mmio_readl(sii_bar)) & (1 << 26))) printf("Warning: Flash seems unconnected.\n"); return 0; -- urjaman

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coreboot May 2009