coreboot May 2009

coreboot@coreboot.org

92 participants
571 discussions

Problems with the gdb debugger and coreboot
by René Reuter 30 May '09

30 May '09

Hi, I'm trying to set up the gdb debugger with coreboot and qemu. I've followed the instructions on that page: http://www.coreboot.org/Debugging If I put uses CONFIG_GDB_STUB default CONFIG_GDB_STUB=1 into the mainboards config.lb how it's written in the instructions the ./buildtarget will fail. That's why I put it into src/config/Config.lb, then the build is successful but gdb can't find any debugging symbols in the coreboot.ram. The CFLAGS are all set correct. Does anybody know an idea what I'm doing wrong? Regards, René

4 10

[v2] r4326 - in trunk/coreboot-v2/src: arch/ppc/lib config
by svn＠coreboot.org 30 May '09

30 May '09

Author: stepan Date: 2009-05-30 17:12:33 +0200 (Sat, 30 May 2009) New Revision: 4326 Added: trunk/coreboot-v2/src/arch/ppc/lib/abort.c Modified: trunk/coreboot-v2/src/arch/ppc/lib/Config.lb trunk/coreboot-v2/src/config/Config.lb Log: Many Kudos go to Segher Boessenkool and Patrick Georgi for figuring this one out. Fix the libgcc dependency on abort() due to nested functions. Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/coreboot-v2/src/arch/ppc/lib/Config.lb =================================================================== --- trunk/coreboot-v2/src/arch/ppc/lib/Config.lb 2009-05-29 18:41:09 UTC (rev 4325) +++ trunk/coreboot-v2/src/arch/ppc/lib/Config.lb 2009-05-30 15:12:33 UTC (rev 4326) @@ -8,6 +8,7 @@ object timebase.S object floats.S object div64.S +object abort.o initobject pci_dev.o initobject printk_init.o initobject timebase.S @@ -15,3 +16,4 @@ initobject floats.S initobject div64.S initobject ppc.o +initobject abort.o Added: trunk/coreboot-v2/src/arch/ppc/lib/abort.c =================================================================== --- trunk/coreboot-v2/src/arch/ppc/lib/abort.c (rev 0) +++ trunk/coreboot-v2/src/arch/ppc/lib/abort.c 2009-05-30 15:12:33 UTC (rev 4326) @@ -0,0 +1,32 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* gcc produces calls to an abort function in their trampoline code on powerpc + * 32bit platforms. + * This trampoline code is emitted for example in nested functions. + */ + +void abort(void) +{ + /* We would want to call die() here, but it might not be available at + * this point, so for now we have to die silently. + */ + for (;;) ; +} + Modified: trunk/coreboot-v2/src/config/Config.lb =================================================================== --- trunk/coreboot-v2/src/config/Config.lb 2009-05-29 18:41:09 UTC (rev 4325) +++ trunk/coreboot-v2/src/config/Config.lb 2009-05-30 15:12:33 UTC (rev 4326) @@ -47,7 +47,7 @@ makerule coreboot_ram.o depends "src/arch/$(ARCH)/lib/c_start.o $(DRIVER) coreboot.a $(LIBGCC_FILE_NAME)" - action "$(CC) $(DISTRO_LFLAGS) -nostdlib -r -o $@ $^" + action "$(CC) $(DISTRO_LFLAGS) -nostdlib -r -o $@ src/arch/$(ARCH)/lib/c_start.o $(DRIVER) -Wl,-$ coreboot.a $(LIBGCC_FILE_NAME) -Wl,-$" end makerule coreboot_ram

1 0

Asus A8N SLI Deluxe
by Ryan McLean 30 May '09

30 May '09

Attached are the outputs of: lspci -tvnn, - (from ubuntu repository) superiotool -dV, - (from ubuntu repository) flashrom -V, - (from ubuntu repository) getpir output (itq_tables.c), - (from svn) mptable output - (from svn) Calibrating delay loop... 597M loops per second, 100 myus = 199 us. OK. No coreboot table found. Found chipset "NVIDIA CK804", enabling flash write... OK. Probing for AMD Am29F002(N)BB, 256 KB: probe_jedec: id1 0xbf, id2 0x60 Probing for AMD Am29F002(N)BT, 256 KB: probe_jedec: id1 0xbf, id2 0x60 Probing for AMD Am29F016D, 2048 KB: probe_29f040b: id1 0xff, id2 0xff Probing for AMD Am29F040B, 512 KB: probe_29f040b: id1 0x21, id2 0x30 Probing for AMD Am29LV040B, 512 KB: probe_29f040b: id1 0x21, id2 0x30 Probing for ASD AE49F2008, 256 KB: probe_jedec: id1 0xbf, id2 0x60 Probing for Atmel AT25DF021, 256 KB: spi_command called, but no SPI chipset/strapping detected Probing for Atmel AT25DF041A, 512 KB: spi_command called, but no SPI chipset/strapping detected Probing for Atmel AT25DF081, 1024 KB: spi_command called, but no SPI chipset/strapping detected Probing for Atmel AT25DF161, 2048 KB: spi_command called, but no SPI chipset/strapping detected Probing for Atmel AT25DF321, 4096 KB: spi_command called, but no SPI chipset/strapping detected Probing for Atmel AT25DF321A, 4096 KB: spi_command called, but no SPI chipset/strapping detected Probing for Atmel AT25DF641, 8192 KB: spi_command called, but no SPI chipset/strapping detected Probing for Atmel AT25F512B, 64 KB: spi_command called, but no SPI chipset/strapping detected Probing for Atmel AT25FS010, 128 KB: spi_command called, but no SPI chipset/strapping detected Probing for Atmel AT25FS040, 512 KB: spi_command called, but no SPI chipset/strapping detected Probing for Atmel AT26DF041, 512 KB: spi_command called, but no SPI chipset/strapping detected Probing for Atmel AT26DF081A, 1024 KB: spi_command called, but no SPI chipset/strapping detected Probing for Atmel AT26DF161, 2048 KB: spi_command called, but no SPI chipset/strapping detected Probing for Atmel AT26DF161A, 2048 KB: spi_command called, but no SPI chipset/strapping detected Probing for Atmel AT26F004, 512 KB: spi_command called, but no SPI chipset/strapping detected Probing for Atmel AT29C020, 256 KB: probe_jedec: id1 0xbf, id2 0x60 Probing for Atmel AT29C040A, 512 KB: probe_jedec: id1 0xbf, id2 0x60 Probing for Atmel AT45CS1282, 16896 KB: spi_command called, but no SPI chipset/strapping detected Probing for Atmel AT45DB011D, 128 KB: spi_command called, but no SPI chipset/strapping detected Probing for Atmel AT45DB021D, 256 KB: spi_command called, but no SPI chipset/strapping detected Probing for Atmel AT45DB041D, 512 KB: spi_command called, but no SPI chipset/strapping detected Probing for Atmel AT45DB081D, 1024 KB: spi_command called, but no SPI chipset/strapping detected Probing for Atmel AT45DB161D, 2048 KB: spi_command called, but no SPI chipset/strapping detected Probing for Atmel AT45DB321C, 4224 KB: spi_command called, but no SPI chipset/strapping detected Probing for Atmel AT45DB321D, 4096 KB: spi_command called, but no SPI chipset/strapping detected Probing for Atmel AT45DB642D, 8192 KB: spi_command called, but no SPI chipset/strapping detected Probing for Atmel AT49F002(N), 256 KB: probe_jedec: id1 0xbf, id2 0x60 Probing for Atmel AT49F002(N)T, 256 KB: probe_jedec: id1 0xbf, id2 0x60 Probing for AMIC A25L40P, 512 KB: 4b ID not supported on this SPI controller Probing for AMIC A29002B, 256 KB: probe_29f002: id1 0xbf, id2 0x60 Probing for AMIC A29002T, 256 KB: probe_29f002: id1 0xbf, id2 0x60 Probing for AMIC A29040B, 512 KB: probe_29f040b: id1 0x21, id2 0x30 Probing for AMIC A49LF040A, 512 KB: probe_jedec: id1 0xbf, id2 0x60 Probing for EMST F49B002UA, 256 KB: probe_jedec: id1 0xbf, id2 0x60 Probing for EON EN29F002(A)(N)B, 256 KB: probe_jedec: id1 0xbf, id2 0x60 Probing for EON EN29F002(A)(N)T, 256 KB: probe_jedec: id1 0xbf, id2 0x60 Probing for Fujitsu MBM29F004BC, 512 KB: probe_jedec: id1 0xbf, id2 0x60 Probing for Fujitsu MBM29F004TC, 512 KB: probe_jedec: id1 0xbf, id2 0x60 Probing for Fujitsu MBM29F400BC, 512 KB: probe_m29f400bt: id1 0x21, id2 0x2d Probing for Fujitsu MBM29F400TC, 512 KB: probe_m29f400bt: id1 0x21, id2 0x2d Probing for Intel 82802AB, 512 KB: probe_82802ab: id1 0x21, id2 0x30 Probing for Intel 82802AC, 1024 KB: probe_82802ab: id1 0xff, id2 0xff Probing for Macronix MX25L512, 64 KB: spi_command called, but no SPI chipset/strapping detected Probing for Macronix MX25L1005, 128 KB: spi_command called, but no SPI chipset/strapping detected Probing for Macronix MX25L2005, 256 KB: spi_command called, but no SPI chipset/strapping detected Probing for Macronix MX25L4005, 512 KB: spi_command called, but no SPI chipset/strapping detected Probing for Macronix MX25L8005, 1024 KB: spi_command called, but no SPI chipset/strapping detected Probing for Macronix MX25L1605, 2048 KB: spi_command called, but no SPI chipset/strapping detected Probing for Macronix MX25L3205, 4096 KB: spi_command called, but no SPI chipset/strapping detected Probing for Macronix MX25L6405, 8192 KB: spi_command called, but no SPI chipset/strapping detected Probing for Macronix MX29F002B, 256 KB: probe_29f002: id1 0xbf, id2 0x60 Probing for Macronix MX29F002T, 256 KB: probe_29f002: id1 0xbf, id2 0x60 Probing for Macronix MX29LV040C, 512 KB: probe_29f002: id1 0xbf, id2 0x60 Probing for Numonyx M25PE10, 128 KB: spi_command called, but no SPI chipset/strapping detected Probing for Numonyx M25PE20, 256 KB: spi_command called, but no SPI chipset/strapping detected Probing for Numonyx M25PE40, 256 KB: spi_command called, but no SPI chipset/strapping detected Probing for Numonyx M25PE80, 1024 KB: spi_command called, but no SPI chipset/strapping detected Probing for Numonyx M25PE16, 2048 KB: spi_command called, but no SPI chipset/strapping detected Probing for PMC Pm25LV010, 128 KB: spi_command called, but no SPI chipset/strapping detected Probing for PMC Pm25LV016B, 2048 KB: spi_command called, but no SPI chipset/strapping detected Probing for PMC Pm25LV020, 256 KB: spi_command called, but no SPI chipset/strapping detected Probing for PMC Pm25LV040, 512 KB: spi_command called, but no SPI chipset/strapping detected Probing for PMC Pm25LV080B, 1024 KB: spi_command called, but no SPI chipset/strapping detected Probing for PMC Pm25LV512, 64 KB: spi_command called, but no SPI chipset/strapping detected Probing for PMC Pm49FL002, 256 KB: probe_jedec: id1 0xbf, id2 0x60 Probing for PMC Pm49FL004, 512 KB: probe_jedec: id1 0xbf, id2 0x60 Probing for Sharp LHF00L04, 1024 KB: probe_lhf00l04: id1 0xff, id2 0xff Probing for Spansion S25FL016A, 2048 KB: spi_command called, but no SPI chipset/strapping detected Probing for SST SST25VF016B, 2048 KB: spi_command called, but no SPI chipset/strapping detected Probing for SST SST25VF032B, 4096 KB: spi_command called, but no SPI chipset/strapping detected Probing for SST SST25VF040B, 512 KB: spi_command called, but no SPI chipset/strapping detected Probing for SST SST25VF080B, 1024 KB: spi_command called, but no SPI chipset/strapping detected Probing for SST SST28SF040A, 512 KB: probe_28sf040: id1 0x21, id2 0x30 Probing for SST SST29EE010, 128 KB: probe_jedec: id1 0xbf, id2 0x60 Probing for SST SST29LE010, 128 KB: probe_jedec: id1 0xbf, id2 0x60 Probing for SST SST29EE020A, 256 KB: probe_jedec: id1 0xbf, id2 0x60 Probing for SST SST29LE020, 256 KB: probe_jedec: id1 0xbf, id2 0x60 Probing for SST SST39SF010A, 128 KB: probe_jedec: id1 0xbf, id2 0x60 Probing for SST SST39SF020A, 256 KB: probe_jedec: id1 0xbf, id2 0x60 Probing for SST SST39SF040, 512 KB: probe_jedec: id1 0xbf, id2 0x60 Probing for SST SST39VF512, 64 KB: probe_jedec: id1 0xbf, id2 0x60 Probing for SST SST39VF010, 128 KB: probe_jedec: id1 0xbf, id2 0x60 Probing for SST SST39VF020, 256 KB: probe_jedec: id1 0xbf, id2 0x60 Probing for SST SST39VF040, 512 KB: probe_jedec: id1 0xbf, id2 0x60 Probing for SST SST49LF002A/B, 256 KB: probe_jedec: id1 0xbf, id2 0x60 Probing for SST SST49LF003A/B, 384 KB: probe_jedec: id1 0xbf, id2 0x60 Probing for SST SST49LF004A/B, 512 KB: probe_jedec: id1 0xbf, id2 0x60 Found chip "SST SST49LF004A/B" (512 KB) at physical address 0xfff80000. Probing for SST SST49LF004C, 512 KB: probe_49lfxxxc: id1 0x21, id2 0x30 Probing for SST SST49LF008A, 1024 KB: probe_jedec: id1 0xbf, id2 0x60 Probing for SST SST49LF008C, 1024 KB: probe_49lfxxxc: id1 0x21, id2 0x30 Probing for SST SST49LF016C, 2048 KB: probe_49lfxxxc: id1 0x21, id2 0x30 Probing for SST SST49LF020A, 256 KB: probe_jedec: id1 0xbf, id2 0x60 Probing for SST SST49LF040, 512 KB: probe_jedec: id1 0xbf, id2 0x60 Probing for SST SST49LF040B, 512 KB: probe_jedec: id1 0xbf, id2 0x60 Probing for SST SST49LF080A, 1024 KB: probe_jedec: id1 0xbf, id2 0x60 Probing for SST SST49LF160C, 2048 KB: probe_49lfxxxc: id1 0x21, id2 0x30 Probing for ST M25P05-A, 64 KB: spi_command called, but no SPI chipset/strapping detected Probing for ST M25P10-A, 128 KB: spi_command called, but no SPI chipset/strapping detected Probing for ST M25P20, 256 KB: spi_command called, but no SPI chipset/strapping detected Probing for ST M25P40, 512 KB: spi_command called, but no SPI chipset/strapping detected Probing for ST M25P40-old, 512 KB: spi_command called, but no SPI chipset/strapping detected spi_command called, but no SPI chipset/strapping detected Probing for ST M25P80, 1024 KB: spi_command called, but no SPI chipset/strapping detected Probing for ST M25P16, 2048 KB: spi_command called, but no SPI chipset/strapping detected Probing for ST M25P32, 4096 KB: spi_command called, but no SPI chipset/strapping detected Probing for ST M25P64, 8192 KB: spi_command called, but no SPI chipset/strapping detected Probing for ST M25P128, 16384 KB: spi_command called, but no SPI chipset/strapping detected Probing for ST M29F002B, 256 KB: probe_jedec: id1 0xbf, id2 0x60 Probing for ST M29F002T/NT, 256 KB: probe_jedec: id1 0xbf, id2 0x60 Probing for ST M29F040B, 512 KB: probe_29f040b: id1 0x21, id2 0x30 Probing for ST M29F400BT, 512 KB: probe_m29f400bt: id1 0x21, id2 0x2d Probing for ST M29W010B, 128 KB: probe_jedec: id1 0xbf, id2 0x60 Probing for ST M29W040B, 512 KB: probe_jedec: id1 0xbf, id2 0x60 Probing for ST M50FLW040A, 512 KB: probe_stm50flw0x0x: id1 0xbf, id2 0x60 Probing for ST M50FLW040B, 512 KB: probe_stm50flw0x0x: id1 0xbf, id2 0x60 Probing for ST M50FLW080A, 1024 KB: probe_stm50flw0x0x: id1 0xbf, id2 0x60 Probing for ST M50FLW080B, 1024 KB: probe_stm50flw0x0x: id1 0xbf, id2 0x60 Probing for ST M50FW002, 256 KB: probe_49lfxxxc: id1 0x21, id2 0x30 Probing for ST M50FW016, 2048 KB: probe_82802ab: id1 0x21, id2 0x30 Probing for ST M50FW040, 512 KB: probe_82802ab: id1 0x21, id2 0x30 Probing for ST M50FW080, 1024 KB: probe_82802ab: id1 0x21, id2 0x30 Probing for ST M50LPW116, 2048 KB: probe_jedec: id1 0xbf, id2 0x60 Probing for SyncMOS S29C31004T, 512 KB: probe_jedec: id1 0xbf, id2 0x60 Probing for SyncMOS S29C51001T, 128 KB: probe_jedec: id1 0xbf, id2 0x60 Probing for SyncMOS S29C51002T, 256 KB: probe_jedec: id1 0xbf, id2 0x60 Probing for SyncMOS S29C51004T, 512 KB: probe_jedec: id1 0xbf, id2 0x60 Probing for Winbond W25x10, 128 KB: spi_command called, but no SPI chipset/strapping detected Probing for Winbond W25x20, 256 KB: spi_command called, but no SPI chipset/strapping detected Probing for Winbond W25x40, 512 KB: spi_command called, but no SPI chipset/strapping detected Probing for Winbond W25x80, 1024 KB: spi_command called, but no SPI chipset/strapping detected Probing for Winbond W29C011, 128 KB: probe_jedec: id1 0xbf, id2 0x60 Probing for Winbond W29C020C, 256 KB: probe_jedec: id1 0xbf, id2 0x60 Probing for Winbond W29C040P, 512 KB: probe_jedec: id1 0xbf, id2 0x60 Probing for Winbond W29EE011, 128 KB: === Probing disabled for Winbond W29EE011 because the probing sequence puts the AMIC A49LF040A in a funky state. Use 'flashrom -c W29EE011' if you have a board with this chip. === Probing for Winbond W39V040A, 512 KB: probe_jedec: id1 0xbf, id2 0x60 Probing for Winbond W39V040B, 512 KB: probe_jedec: id1 0xbf, id2 0x60 Probing for Winbond W39V040C, 512 KB: probe_w39v040c: id1 0xbf, id2 0x60 Probing for Winbond W39V040FA, 512 KB: probe_jedec: id1 0xbf, id2 0x60 Probing for Winbond W39V080A, 1024 KB: probe_jedec: id1 0xbf, id2 0x60 Probing for Winbond W49F002U, 256 KB: probe_jedec: id1 0xbf, id2 0x60 Probing for Winbond W49V002A, 256 KB: probe_jedec: id1 0xbf, id2 0x60 Probing for Winbond W49V002FA, 256 KB: probe_jedec: id1 0xbf, id2 0x60 Probing for Winbond W39V080FA, 1024 KB: probe_winbond_fwhub: vid 0xbf, did 0x60 Probing for Winbond W39V080FA (dual mode), 512 KB: probe_winbond_fwhub: vid 0xbf, did 0x60 Probing for Atmel unknown Atmel SPI chip, 0 KB: spi_command called, but no SPI chipset/strapping detected Probing for EON unknown EON SPI chip, 0 KB: spi_command called, but no SPI chipset/strapping detected Probing for Macronix unknown Macronix SPI chip, 0 KB: spi_command called, but no SPI chipset/strapping detected Probing for PMC unknown PMC SPI chip, 0 KB: spi_command called, but no SPI chipset/strapping detected Probing for SST unknown SST SPI chip, 0 KB: spi_command called, but no SPI chipset/strapping detected Probing for ST unknown ST SPI chip, 0 KB: spi_command called, but no SPI chipset/strapping detected No operations were specified. -[0000:00]-+-00.0 nVidia Corporation CK804 Memory Controller [10de:005e] +-01.0 nVidia Corporation CK804 ISA Bridge [10de:0050] +-01.1 nVidia Corporation CK804 SMBus [10de:0052] +-02.0 nVidia Corporation CK804 USB Controller [10de:005a] +-02.1 nVidia Corporation CK804 USB Controller [10de:005b] +-04.0 nVidia Corporation CK804 AC'97 Audio Controller [10de:0059] +-06.0 nVidia Corporation CK804 IDE [10de:0053] +-08.0 nVidia Corporation CK804 Serial ATA Controller [10de:0055] +-09.0-[0000:05]--+-06.0 Creative Labs SB Audigy [1102:0004] | +-06.1 Creative Labs SB Audigy Game Port [1102:7003] | +-06.2 Creative Labs SB Audigy FireWire Port [1102:4001] | \-0b.0 Texas Instruments TSB43AB22/A IEEE-1394a-2000 Controller (PHY/Link) [104c:8023] +-0a.0 nVidia Corporation CK804 Ethernet Controller [10de:0057] +-0b.0-[0000:04]-- +-0c.0-[0000:03]-- +-0d.0-[0000:02]-- +-0e.0-[0000:01]----00.0 nVidia Corporation D9M-20 [GeForce 9400 GT] [10de:0641] +-18.0 Advanced Micro Devices [AMD] K8 [Athlon64/Opteron] HyperTransport Technology Configuration [1022:1100] +-18.1 Advanced Micro Devices [AMD] K8 [Athlon64/Opteron] Address Map [1022:1101] +-18.2 Advanced Micro Devices [AMD] K8 [Athlon64/Opteron] DRAM Controller [1022:1102] \-18.3 Advanced Micro Devices [AMD] K8 [Athlon64/Opteron] Miscellaneous Control [1022:1103] /* generated by MPTable, version 2.0.15*/ /* as modified by RGM for coreboot */ #include <console/console.h> #include <arch/smp/mpspec.h> #include <device/pci.h> #include <string.h> #include <stdint.h> void *smp_write_config_table(void *v) { static const char sig[4] = "PCMP"; static const char oem[8] = "LNXI "; static const char productid[12] = "P4DPE "; struct mp_config_table *mc; mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); memset(mc, 0, sizeof(*mc)); memcpy(mc->mpc_signature, sig, sizeof(sig)); mc->mpc_length = sizeof(*mc); /* initially just the header */ mc->mpc_spec = 0x04; mc->mpc_checksum = 0; /* not yet computed */ memcpy(mc->mpc_oem, oem, sizeof(oem)); memcpy(mc->mpc_productid, productid, sizeof(productid)); mc->mpc_oemptr = 0; mc->mpc_oemsize = 0; mc->mpc_entry_count = 0; /* No entries yet... */ mc->mpc_lapic = LAPIC_ADDR; mc->mpe_length = 0; mc->mpe_checksum = 0; mc->reserved = 0; smp_write_processors(mc); /*Bus: Bus ID Type*/ smp_write_bus(mc, 0, "PCI "); smp_write_bus(mc, 1, "PCI "); smp_write_bus(mc, 2, "PCI "); smp_write_bus(mc, 3, "PCI "); smp_write_bus(mc, 4, "PCI "); smp_write_bus(mc, 5, "PCI "); smp_write_bus(mc, 6, "ISA "); /*I/O APICs: APIC ID Version State Address*/ smp_write_ioapic(mc, 2, 0x20, 0xfec00000); { device_t dev; struct resource *res; dev = dev_find_slot(1, PCI_DEVFN(0x1e,0)); if (dev) { res = find_resource(dev, PCI_BASE_ADDRESS_0); if (res) { smp_write_ioapic(mc, 3, 0x20, res->base); } } dev = dev_find_slot(1, PCI_DEVFN(0x1c,0)); if (dev) { res = find_resource(dev, PCI_BASE_ADDRESS_0); if (res) { smp_write_ioapic(mc, 4, 0x20, res->base); } } dev = dev_find_slot(4, PCI_DEVFN(0x1e,0)); if (dev) { res = find_resource(dev, PCI_BASE_ADDRESS_0); if (res) { smp_write_ioapic(mc, 5, 0x20, res->base); } } dev = dev_find_slot(4, PCI_DEVFN(0x1c,0)); if (dev) { res = find_resource(dev, PCI_BASE_ADDRESS_0); if (res) { smp_write_ioapic(mc, 8, 0x20, res->base); } } } /*I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x4, 0x2, 0xb); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x9, 0x2, 0x3); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x8, 0x2, 0x5); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x5, 0x2c, 0x2, 0x3); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x5, 0x19, 0x2, 0xc); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x28, 0x2, 0xb); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x10, 0x2, 0x3); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x5, 0x18, 0x2, 0x3); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x1, 0x0, 0x2, 0xc); smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x6, 0x0, 0x2, 0x0); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x6, 0x1, 0x2, 0x1); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x6, 0x0, 0x2, 0x2); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x6, 0x4, 0x2, 0x4); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x6, 0x6, 0x2, 0x6); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x6, 0x7, 0x2, 0x7); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x6, 0x8, 0x2, 0x8); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x6, 0x9, 0x2, 0x9); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x6, 0xa, 0x2, 0xa); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x6, 0xd, 0x2, 0xd); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x6, 0xe, 0x2, 0xe); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x6, 0xf, 0x2, 0xf); /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/ smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x0, 0x0, MP_APIC_ALL, 0x0); smp_write_intsrc(mc, mp_NMI, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x0, 0x0, MP_APIC_ALL, 0x1); /* There is no extension information... */ /* Compute the checksums */ mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length); mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length); printk_debug("Wrote the mp table end at: %p - %p\n", mc, smp_next_mpe_entry(mc)); return smp_next_mpe_entry(mc); } unsigned long write_smp_table(unsigned long addr) { void *v; v = smp_write_floating_table(addr); return (unsigned long)smp_write_config_table(v); } /* generated by MPTable, version 2.0.15*/ /* as modified by RGM for coreboot */ #include <console/console.h> #include <arch/smp/mpspec.h> #include <device/pci.h> #include <string.h> #include <stdint.h> void *smp_write_config_table(void *v) { static const char sig[4] = "PCMP"; static const char oem[8] = "LNXI "; static const char productid[12] = "P4DPE "; struct mp_config_table *mc; mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); memset(mc, 0, sizeof(*mc)); memcpy(mc->mpc_signature, sig, sizeof(sig)); mc->mpc_length = sizeof(*mc); /* initially just the header */ mc->mpc_spec = 0x04; mc->mpc_checksum = 0; /* not yet computed */ memcpy(mc->mpc_oem, oem, sizeof(oem)); memcpy(mc->mpc_productid, productid, sizeof(productid)); mc->mpc_oemptr = 0; mc->mpc_oemsize = 0; mc->mpc_entry_count = 0; /* No entries yet... */ mc->mpc_lapic = LAPIC_ADDR; mc->mpe_length = 0; mc->mpe_checksum = 0; mc->reserved = 0; smp_write_processors(mc); looking for EBDA pointer @ 0x040e, found, searching EBDA @ 0x0009f400 searching for coreboot MP table @ 0x00000000 (0K) searching CMOS 'top of mem' @ 0x0009f000 (636K) searching default 'top of mem' @ 0x0009fc00 (639K) searching BIOS @ 0x000f0000 MP FPS found in BIOS @ physical addr: 0x000f5500 ------------------------------------------------------------------------------- MP Floating Pointer Structure: location: BIOS physical address: 0x000f5500 signature: '_MP_' length: 16 bytes version: 1.4 checksum: 0x7d mode: Virtual Wire ------------------------------------------------------------------------------- MP Config Table Header: physical address: 0x000f1400 signature: 'PCMP' base table length: 332 version: 1.4 checksum: 0xd2 OEM ID: 'OEM00000' Product ID: 'PROD00000000' OEM table pointer: 0x00000000 OEM table size: 0 entry count: 33 local APIC address: 0xfee00000 extended table length: 0 extended table checksum: 0 ------------------------------------------------------------------------------- MP Config Base Table Entries: -- Processors: APIC ID Version State Family Model Step Flags /*Bus: Bus ID Type*/ 0 PCI smp_write_bus(mc, 0, "PCI "); 1 PCI smp_write_bus(mc, 1, "PCI "); 2 PCI smp_write_bus(mc, 2, "PCI "); 3 PCI smp_write_bus(mc, 3, "PCI "); 4 PCI smp_write_bus(mc, 4, "PCI "); 5 PCI smp_write_bus(mc, 5, "PCI "); 6 ISA smp_write_bus(mc, 6, "ISA "); /*I/O APICs: APIC ID Version State Address*/ smp_write_ioapic(mc, 2, 0x20, 0xfec00000); { device_t dev; struct resource *res; dev = dev_find_slot(1, PCI_DEVFN(0x1e,0)); if (dev) { res = find_resource(dev, PCI_BASE_ADDRESS_0); if (res) { smp_write_ioapic(mc, 3, 0x20, res->base); } } dev = dev_find_slot(1, PCI_DEVFN(0x1c,0)); if (dev) { res = find_resource(dev, PCI_BASE_ADDRESS_0); if (res) { smp_write_ioapic(mc, 4, 0x20, res->base); } } dev = dev_find_slot(4, PCI_DEVFN(0x1e,0)); if (dev) { res = find_resource(dev, PCI_BASE_ADDRESS_0); if (res) { smp_write_ioapic(mc, 5, 0x20, res->base); } } dev = dev_find_slot(4, PCI_DEVFN(0x1c,0)); if (dev) { res = find_resource(dev, PCI_BASE_ADDRESS_0); if (res) { smp_write_ioapic(mc, 8, 0x20, res->base); } } } /*I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x4, 0x2, 0xb); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x9, 0x2, 0x3); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x8, 0x2, 0x5); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x5, 0x2c, 0x2, 0x3); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x5, 0x19, 0x2, 0xc); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x28, 0x2, 0xb); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x10, 0x2, 0x3); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x5, 0x18, 0x2, 0x3); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x1, 0x0, 0x2, 0xc); smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x6, 0x0, 0x2, 0x0); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x6, 0x1, 0x2, 0x1); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x6, 0x0, 0x2, 0x2); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x6, 0x4, 0x2, 0x4); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x6, 0x6, 0x2, 0x6); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x6, 0x7, 0x2, 0x7); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x6, 0x8, 0x2, 0x8); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x6, 0x9, 0x2, 0x9); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x6, 0xa, 0x2, 0xa); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x6, 0xd, 0x2, 0xd); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x6, 0xe, 0x2, 0xe); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x6, 0xf, 0x2, 0xf); /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/ smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x0, 0x0, MP_APIC_ALL, 0x0); smp_write_intsrc(mc, mp_NMI, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x0, 0x0, MP_APIC_ALL, 0x1); /* There is no extension information... */ /* Compute the checksums */ mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length); mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length); printk_debug("Wrote the mp table end at: %p - %p\n", mc, smp_next_mpe_entry(mc)); return smp_next_mpe_entry(mc); } unsigned long write_smp_table(unsigned long addr) { void *v; v = smp_write_floating_table(addr); return (unsigned long)smp_write_config_table(v); } =============================================================================== superiotool r3695 Probing for ALi Super I/O at 0x3f0... Failed. Returned data: id=0xffff, rev=0xff Probing for ALi Super I/O at 0x370... Failed. Returned data: id=0xffff, rev=0xff Probing for Fintek Super I/O at 0x2e... Failed. Returned data: vid=0xffff, id=0xffff Probing for Fintek Super I/O at 0x4e... Failed. Returned data: vid=0xffff, id=0xffff Probing for ITE Super I/O (init=0x87,0x01,0x55,0x55/0xaa) at 0x2e... Found ITE IT8712F (id=0x8712, rev=0x7) at 0x2e Register dump: idx 20 21 22 23 24 2b val 87 12 07 01 00 00 def 87 12 08 00 00 00 LDN 0x00 (Floppy) idx 30 60 61 70 74 f0 f1 val 00 00 00 00 04 00 00 def 00 03 f0 06 02 00 00 LDN 0x01 (COM1) idx 30 60 61 70 f0 f1 f2 f3 val 01 03 f8 04 00 50 00 7f def 00 03 f8 04 00 50 00 7f LDN 0x02 (COM2) idx 30 60 61 70 f0 f1 f2 f3 val 00 00 00 00 00 50 00 7f def 00 02 f8 03 00 50 00 7f LDN 0x03 (Parallel port) idx 30 60 61 62 63 70 74 f0 val 01 03 78 07 78 07 03 0b def 00 03 78 07 78 07 03 03 LDN 0x04 (Environment controller) idx 30 60 61 62 63 70 f0 f1 f2 f3 f4 f5 f6 val 01 02 90 00 00 00 80 00 0a 00 80 00 bf def 00 02 90 02 30 09 00 00 00 00 00 NA NA LDN 0x05 (Keyboard) idx 30 60 61 62 63 70 71 f0 val 01 00 60 00 64 01 02 68 def 01 00 60 00 64 01 02 08 LDN 0x06 (Mouse) idx 30 70 71 f0 val 00 00 02 00 def 00 0c 02 00 LDN 0x07 (GPIO) idx 25 26 27 28 29 2a 2c 60 61 62 63 64 65 70 71 72 73 74 b0 b1 b2 b3 b4 b5 b8 b9 ba bb bc bd c0 c1 c2 c3 c4 c8 c9 ca cb cc e0 e1 e2 e3 e4 f0 f1 f2 f3 f4 f5 f6 f7 f8 f9 fa fb fc fd val 06 00 21 40 00 06 1f 00 00 08 00 00 00 00 00 00 00 04 06 00 21 00 00 00 00 00 01 00 00 00 06 00 21 40 00 00 00 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 3f 00 def 01 00 00 40 00 00 00 00 00 00 00 00 00 00 00 00 c0 00 00 00 00 00 00 00 00 00 00 00 00 00 01 00 00 40 00 01 00 00 40 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 NA 00 LDN 0x08 (MIDI port) idx 30 60 61 70 f0 val 01 03 30 0a 00 def 00 03 00 0a 00 LDN 0x09 (Game port) idx 30 60 61 val 01 02 01 def 00 02 01 LDN 0x0a (Consumer IR) idx 30 60 61 70 f0 val 00 03 10 0b 06 def 00 03 10 0b 00 Probing for ITE Super I/O (init=0x87,0x87) at 0x2e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=0x87,0x01,0x55,0x55/0xaa) at 0x4e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=0x87,0x87) at 0x4e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=legacy/it8661f) at 0x370... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=legacy/it8671f) at 0x370... Failed. Returned data: id=0xffff, rev=0xf Probing for NSC Super I/O at 0x2e... Failed. Returned data: port=0xff, port+1=0xff Probing for NSC Super I/O at 0x4e... Failed. Returned data: port=0xff, port+1=0xff Probing for NSC Super I/O at 0x15c... Failed. Returned data: port=0xff, port+1=0xff Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x2e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x2e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x4e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x4e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x162e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x162e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x164e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x164e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x3f0... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x3f0... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x370... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x370... Failed. Returned data: id=0xff, rev=0xff Probing for Winbond Super I/O (init=0x88) at 0x2e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x89) at 0x2e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x86,0x86) at 0x2e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x87,0x87) at 0x2e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x88) at 0x4e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x89) at 0x4e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x86,0x86) at 0x4e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x87,0x87) at 0x4e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x88) at 0x3f0... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x89) at 0x3f0... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x86,0x86) at 0x3f0... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x87,0x87) at 0x3f0... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x88) at 0x370... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x89) at 0x370... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x86,0x86) at 0x370... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x87,0x87) at 0x370... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x88) at 0x250... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x89) at 0x250... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x86,0x86) at 0x250... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x87,0x87) at 0x250... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff

1 1

Product support
by david mackney 30 May '09

30 May '09

/My interests lie in the advancing product lines, hence I tend to focus on newer trends; therefor, you may appreciate that I am focused on products lines, such as the minITX motherboards. >From my perspective, it would be desirable if you would embrace products from Zotac and J&W, both companies produce products which are pushing the next generation of computer builds. With the `new` openness from ATI and NVidia, surely it is possible to embrace these newer motherboards, rather than what I see as support for `dated` component. Regards, David. /

4 4

[PATCH] Good bye vm86, hello x86 real mode ;-)
by Stefan Reinauer 30 May '09

30 May '09

See patch. The subject is a bit misleading, since we never used vm86 mode in coreboot. Stefan -- coresystems GmbH • Brahmsstr. 16 • D-79104 Freiburg i. Br. Tel.: +49 761 7668825 • Fax: +49 761 7664613 Email: info(a)coresystems.de • http://www.coresystems.de/ Registergericht: Amtsgericht Freiburg • HRB 7656 Geschäftsführer: Stefan Reinauer • Ust-IdNr.: DE245674866

5 8

build service results for r4325
by coreboot information 29 May '09

29 May '09

Dear coreboot readers! This is the automatic build system of coreboot. The developer "linux_junkie" checked in revision 4325 to the coreboot repository. This caused the following changes: Change Log: rename the option CONFIG_PCI_OPTION_ROM_RUN_VM86 to CONFIG_PCI_OPTION_ROM_RUN_REALMODE. Signed-off-by: Joseph Smith <joe(a)settoplinux.org> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Build Log: Configuration of a-trend:atc-6220 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4325&device=atc-6220&vendo… Configuration of a-trend:atc-6240 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4325&device=atc-6240&vendo… Configuration of abit:be6-ii_v2_0 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4325&device=be6-ii_v2_0&ve… Configuration of amd:dbm690t has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4325&device=dbm690t&vendor… Configuration of amd:pistachio has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4325&device=pistachio&vend… Configuration of amd:serengeti_cheetah has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4325&device=serengeti_chee… Configuration of amd:serengeti_cheetah_fam10 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4325&device=serengeti_chee… Configuration of arima:hdama has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4325&device=hdama&vendor=a… Configuration of asus:a8n_e has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4325&device=a8n_e&vendor=a… Configuration of asus:a8v-e_se has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4325&device=a8v-e_se&vendo… Configuration of asus:mew-am has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4325&device=mew-am&vendor=… Configuration of asus:p2b has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4325&device=p2b&vendor=asu… Configuration of asus:p2b-d has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4325&device=p2b-d&vendor=a… Configuration of asus:p2b-ds has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4325&device=p2b-ds&vendor=… Configuration of asus:p2b-f has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4325&device=p2b-f&vendor=a… Configuration of asus:p3b-f has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4325&device=p3b-f&vendor=a… Configuration of azza:pt-6ibd has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4325&device=pt-6ibd&vendor… Configuration of biostar:m6tba has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4325&device=m6tba&vendor=b… Configuration of compaq:deskpro_en_sff_p600 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4325&device=deskpro_en_sff… Compilation of embeddedplanet:ep405pc is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4325&device=ep405pc&vendor… Configuration of emulation:qemu-x86 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4325&device=qemu-x86&vendo… Configuration of gigabyte:ga-6bxc has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4325&device=ga-6bxc&vendor… Configuration of gigabyte:ga_2761gxdk has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4325&device=ga_2761gxdk&ve… Configuration of gigabyte:m57sli has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4325&device=m57sli&vendor=… Configuration of ibm:e326 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4325&device=e326&vendor=ib… Configuration of iei:nova4899r has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4325&device=nova4899r&vend… Configuration of iwill:dk8_htx has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4325&device=dk8_htx&vendor… Configuration of kontron:986lcd-m has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4325&device=986lcd-m&vendo… Compilation of motorola:sandpointx3_altimus_mpc7410 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4325&device=sandpointx3_al… Configuration of msi:ms6119 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4325&device=ms6119&vendor=… Configuration of msi:ms6147 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4325&device=ms6147&vendor=… Configuration of msi:ms6178 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4325&device=ms6178&vendor=… Configuration of msi:ms7135 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4325&device=ms7135&vendor=… Configuration of msi:ms7260 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4325&device=ms7260&vendor=… Configuration of msi:ms9185 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4325&device=ms9185&vendor=… Configuration of msi:ms9282 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4325&device=ms9282&vendor=… Configuration of nec:powermate2000 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4325&device=powermate2000&… Configuration of newisys:khepri has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4325&device=khepri&vendor=… Configuration of nvidia:l1_2pvv has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4325&device=l1_2pvv&vendor… Configuration of sunw:ultra40 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4325&device=ultra40&vendor… Configuration of supermicro:h8dme has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4325&device=h8dme&vendor=s… Configuration of supermicro:h8dmr has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4325&device=h8dmr&vendor=s… Configuration of technexion:tim8690 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4325&device=tim8690&vendor… Compilation of totalimpact:briq is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4325&device=briq&vendor=to… Configuration of tyan:s1846 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4325&device=s1846&vendor=t… Configuration of tyan:s2850 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4325&device=s2850&vendor=t… Configuration of tyan:s2875 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4325&device=s2875&vendor=t… Configuration of tyan:s2880 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4325&device=s2880&vendor=t… Configuration of tyan:s2881 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4325&device=s2881&vendor=t… Configuration of tyan:s2882 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4325&device=s2882&vendor=t… Configuration of tyan:s2885 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4325&device=s2885&vendor=t… Configuration of tyan:s2891 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4325&device=s2891&vendor=t… Configuration of tyan:s2892 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4325&device=s2892&vendor=t… Configuration of tyan:s2895 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4325&device=s2895&vendor=t… Configuration of tyan:s2912 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4325&device=s2912&vendor=t… Configuration of tyan:s2912_fam10 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4325&device=s2912_fam10&ve… Configuration of tyan:s4880 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4325&device=s4880&vendor=t… If something broke during this checkin please be a pain in linux_junkie's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

2 3

[PATCH] Rename Option VM86 to REALMODE
by Joseph Smith 29 May '09

29 May '09

Here is patches to rename the option CONFIG_PCI_OPTION_ROM_RUN_VM86 to CONFIG_PCI_OPTION_ROM_RUN_REALMODE. abuild tested Signed-off-by: Joseph Smith <joe(a)settoplinux.org> -- Thanks, Joseph Smith Set-Top-Linux www.settoplinux.org

2 2

[v3] r1170 - coreboot-v3/util/x86emu
by svn＠coreboot.org 29 May '09

29 May '09

Author: linux_junkie Date: 2009-05-29 20:42:23 +0200 (Fri, 29 May 2009) New Revision: 1170 Modified: coreboot-v3/util/x86emu/Config.lb coreboot-v3/util/x86emu/Makefile Log: rename the option CONFIG_PCI_OPTION_ROM_RUN_VM86 to CONFIG_PCI_OPTION_ROM_RUN_REALMODE. Signed-off-by: Joseph Smith <joe(a)settoplinux.org> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: coreboot-v3/util/x86emu/Config.lb =================================================================== --- coreboot-v3/util/x86emu/Config.lb 2009-05-29 17:38:46 UTC (rev 1169) +++ coreboot-v3/util/x86emu/Config.lb 2009-05-29 18:42:23 UTC (rev 1170) @@ -1,11 +1,11 @@ uses CONFIG_PCI_OPTION_ROM_RUN_YABEL -uses CONFIG_PCI_OPTION_ROM_RUN_VM86 +uses CONFIG_PCI_OPTION_ROM_RUN_REALMODE if CONFIG_PCI_OPTION_ROM_RUN_YABEL dir yabel dir x86emu else - if CONFIG_PCI_OPTION_ROM_RUN_VM86 + if CONFIG_PCI_OPTION_ROM_RUN_REALMODE object x86.o object x86_interrupts.o object x86_asm.S Modified: coreboot-v3/util/x86emu/Makefile =================================================================== --- coreboot-v3/util/x86emu/Makefile 2009-05-29 17:38:46 UTC (rev 1169) +++ coreboot-v3/util/x86emu/Makefile 2009-05-29 18:42:23 UTC (rev 1170) @@ -37,7 +37,7 @@ #TODO: remove these, these are .h files from slof, to make the merge easier... X86EMU_INCLUDE += -I $(src)/util/x86emu/yabel/compat endif -VM86_SRC = x86.c x86_asm.S +REALMODE_SRC = x86.c x86_asm.S ifeq ($(CONFIG_PCI_OPTION_ROM_RUN_X86EMU),y) LIBX86EMU_SRC=$(patsubst %,x86emu/%,$(X86EMU_SRC)) $(BIOSEMU_SRC) @@ -47,8 +47,8 @@ LIBX86EMU_SRC=$(patsubst %,x86emu/%,$(X86EMU_SRC)) $(patsubst %,yabel/%,$(BIOSEMU_SRC)) endif -ifeq ($(CONFIG_PCI_OPTION_ROM_RUN_VM86),y) -LIBX86EMU_SRC=$(VM86_SRC) +ifeq ($(CONFIG_PCI_OPTION_ROM_RUN_REALMODE),y) +LIBX86EMU_SRC=$(REALMODE_SRC) endif LIBX86EMU_OBJS = $(patsubst %.c,$(obj)/util/x86emu/%.o,$(LIBX86EMU_SRC))

1 0

[v2] r4325 - in trunk/coreboot-v2: src/config src/mainboard/emulation/qemu-x86 src/mainboard/rca/rm4100 src/mainboard/thomson/ip1000 targets/rca/rm4100 targets/thomson/ip1000
by svn＠coreboot.org 29 May '09

29 May '09

Author: linux_junkie Date: 2009-05-29 20:41:09 +0200 (Fri, 29 May 2009) New Revision: 4325 Modified: trunk/coreboot-v2/src/config/Options.lb trunk/coreboot-v2/src/mainboard/emulation/qemu-x86/Options.lb trunk/coreboot-v2/src/mainboard/rca/rm4100/Options.lb trunk/coreboot-v2/src/mainboard/thomson/ip1000/Options.lb trunk/coreboot-v2/targets/rca/rm4100/Config.lb trunk/coreboot-v2/targets/thomson/ip1000/Config.lb Log: rename the option CONFIG_PCI_OPTION_ROM_RUN_VM86 to CONFIG_PCI_OPTION_ROM_RUN_REALMODE. Signed-off-by: Joseph Smith <joe(a)settoplinux.org> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/coreboot-v2/src/config/Options.lb =================================================================== --- trunk/coreboot-v2/src/config/Options.lb 2009-05-29 13:45:22 UTC (rev 4324) +++ trunk/coreboot-v2/src/config/Options.lb 2009-05-29 18:41:09 UTC (rev 4325) @@ -1114,7 +1114,7 @@ end -define CONFIG_PCI_OPTION_ROM_RUN_VM86 +define CONFIG_PCI_OPTION_ROM_RUN_REALMODE default 0 export used comment "Use Yabel instead of old bios emulator" Modified: trunk/coreboot-v2/src/mainboard/emulation/qemu-x86/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/emulation/qemu-x86/Options.lb 2009-05-29 13:45:22 UTC (rev 4324) +++ trunk/coreboot-v2/src/mainboard/emulation/qemu-x86/Options.lb 2009-05-29 18:41:09 UTC (rev 4325) @@ -37,7 +37,7 @@ uses HOSTCC uses OBJCOPY uses CONFIG_PCI_ROM_RUN -uses CONFIG_PCI_OPTION_ROM_RUN_VM86 +uses CONFIG_PCI_OPTION_ROM_RUN_REALMODE uses CONFIG_CONSOLE_SERIAL8250 uses USE_DCACHE_RAM @@ -92,7 +92,7 @@ ## Option ROM init ## default CONFIG_PCI_ROM_RUN=1 -default CONFIG_PCI_OPTION_ROM_RUN_VM86=1 +default CONFIG_PCI_OPTION_ROM_RUN_REALMODE=1 ### ### coreboot layout values Modified: trunk/coreboot-v2/src/mainboard/rca/rm4100/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/rca/rm4100/Options.lb 2009-05-29 13:45:22 UTC (rev 4324) +++ trunk/coreboot-v2/src/mainboard/rca/rm4100/Options.lb 2009-05-29 18:41:09 UTC (rev 4325) @@ -24,7 +24,7 @@ uses CONFIG_CONSOLE_VGA uses CONFIG_COMPRESSED_PAYLOAD_LZMA uses CONFIG_IOAPIC -uses CONFIG_PCI_OPTION_ROM_RUN_VM86 +uses CONFIG_PCI_OPTION_ROM_RUN_REALMODE uses CONFIG_PCI_ROM_RUN uses CONFIG_ROM_PAYLOAD uses CONFIG_ROM_PAYLOAD_START @@ -79,7 +79,7 @@ default HAVE_OPTION_TABLE = 0 default CONFIG_CONSOLE_VGA = 0 default CONFIG_PCI_ROM_RUN = 0 -default CONFIG_PCI_OPTION_ROM_RUN_VM86 = 0 +default CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0 default CONFIG_VIDEO_MB = 0 default STACK_SIZE = 0x2000 default HEAP_SIZE = 0x4000 Modified: trunk/coreboot-v2/src/mainboard/thomson/ip1000/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/thomson/ip1000/Options.lb 2009-05-29 13:45:22 UTC (rev 4324) +++ trunk/coreboot-v2/src/mainboard/thomson/ip1000/Options.lb 2009-05-29 18:41:09 UTC (rev 4325) @@ -24,7 +24,7 @@ uses CONFIG_CONSOLE_VGA uses CONFIG_COMPRESSED_PAYLOAD_LZMA uses CONFIG_IOAPIC -uses CONFIG_PCI_OPTION_ROM_RUN_VM86 +uses CONFIG_PCI_OPTION_ROM_RUN_REALMODE uses CONFIG_PCI_ROM_RUN uses CONFIG_ROM_PAYLOAD uses CONFIG_ROM_PAYLOAD_START @@ -79,7 +79,7 @@ default HAVE_OPTION_TABLE = 0 default CONFIG_CONSOLE_VGA = 0 default CONFIG_PCI_ROM_RUN = 0 -default CONFIG_PCI_OPTION_ROM_RUN_VM86 = 0 +default CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0 default CONFIG_VIDEO_MB = 0 default STACK_SIZE = 0x2000 default HEAP_SIZE = 0x4000 Modified: trunk/coreboot-v2/targets/rca/rm4100/Config.lb =================================================================== --- trunk/coreboot-v2/targets/rca/rm4100/Config.lb 2009-05-29 13:45:22 UTC (rev 4324) +++ trunk/coreboot-v2/targets/rca/rm4100/Config.lb 2009-05-29 18:41:09 UTC (rev 4325) @@ -37,7 +37,7 @@ ## option CONFIG_CONSOLE_VGA = 1 option CONFIG_PCI_ROM_RUN = 1 -option CONFIG_PCI_OPTION_ROM_RUN_VM86 = 1 +option CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 1 ## ## Choose the amount of memory pre-allocated for VGA Modified: trunk/coreboot-v2/targets/thomson/ip1000/Config.lb =================================================================== --- trunk/coreboot-v2/targets/thomson/ip1000/Config.lb 2009-05-29 13:45:22 UTC (rev 4324) +++ trunk/coreboot-v2/targets/thomson/ip1000/Config.lb 2009-05-29 18:41:09 UTC (rev 4325) @@ -37,7 +37,7 @@ ## option CONFIG_CONSOLE_VGA = 1 option CONFIG_PCI_ROM_RUN = 1 -option CONFIG_PCI_OPTION_ROM_RUN_VM86 = 1 +option CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 1 ## ## Choose the amount of memory pre-allocated for VGA

1 0

[v3] r1169 - coreboot-v3/util/x86emu
by svn＠coreboot.org 29 May '09

29 May '09

Author: uwe Date: 2009-05-29 19:38:46 +0200 (Fri, 29 May 2009) New Revision: 1169 Modified: coreboot-v3/util/x86emu/x86.c coreboot-v3/util/x86emu/x86_asm.S coreboot-v3/util/x86emu/x86_interrupts.c Log: Header file consistency fixes (no functional changes). Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Modified: coreboot-v3/util/x86emu/x86.c =================================================================== --- coreboot-v3/util/x86emu/x86.c 2009-05-29 13:10:50 UTC (rev 1168) +++ coreboot-v3/util/x86emu/x86.c 2009-05-29 17:38:46 UTC (rev 1169) @@ -1,19 +1,20 @@ /* - * Copyright (C) 2009 coresystems GmbH + * This file is part of the coreboot project. * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. + * Copyright (C) 2009 coresystems GmbH * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ #include <device/pci.h> Modified: coreboot-v3/util/x86emu/x86_asm.S =================================================================== --- coreboot-v3/util/x86emu/x86_asm.S 2009-05-29 13:10:50 UTC (rev 1168) +++ coreboot-v3/util/x86emu/x86_asm.S 2009-05-29 17:38:46 UTC (rev 1169) @@ -1,19 +1,20 @@ /* - * Copyright (C) 2009 coresystems GmbH + * This file is part of the coreboot project. * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. + * Copyright (C) 2009 coresystems GmbH * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ #define REALMODE_BASE 0x500 Modified: coreboot-v3/util/x86emu/x86_interrupts.c =================================================================== --- coreboot-v3/util/x86emu/x86_interrupts.c 2009-05-29 13:10:50 UTC (rev 1168) +++ coreboot-v3/util/x86emu/x86_interrupts.c 2009-05-29 17:38:46 UTC (rev 1169) @@ -1,21 +1,22 @@ /* - * Copyright (C) 2001 Ronald G. Minnich - * Copyright (C) 2005 Nick.Barker9(a)btinternet.com - * Copyright (C) 2007-2009 coresystems GmbH + * This file is part of the coreboot project. * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. + * Copyright (C) 2001 Ronald G. Minnich + * Copyright (C) 2005 Nick.Barker9(a)btinternet.com + * Copyright (C) 2007-2009 coresystems GmbH * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ #include <device/pci.h>

1 0

← Newer
1
...
5
6
7
8
9
10
11
...
58
Older →

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

2012

2011

2010

2009

2008

2007

2006

2005

2004

2003

2002

coreboot May 2009