coreboot April 2009

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[PATCH] Factor out ROM size calculation from Config.lb
by Carl-Daniel Hailfinger 22 Apr '09

22 Apr '09

Thanks to Myles' patch adding support for include statements, refactoring Config.lb became possible. Factor out ROM size calculation from Config.lb. Only targets with USE_FAILOVER_IMAGE support are part of this patch, the other targets will come as separate patch. The diffstat is impressive and shows a major code reduction. src/failovercalculation.lb | 47 +++++++++++++++++++ src/mainboard/amd/serengeti_cheetah/Config.lb | 48 -------------------- src/mainboard/amd/serengeti_cheetah_fam10/Config.lb | 48 -------------------- src/mainboard/asus/a8n_e/Config.lb | 29 ------------ src/mainboard/gigabyte/ga_2761gxdk/Config.lb | 48 -------------------- src/mainboard/gigabyte/m57sli/Config.lb | 48 -------------------- src/mainboard/iwill/dk8_htx/Config.lb | 48 -------------------- src/mainboard/msi/ms7135/Config.lb | 47 ------------------- src/mainboard/msi/ms7260/Config.lb | 28 ----------- src/mainboard/nvidia/l1_2pvv/Config.lb | 48 -------------------- src/mainboard/supermicro/h8dme/Config.lb | 48 -------------------- src/mainboard/supermicro/h8dmr/Config.lb | 48 -------------------- src/mainboard/tyan/s2895/Config.lb | 48 -------------------- src/mainboard/tyan/s2912/Config.lb | 48 -------------------- src/mainboard/tyan/s2912_fam10/Config.lb | 48 -------------------- 15 files changed, 62 insertions(+), 617 deletions(-) Abuild tested. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: LinuxBIOSv2-Configlb_refactor/src/failovercalculation.lb =================================================================== --- LinuxBIOSv2-Configlb_refactor/src/failovercalculation.lb (Revision 0) +++ LinuxBIOSv2-Configlb_refactor/src/failovercalculation.lb (Revision 0) @@ -0,0 +1,47 @@ +## +## Compute the location and size of where this firmware image +## (coreboot plus bootloader) will live in the boot rom chip. +## +if USE_FAILOVER_IMAGE + default ROM_SECTION_SIZE = FAILOVER_SIZE + default ROM_SECTION_OFFSET = ( ROM_SIZE - FAILOVER_SIZE ) +else + if USE_FALLBACK_IMAGE + default ROM_SECTION_SIZE = FALLBACK_SIZE + default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE - FAILOVER_SIZE ) + else + default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE - FAILOVER_SIZE ) + default ROM_SECTION_OFFSET = 0 + end +end +## +## Compute the start location and size size of +## The coreboot bootloader. +## +default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE ) +default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) + +## +## Compute where this copy of coreboot will start in the boot rom +## +default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE ) + +## +## Compute a range of ROM that can cached to speed up coreboot, +## execution speed. +## +## XIP_ROM_SIZE must be a power of 2. +## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE +## +default XIP_ROM_SIZE = (64 * 1024) + +if USE_FAILOVER_IMAGE + default XIP_ROM_BASE = ( _ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE) +else + if USE_FALLBACK_IMAGE + default XIP_ROM_BASE = ( _ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE + FAILOVER_SIZE) + else + default XIP_ROM_BASE = ( _ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE) + end +end + Index: LinuxBIOSv2-Configlb_refactor/src/mainboard/iwill/dk8_htx/Config.lb =================================================================== --- LinuxBIOSv2-Configlb_refactor/src/mainboard/iwill/dk8_htx/Config.lb (Revision 4131) +++ LinuxBIOSv2-Configlb_refactor/src/mainboard/iwill/dk8_htx/Config.lb (Arbeitskopie) @@ -1,51 +1,5 @@ -## -## Compute the location and size of where this firmware image -## (coreboot plus bootloader) will live in the boot rom chip. -## -if USE_FAILOVER_IMAGE - default ROM_SECTION_SIZE = FAILOVER_SIZE - default ROM_SECTION_OFFSET = ( ROM_SIZE - FAILOVER_SIZE ) -else - if USE_FALLBACK_IMAGE - default ROM_SECTION_SIZE = FALLBACK_SIZE - default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE - FAILOVER_SIZE ) - else - default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE - FAILOVER_SIZE ) - default ROM_SECTION_OFFSET = 0 - end -end +include /failovercalculation.lb -## -## Compute the start location and size size of -## The coreboot bootloader. -## -default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE ) -default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) - -## -## Compute where this copy of coreboot will start in the boot rom -## -default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE ) - -## -## Compute a range of ROM that can cached to speed up coreboot, -## execution speed. -## -## XIP_ROM_SIZE must be a power of 2. -## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE -## -default XIP_ROM_SIZE=65536 - -if USE_FAILOVER_IMAGE - default XIP_ROM_BASE = ( _ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE) -else - if USE_FALLBACK_IMAGE - default XIP_ROM_BASE = ( _ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE + FAILOVER_SIZE) - else - default XIP_ROM_BASE = ( _ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE) - end -end - arch i386 end ## Index: LinuxBIOSv2-Configlb_refactor/src/mainboard/supermicro/h8dmr/Config.lb =================================================================== --- LinuxBIOSv2-Configlb_refactor/src/mainboard/supermicro/h8dmr/Config.lb (Revision 4131) +++ LinuxBIOSv2-Configlb_refactor/src/mainboard/supermicro/h8dmr/Config.lb (Arbeitskopie) @@ -19,54 +19,8 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -## -## Compute the location and size of where this firmware image -## (coreboot plus bootloader) will live in the boot rom chip. -## -if USE_FAILOVER_IMAGE - default ROM_SECTION_SIZE = FAILOVER_SIZE - default ROM_SECTION_OFFSET = ( ROM_SIZE - FAILOVER_SIZE ) -else - if USE_FALLBACK_IMAGE - default ROM_SECTION_SIZE = FALLBACK_SIZE - default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE - FAILOVER_SIZE ) - else - default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE - FAILOVER_SIZE ) - default ROM_SECTION_OFFSET = 0 - end -end +include /failovercalculation.lb -## -## Compute the start location and size size of -## The coreboot bootloader. -## -default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE ) -default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) - -## -## Compute where this copy of coreboot will start in the boot rom -## -default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE ) - -## -## Compute a range of ROM that can cached to speed up coreboot, -## execution speed. -## -## XIP_ROM_SIZE must be a power of 2. -## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE -## -default XIP_ROM_SIZE=65536 - -if USE_FAILOVER_IMAGE - default XIP_ROM_BASE = ( _ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE) -else - if USE_FALLBACK_IMAGE - default XIP_ROM_BASE = ( _ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE + FAILOVER_SIZE) - else - default XIP_ROM_BASE = ( _ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE) - end -end - arch i386 end ## Index: LinuxBIOSv2-Configlb_refactor/src/mainboard/supermicro/h8dme/Config.lb =================================================================== --- LinuxBIOSv2-Configlb_refactor/src/mainboard/supermicro/h8dme/Config.lb (Revision 4131) +++ LinuxBIOSv2-Configlb_refactor/src/mainboard/supermicro/h8dme/Config.lb (Arbeitskopie) @@ -16,54 +16,8 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -## -## Compute the location and size of where this firmware image -## (coreboot plus bootloader) will live in the boot rom chip. -## -if USE_FAILOVER_IMAGE - default ROM_SECTION_SIZE = FAILOVER_SIZE - default ROM_SECTION_OFFSET = ( ROM_SIZE - FAILOVER_SIZE ) -else - if USE_FALLBACK_IMAGE - default ROM_SECTION_SIZE = FALLBACK_SIZE - default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE - FAILOVER_SIZE ) - else - default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE - FAILOVER_SIZE ) - default ROM_SECTION_OFFSET = 0 - end -end +include /failovercalculation.lb -## -## Compute the start location and size size of -## The coreboot bootloader. -## -default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE ) -default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) - -## -## Compute where this copy of coreboot will start in the boot rom -## -default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE ) - -## -## Compute a range of ROM that can cached to speed up coreboot, -## execution speed. -## -## XIP_ROM_SIZE must be a power of 2. -## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE -## -default XIP_ROM_SIZE=65536 - -if USE_FAILOVER_IMAGE - default XIP_ROM_BASE = ( _ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE) -else - if USE_FALLBACK_IMAGE - default XIP_ROM_BASE = ( _ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE + FAILOVER_SIZE) - else - default XIP_ROM_BASE = ( _ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE) - end -end - arch i386 end ## Index: LinuxBIOSv2-Configlb_refactor/src/mainboard/gigabyte/m57sli/Config.lb =================================================================== --- LinuxBIOSv2-Configlb_refactor/src/mainboard/gigabyte/m57sli/Config.lb (Revision 4131) +++ LinuxBIOSv2-Configlb_refactor/src/mainboard/gigabyte/m57sli/Config.lb (Arbeitskopie) @@ -19,54 +19,8 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -## -## Compute the location and size of where this firmware image -## (coreboot plus bootloader) will live in the boot rom chip. -## -if USE_FAILOVER_IMAGE - default ROM_SECTION_SIZE = FAILOVER_SIZE - default ROM_SECTION_OFFSET = ( ROM_SIZE - FAILOVER_SIZE ) -else - if USE_FALLBACK_IMAGE - default ROM_SECTION_SIZE = FALLBACK_SIZE - default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE - FAILOVER_SIZE ) - else - default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE - FAILOVER_SIZE ) - default ROM_SECTION_OFFSET = 0 - end -end +include /failovercalculation.lb -## -## Compute the start location and size size of -## The coreboot bootloader. -## -default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE ) -default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) - -## -## Compute where this copy of coreboot will start in the boot rom -## -default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE ) - -## -## Compute a range of ROM that can cached to speed up coreboot, -## execution speed. -## -## XIP_ROM_SIZE must be a power of 2. -## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE -## -default XIP_ROM_SIZE=65536 - -if USE_FAILOVER_IMAGE - default XIP_ROM_BASE = ( _ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE) -else - if USE_FALLBACK_IMAGE - default XIP_ROM_BASE = ( _ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE + FAILOVER_SIZE) - else - default XIP_ROM_BASE = ( _ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE) - end -end - arch i386 end ## Index: LinuxBIOSv2-Configlb_refactor/src/mainboard/gigabyte/ga_2761gxdk/Config.lb =================================================================== --- LinuxBIOSv2-Configlb_refactor/src/mainboard/gigabyte/ga_2761gxdk/Config.lb (Revision 4131) +++ LinuxBIOSv2-Configlb_refactor/src/mainboard/gigabyte/ga_2761gxdk/Config.lb (Arbeitskopie) @@ -21,54 +21,8 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -## -## Compute the location and size of where this firmware image -## (coreboot plus bootloader) will live in the boot rom chip. -## -if USE_FAILOVER_IMAGE - default ROM_SECTION_SIZE = FAILOVER_SIZE - default ROM_SECTION_OFFSET = ( ROM_SIZE - FAILOVER_SIZE ) -else - if USE_FALLBACK_IMAGE - default ROM_SECTION_SIZE = FALLBACK_SIZE - default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE - FAILOVER_SIZE ) - else - default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE - FAILOVER_SIZE ) - default ROM_SECTION_OFFSET = 0 - end -end +include /failovercalculation.lb -## -## Compute the start location and size size of -## The coreboot bootloader. -## -default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE ) -default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) - -## -## Compute where this copy of coreboot will start in the boot rom -## -default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE ) - -## -## Compute a range of ROM that can cached to speed up coreboot, -## execution speed. -## -## XIP_ROM_SIZE must be a power of 2. -## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE -## -default XIP_ROM_SIZE=65536 - -if USE_FAILOVER_IMAGE - default XIP_ROM_BASE = ( _ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE) -else - if USE_FALLBACK_IMAGE - default XIP_ROM_BASE = ( _ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE + FAILOVER_SIZE) - else - default XIP_ROM_BASE = ( _ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE) - end -end - arch i386 end ## Index: LinuxBIOSv2-Configlb_refactor/src/mainboard/amd/serengeti_cheetah/Config.lb =================================================================== --- LinuxBIOSv2-Configlb_refactor/src/mainboard/amd/serengeti_cheetah/Config.lb (Revision 4131) +++ LinuxBIOSv2-Configlb_refactor/src/mainboard/amd/serengeti_cheetah/Config.lb (Arbeitskopie) @@ -1,51 +1,5 @@ -## -## Compute the location and size of where this firmware image -## (coreboot plus bootloader) will live in the boot rom chip. -## -if USE_FAILOVER_IMAGE - default ROM_SECTION_SIZE = FAILOVER_SIZE - default ROM_SECTION_OFFSET = ( ROM_SIZE - FAILOVER_SIZE ) -else - if USE_FALLBACK_IMAGE - default ROM_SECTION_SIZE = FALLBACK_SIZE - default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE - FAILOVER_SIZE ) - else - default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE - FAILOVER_SIZE ) - default ROM_SECTION_OFFSET = 0 - end -end +include /failovercalculation.lb -## -## Compute the start location and size size of -## The coreboot bootloader. -## -default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE ) -default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) - -## -## Compute where this copy of coreboot will start in the boot rom -## -default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE ) - -## -## Compute a range of ROM that can cached to speed up coreboot, -## execution speed. -## -## XIP_ROM_SIZE must be a power of 2. -## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE -## -default XIP_ROM_SIZE=65536 - -if USE_FAILOVER_IMAGE - default XIP_ROM_BASE = ( _ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE) -else - if USE_FALLBACK_IMAGE - default XIP_ROM_BASE = ( _ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE + FAILOVER_SIZE) - else - default XIP_ROM_BASE = ( _ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE) - end -end - arch i386 end ## Index: LinuxBIOSv2-Configlb_refactor/src/mainboard/amd/serengeti_cheetah_fam10/Config.lb =================================================================== --- LinuxBIOSv2-Configlb_refactor/src/mainboard/amd/serengeti_cheetah_fam10/Config.lb (Revision 4131) +++ LinuxBIOSv2-Configlb_refactor/src/mainboard/amd/serengeti_cheetah_fam10/Config.lb (Arbeitskopie) @@ -17,54 +17,8 @@ # Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA # -## -## Compute the location and size of where this firmware image -## (coreboot plus bootloader) will live in the boot rom chip. -## -if USE_FAILOVER_IMAGE - default ROM_SECTION_SIZE = FAILOVER_SIZE - default ROM_SECTION_OFFSET = ( ROM_SIZE - FAILOVER_SIZE ) -else - if USE_FALLBACK_IMAGE - default ROM_SECTION_SIZE = FALLBACK_SIZE - default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE - FAILOVER_SIZE ) - else - default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE - FAILOVER_SIZE ) - default ROM_SECTION_OFFSET = 0 - end -end +include /failovercalculation.lb -## -## Compute the start location and size size of -## The coreboot bootloader. -## -default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE ) -default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) - -## -## Compute where this copy of coreboot will start in the boot rom -## -default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE ) - -## -## Compute a range of ROM that can cached to speed up coreboot, -## execution speed. -## -## XIP_ROM_SIZE must be a power of 2. -## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE -## -default XIP_ROM_SIZE=65536 -# -if USE_FAILOVER_IMAGE - default XIP_ROM_BASE = ( _ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE) -else - if USE_FALLBACK_IMAGE - default XIP_ROM_BASE = ( _ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE + FAILOVER_SIZE) - else - default XIP_ROM_BASE = ( _ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE) - end -end - arch i386 end ## Index: LinuxBIOSv2-Configlb_refactor/src/mainboard/tyan/s2912/Config.lb =================================================================== --- LinuxBIOSv2-Configlb_refactor/src/mainboard/tyan/s2912/Config.lb (Revision 4131) +++ LinuxBIOSv2-Configlb_refactor/src/mainboard/tyan/s2912/Config.lb (Arbeitskopie) @@ -19,54 +19,8 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -## -## Compute the location and size of where this firmware image -## (coreboot plus bootloader) will live in the boot rom chip. -## -if USE_FAILOVER_IMAGE - default ROM_SECTION_SIZE = FAILOVER_SIZE - default ROM_SECTION_OFFSET = ( ROM_SIZE - FAILOVER_SIZE ) -else - if USE_FALLBACK_IMAGE - default ROM_SECTION_SIZE = FALLBACK_SIZE - default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE - FAILOVER_SIZE ) - else - default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE - FAILOVER_SIZE ) - default ROM_SECTION_OFFSET = 0 - end -end +include /failovercalculation.lb -## -## Compute the start location and size size of -## The coreboot bootloader. -## -default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE ) -default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) - -## -## Compute where this copy of coreboot will start in the boot rom -## -default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE ) - -## -## Compute a range of ROM that can cached to speed up coreboot, -## execution speed. -## -## XIP_ROM_SIZE must be a power of 2. -## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE -## -default XIP_ROM_SIZE=65536 - -if USE_FAILOVER_IMAGE - default XIP_ROM_BASE = ( _ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE) -else - if USE_FALLBACK_IMAGE - default XIP_ROM_BASE = ( _ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE + FAILOVER_SIZE) - else - default XIP_ROM_BASE = ( _ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE) - end -end - arch i386 end ## Index: LinuxBIOSv2-Configlb_refactor/src/mainboard/tyan/s2895/Config.lb =================================================================== --- LinuxBIOSv2-Configlb_refactor/src/mainboard/tyan/s2895/Config.lb (Revision 4131) +++ LinuxBIOSv2-Configlb_refactor/src/mainboard/tyan/s2895/Config.lb (Arbeitskopie) @@ -1,51 +1,5 @@ -## -## Compute the location and size of where this firmware image -## (coreboot plus bootloader) will live in the boot rom chip. -## -if USE_FAILOVER_IMAGE - default ROM_SECTION_SIZE = FAILOVER_SIZE - default ROM_SECTION_OFFSET = ( ROM_SIZE - FAILOVER_SIZE ) -else - if USE_FALLBACK_IMAGE - default ROM_SECTION_SIZE = FALLBACK_SIZE - default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE - FAILOVER_SIZE ) - else - default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE - FAILOVER_SIZE ) - default ROM_SECTION_OFFSET = 0 - end -end +include /failovercalculation.lb -## -## Compute the start location and size size of -## The coreboot bootloader. -## -default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE ) -default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) - -## -## Compute where this copy of coreboot will start in the boot rom -## -default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE ) - -## -## Compute a range of ROM that can cached to speed up coreboot, -## execution speed. -## -## XIP_ROM_SIZE must be a power of 2. -## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE -## -default XIP_ROM_SIZE=65536 - -if USE_FAILOVER_IMAGE - default XIP_ROM_BASE = ( _ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE) -else - if USE_FALLBACK_IMAGE - default XIP_ROM_BASE = ( _ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE + FAILOVER_SIZE) - else - default XIP_ROM_BASE = ( _ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE) - end -end - arch i386 end ## Index: LinuxBIOSv2-Configlb_refactor/src/mainboard/tyan/s2912_fam10/Config.lb =================================================================== --- LinuxBIOSv2-Configlb_refactor/src/mainboard/tyan/s2912_fam10/Config.lb (Revision 4131) +++ LinuxBIOSv2-Configlb_refactor/src/mainboard/tyan/s2912_fam10/Config.lb (Arbeitskopie) @@ -19,54 +19,8 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -## -## Compute the location and size of where this firmware image -## (coreboot plus bootloader) will live in the boot rom chip. -## -if USE_FAILOVER_IMAGE - default ROM_SECTION_SIZE = FAILOVER_SIZE - default ROM_SECTION_OFFSET = ( ROM_SIZE - FAILOVER_SIZE ) -else - if USE_FALLBACK_IMAGE - default ROM_SECTION_SIZE = FALLBACK_SIZE - default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE - FAILOVER_SIZE ) - else - default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE - FAILOVER_SIZE ) - default ROM_SECTION_OFFSET = 0 - end -end +include /failovercalculation.lb -## -## Compute the start location and size size of -## The coreboot bootloader. -## -default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE ) -default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) - -## -## Compute where this copy of coreboot will start in the boot rom -## -default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE ) - -## -## Compute a range of ROM that can cached to speed up coreboot, -## execution speed. -## -## XIP_ROM_SIZE must be a power of 2. -## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE -## -default XIP_ROM_SIZE=65536 - -if USE_FAILOVER_IMAGE - default XIP_ROM_BASE = ( _ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE) -else - if USE_FALLBACK_IMAGE - default XIP_ROM_BASE = ( _ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE + FAILOVER_SIZE) - else - default XIP_ROM_BASE = ( _ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE) - end -end - arch i386 end ## Index: LinuxBIOSv2-Configlb_refactor/src/mainboard/msi/ms7135/Config.lb =================================================================== --- LinuxBIOSv2-Configlb_refactor/src/mainboard/msi/ms7135/Config.lb (Revision 4131) +++ LinuxBIOSv2-Configlb_refactor/src/mainboard/msi/ms7135/Config.lb (Arbeitskopie) @@ -22,53 +22,8 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -## -## Compute the location and size of where this firmware image -## (coreboot plus bootloader) will live in the boot rom chip. -## -if USE_FAILOVER_IMAGE - default ROM_SECTION_SIZE = FAILOVER_SIZE - default ROM_SECTION_OFFSET = (ROM_SIZE - FAILOVER_SIZE) -else - if USE_FALLBACK_IMAGE - default ROM_SECTION_SIZE = FALLBACK_SIZE - default ROM_SECTION_OFFSET = (ROM_SIZE - FALLBACK_SIZE - FAILOVER_SIZE) - else - default ROM_SECTION_SIZE = (ROM_SIZE - FALLBACK_SIZE - FAILOVER_SIZE) - default ROM_SECTION_OFFSET = 0 - end -end +include /failovercalculation.lb -## -## Compute the start location and size size of the coreboot bootloader. -## -default PAYLOAD_SIZE = (ROM_SECTION_SIZE - ROM_IMAGE_SIZE) -default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) - -## -## Compute where this copy of coreboot will start in the boot ROM. -## -default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE ) - -## -## Compute a range of ROM that can be cached to speed up coreboot -## execution speed. -## -## XIP_ROM_SIZE must be a power of 2 (here 64 Kbyte) -## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE -## -default XIP_ROM_SIZE = (64 * 1024) - -if USE_FAILOVER_IMAGE - default XIP_ROM_BASE = (_ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE) -else - if USE_FALLBACK_IMAGE - default XIP_ROM_BASE = (_ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE + FAILOVER_SIZE) - else - default XIP_ROM_BASE = (_ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE) - end -end - arch i386 end ## Index: LinuxBIOSv2-Configlb_refactor/src/mainboard/msi/ms7260/Config.lb =================================================================== --- LinuxBIOSv2-Configlb_refactor/src/mainboard/msi/ms7260/Config.lb (Revision 4131) +++ LinuxBIOSv2-Configlb_refactor/src/mainboard/msi/ms7260/Config.lb (Arbeitskopie) @@ -18,34 +18,8 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -if USE_FAILOVER_IMAGE - default ROM_SECTION_SIZE = FAILOVER_SIZE - default ROM_SECTION_OFFSET = (ROM_SIZE - FAILOVER_SIZE) -else - if USE_FALLBACK_IMAGE - default ROM_SECTION_SIZE = FALLBACK_SIZE - default ROM_SECTION_OFFSET = (ROM_SIZE - FALLBACK_SIZE - FAILOVER_SIZE) - else - default ROM_SECTION_SIZE = (ROM_SIZE - FALLBACK_SIZE - FAILOVER_SIZE) - default ROM_SECTION_OFFSET = 0 - end -end +include /failovercalculation.lb -default PAYLOAD_SIZE = (ROM_SECTION_SIZE - ROM_IMAGE_SIZE) -default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) -default _ROMBASE = (CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE) -default XIP_ROM_SIZE = 65536 - -if USE_FAILOVER_IMAGE - default XIP_ROM_BASE = (_ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE) -else - if USE_FALLBACK_IMAGE - default XIP_ROM_BASE = (_ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE + FAILOVER_SIZE) - else - default XIP_ROM_BASE = (_ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE) - end -end - arch i386 end driver mainboard.o Index: LinuxBIOSv2-Configlb_refactor/src/mainboard/nvidia/l1_2pvv/Config.lb =================================================================== --- LinuxBIOSv2-Configlb_refactor/src/mainboard/nvidia/l1_2pvv/Config.lb (Revision 4131) +++ LinuxBIOSv2-Configlb_refactor/src/mainboard/nvidia/l1_2pvv/Config.lb (Arbeitskopie) @@ -19,54 +19,8 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -## -## Compute the location and size of where this firmware image -## (coreboot plus bootloader) will live in the boot rom chip. -## -if USE_FAILOVER_IMAGE - default ROM_SECTION_SIZE = FAILOVER_SIZE - default ROM_SECTION_OFFSET = ( ROM_SIZE - FAILOVER_SIZE ) -else - if USE_FALLBACK_IMAGE - default ROM_SECTION_SIZE = FALLBACK_SIZE - default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE - FAILOVER_SIZE ) - else - default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE - FAILOVER_SIZE ) - default ROM_SECTION_OFFSET = 0 - end -end +include /failovercalculation.lb -## -## Compute the start location and size size of -## The coreboot bootloader. -## -default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE ) -default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) - -## -## Compute where this copy of coreboot will start in the boot rom -## -default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE ) - -## -## Compute a range of ROM that can cached to speed up coreboot, -## execution speed. -## -## XIP_ROM_SIZE must be a power of 2. -## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE -## -default XIP_ROM_SIZE=65536 - -if USE_FAILOVER_IMAGE - default XIP_ROM_BASE = ( _ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE) -else - if USE_FALLBACK_IMAGE - default XIP_ROM_BASE = ( _ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE + FAILOVER_SIZE) - else - default XIP_ROM_BASE = ( _ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE) - end -end - arch i386 end ## Index: LinuxBIOSv2-Configlb_refactor/src/mainboard/asus/a8n_e/Config.lb =================================================================== --- LinuxBIOSv2-Configlb_refactor/src/mainboard/asus/a8n_e/Config.lb (Revision 4131) +++ LinuxBIOSv2-Configlb_refactor/src/mainboard/asus/a8n_e/Config.lb (Arbeitskopie) @@ -21,33 +21,8 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -if USE_FAILOVER_IMAGE - default ROM_SECTION_SIZE = FAILOVER_SIZE - default ROM_SECTION_OFFSET = (ROM_SIZE - FAILOVER_SIZE) -else - if USE_FALLBACK_IMAGE - default ROM_SECTION_SIZE = FALLBACK_SIZE - default ROM_SECTION_OFFSET = (ROM_SIZE - FALLBACK_SIZE - FAILOVER_SIZE) - else - default ROM_SECTION_SIZE = (ROM_SIZE - FALLBACK_SIZE - FAILOVER_SIZE) - default ROM_SECTION_OFFSET = 0 - end -end -default PAYLOAD_SIZE = (ROM_SECTION_SIZE - ROM_IMAGE_SIZE) -default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) -default _ROMBASE = (CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE) -# XIP_ROM_SIZE must be a power of 2. -# XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE. -default XIP_ROM_SIZE = 64 * 1024 -if USE_FAILOVER_IMAGE - default XIP_ROM_BASE = (_ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE) -else - if USE_FALLBACK_IMAGE - default XIP_ROM_BASE = (_ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE + FAILOVER_SIZE) - else - default XIP_ROM_BASE = (_ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE) - end -end +include /failovercalculation.lb + arch i386 end driver mainboard.o # Needed by irq_tables and mptable and acpi_tables. -- http://www.hailfinger.org/ Index: LinuxBIOSv2-Configlb_refactor/src/failovercalculation.lb =================================================================== --- LinuxBIOSv2-Configlb_refactor/src/failovercalculation.lb (Revision 0) +++ LinuxBIOSv2-Configlb_refactor/src/failovercalculation.lb (Revision 0) @@ -0,0 +1,47 @@ +## +## Compute the location and size of where this firmware image +## (coreboot plus bootloader) will live in the boot rom chip. +## +if USE_FAILOVER_IMAGE + default ROM_SECTION_SIZE = FAILOVER_SIZE + default ROM_SECTION_OFFSET = ( ROM_SIZE - FAILOVER_SIZE ) +else + if USE_FALLBACK_IMAGE + default ROM_SECTION_SIZE = FALLBACK_SIZE + default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE - FAILOVER_SIZE ) + else + default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE - FAILOVER_SIZE ) + default ROM_SECTION_OFFSET = 0 + end +end +## +## Compute the start location and size size of +## The coreboot bootloader. +## +default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE ) +default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) + +## +## Compute where this copy of coreboot will start in the boot rom +## +default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE ) + +## +## Compute a range of ROM that can cached to speed up coreboot, +## execution speed. +## +## XIP_ROM_SIZE must be a power of 2. +## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE +## +default XIP_ROM_SIZE = (64 * 1024) + +if USE_FAILOVER_IMAGE + default XIP_ROM_BASE = ( _ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE) +else + if USE_FALLBACK_IMAGE + default XIP_ROM_BASE = ( _ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE + FAILOVER_SIZE) + else + default XIP_ROM_BASE = ( _ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE) + end +end + Index: LinuxBIOSv2-Configlb_refactor/src/mainboard/iwill/dk8_htx/Config.lb =================================================================== --- LinuxBIOSv2-Configlb_refactor/src/mainboard/iwill/dk8_htx/Config.lb (Revision 4131) +++ LinuxBIOSv2-Configlb_refactor/src/mainboard/iwill/dk8_htx/Config.lb (Arbeitskopie) @@ -1,51 +1,5 @@ -## -## Compute the location and size of where this firmware image -## (coreboot plus bootloader) will live in the boot rom chip. -## -if USE_FAILOVER_IMAGE - default ROM_SECTION_SIZE = FAILOVER_SIZE - default ROM_SECTION_OFFSET = ( ROM_SIZE - FAILOVER_SIZE ) -else - if USE_FALLBACK_IMAGE - default ROM_SECTION_SIZE = FALLBACK_SIZE - default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE - FAILOVER_SIZE ) - else - default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE - FAILOVER_SIZE ) - default ROM_SECTION_OFFSET = 0 - end -end +include /failovercalculation.lb -## -## Compute the start location and size size of -## The coreboot bootloader. -## -default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE ) -default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) - -## -## Compute where this copy of coreboot will start in the boot rom -## -default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE ) - -## -## Compute a range of ROM that can cached to speed up coreboot, -## execution speed. -## -## XIP_ROM_SIZE must be a power of 2. -## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE -## -default XIP_ROM_SIZE=65536 - -if USE_FAILOVER_IMAGE - default XIP_ROM_BASE = ( _ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE) -else - if USE_FALLBACK_IMAGE - default XIP_ROM_BASE = ( _ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE + FAILOVER_SIZE) - else - default XIP_ROM_BASE = ( _ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE) - end -end - arch i386 end ## Index: LinuxBIOSv2-Configlb_refactor/src/mainboard/supermicro/h8dmr/Config.lb =================================================================== --- LinuxBIOSv2-Configlb_refactor/src/mainboard/supermicro/h8dmr/Config.lb (Revision 4131) +++ LinuxBIOSv2-Configlb_refactor/src/mainboard/supermicro/h8dmr/Config.lb (Arbeitskopie) @@ -19,54 +19,8 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -## -## Compute the location and size of where this firmware image -## (coreboot plus bootloader) will live in the boot rom chip. -## -if USE_FAILOVER_IMAGE - default ROM_SECTION_SIZE = FAILOVER_SIZE - default ROM_SECTION_OFFSET = ( ROM_SIZE - FAILOVER_SIZE ) -else - if USE_FALLBACK_IMAGE - default ROM_SECTION_SIZE = FALLBACK_SIZE - default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE - FAILOVER_SIZE ) - else - default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE - FAILOVER_SIZE ) - default ROM_SECTION_OFFSET = 0 - end -end +include /failovercalculation.lb -## -## Compute the start location and size size of -## The coreboot bootloader. -## -default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE ) -default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) - -## -## Compute where this copy of coreboot will start in the boot rom -## -default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE ) - -## -## Compute a range of ROM that can cached to speed up coreboot, -## execution speed. -## -## XIP_ROM_SIZE must be a power of 2. -## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE -## -default XIP_ROM_SIZE=65536 - -if USE_FAILOVER_IMAGE - default XIP_ROM_BASE = ( _ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE) -else - if USE_FALLBACK_IMAGE - default XIP_ROM_BASE = ( _ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE + FAILOVER_SIZE) - else - default XIP_ROM_BASE = ( _ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE) - end -end - arch i386 end ## Index: LinuxBIOSv2-Configlb_refactor/src/mainboard/supermicro/h8dme/Config.lb =================================================================== --- LinuxBIOSv2-Configlb_refactor/src/mainboard/supermicro/h8dme/Config.lb (Revision 4131) +++ LinuxBIOSv2-Configlb_refactor/src/mainboard/supermicro/h8dme/Config.lb (Arbeitskopie) @@ -16,54 +16,8 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -## -## Compute the location and size of where this firmware image -## (coreboot plus bootloader) will live in the boot rom chip. -## -if USE_FAILOVER_IMAGE - default ROM_SECTION_SIZE = FAILOVER_SIZE - default ROM_SECTION_OFFSET = ( ROM_SIZE - FAILOVER_SIZE ) -else - if USE_FALLBACK_IMAGE - default ROM_SECTION_SIZE = FALLBACK_SIZE - default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE - FAILOVER_SIZE ) - else - default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE - FAILOVER_SIZE ) - default ROM_SECTION_OFFSET = 0 - end -end +include /failovercalculation.lb -## -## Compute the start location and size size of -## The coreboot bootloader. -## -default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE ) -default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) - -## -## Compute where this copy of coreboot will start in the boot rom -## -default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE ) - -## -## Compute a range of ROM that can cached to speed up coreboot, -## execution speed. -## -## XIP_ROM_SIZE must be a power of 2. -## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE -## -default XIP_ROM_SIZE=65536 - -if USE_FAILOVER_IMAGE - default XIP_ROM_BASE = ( _ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE) -else - if USE_FALLBACK_IMAGE - default XIP_ROM_BASE = ( _ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE + FAILOVER_SIZE) - else - default XIP_ROM_BASE = ( _ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE) - end -end - arch i386 end ## Index: LinuxBIOSv2-Configlb_refactor/src/mainboard/gigabyte/m57sli/Config.lb =================================================================== --- LinuxBIOSv2-Configlb_refactor/src/mainboard/gigabyte/m57sli/Config.lb (Revision 4131) +++ LinuxBIOSv2-Configlb_refactor/src/mainboard/gigabyte/m57sli/Config.lb (Arbeitskopie) @@ -19,54 +19,8 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -## -## Compute the location and size of where this firmware image -## (coreboot plus bootloader) will live in the boot rom chip. -## -if USE_FAILOVER_IMAGE - default ROM_SECTION_SIZE = FAILOVER_SIZE - default ROM_SECTION_OFFSET = ( ROM_SIZE - FAILOVER_SIZE ) -else - if USE_FALLBACK_IMAGE - default ROM_SECTION_SIZE = FALLBACK_SIZE - default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE - FAILOVER_SIZE ) - else - default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE - FAILOVER_SIZE ) - default ROM_SECTION_OFFSET = 0 - end -end +include /failovercalculation.lb -## -## Compute the start location and size size of -## The coreboot bootloader. -## -default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE ) -default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) - -## -## Compute where this copy of coreboot will start in the boot rom -## -default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE ) - -## -## Compute a range of ROM that can cached to speed up coreboot, -## execution speed. -## -## XIP_ROM_SIZE must be a power of 2. -## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE -## -default XIP_ROM_SIZE=65536 - -if USE_FAILOVER_IMAGE - default XIP_ROM_BASE = ( _ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE) -else - if USE_FALLBACK_IMAGE - default XIP_ROM_BASE = ( _ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE + FAILOVER_SIZE) - else - default XIP_ROM_BASE = ( _ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE) - end -end - arch i386 end ## Index: LinuxBIOSv2-Configlb_refactor/src/mainboard/gigabyte/ga_2761gxdk/Config.lb =================================================================== --- LinuxBIOSv2-Configlb_refactor/src/mainboard/gigabyte/ga_2761gxdk/Config.lb (Revision 4131) +++ LinuxBIOSv2-Configlb_refactor/src/mainboard/gigabyte/ga_2761gxdk/Config.lb (Arbeitskopie) @@ -21,54 +21,8 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -## -## Compute the location and size of where this firmware image -## (coreboot plus bootloader) will live in the boot rom chip. -## -if USE_FAILOVER_IMAGE - default ROM_SECTION_SIZE = FAILOVER_SIZE - default ROM_SECTION_OFFSET = ( ROM_SIZE - FAILOVER_SIZE ) -else - if USE_FALLBACK_IMAGE - default ROM_SECTION_SIZE = FALLBACK_SIZE - default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE - FAILOVER_SIZE ) - else - default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE - FAILOVER_SIZE ) - default ROM_SECTION_OFFSET = 0 - end -end +include /failovercalculation.lb -## -## Compute the start location and size size of -## The coreboot bootloader. -## -default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE ) -default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) - -## -## Compute where this copy of coreboot will start in the boot rom -## -default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE ) - -## -## Compute a range of ROM that can cached to speed up coreboot, -## execution speed. -## -## XIP_ROM_SIZE must be a power of 2. -## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE -## -default XIP_ROM_SIZE=65536 - -if USE_FAILOVER_IMAGE - default XIP_ROM_BASE = ( _ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE) -else - if USE_FALLBACK_IMAGE - default XIP_ROM_BASE = ( _ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE + FAILOVER_SIZE) - else - default XIP_ROM_BASE = ( _ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE) - end -end - arch i386 end ## Index: LinuxBIOSv2-Configlb_refactor/src/mainboard/amd/serengeti_cheetah/Config.lb =================================================================== --- LinuxBIOSv2-Configlb_refactor/src/mainboard/amd/serengeti_cheetah/Config.lb (Revision 4131) +++ LinuxBIOSv2-Configlb_refactor/src/mainboard/amd/serengeti_cheetah/Config.lb (Arbeitskopie) @@ -1,51 +1,5 @@ -## -## Compute the location and size of where this firmware image -## (coreboot plus bootloader) will live in the boot rom chip. -## -if USE_FAILOVER_IMAGE - default ROM_SECTION_SIZE = FAILOVER_SIZE - default ROM_SECTION_OFFSET = ( ROM_SIZE - FAILOVER_SIZE ) -else - if USE_FALLBACK_IMAGE - default ROM_SECTION_SIZE = FALLBACK_SIZE - default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE - FAILOVER_SIZE ) - else - default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE - FAILOVER_SIZE ) - default ROM_SECTION_OFFSET = 0 - end -end +include /failovercalculation.lb -## -## Compute the start location and size size of -## The coreboot bootloader. -## -default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE ) -default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) - -## -## Compute where this copy of coreboot will start in the boot rom -## -default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE ) - -## -## Compute a range of ROM that can cached to speed up coreboot, -## execution speed. -## -## XIP_ROM_SIZE must be a power of 2. -## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE -## -default XIP_ROM_SIZE=65536 - -if USE_FAILOVER_IMAGE - default XIP_ROM_BASE = ( _ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE) -else - if USE_FALLBACK_IMAGE - default XIP_ROM_BASE = ( _ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE + FAILOVER_SIZE) - else - default XIP_ROM_BASE = ( _ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE) - end -end - arch i386 end ## Index: LinuxBIOSv2-Configlb_refactor/src/mainboard/amd/serengeti_cheetah_fam10/Config.lb =================================================================== --- LinuxBIOSv2-Configlb_refactor/src/mainboard/amd/serengeti_cheetah_fam10/Config.lb (Revision 4131) +++ LinuxBIOSv2-Configlb_refactor/src/mainboard/amd/serengeti_cheetah_fam10/Config.lb (Arbeitskopie) @@ -17,54 +17,8 @@ # Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA # -## -## Compute the location and size of where this firmware image -## (coreboot plus bootloader) will live in the boot rom chip. -## -if USE_FAILOVER_IMAGE - default ROM_SECTION_SIZE = FAILOVER_SIZE - default ROM_SECTION_OFFSET = ( ROM_SIZE - FAILOVER_SIZE ) -else - if USE_FALLBACK_IMAGE - default ROM_SECTION_SIZE = FALLBACK_SIZE - default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE - FAILOVER_SIZE ) - else - default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE - FAILOVER_SIZE ) - default ROM_SECTION_OFFSET = 0 - end -end +include /failovercalculation.lb -## -## Compute the start location and size size of -## The coreboot bootloader. -## -default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE ) -default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) - -## -## Compute where this copy of coreboot will start in the boot rom -## -default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE ) - -## -## Compute a range of ROM that can cached to speed up coreboot, -## execution speed. -## -## XIP_ROM_SIZE must be a power of 2. -## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE -## -default XIP_ROM_SIZE=65536 -# -if USE_FAILOVER_IMAGE - default XIP_ROM_BASE = ( _ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE) -else - if USE_FALLBACK_IMAGE - default XIP_ROM_BASE = ( _ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE + FAILOVER_SIZE) - else - default XIP_ROM_BASE = ( _ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE) - end -end - arch i386 end ## Index: LinuxBIOSv2-Configlb_refactor/src/mainboard/tyan/s2912/Config.lb =================================================================== --- LinuxBIOSv2-Configlb_refactor/src/mainboard/tyan/s2912/Config.lb (Revision 4131) +++ LinuxBIOSv2-Configlb_refactor/src/mainboard/tyan/s2912/Config.lb (Arbeitskopie) @@ -19,54 +19,8 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -## -## Compute the location and size of where this firmware image -## (coreboot plus bootloader) will live in the boot rom chip. -## -if USE_FAILOVER_IMAGE - default ROM_SECTION_SIZE = FAILOVER_SIZE - default ROM_SECTION_OFFSET = ( ROM_SIZE - FAILOVER_SIZE ) -else - if USE_FALLBACK_IMAGE - default ROM_SECTION_SIZE = FALLBACK_SIZE - default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE - FAILOVER_SIZE ) - else - default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE - FAILOVER_SIZE ) - default ROM_SECTION_OFFSET = 0 - end -end +include /failovercalculation.lb -## -## Compute the start location and size size of -## The coreboot bootloader. -## -default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE ) -default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) - -## -## Compute where this copy of coreboot will start in the boot rom -## -default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE ) - -## -## Compute a range of ROM that can cached to speed up coreboot, -## execution speed. -## -## XIP_ROM_SIZE must be a power of 2. -## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE -## -default XIP_ROM_SIZE=65536 - -if USE_FAILOVER_IMAGE - default XIP_ROM_BASE = ( _ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE) -else - if USE_FALLBACK_IMAGE - default XIP_ROM_BASE = ( _ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE + FAILOVER_SIZE) - else - default XIP_ROM_BASE = ( _ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE) - end -end - arch i386 end ## Index: LinuxBIOSv2-Configlb_refactor/src/mainboard/tyan/s2895/Config.lb =================================================================== --- LinuxBIOSv2-Configlb_refactor/src/mainboard/tyan/s2895/Config.lb (Revision 4131) +++ LinuxBIOSv2-Configlb_refactor/src/mainboard/tyan/s2895/Config.lb (Arbeitskopie) @@ -1,51 +1,5 @@ -## -## Compute the location and size of where this firmware image -## (coreboot plus bootloader) will live in the boot rom chip. -## -if USE_FAILOVER_IMAGE - default ROM_SECTION_SIZE = FAILOVER_SIZE - default ROM_SECTION_OFFSET = ( ROM_SIZE - FAILOVER_SIZE ) -else - if USE_FALLBACK_IMAGE - default ROM_SECTION_SIZE = FALLBACK_SIZE - default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE - FAILOVER_SIZE ) - else - default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE - FAILOVER_SIZE ) - default ROM_SECTION_OFFSET = 0 - end -end +include /failovercalculation.lb -## -## Compute the start location and size size of -## The coreboot bootloader. -## -default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE ) -default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) - -## -## Compute where this copy of coreboot will start in the boot rom -## -default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE ) - -## -## Compute a range of ROM that can cached to speed up coreboot, -## execution speed. -## -## XIP_ROM_SIZE must be a power of 2. -## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE -## -default XIP_ROM_SIZE=65536 - -if USE_FAILOVER_IMAGE - default XIP_ROM_BASE = ( _ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE) -else - if USE_FALLBACK_IMAGE - default XIP_ROM_BASE = ( _ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE + FAILOVER_SIZE) - else - default XIP_ROM_BASE = ( _ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE) - end -end - arch i386 end ## Index: LinuxBIOSv2-Configlb_refactor/src/mainboard/tyan/s2912_fam10/Config.lb =================================================================== --- LinuxBIOSv2-Configlb_refactor/src/mainboard/tyan/s2912_fam10/Config.lb (Revision 4131) +++ LinuxBIOSv2-Configlb_refactor/src/mainboard/tyan/s2912_fam10/Config.lb (Arbeitskopie) @@ -19,54 +19,8 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -## -## Compute the location and size of where this firmware image -## (coreboot plus bootloader) will live in the boot rom chip. -## -if USE_FAILOVER_IMAGE - default ROM_SECTION_SIZE = FAILOVER_SIZE - default ROM_SECTION_OFFSET = ( ROM_SIZE - FAILOVER_SIZE ) -else - if USE_FALLBACK_IMAGE - default ROM_SECTION_SIZE = FALLBACK_SIZE - default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE - FAILOVER_SIZE ) - else - default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE - FAILOVER_SIZE ) - default ROM_SECTION_OFFSET = 0 - end -end +include /failovercalculation.lb -## -## Compute the start location and size size of -## The coreboot bootloader. -## -default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE ) -default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) - -## -## Compute where this copy of coreboot will start in the boot rom -## -default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE ) - -## -## Compute a range of ROM that can cached to speed up coreboot, -## execution speed. -## -## XIP_ROM_SIZE must be a power of 2. -## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE -## -default XIP_ROM_SIZE=65536 - -if USE_FAILOVER_IMAGE - default XIP_ROM_BASE = ( _ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE) -else - if USE_FALLBACK_IMAGE - default XIP_ROM_BASE = ( _ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE + FAILOVER_SIZE) - else - default XIP_ROM_BASE = ( _ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE) - end -end - arch i386 end ## Index: LinuxBIOSv2-Configlb_refactor/src/mainboard/msi/ms7135/Config.lb =================================================================== --- LinuxBIOSv2-Configlb_refactor/src/mainboard/msi/ms7135/Config.lb (Revision 4131) +++ LinuxBIOSv2-Configlb_refactor/src/mainboard/msi/ms7135/Config.lb (Arbeitskopie) @@ -22,53 +22,8 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -## -## Compute the location and size of where this firmware image -## (coreboot plus bootloader) will live in the boot rom chip. -## -if USE_FAILOVER_IMAGE - default ROM_SECTION_SIZE = FAILOVER_SIZE - default ROM_SECTION_OFFSET = (ROM_SIZE - FAILOVER_SIZE) -else - if USE_FALLBACK_IMAGE - default ROM_SECTION_SIZE = FALLBACK_SIZE - default ROM_SECTION_OFFSET = (ROM_SIZE - FALLBACK_SIZE - FAILOVER_SIZE) - else - default ROM_SECTION_SIZE = (ROM_SIZE - FALLBACK_SIZE - FAILOVER_SIZE) - default ROM_SECTION_OFFSET = 0 - end -end +include /failovercalculation.lb -## -## Compute the start location and size size of the coreboot bootloader. -## -default PAYLOAD_SIZE = (ROM_SECTION_SIZE - ROM_IMAGE_SIZE) -default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) - -## -## Compute where this copy of coreboot will start in the boot ROM. -## -default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE ) - -## -## Compute a range of ROM that can be cached to speed up coreboot -## execution speed. -## -## XIP_ROM_SIZE must be a power of 2 (here 64 Kbyte) -## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE -## -default XIP_ROM_SIZE = (64 * 1024) - -if USE_FAILOVER_IMAGE - default XIP_ROM_BASE = (_ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE) -else - if USE_FALLBACK_IMAGE - default XIP_ROM_BASE = (_ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE + FAILOVER_SIZE) - else - default XIP_ROM_BASE = (_ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE) - end -end - arch i386 end ## Index: LinuxBIOSv2-Configlb_refactor/src/mainboard/msi/ms7260/Config.lb =================================================================== --- LinuxBIOSv2-Configlb_refactor/src/mainboard/msi/ms7260/Config.lb (Revision 4131) +++ LinuxBIOSv2-Configlb_refactor/src/mainboard/msi/ms7260/Config.lb (Arbeitskopie) @@ -18,34 +18,8 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -if USE_FAILOVER_IMAGE - default ROM_SECTION_SIZE = FAILOVER_SIZE - default ROM_SECTION_OFFSET = (ROM_SIZE - FAILOVER_SIZE) -else - if USE_FALLBACK_IMAGE - default ROM_SECTION_SIZE = FALLBACK_SIZE - default ROM_SECTION_OFFSET = (ROM_SIZE - FALLBACK_SIZE - FAILOVER_SIZE) - else - default ROM_SECTION_SIZE = (ROM_SIZE - FALLBACK_SIZE - FAILOVER_SIZE) - default ROM_SECTION_OFFSET = 0 - end -end +include /failovercalculation.lb -default PAYLOAD_SIZE = (ROM_SECTION_SIZE - ROM_IMAGE_SIZE) -default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) -default _ROMBASE = (CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE) -default XIP_ROM_SIZE = 65536 - -if USE_FAILOVER_IMAGE - default XIP_ROM_BASE = (_ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE) -else - if USE_FALLBACK_IMAGE - default XIP_ROM_BASE = (_ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE + FAILOVER_SIZE) - else - default XIP_ROM_BASE = (_ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE) - end -end - arch i386 end driver mainboard.o Index: LinuxBIOSv2-Configlb_refactor/src/mainboard/nvidia/l1_2pvv/Config.lb =================================================================== --- LinuxBIOSv2-Configlb_refactor/src/mainboard/nvidia/l1_2pvv/Config.lb (Revision 4131) +++ LinuxBIOSv2-Configlb_refactor/src/mainboard/nvidia/l1_2pvv/Config.lb (Arbeitskopie) @@ -19,54 +19,8 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -## -## Compute the location and size of where this firmware image -## (coreboot plus bootloader) will live in the boot rom chip. -## -if USE_FAILOVER_IMAGE - default ROM_SECTION_SIZE = FAILOVER_SIZE - default ROM_SECTION_OFFSET = ( ROM_SIZE - FAILOVER_SIZE ) -else - if USE_FALLBACK_IMAGE - default ROM_SECTION_SIZE = FALLBACK_SIZE - default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE - FAILOVER_SIZE ) - else - default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE - FAILOVER_SIZE ) - default ROM_SECTION_OFFSET = 0 - end -end +include /failovercalculation.lb -## -## Compute the start location and size size of -## The coreboot bootloader. -## -default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE ) -default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) - -## -## Compute where this copy of coreboot will start in the boot rom -## -default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE ) - -## -## Compute a range of ROM that can cached to speed up coreboot, -## execution speed. -## -## XIP_ROM_SIZE must be a power of 2. -## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE -## -default XIP_ROM_SIZE=65536 - -if USE_FAILOVER_IMAGE - default XIP_ROM_BASE = ( _ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE) -else - if USE_FALLBACK_IMAGE - default XIP_ROM_BASE = ( _ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE + FAILOVER_SIZE) - else - default XIP_ROM_BASE = ( _ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE) - end -end - arch i386 end ## Index: LinuxBIOSv2-Configlb_refactor/src/mainboard/asus/a8n_e/Config.lb =================================================================== --- LinuxBIOSv2-Configlb_refactor/src/mainboard/asus/a8n_e/Config.lb (Revision 4131) +++ LinuxBIOSv2-Configlb_refactor/src/mainboard/asus/a8n_e/Config.lb (Arbeitskopie) @@ -21,33 +21,8 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -if USE_FAILOVER_IMAGE - default ROM_SECTION_SIZE = FAILOVER_SIZE - default ROM_SECTION_OFFSET = (ROM_SIZE - FAILOVER_SIZE) -else - if USE_FALLBACK_IMAGE - default ROM_SECTION_SIZE = FALLBACK_SIZE - default ROM_SECTION_OFFSET = (ROM_SIZE - FALLBACK_SIZE - FAILOVER_SIZE) - else - default ROM_SECTION_SIZE = (ROM_SIZE - FALLBACK_SIZE - FAILOVER_SIZE) - default ROM_SECTION_OFFSET = 0 - end -end -default PAYLOAD_SIZE = (ROM_SECTION_SIZE - ROM_IMAGE_SIZE) -default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) -default _ROMBASE = (CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE) -# XIP_ROM_SIZE must be a power of 2. -# XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE. -default XIP_ROM_SIZE = 64 * 1024 -if USE_FAILOVER_IMAGE - default XIP_ROM_BASE = (_ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE) -else - if USE_FALLBACK_IMAGE - default XIP_ROM_BASE = (_ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE + FAILOVER_SIZE) - else - default XIP_ROM_BASE = (_ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE) - end -end +include /failovercalculation.lb + arch i386 end driver mainboard.o # Needed by irq_tables and mptable and acpi_tables.

6 29

[v2] r4187 - in trunk/coreboot-v2: src/config util/newconfig
by svn＠coreboot.org 22 Apr '09

22 Apr '09

Author: myles Date: 2009-04-23 00:25:45 +0200 (Thu, 23 Apr 2009) New Revision: 4187 Modified: trunk/coreboot-v2/src/config/nofailovercalculation.lb trunk/coreboot-v2/src/config/nofailovercalculation128.lb trunk/coreboot-v2/util/newconfig/config.g Log: This patch fixes the parser. '|' has special meaning so [|] is used. Signed-off-by: Myles Watson <mylesgw(a)gmail.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Modified: trunk/coreboot-v2/src/config/nofailovercalculation.lb =================================================================== --- trunk/coreboot-v2/src/config/nofailovercalculation.lb 2009-04-22 22:08:00 UTC (rev 4186) +++ trunk/coreboot-v2/src/config/nofailovercalculation.lb 2009-04-22 22:25:45 UTC (rev 4187) @@ -31,8 +31,3 @@ ## default XIP_ROM_SIZE = 64 * 1024 default XIP_ROM_BASE = ( _ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE ) - -## This is needed to work around a parser bug. -if USE_FALLBACK_IMAGE -end - Modified: trunk/coreboot-v2/src/config/nofailovercalculation128.lb =================================================================== --- trunk/coreboot-v2/src/config/nofailovercalculation128.lb 2009-04-22 22:08:00 UTC (rev 4186) +++ trunk/coreboot-v2/src/config/nofailovercalculation128.lb 2009-04-22 22:25:45 UTC (rev 4187) @@ -31,8 +31,3 @@ ## default XIP_ROM_SIZE = 128 * 1024 default XIP_ROM_BASE = ( _ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE ) - -## This is needed to work around a parser bug. -if USE_FALLBACK_IMAGE -end - Modified: trunk/coreboot-v2/util/newconfig/config.g =================================================================== --- trunk/coreboot-v2/util/newconfig/config.g 2009-04-22 22:08:00 UTC (rev 4186) +++ trunk/coreboot-v2/util/newconfig/config.g 2009-04-22 22:25:45 UTC (rev 4187) @@ -1709,7 +1709,7 @@ rule expr: logical {{ l = logical }} ( "&&" logical {{ l = l and logical }} - | "||" logical {{ l = l or logical }} + | "[|][|]" logical {{ l = l or logical }} )* {{ return l }} rule logical: factor {{ n = factor }}

1 0

build service results for r4185
by coreboot information 22 Apr '09

22 Apr '09

Dear coreboot readers! This is the automatic build system of coreboot. The developer "myles" checked in revision 4185 to the coreboot repository. This caused the following changes: Change Log: Trivial patch. I forgot to update K8_SET_FIDVID. Signed-off-by: Myles Watson <mylesgw(a)gmail.com> Acked-by: Myles Watson <mylesgw(a)gmail.com> Build Log: Compilation of hp:dl145_g3 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4185&device=dl145_g3&vendo… If something broke during this checkin please be a pain in myles's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

1 0

Re: [coreboot] [v2] r4186 - in trunk/coreboot-v2/src: config mainboard/arima/hdama mainboard/dell/s1850 mainboard/intel/jarrell mainboard/intel/mtarvon mainboard/intel/truxton mainboard/intel/xe7501devkit mainboard/kontron/986lcd-m mainboard/supermic
by Myles Watson 22 Apr '09

22 Apr '09

On Wed, Apr 22, 2009 at 4:08 PM, <svn(a)coreboot.org> wrote: > Author: hailfinger > Date: 2009-04-23 00:08:00 +0200 (Thu, 23 Apr 2009) > New Revision: 4186 > > Added: > trunk/coreboot-v2/src/config/nofailovercalculation128.lb > Modified: > trunk/coreboot-v2/src/mainboard/arima/hdama/Config.lb > trunk/coreboot-v2/src/mainboard/dell/s1850/Config.lb > trunk/coreboot-v2/src/mainboard/intel/jarrell/Config.lb > trunk/coreboot-v2/src/mainboard/intel/mtarvon/Config.lb > trunk/coreboot-v2/src/mainboard/intel/truxton/Config.lb > trunk/coreboot-v2/src/mainboard/intel/xe7501devkit/Config.lb > trunk/coreboot-v2/src/mainboard/kontron/986lcd-m/Config.lb > trunk/coreboot-v2/src/mainboard/supermicro/x6dai_g/Config.lb > trunk/coreboot-v2/src/mainboard/supermicro/x6dhe_g/Config.lb > trunk/coreboot-v2/src/mainboard/supermicro/x6dhe_g2/Config.lb > trunk/coreboot-v2/src/mainboard/supermicro/x6dhr_ig/Config.lb > trunk/coreboot-v2/src/mainboard/supermicro/x6dhr_ig2/Config.lb > Log: > Convert 12 more boards to use include statements in Config.lb. > > Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> > Acked-by: Peter Stuge <peter(a)stuge.se> > > > Added: trunk/coreboot-v2/src/config/nofailovercalculation128.lb > =================================================================== > --- trunk/coreboot-v2/src/config/nofailovercalculation128.lb (rev 0) > +++ trunk/coreboot-v2/src/config/nofailovercalculation128.lb 2009-04-22 22:08:00 UTC (rev 4186) > @@ -0,0 +1,38 @@ > +## > +## Compute the location and size of where this firmware image > +## (coreboot plus bootloader) will live in the boot rom chip. > +## ... > +## This is needed to work around a parser bug. > +if USE_FALLBACK_IMAGE > +end > + Have you tried the parser fix I sent? Myles

1 0

[PATCH] More Config.lb refactoring
by Carl-Daniel Hailfinger 22 Apr '09

22 Apr '09

Convert 12 more boards to use include statements. abuild tested. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: LinuxBIOSv2-Configlb_refactor/src/mainboard/supermicro/x6dai_g/Config.lb =================================================================== --- LinuxBIOSv2-Configlb_refactor/src/mainboard/supermicro/x6dai_g/Config.lb (Revision 4150) +++ LinuxBIOSv2-Configlb_refactor/src/mainboard/supermicro/x6dai_g/Config.lb (Arbeitskopie) @@ -3,41 +3,9 @@ ## default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE -## -## Compute the location and size of where this firmware image -## (coreboot plus bootloader) will live in the boot rom chip. -## -if USE_FALLBACK_IMAGE - default ROM_SECTION_SIZE = FALLBACK_SIZE - default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE ) -else - default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE ) - default ROM_SECTION_OFFSET = 0 -end +include /config/nofailovercalculation128.lb ## -## Compute the start location and size size of -## The coreboot bootloader. -## -default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE ) -default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) - -## -## Compute where this copy of coreboot will start in the boot rom -## -default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE ) - -## -## Compute a range of ROM that can be cached to speed up coreboot, -## execution speed. -## -## XIP_ROM_SIZE must be a power of 2. -## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE -## -default XIP_ROM_SIZE=131072 -default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE ) - -## ## Set all of the defaults for an x86 architecture ## Index: LinuxBIOSv2-Configlb_refactor/src/mainboard/supermicro/x6dhe_g/Config.lb =================================================================== --- LinuxBIOSv2-Configlb_refactor/src/mainboard/supermicro/x6dhe_g/Config.lb (Revision 4150) +++ LinuxBIOSv2-Configlb_refactor/src/mainboard/supermicro/x6dhe_g/Config.lb (Arbeitskopie) @@ -3,39 +3,8 @@ ## default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE -## -## Compute the location and size of where this firmware image -## (coreboot plus bootloader) will live in the boot rom chip. -## -if USE_FALLBACK_IMAGE - default ROM_SECTION_SIZE = FALLBACK_SIZE - default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE ) -else - default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE ) - default ROM_SECTION_OFFSET = 0 -end +include /config/nofailovercalculation128.lb -## -## Compute the start location and size size of -## The coreboot bootloader. -## -default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE ) -default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) - -## -## Compute where this copy of coreboot will start in the boot rom -## -default _ROMBASE =( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE ) - -## -## Compute a range of ROM that can be cached to speed up coreboot. -## execution speed. -## XIP_ROM_SIZE must be a power of 2. -## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE -default XIP_ROM_SIZE=131072 -default XIP_ROM_BASE= ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE ) - -## ## Set all of the defaults for an x86 architecture ## Index: LinuxBIOSv2-Configlb_refactor/src/mainboard/supermicro/x6dhe_g2/Config.lb =================================================================== --- LinuxBIOSv2-Configlb_refactor/src/mainboard/supermicro/x6dhe_g2/Config.lb (Revision 4150) +++ LinuxBIOSv2-Configlb_refactor/src/mainboard/supermicro/x6dhe_g2/Config.lb (Arbeitskopie) @@ -3,39 +3,8 @@ ## default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE -## -## Compute the location and size of where this firmware image -## (coreboot plus bootloader) will live in the boot rom chip. -## -if USE_FALLBACK_IMAGE - default ROM_SECTION_SIZE = FALLBACK_SIZE - default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE ) -else - default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE ) - default ROM_SECTION_OFFSET = 0 -end +include /config/nofailovercalculation128.lb -## -## Compute the start location and size size of -## The coreboot bootloader. -## -default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE ) -default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) - -## -## Compute where this copy of coreboot will start in the boot rom -## -default _ROMBASE =( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE ) - -## -## Compute a range of ROM that can be cached to speed up coreboot. -## execution speed. -## XIP_ROM_SIZE must be a power of 2. -## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE -default XIP_ROM_SIZE=131072 -default XIP_ROM_BASE= ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE ) - -## ## Set all of the defaults for an x86 architecture ## Index: LinuxBIOSv2-Configlb_refactor/src/mainboard/supermicro/x6dhr_ig/Config.lb =================================================================== --- LinuxBIOSv2-Configlb_refactor/src/mainboard/supermicro/x6dhr_ig/Config.lb (Revision 4150) +++ LinuxBIOSv2-Configlb_refactor/src/mainboard/supermicro/x6dhr_ig/Config.lb (Arbeitskopie) @@ -3,41 +3,9 @@ ## default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE -## -## Compute the location and size of where this firmware image -## (coreboot plus bootloader) will live in the boot rom chip. -## -if USE_FALLBACK_IMAGE - default ROM_SECTION_SIZE = FALLBACK_SIZE - default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE ) -else - default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE ) - default ROM_SECTION_OFFSET = 0 -end +include /config/nofailovercalculation128.lb ## -## Compute the start location and size size of -## The coreboot bootloader. -## -default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE ) -default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) - -## -## Compute where this copy of coreboot will start in the boot rom -## -default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE ) - -## -## Compute a range of ROM that can cached to speed up coreboot, -## execution speed. -## -## XIP_ROM_SIZE must be a power of 2. -## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE -## -default XIP_ROM_SIZE=131072 -default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE ) - -## ## Set all of the defaults for an x86 architecture ## Index: LinuxBIOSv2-Configlb_refactor/src/mainboard/supermicro/x6dhr_ig2/Config.lb =================================================================== --- LinuxBIOSv2-Configlb_refactor/src/mainboard/supermicro/x6dhr_ig2/Config.lb (Revision 4150) +++ LinuxBIOSv2-Configlb_refactor/src/mainboard/supermicro/x6dhr_ig2/Config.lb (Arbeitskopie) @@ -3,41 +3,9 @@ ## default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE -## -## Compute the location and size of where this firmware image -## (coreboot plus bootloader) will live in the boot rom chip. -## -if USE_FALLBACK_IMAGE - default ROM_SECTION_SIZE = FALLBACK_SIZE - default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE ) -else - default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE ) - default ROM_SECTION_OFFSET = 0 -end +include /config/nofailovercalculation128.lb ## -## Compute the start location and size size of -## The coreboot bootloader. -## -default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE ) -default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) - -## -## Compute where this copy of coreboot will start in the boot rom -## -default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE ) - -## -## Compute a range of ROM that can cached to speed up coreboot, -## execution speed. -## -## XIP_ROM_SIZE must be a power of 2. -## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE -## -default XIP_ROM_SIZE=131072 -default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE ) - -## ## Set all of the defaults for an x86 architecture ## Index: LinuxBIOSv2-Configlb_refactor/src/mainboard/kontron/986lcd-m/Config.lb =================================================================== --- LinuxBIOSv2-Configlb_refactor/src/mainboard/kontron/986lcd-m/Config.lb (Revision 4150) +++ LinuxBIOSv2-Configlb_refactor/src/mainboard/kontron/986lcd-m/Config.lb (Arbeitskopie) @@ -28,41 +28,9 @@ ## default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE -## -## Compute the location and size of where this firmware image -## (coreboot plus bootloader) will live in the boot rom chip. -## -if USE_FALLBACK_IMAGE - default ROM_SECTION_SIZE = FALLBACK_SIZE - default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE ) -else - default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE ) - default ROM_SECTION_OFFSET = 0 -end +include /config/nofailovercalculation.lb ## -## Compute the start location and size size of -## The coreboot bootloader. -## -default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE ) -default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) - -## -## Compute where this copy of coreboot will start in the boot rom -## -default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE ) - -## -## Compute a range of ROM that can cached to speed up coreboot, -## execution speed. -## -## XIP_ROM_SIZE must be a power of 2. -## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE -## -default XIP_ROM_SIZE=(64*1024) -default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE ) - -## ## Set all of the defaults for an x86 architecture ## Index: LinuxBIOSv2-Configlb_refactor/src/mainboard/dell/s1850/Config.lb =================================================================== --- LinuxBIOSv2-Configlb_refactor/src/mainboard/dell/s1850/Config.lb (Revision 4150) +++ LinuxBIOSv2-Configlb_refactor/src/mainboard/dell/s1850/Config.lb (Arbeitskopie) @@ -3,41 +3,9 @@ ## default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE -## -## Compute the location and size of where this firmware image -## (coreboot plus bootloader) will live in the boot rom chip. -## -if USE_FALLBACK_IMAGE - default ROM_SECTION_SIZE = FALLBACK_SIZE - default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE ) -else - default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE ) - default ROM_SECTION_OFFSET = 0 -end +include /config/nofailovercalculation128.lb ## -## Compute the start location and size size of -## The coreboot bootloader. -## -default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE ) -default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) - -## -## Compute where this copy of coreboot will start in the boot rom -## -default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE ) - -## -## Compute a range of ROM that can cached to speed up coreboot, -## execution speed. -## -## XIP_ROM_SIZE must be a power of 2. -## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE -## -default XIP_ROM_SIZE=131072 -default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE ) - -## ## Set all of the defaults for an x86 architecture ## Index: LinuxBIOSv2-Configlb_refactor/src/mainboard/arima/hdama/Config.lb =================================================================== --- LinuxBIOSv2-Configlb_refactor/src/mainboard/arima/hdama/Config.lb (Revision 4150) +++ LinuxBIOSv2-Configlb_refactor/src/mainboard/arima/hdama/Config.lb (Arbeitskopie) @@ -1,38 +1,6 @@ -## -## Compute the location and size of where this firmware image -## (coreboot plus bootloader) will live in the boot rom chip. -## -if USE_FALLBACK_IMAGE - default ROM_SECTION_SIZE = FALLBACK_SIZE - default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE ) -else - default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE ) - default ROM_SECTION_OFFSET = 0 -end +include /config/nofailovercalculation128.lb ## -## Compute the start location and size size of -## The coreboot bootloader. -## -default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE ) -default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) - -## -## Compute where this copy of coreboot will start in the boot rom -## -default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE ) - -## -## Compute a range of ROM that can cached to speed up coreboot, -## execution speed. -## -## XIP_ROM_SIZE must be a power of 2. -## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE -## -default XIP_ROM_SIZE=131072 -default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE ) - -## ## Set all of the defaults for an x86 architecture ## Index: LinuxBIOSv2-Configlb_refactor/src/mainboard/intel/xe7501devkit/Config.lb =================================================================== --- LinuxBIOSv2-Configlb_refactor/src/mainboard/intel/xe7501devkit/Config.lb (Revision 4150) +++ LinuxBIOSv2-Configlb_refactor/src/mainboard/intel/xe7501devkit/Config.lb (Arbeitskopie) @@ -1,40 +1,5 @@ -################################################################## -## BEGIN BOILERPLATE - DO NOT EDIT -## -## Compute the location and size of where this firmware image -## (coreboot plus payload) will live in the boot rom chip. -## -if USE_FALLBACK_IMAGE -# The fallback image uses FALLBACK_SIZE bytes at the end of the ROM +include /config/nofailovercalculation128.lb - default ROM_SECTION_SIZE = FALLBACK_SIZE - default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE ) - -else -# The normal image goes at the beginning of the coreboot ROM region -# and uses all the remaining space - - default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE ) - default ROM_SECTION_OFFSET = 0 -end - -## -## Compute where this copy of coreboot will start in the boot rom -## -default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE ) - -## -## Compute a range of ROM that can cached to speed up coreboot, -## execution speed. -## -## XIP_ROM_SIZE must be a power of 2. -## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE -default XIP_ROM_SIZE = 65536 -default XIP_ROM_BASE = ((( _ROMBASE + ROM_IMAGE_SIZE ) / XIP_ROM_SIZE ) * XIP_ROM_SIZE - XIP_ROM_SIZE ) - -## END BOILERPLATE -################################################################## - arch i386 end ## Index: LinuxBIOSv2-Configlb_refactor/src/mainboard/intel/truxton/Config.lb =================================================================== --- LinuxBIOSv2-Configlb_refactor/src/mainboard/intel/truxton/Config.lb (Revision 4150) +++ LinuxBIOSv2-Configlb_refactor/src/mainboard/intel/truxton/Config.lb (Arbeitskopie) @@ -17,40 +17,9 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -## -## Compute the location and size of where this firmware image -## (coreboot plus bootloader) will live in the boot ROM chip -## -if USE_FALLBACK_IMAGE - default ROM_SECTION_SIZE = FALLBACK_SIZE - default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE ) -else - default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE ) - default ROM_SECTION_OFFSET = 0 -end +include /config/nofailovercalculation128.lb ## -## Compute the start location and size size of the coreboot bootloader -## -default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE ) -default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) - -## -## Compute where this copy of coreboot will start in the boot ROM -## -default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE ) - -## -## Compute a range of ROM that can cached to speed up coreboot, -## execution speed. -## -## XIP_ROM_SIZE must be a power of 2. -## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE -## -default XIP_ROM_SIZE=131072 -default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE ) - -## ## Set all of the defaults for an x86 architecture ## Index: LinuxBIOSv2-Configlb_refactor/src/mainboard/intel/mtarvon/Config.lb =================================================================== --- LinuxBIOSv2-Configlb_refactor/src/mainboard/intel/mtarvon/Config.lb (Revision 4150) +++ LinuxBIOSv2-Configlb_refactor/src/mainboard/intel/mtarvon/Config.lb (Arbeitskopie) @@ -17,40 +17,9 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -## -## Compute the location and size of where this firmware image -## (coreboot plus bootloader) will live in the boot ROM chip -## -if USE_FALLBACK_IMAGE - default ROM_SECTION_SIZE = FALLBACK_SIZE - default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE ) -else - default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE ) - default ROM_SECTION_OFFSET = 0 -end +include /config/nofailovercalculation128.lb ## -## Compute the start location and size size of the coreboot bootloader -## -default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE ) -default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) - -## -## Compute where this copy of coreboot will start in the boot ROM -## -default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE ) - -## -## Compute a range of ROM that can cached to speed up coreboot, -## execution speed. -## -## XIP_ROM_SIZE must be a power of 2. -## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE -## -default XIP_ROM_SIZE=131072 -default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE ) - -## ## Set all of the defaults for an x86 architecture ## Index: LinuxBIOSv2-Configlb_refactor/src/mainboard/intel/jarrell/Config.lb =================================================================== --- LinuxBIOSv2-Configlb_refactor/src/mainboard/intel/jarrell/Config.lb (Revision 4150) +++ LinuxBIOSv2-Configlb_refactor/src/mainboard/intel/jarrell/Config.lb (Arbeitskopie) @@ -3,41 +3,9 @@ ## default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE -## -## Compute the location and size of where this firmware image -## (coreboot plus bootloader) will live in the boot rom chip. -## -if USE_FALLBACK_IMAGE - default ROM_SECTION_SIZE = FALLBACK_SIZE - default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE ) -else - default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE ) - default ROM_SECTION_OFFSET = 0 -end +include /config/nofailovercalculation128.lb ## -## Compute the start location and size size of -## The coreboot bootloader. -## -default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE ) -default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) - -## -## Compute where this copy of coreboot will start in the boot rom -## -default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE ) - -## -## Compute a range of ROM that can cached to speed up coreboot, -## execution speed. -## -## XIP_ROM_SIZE must be a power of 2. -## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE -## -default XIP_ROM_SIZE=131072 -default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE ) - -## ## Set all of the defaults for an x86 architecture ## Index: LinuxBIOSv2-Configlb_refactor/src/config/nofailovercalculation128.lb =================================================================== --- LinuxBIOSv2-Configlb_refactor/src/config/nofailovercalculation128.lb (Revision 0) +++ LinuxBIOSv2-Configlb_refactor/src/config/nofailovercalculation128.lb (Revision 0) @@ -0,0 +1,38 @@ +## +## Compute the location and size of where this firmware image +## (coreboot plus bootloader) will live in the boot rom chip. +## +if USE_FALLBACK_IMAGE + default ROM_SECTION_SIZE = FALLBACK_SIZE + default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE ) +else + default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE ) + default ROM_SECTION_OFFSET = 0 +end + +## +## Compute the start location and size size of +## The coreboot bootloader. +## +default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE ) +default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) + +## +## Compute where this copy of coreboot will start in the boot rom +## +default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE ) + +## +## Compute a range of ROM that can cached to speed up coreboot, +## execution speed. +## +## XIP_ROM_SIZE must be a power of 2. +## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE +## +default XIP_ROM_SIZE = 128 * 1024 +default XIP_ROM_BASE = ( _ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE ) + +## This is needed to work around a parser bug. +if USE_FALLBACK_IMAGE +end + -- http://www.hailfinger.org/ Index: LinuxBIOSv2-Configlb_refactor/src/mainboard/supermicro/x6dai_g/Config.lb =================================================================== --- LinuxBIOSv2-Configlb_refactor/src/mainboard/supermicro/x6dai_g/Config.lb (Revision 4150) +++ LinuxBIOSv2-Configlb_refactor/src/mainboard/supermicro/x6dai_g/Config.lb (Arbeitskopie) @@ -3,41 +3,9 @@ ## default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE -## -## Compute the location and size of where this firmware image -## (coreboot plus bootloader) will live in the boot rom chip. -## -if USE_FALLBACK_IMAGE - default ROM_SECTION_SIZE = FALLBACK_SIZE - default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE ) -else - default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE ) - default ROM_SECTION_OFFSET = 0 -end +include /config/nofailovercalculation128.lb ## -## Compute the start location and size size of -## The coreboot bootloader. -## -default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE ) -default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) - -## -## Compute where this copy of coreboot will start in the boot rom -## -default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE ) - -## -## Compute a range of ROM that can be cached to speed up coreboot, -## execution speed. -## -## XIP_ROM_SIZE must be a power of 2. -## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE -## -default XIP_ROM_SIZE=131072 -default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE ) - -## ## Set all of the defaults for an x86 architecture ## Index: LinuxBIOSv2-Configlb_refactor/src/mainboard/supermicro/x6dhe_g/Config.lb =================================================================== --- LinuxBIOSv2-Configlb_refactor/src/mainboard/supermicro/x6dhe_g/Config.lb (Revision 4150) +++ LinuxBIOSv2-Configlb_refactor/src/mainboard/supermicro/x6dhe_g/Config.lb (Arbeitskopie) @@ -3,39 +3,8 @@ ## default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE -## -## Compute the location and size of where this firmware image -## (coreboot plus bootloader) will live in the boot rom chip. -## -if USE_FALLBACK_IMAGE - default ROM_SECTION_SIZE = FALLBACK_SIZE - default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE ) -else - default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE ) - default ROM_SECTION_OFFSET = 0 -end +include /config/nofailovercalculation128.lb -## -## Compute the start location and size size of -## The coreboot bootloader. -## -default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE ) -default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) - -## -## Compute where this copy of coreboot will start in the boot rom -## -default _ROMBASE =( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE ) - -## -## Compute a range of ROM that can be cached to speed up coreboot. -## execution speed. -## XIP_ROM_SIZE must be a power of 2. -## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE -default XIP_ROM_SIZE=131072 -default XIP_ROM_BASE= ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE ) - -## ## Set all of the defaults for an x86 architecture ## Index: LinuxBIOSv2-Configlb_refactor/src/mainboard/supermicro/x6dhe_g2/Config.lb =================================================================== --- LinuxBIOSv2-Configlb_refactor/src/mainboard/supermicro/x6dhe_g2/Config.lb (Revision 4150) +++ LinuxBIOSv2-Configlb_refactor/src/mainboard/supermicro/x6dhe_g2/Config.lb (Arbeitskopie) @@ -3,39 +3,8 @@ ## default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE -## -## Compute the location and size of where this firmware image -## (coreboot plus bootloader) will live in the boot rom chip. -## -if USE_FALLBACK_IMAGE - default ROM_SECTION_SIZE = FALLBACK_SIZE - default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE ) -else - default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE ) - default ROM_SECTION_OFFSET = 0 -end +include /config/nofailovercalculation128.lb -## -## Compute the start location and size size of -## The coreboot bootloader. -## -default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE ) -default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) - -## -## Compute where this copy of coreboot will start in the boot rom -## -default _ROMBASE =( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE ) - -## -## Compute a range of ROM that can be cached to speed up coreboot. -## execution speed. -## XIP_ROM_SIZE must be a power of 2. -## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE -default XIP_ROM_SIZE=131072 -default XIP_ROM_BASE= ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE ) - -## ## Set all of the defaults for an x86 architecture ## Index: LinuxBIOSv2-Configlb_refactor/src/mainboard/supermicro/x6dhr_ig/Config.lb =================================================================== --- LinuxBIOSv2-Configlb_refactor/src/mainboard/supermicro/x6dhr_ig/Config.lb (Revision 4150) +++ LinuxBIOSv2-Configlb_refactor/src/mainboard/supermicro/x6dhr_ig/Config.lb (Arbeitskopie) @@ -3,41 +3,9 @@ ## default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE -## -## Compute the location and size of where this firmware image -## (coreboot plus bootloader) will live in the boot rom chip. -## -if USE_FALLBACK_IMAGE - default ROM_SECTION_SIZE = FALLBACK_SIZE - default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE ) -else - default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE ) - default ROM_SECTION_OFFSET = 0 -end +include /config/nofailovercalculation128.lb ## -## Compute the start location and size size of -## The coreboot bootloader. -## -default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE ) -default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) - -## -## Compute where this copy of coreboot will start in the boot rom -## -default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE ) - -## -## Compute a range of ROM that can cached to speed up coreboot, -## execution speed. -## -## XIP_ROM_SIZE must be a power of 2. -## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE -## -default XIP_ROM_SIZE=131072 -default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE ) - -## ## Set all of the defaults for an x86 architecture ## Index: LinuxBIOSv2-Configlb_refactor/src/mainboard/supermicro/x6dhr_ig2/Config.lb =================================================================== --- LinuxBIOSv2-Configlb_refactor/src/mainboard/supermicro/x6dhr_ig2/Config.lb (Revision 4150) +++ LinuxBIOSv2-Configlb_refactor/src/mainboard/supermicro/x6dhr_ig2/Config.lb (Arbeitskopie) @@ -3,41 +3,9 @@ ## default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE -## -## Compute the location and size of where this firmware image -## (coreboot plus bootloader) will live in the boot rom chip. -## -if USE_FALLBACK_IMAGE - default ROM_SECTION_SIZE = FALLBACK_SIZE - default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE ) -else - default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE ) - default ROM_SECTION_OFFSET = 0 -end +include /config/nofailovercalculation128.lb ## -## Compute the start location and size size of -## The coreboot bootloader. -## -default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE ) -default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) - -## -## Compute where this copy of coreboot will start in the boot rom -## -default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE ) - -## -## Compute a range of ROM that can cached to speed up coreboot, -## execution speed. -## -## XIP_ROM_SIZE must be a power of 2. -## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE -## -default XIP_ROM_SIZE=131072 -default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE ) - -## ## Set all of the defaults for an x86 architecture ## Index: LinuxBIOSv2-Configlb_refactor/src/mainboard/kontron/986lcd-m/Config.lb =================================================================== --- LinuxBIOSv2-Configlb_refactor/src/mainboard/kontron/986lcd-m/Config.lb (Revision 4150) +++ LinuxBIOSv2-Configlb_refactor/src/mainboard/kontron/986lcd-m/Config.lb (Arbeitskopie) @@ -28,41 +28,9 @@ ## default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE -## -## Compute the location and size of where this firmware image -## (coreboot plus bootloader) will live in the boot rom chip. -## -if USE_FALLBACK_IMAGE - default ROM_SECTION_SIZE = FALLBACK_SIZE - default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE ) -else - default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE ) - default ROM_SECTION_OFFSET = 0 -end +include /config/nofailovercalculation.lb ## -## Compute the start location and size size of -## The coreboot bootloader. -## -default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE ) -default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) - -## -## Compute where this copy of coreboot will start in the boot rom -## -default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE ) - -## -## Compute a range of ROM that can cached to speed up coreboot, -## execution speed. -## -## XIP_ROM_SIZE must be a power of 2. -## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE -## -default XIP_ROM_SIZE=(64*1024) -default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE ) - -## ## Set all of the defaults for an x86 architecture ## Index: LinuxBIOSv2-Configlb_refactor/src/mainboard/dell/s1850/Config.lb =================================================================== --- LinuxBIOSv2-Configlb_refactor/src/mainboard/dell/s1850/Config.lb (Revision 4150) +++ LinuxBIOSv2-Configlb_refactor/src/mainboard/dell/s1850/Config.lb (Arbeitskopie) @@ -3,41 +3,9 @@ ## default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE -## -## Compute the location and size of where this firmware image -## (coreboot plus bootloader) will live in the boot rom chip. -## -if USE_FALLBACK_IMAGE - default ROM_SECTION_SIZE = FALLBACK_SIZE - default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE ) -else - default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE ) - default ROM_SECTION_OFFSET = 0 -end +include /config/nofailovercalculation128.lb ## -## Compute the start location and size size of -## The coreboot bootloader. -## -default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE ) -default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) - -## -## Compute where this copy of coreboot will start in the boot rom -## -default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE ) - -## -## Compute a range of ROM that can cached to speed up coreboot, -## execution speed. -## -## XIP_ROM_SIZE must be a power of 2. -## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE -## -default XIP_ROM_SIZE=131072 -default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE ) - -## ## Set all of the defaults for an x86 architecture ## Index: LinuxBIOSv2-Configlb_refactor/src/mainboard/arima/hdama/Config.lb =================================================================== --- LinuxBIOSv2-Configlb_refactor/src/mainboard/arima/hdama/Config.lb (Revision 4150) +++ LinuxBIOSv2-Configlb_refactor/src/mainboard/arima/hdama/Config.lb (Arbeitskopie) @@ -1,38 +1,6 @@ -## -## Compute the location and size of where this firmware image -## (coreboot plus bootloader) will live in the boot rom chip. -## -if USE_FALLBACK_IMAGE - default ROM_SECTION_SIZE = FALLBACK_SIZE - default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE ) -else - default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE ) - default ROM_SECTION_OFFSET = 0 -end +include /config/nofailovercalculation128.lb ## -## Compute the start location and size size of -## The coreboot bootloader. -## -default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE ) -default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) - -## -## Compute where this copy of coreboot will start in the boot rom -## -default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE ) - -## -## Compute a range of ROM that can cached to speed up coreboot, -## execution speed. -## -## XIP_ROM_SIZE must be a power of 2. -## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE -## -default XIP_ROM_SIZE=131072 -default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE ) - -## ## Set all of the defaults for an x86 architecture ## Index: LinuxBIOSv2-Configlb_refactor/src/mainboard/intel/xe7501devkit/Config.lb =================================================================== --- LinuxBIOSv2-Configlb_refactor/src/mainboard/intel/xe7501devkit/Config.lb (Revision 4150) +++ LinuxBIOSv2-Configlb_refactor/src/mainboard/intel/xe7501devkit/Config.lb (Arbeitskopie) @@ -1,40 +1,5 @@ -################################################################## -## BEGIN BOILERPLATE - DO NOT EDIT -## -## Compute the location and size of where this firmware image -## (coreboot plus payload) will live in the boot rom chip. -## -if USE_FALLBACK_IMAGE -# The fallback image uses FALLBACK_SIZE bytes at the end of the ROM +include /config/nofailovercalculation128.lb - default ROM_SECTION_SIZE = FALLBACK_SIZE - default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE ) - -else -# The normal image goes at the beginning of the coreboot ROM region -# and uses all the remaining space - - default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE ) - default ROM_SECTION_OFFSET = 0 -end - -## -## Compute where this copy of coreboot will start in the boot rom -## -default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE ) - -## -## Compute a range of ROM that can cached to speed up coreboot, -## execution speed. -## -## XIP_ROM_SIZE must be a power of 2. -## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE -default XIP_ROM_SIZE = 65536 -default XIP_ROM_BASE = ((( _ROMBASE + ROM_IMAGE_SIZE ) / XIP_ROM_SIZE ) * XIP_ROM_SIZE - XIP_ROM_SIZE ) - -## END BOILERPLATE -################################################################## - arch i386 end ## Index: LinuxBIOSv2-Configlb_refactor/src/mainboard/intel/truxton/Config.lb =================================================================== --- LinuxBIOSv2-Configlb_refactor/src/mainboard/intel/truxton/Config.lb (Revision 4150) +++ LinuxBIOSv2-Configlb_refactor/src/mainboard/intel/truxton/Config.lb (Arbeitskopie) @@ -17,40 +17,9 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -## -## Compute the location and size of where this firmware image -## (coreboot plus bootloader) will live in the boot ROM chip -## -if USE_FALLBACK_IMAGE - default ROM_SECTION_SIZE = FALLBACK_SIZE - default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE ) -else - default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE ) - default ROM_SECTION_OFFSET = 0 -end +include /config/nofailovercalculation128.lb ## -## Compute the start location and size size of the coreboot bootloader -## -default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE ) -default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) - -## -## Compute where this copy of coreboot will start in the boot ROM -## -default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE ) - -## -## Compute a range of ROM that can cached to speed up coreboot, -## execution speed. -## -## XIP_ROM_SIZE must be a power of 2. -## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE -## -default XIP_ROM_SIZE=131072 -default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE ) - -## ## Set all of the defaults for an x86 architecture ## Index: LinuxBIOSv2-Configlb_refactor/src/mainboard/intel/mtarvon/Config.lb =================================================================== --- LinuxBIOSv2-Configlb_refactor/src/mainboard/intel/mtarvon/Config.lb (Revision 4150) +++ LinuxBIOSv2-Configlb_refactor/src/mainboard/intel/mtarvon/Config.lb (Arbeitskopie) @@ -17,40 +17,9 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -## -## Compute the location and size of where this firmware image -## (coreboot plus bootloader) will live in the boot ROM chip -## -if USE_FALLBACK_IMAGE - default ROM_SECTION_SIZE = FALLBACK_SIZE - default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE ) -else - default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE ) - default ROM_SECTION_OFFSET = 0 -end +include /config/nofailovercalculation128.lb ## -## Compute the start location and size size of the coreboot bootloader -## -default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE ) -default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) - -## -## Compute where this copy of coreboot will start in the boot ROM -## -default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE ) - -## -## Compute a range of ROM that can cached to speed up coreboot, -## execution speed. -## -## XIP_ROM_SIZE must be a power of 2. -## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE -## -default XIP_ROM_SIZE=131072 -default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE ) - -## ## Set all of the defaults for an x86 architecture ## Index: LinuxBIOSv2-Configlb_refactor/src/mainboard/intel/jarrell/Config.lb =================================================================== --- LinuxBIOSv2-Configlb_refactor/src/mainboard/intel/jarrell/Config.lb (Revision 4150) +++ LinuxBIOSv2-Configlb_refactor/src/mainboard/intel/jarrell/Config.lb (Arbeitskopie) @@ -3,41 +3,9 @@ ## default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE -## -## Compute the location and size of where this firmware image -## (coreboot plus bootloader) will live in the boot rom chip. -## -if USE_FALLBACK_IMAGE - default ROM_SECTION_SIZE = FALLBACK_SIZE - default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE ) -else - default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE ) - default ROM_SECTION_OFFSET = 0 -end +include /config/nofailovercalculation128.lb ## -## Compute the start location and size size of -## The coreboot bootloader. -## -default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE ) -default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) - -## -## Compute where this copy of coreboot will start in the boot rom -## -default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE ) - -## -## Compute a range of ROM that can cached to speed up coreboot, -## execution speed. -## -## XIP_ROM_SIZE must be a power of 2. -## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE -## -default XIP_ROM_SIZE=131072 -default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE ) - -## ## Set all of the defaults for an x86 architecture ## Index: LinuxBIOSv2-Configlb_refactor/src/config/nofailovercalculation128.lb =================================================================== --- LinuxBIOSv2-Configlb_refactor/src/config/nofailovercalculation128.lb (Revision 0) +++ LinuxBIOSv2-Configlb_refactor/src/config/nofailovercalculation128.lb (Revision 0) @@ -0,0 +1,38 @@ +## +## Compute the location and size of where this firmware image +## (coreboot plus bootloader) will live in the boot rom chip. +## +if USE_FALLBACK_IMAGE + default ROM_SECTION_SIZE = FALLBACK_SIZE + default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE ) +else + default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE ) + default ROM_SECTION_OFFSET = 0 +end + +## +## Compute the start location and size size of +## The coreboot bootloader. +## +default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE ) +default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) + +## +## Compute where this copy of coreboot will start in the boot rom +## +default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE ) + +## +## Compute a range of ROM that can cached to speed up coreboot, +## execution speed. +## +## XIP_ROM_SIZE must be a power of 2. +## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE +## +default XIP_ROM_SIZE = 128 * 1024 +default XIP_ROM_BASE = ( _ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE ) + +## This is needed to work around a parser bug. +if USE_FALLBACK_IMAGE +end +

2 2

[v2] r4186 - in trunk/coreboot-v2/src: config mainboard/arima/hdama mainboard/dell/s1850 mainboard/intel/jarrell mainboard/intel/mtarvon mainboard/intel/truxton mainboard/intel/xe7501devkit mainboard/kontron/986lcd-m mainboard/supermicro/x6dai_g mainboard/supermicro/x6dhe_g mainboard/supermicro/x6dhe_g2 mainboard/supermicro/x6dhr_ig mainboard/supermicro/x6dhr_ig2
by svn＠coreboot.org 22 Apr '09

22 Apr '09

Author: hailfinger Date: 2009-04-23 00:08:00 +0200 (Thu, 23 Apr 2009) New Revision: 4186 Added: trunk/coreboot-v2/src/config/nofailovercalculation128.lb Modified: trunk/coreboot-v2/src/mainboard/arima/hdama/Config.lb trunk/coreboot-v2/src/mainboard/dell/s1850/Config.lb trunk/coreboot-v2/src/mainboard/intel/jarrell/Config.lb trunk/coreboot-v2/src/mainboard/intel/mtarvon/Config.lb trunk/coreboot-v2/src/mainboard/intel/truxton/Config.lb trunk/coreboot-v2/src/mainboard/intel/xe7501devkit/Config.lb trunk/coreboot-v2/src/mainboard/kontron/986lcd-m/Config.lb trunk/coreboot-v2/src/mainboard/supermicro/x6dai_g/Config.lb trunk/coreboot-v2/src/mainboard/supermicro/x6dhe_g/Config.lb trunk/coreboot-v2/src/mainboard/supermicro/x6dhe_g2/Config.lb trunk/coreboot-v2/src/mainboard/supermicro/x6dhr_ig/Config.lb trunk/coreboot-v2/src/mainboard/supermicro/x6dhr_ig2/Config.lb Log: Convert 12 more boards to use include statements in Config.lb. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Peter Stuge <peter(a)stuge.se> Added: trunk/coreboot-v2/src/config/nofailovercalculation128.lb =================================================================== --- trunk/coreboot-v2/src/config/nofailovercalculation128.lb (rev 0) +++ trunk/coreboot-v2/src/config/nofailovercalculation128.lb 2009-04-22 22:08:00 UTC (rev 4186) @@ -0,0 +1,38 @@ +## +## Compute the location and size of where this firmware image +## (coreboot plus bootloader) will live in the boot rom chip. +## +if USE_FALLBACK_IMAGE + default ROM_SECTION_SIZE = FALLBACK_SIZE + default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE ) +else + default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE ) + default ROM_SECTION_OFFSET = 0 +end + +## +## Compute the start location and size size of +## The coreboot bootloader. +## +default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE ) +default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) + +## +## Compute where this copy of coreboot will start in the boot rom +## +default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE ) + +## +## Compute a range of ROM that can cached to speed up coreboot, +## execution speed. +## +## XIP_ROM_SIZE must be a power of 2. +## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE +## +default XIP_ROM_SIZE = 128 * 1024 +default XIP_ROM_BASE = ( _ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE ) + +## This is needed to work around a parser bug. +if USE_FALLBACK_IMAGE +end + Modified: trunk/coreboot-v2/src/mainboard/arima/hdama/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/arima/hdama/Config.lb 2009-04-22 20:41:42 UTC (rev 4185) +++ trunk/coreboot-v2/src/mainboard/arima/hdama/Config.lb 2009-04-22 22:08:00 UTC (rev 4186) @@ -1,38 +1,6 @@ -## -## Compute the location and size of where this firmware image -## (coreboot plus bootloader) will live in the boot rom chip. -## -if USE_FALLBACK_IMAGE - default ROM_SECTION_SIZE = FALLBACK_SIZE - default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE ) -else - default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE ) - default ROM_SECTION_OFFSET = 0 -end +include /config/nofailovercalculation128.lb ## -## Compute the start location and size size of -## The coreboot bootloader. -## -default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE ) -default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) - -## -## Compute where this copy of coreboot will start in the boot rom -## -default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE ) - -## -## Compute a range of ROM that can cached to speed up coreboot, -## execution speed. -## -## XIP_ROM_SIZE must be a power of 2. -## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE -## -default XIP_ROM_SIZE=131072 -default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE ) - -## ## Set all of the defaults for an x86 architecture ## Modified: trunk/coreboot-v2/src/mainboard/dell/s1850/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/dell/s1850/Config.lb 2009-04-22 20:41:42 UTC (rev 4185) +++ trunk/coreboot-v2/src/mainboard/dell/s1850/Config.lb 2009-04-22 22:08:00 UTC (rev 4186) @@ -3,41 +3,9 @@ ## default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE -## -## Compute the location and size of where this firmware image -## (coreboot plus bootloader) will live in the boot rom chip. -## -if USE_FALLBACK_IMAGE - default ROM_SECTION_SIZE = FALLBACK_SIZE - default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE ) -else - default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE ) - default ROM_SECTION_OFFSET = 0 -end +include /config/nofailovercalculation128.lb ## -## Compute the start location and size size of -## The coreboot bootloader. -## -default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE ) -default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) - -## -## Compute where this copy of coreboot will start in the boot rom -## -default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE ) - -## -## Compute a range of ROM that can cached to speed up coreboot, -## execution speed. -## -## XIP_ROM_SIZE must be a power of 2. -## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE -## -default XIP_ROM_SIZE=131072 -default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE ) - -## ## Set all of the defaults for an x86 architecture ## Modified: trunk/coreboot-v2/src/mainboard/intel/jarrell/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/intel/jarrell/Config.lb 2009-04-22 20:41:42 UTC (rev 4185) +++ trunk/coreboot-v2/src/mainboard/intel/jarrell/Config.lb 2009-04-22 22:08:00 UTC (rev 4186) @@ -3,41 +3,9 @@ ## default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE -## -## Compute the location and size of where this firmware image -## (coreboot plus bootloader) will live in the boot rom chip. -## -if USE_FALLBACK_IMAGE - default ROM_SECTION_SIZE = FALLBACK_SIZE - default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE ) -else - default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE ) - default ROM_SECTION_OFFSET = 0 -end +include /config/nofailovercalculation128.lb ## -## Compute the start location and size size of -## The coreboot bootloader. -## -default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE ) -default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) - -## -## Compute where this copy of coreboot will start in the boot rom -## -default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE ) - -## -## Compute a range of ROM that can cached to speed up coreboot, -## execution speed. -## -## XIP_ROM_SIZE must be a power of 2. -## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE -## -default XIP_ROM_SIZE=131072 -default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE ) - -## ## Set all of the defaults for an x86 architecture ## Modified: trunk/coreboot-v2/src/mainboard/intel/mtarvon/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/intel/mtarvon/Config.lb 2009-04-22 20:41:42 UTC (rev 4185) +++ trunk/coreboot-v2/src/mainboard/intel/mtarvon/Config.lb 2009-04-22 22:08:00 UTC (rev 4186) @@ -17,40 +17,9 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -## -## Compute the location and size of where this firmware image -## (coreboot plus bootloader) will live in the boot ROM chip -## -if USE_FALLBACK_IMAGE - default ROM_SECTION_SIZE = FALLBACK_SIZE - default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE ) -else - default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE ) - default ROM_SECTION_OFFSET = 0 -end +include /config/nofailovercalculation128.lb ## -## Compute the start location and size size of the coreboot bootloader -## -default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE ) -default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) - -## -## Compute where this copy of coreboot will start in the boot ROM -## -default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE ) - -## -## Compute a range of ROM that can cached to speed up coreboot, -## execution speed. -## -## XIP_ROM_SIZE must be a power of 2. -## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE -## -default XIP_ROM_SIZE=131072 -default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE ) - -## ## Set all of the defaults for an x86 architecture ## Modified: trunk/coreboot-v2/src/mainboard/intel/truxton/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/intel/truxton/Config.lb 2009-04-22 20:41:42 UTC (rev 4185) +++ trunk/coreboot-v2/src/mainboard/intel/truxton/Config.lb 2009-04-22 22:08:00 UTC (rev 4186) @@ -17,40 +17,9 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -## -## Compute the location and size of where this firmware image -## (coreboot plus bootloader) will live in the boot ROM chip -## -if USE_FALLBACK_IMAGE - default ROM_SECTION_SIZE = FALLBACK_SIZE - default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE ) -else - default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE ) - default ROM_SECTION_OFFSET = 0 -end +include /config/nofailovercalculation128.lb ## -## Compute the start location and size size of the coreboot bootloader -## -default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE ) -default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) - -## -## Compute where this copy of coreboot will start in the boot ROM -## -default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE ) - -## -## Compute a range of ROM that can cached to speed up coreboot, -## execution speed. -## -## XIP_ROM_SIZE must be a power of 2. -## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE -## -default XIP_ROM_SIZE=131072 -default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE ) - -## ## Set all of the defaults for an x86 architecture ## Modified: trunk/coreboot-v2/src/mainboard/intel/xe7501devkit/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/intel/xe7501devkit/Config.lb 2009-04-22 20:41:42 UTC (rev 4185) +++ trunk/coreboot-v2/src/mainboard/intel/xe7501devkit/Config.lb 2009-04-22 22:08:00 UTC (rev 4186) @@ -1,40 +1,5 @@ -################################################################## -## BEGIN BOILERPLATE - DO NOT EDIT -## -## Compute the location and size of where this firmware image -## (coreboot plus payload) will live in the boot rom chip. -## -if USE_FALLBACK_IMAGE -# The fallback image uses FALLBACK_SIZE bytes at the end of the ROM +include /config/nofailovercalculation128.lb - default ROM_SECTION_SIZE = FALLBACK_SIZE - default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE ) - -else -# The normal image goes at the beginning of the coreboot ROM region -# and uses all the remaining space - - default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE ) - default ROM_SECTION_OFFSET = 0 -end - -## -## Compute where this copy of coreboot will start in the boot rom -## -default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE ) - -## -## Compute a range of ROM that can cached to speed up coreboot, -## execution speed. -## -## XIP_ROM_SIZE must be a power of 2. -## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE -default XIP_ROM_SIZE = 65536 -default XIP_ROM_BASE = ((( _ROMBASE + ROM_IMAGE_SIZE ) / XIP_ROM_SIZE ) * XIP_ROM_SIZE - XIP_ROM_SIZE ) - -## END BOILERPLATE -################################################################## - arch i386 end ## Modified: trunk/coreboot-v2/src/mainboard/kontron/986lcd-m/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/kontron/986lcd-m/Config.lb 2009-04-22 20:41:42 UTC (rev 4185) +++ trunk/coreboot-v2/src/mainboard/kontron/986lcd-m/Config.lb 2009-04-22 22:08:00 UTC (rev 4186) @@ -28,41 +28,9 @@ ## default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE -## -## Compute the location and size of where this firmware image -## (coreboot plus bootloader) will live in the boot rom chip. -## -if USE_FALLBACK_IMAGE - default ROM_SECTION_SIZE = FALLBACK_SIZE - default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE ) -else - default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE ) - default ROM_SECTION_OFFSET = 0 -end +include /config/nofailovercalculation.lb ## -## Compute the start location and size size of -## The coreboot bootloader. -## -default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE ) -default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) - -## -## Compute where this copy of coreboot will start in the boot rom -## -default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE ) - -## -## Compute a range of ROM that can cached to speed up coreboot, -## execution speed. -## -## XIP_ROM_SIZE must be a power of 2. -## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE -## -default XIP_ROM_SIZE=(64*1024) -default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE ) - -## ## Set all of the defaults for an x86 architecture ## Modified: trunk/coreboot-v2/src/mainboard/supermicro/x6dai_g/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/supermicro/x6dai_g/Config.lb 2009-04-22 20:41:42 UTC (rev 4185) +++ trunk/coreboot-v2/src/mainboard/supermicro/x6dai_g/Config.lb 2009-04-22 22:08:00 UTC (rev 4186) @@ -3,41 +3,9 @@ ## default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE -## -## Compute the location and size of where this firmware image -## (coreboot plus bootloader) will live in the boot rom chip. -## -if USE_FALLBACK_IMAGE - default ROM_SECTION_SIZE = FALLBACK_SIZE - default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE ) -else - default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE ) - default ROM_SECTION_OFFSET = 0 -end +include /config/nofailovercalculation128.lb ## -## Compute the start location and size size of -## The coreboot bootloader. -## -default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE ) -default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) - -## -## Compute where this copy of coreboot will start in the boot rom -## -default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE ) - -## -## Compute a range of ROM that can be cached to speed up coreboot, -## execution speed. -## -## XIP_ROM_SIZE must be a power of 2. -## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE -## -default XIP_ROM_SIZE=131072 -default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE ) - -## ## Set all of the defaults for an x86 architecture ## Modified: trunk/coreboot-v2/src/mainboard/supermicro/x6dhe_g/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/supermicro/x6dhe_g/Config.lb 2009-04-22 20:41:42 UTC (rev 4185) +++ trunk/coreboot-v2/src/mainboard/supermicro/x6dhe_g/Config.lb 2009-04-22 22:08:00 UTC (rev 4186) @@ -3,39 +3,8 @@ ## default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE -## -## Compute the location and size of where this firmware image -## (coreboot plus bootloader) will live in the boot rom chip. -## -if USE_FALLBACK_IMAGE - default ROM_SECTION_SIZE = FALLBACK_SIZE - default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE ) -else - default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE ) - default ROM_SECTION_OFFSET = 0 -end +include /config/nofailovercalculation128.lb -## -## Compute the start location and size size of -## The coreboot bootloader. -## -default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE ) -default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) - -## -## Compute where this copy of coreboot will start in the boot rom -## -default _ROMBASE =( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE ) - -## -## Compute a range of ROM that can be cached to speed up coreboot. -## execution speed. -## XIP_ROM_SIZE must be a power of 2. -## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE -default XIP_ROM_SIZE=131072 -default XIP_ROM_BASE= ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE ) - -## ## Set all of the defaults for an x86 architecture ## Modified: trunk/coreboot-v2/src/mainboard/supermicro/x6dhe_g2/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/supermicro/x6dhe_g2/Config.lb 2009-04-22 20:41:42 UTC (rev 4185) +++ trunk/coreboot-v2/src/mainboard/supermicro/x6dhe_g2/Config.lb 2009-04-22 22:08:00 UTC (rev 4186) @@ -3,39 +3,8 @@ ## default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE -## -## Compute the location and size of where this firmware image -## (coreboot plus bootloader) will live in the boot rom chip. -## -if USE_FALLBACK_IMAGE - default ROM_SECTION_SIZE = FALLBACK_SIZE - default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE ) -else - default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE ) - default ROM_SECTION_OFFSET = 0 -end +include /config/nofailovercalculation128.lb -## -## Compute the start location and size size of -## The coreboot bootloader. -## -default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE ) -default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) - -## -## Compute where this copy of coreboot will start in the boot rom -## -default _ROMBASE =( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE ) - -## -## Compute a range of ROM that can be cached to speed up coreboot. -## execution speed. -## XIP_ROM_SIZE must be a power of 2. -## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE -default XIP_ROM_SIZE=131072 -default XIP_ROM_BASE= ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE ) - -## ## Set all of the defaults for an x86 architecture ## Modified: trunk/coreboot-v2/src/mainboard/supermicro/x6dhr_ig/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/supermicro/x6dhr_ig/Config.lb 2009-04-22 20:41:42 UTC (rev 4185) +++ trunk/coreboot-v2/src/mainboard/supermicro/x6dhr_ig/Config.lb 2009-04-22 22:08:00 UTC (rev 4186) @@ -3,41 +3,9 @@ ## default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE -## -## Compute the location and size of where this firmware image -## (coreboot plus bootloader) will live in the boot rom chip. -## -if USE_FALLBACK_IMAGE - default ROM_SECTION_SIZE = FALLBACK_SIZE - default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE ) -else - default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE ) - default ROM_SECTION_OFFSET = 0 -end +include /config/nofailovercalculation128.lb ## -## Compute the start location and size size of -## The coreboot bootloader. -## -default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE ) -default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) - -## -## Compute where this copy of coreboot will start in the boot rom -## -default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE ) - -## -## Compute a range of ROM that can cached to speed up coreboot, -## execution speed. -## -## XIP_ROM_SIZE must be a power of 2. -## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE -## -default XIP_ROM_SIZE=131072 -default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE ) - -## ## Set all of the defaults for an x86 architecture ## Modified: trunk/coreboot-v2/src/mainboard/supermicro/x6dhr_ig2/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/supermicro/x6dhr_ig2/Config.lb 2009-04-22 20:41:42 UTC (rev 4185) +++ trunk/coreboot-v2/src/mainboard/supermicro/x6dhr_ig2/Config.lb 2009-04-22 22:08:00 UTC (rev 4186) @@ -3,41 +3,9 @@ ## default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE -## -## Compute the location and size of where this firmware image -## (coreboot plus bootloader) will live in the boot rom chip. -## -if USE_FALLBACK_IMAGE - default ROM_SECTION_SIZE = FALLBACK_SIZE - default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE ) -else - default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE ) - default ROM_SECTION_OFFSET = 0 -end +include /config/nofailovercalculation128.lb ## -## Compute the start location and size size of -## The coreboot bootloader. -## -default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE ) -default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) - -## -## Compute where this copy of coreboot will start in the boot rom -## -default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE ) - -## -## Compute a range of ROM that can cached to speed up coreboot, -## execution speed. -## -## XIP_ROM_SIZE must be a power of 2. -## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE -## -default XIP_ROM_SIZE=131072 -default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE ) - -## ## Set all of the defaults for an x86 architecture ##

1 0

build service results for r4184
by coreboot information 22 Apr '09

22 Apr '09

Dear coreboot readers! This is the automatic build system of coreboot. The developer "myles" checked in revision 4184 to the coreboot repository. This caused the following changes: Change Log: This patch adds the target hp/dl145_g3 together with the appropriate mainboard sources. Signed-off-by: Mondrian nuessle <nuessle(a)uni-hd.de> Acked-by: Samuel Verstraete <samuel.verstraete(a)gmail.com> I updated some whitespace and the Config files. - Myles Build Log: Compilation of hp:dl145_g3 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4184&device=dl145_g3&vendo… If something broke during this checkin please be a pain in myles's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

2 1

[PATCH] flashrom: Reflect generic match status more accurately
by Carl-Daniel Hailfinger 22 Apr '09

22 Apr '09

All "unknown xy SPI chip" entries claim to have status UNTESTED for probe/read/erase/write. That is incorrect. A bit of confusion comes from how the #defines are named. We call them TEST_BAD_*, but the message printed by flashrom says: "This flash part has status NOT WORKING for operations:" Something that is unimplemented is definitely not working. Neither of the chip entries mentioned above has erase or write functions implemented, so erase and write are not working. Since their size is unknown, we can't read them in. That means read is not working as well. Probing is a different matter. If a chip-specific probe function had matched, we wouldn't have to handle the chip with the "unknown xy SPI chip" fallback. I'm tempted to call that "not working" as well, but I'm open to discussion on this point. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: flashrom-test_bad/flashchips.c =================================================================== --- flashrom-test_bad/flashchips.c (Revision 4162) +++ flashrom-test_bad/flashchips.c (Arbeitskopie) @@ -2167,7 +2167,7 @@ .model_id = GENERIC_DEVICE_ID, .total_size = 0, .page_size = 256, - .tested = TEST_UNTESTED, + .tested = TEST_BAD_PREW, .probe = probe_spi_rdid, .erase = NULL, .write = NULL, @@ -2180,7 +2180,7 @@ .model_id = GENERIC_DEVICE_ID, .total_size = 0, .page_size = 256, - .tested = TEST_UNTESTED, + .tested = TEST_BAD_PREW, .probe = probe_spi_rdid, .erase = NULL, .write = NULL, @@ -2193,7 +2193,7 @@ .model_id = GENERIC_DEVICE_ID, .total_size = 0, .page_size = 256, - .tested = TEST_UNTESTED, + .tested = TEST_BAD_PREW, .probe = probe_spi_rdid, .erase = NULL, .write = NULL, @@ -2206,7 +2206,7 @@ .model_id = GENERIC_DEVICE_ID, .total_size = 0, .page_size = 256, - .tested = TEST_UNTESTED, + .tested = TEST_BAD_PREW, .probe = probe_spi_rdid, .erase = NULL, .write = NULL, @@ -2219,7 +2219,7 @@ .model_id = GENERIC_DEVICE_ID, .total_size = 0, .page_size = 256, - .tested = TEST_UNTESTED, + .tested = TEST_BAD_PREW, .probe = probe_spi_rdid, .erase = NULL, .write = NULL, @@ -2232,7 +2232,7 @@ .model_id = GENERIC_DEVICE_ID, .total_size = 0, .page_size = 256, - .tested = TEST_UNTESTED, + .tested = TEST_BAD_PREW, .probe = probe_spi_rdid, .erase = NULL, .write = NULL, -- http://www.hailfinger.org/ Index: flashrom-test_bad/flashchips.c =================================================================== --- flashrom-test_bad/flashchips.c (Revision 4162) +++ flashrom-test_bad/flashchips.c (Arbeitskopie) @@ -2167,7 +2167,7 @@ .model_id = GENERIC_DEVICE_ID, .total_size = 0, .page_size = 256, - .tested = TEST_UNTESTED, + .tested = TEST_BAD_PREW, .probe = probe_spi_rdid, .erase = NULL, .write = NULL, @@ -2180,7 +2180,7 @@ .model_id = GENERIC_DEVICE_ID, .total_size = 0, .page_size = 256, - .tested = TEST_UNTESTED, + .tested = TEST_BAD_PREW, .probe = probe_spi_rdid, .erase = NULL, .write = NULL, @@ -2193,7 +2193,7 @@ .model_id = GENERIC_DEVICE_ID, .total_size = 0, .page_size = 256, - .tested = TEST_UNTESTED, + .tested = TEST_BAD_PREW, .probe = probe_spi_rdid, .erase = NULL, .write = NULL, @@ -2206,7 +2206,7 @@ .model_id = GENERIC_DEVICE_ID, .total_size = 0, .page_size = 256, - .tested = TEST_UNTESTED, + .tested = TEST_BAD_PREW, .probe = probe_spi_rdid, .erase = NULL, .write = NULL, @@ -2219,7 +2219,7 @@ .model_id = GENERIC_DEVICE_ID, .total_size = 0, .page_size = 256, - .tested = TEST_UNTESTED, + .tested = TEST_BAD_PREW, .probe = probe_spi_rdid, .erase = NULL, .write = NULL, @@ -2232,7 +2232,7 @@ .model_id = GENERIC_DEVICE_ID, .total_size = 0, .page_size = 256, - .tested = TEST_UNTESTED, + .tested = TEST_BAD_PREW, .probe = probe_spi_rdid, .erase = NULL, .write = NULL,

3 4

[v2] r4185 - trunk/coreboot-v2/src/mainboard/hp/dl145_g3
by svn＠coreboot.org 22 Apr '09

22 Apr '09

Author: myles Date: 2009-04-22 22:41:42 +0200 (Wed, 22 Apr 2009) New Revision: 4185 Modified: trunk/coreboot-v2/src/mainboard/hp/dl145_g3/cache_as_ram_auto.c Log: Trivial patch. I forgot to update K8_SET_FIDVID. Signed-off-by: Myles Watson <mylesgw(a)gmail.com> Acked-by: Myles Watson <mylesgw(a)gmail.com> Modified: trunk/coreboot-v2/src/mainboard/hp/dl145_g3/cache_as_ram_auto.c =================================================================== --- trunk/coreboot-v2/src/mainboard/hp/dl145_g3/cache_as_ram_auto.c 2009-04-22 20:34:05 UTC (rev 4184) +++ trunk/coreboot-v2/src/mainboard/hp/dl145_g3/cache_as_ram_auto.c 2009-04-22 20:41:42 UTC (rev 4185) @@ -40,7 +40,7 @@ #endif //used by init_cpus and fidvid -#define K8_SET_FIDVID 0 +#define K8_SET_FIDVID 1 //if we want to wait for core1 done before DQS training, set it to 0 #define K8_SET_FIDVID_CORE0_ONLY 1

1 0

[PATCH] First support for HP DL145 G3
by Mondrian Nuessle 22 Apr '09

22 Apr '09

Hi everybody, I prepared an initial set of patches to support the HP DL145 G3 server, which is a Broadcom HT-1000/HT-2100 based Socket F machine. The current status of the port is: * we have serial output (using the serverengines pilot chip on the board, see attached pilot_superio.patch) * CPU and memory gets initialized * on-board eth0 is working * SATA is working * the on-board graphic was not tested (not important for a server and the graphics sucks anyway...) * USB and PS2 work * no ACPI * I remember that I could also use a PCIe card, see attached bcm21000.patch * HTX card does work. * Earlier problems we had in respect to timer interrupt are not there anymore. * the hp_dl145_g3.patch includes the mainboard and the target dirs BUT: * if I coldboot, the CPUs are only running at 1 GHz and not with 2.6 GHz as they should... * if we boot the factory BIOS and then perform a warm-reset into Coreboot, the CPUs run with 2.6 GHz. I hope someone on the list can help. * There are also some more problems with the HT-1000 (aka bcm5785) southbridge: - if I activate IDE in bcm5785_early_setup.c, the machine will freeze shortly after being completely booted - if I activate the second IOAPIC (line 179 in bcm5785_early_setup.c), my linux boot hangs when starting udevd... - with both features disabled (see attached bcm5785_noide.patch), the machine boots and does not crash, of course PATA drives are not available. To boot the machine, I tested FILO. The on-board SATA adapter uses a class id of 0x104 in sata mode (which we use). FILO does not accept this class ID; I prepared a patch that adds this class ID to the respective if statement in driver/ide.c. FILO does then boot from SATA without any problems (see attached filo_dl145_sata.patch). I hope this gets you started Samuel, and I hope the list can provide some insight regarding the CPU frequency problem. Regards, Mondrian -- Dr. Mondrian Nuessle Phone: +49 621 181 2717 University of Heidelberg Fax: +49 621 181 2713 Computer Architecture Group mailto:nuessle@uni-hd.de http://ra.ziti.uni-heidelberg.de

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coreboot April 2009