coreboot April 2009

coreboot@coreboot.org

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583 discussions

[v2] r4178 - trunk/coreboot-v2/targets/msi/ms9282
by svn＠coreboot.org 22 Apr '09

22 Apr '09

Author: stepan Date: 2009-04-22 17:49:28 +0200 (Wed, 22 Apr 2009) New Revision: 4178 Modified: trunk/coreboot-v2/targets/msi/ms9282/Config-abuild.lb Log: increase rom sizes for abuild Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/coreboot-v2/targets/msi/ms9282/Config-abuild.lb =================================================================== --- trunk/coreboot-v2/targets/msi/ms9282/Config-abuild.lb 2009-04-22 13:33:43 UTC (rev 4177) +++ trunk/coreboot-v2/targets/msi/ms9282/Config-abuild.lb 2009-04-22 15:49:28 UTC (rev 4178) @@ -12,14 +12,14 @@ romimage "normal" option USE_FALLBACK_IMAGE=0 - option ROM_IMAGE_SIZE = 96 * 1024 + option ROM_IMAGE_SIZE = 128 * 1024 option COREBOOT_EXTRA_VERSION=".0-normal" payload __PAYLOAD__ end romimage "fallback" option USE_FALLBACK_IMAGE=1 - option ROM_IMAGE_SIZE = 96 * 1024 + option ROM_IMAGE_SIZE = 128 * 1024 option COREBOOT_EXTRA_VERSION=".0-fallback" payload __PAYLOAD__ end

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build service results for r4177
by coreboot information 22 Apr '09

22 Apr '09

Dear coreboot readers! This is the automatic build system of coreboot. The developer "hailfinger" checked in revision 4177 to the coreboot repository. This caused the following changes: Change Log: All "unknown xy SPI chip" entries claim to have status UNTESTED for probe/read/erase/write. That is incorrect. A bit of confusion comes from how the #defines are named. We call them TEST_BAD_*, but the message printed by flashrom says: "This flash part has status NOT WORKING for operations:" Something that is unimplemented is definitely not working. Neither of the chip entries mentioned above has erase or write functions implemented, so erase and write are not working. Since their size is unknown, we can't read them in. That means read is not working as well. Probing is a different matter. If a chip-specific probe function had matched, we wouldn't have to handle the chip with the "unknown xy SPI chip" fallback. I'm tempted to call that "not working" as well, but I'm open to discussion on this point. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Build Log: Compilation of msi:ms9282 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4177&device=ms9282&vendor=… If something broke during this checkin please be a pain in hailfinger's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

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build service results for r4176
by coreboot information 22 Apr '09

22 Apr '09

Dear coreboot readers! This is the automatic build system of coreboot. The developer "stepan" checked in revision 4176 to the coreboot repository. This caused the following changes: Change Log: drop unused variable. Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Build Log: Compilation of msi:ms9282 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4176&device=ms9282&vendor=… If something broke during this checkin please be a pain in stepan's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

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build service results for r4175
by coreboot information 22 Apr '09

22 Apr '09

Dear coreboot readers! This is the automatic build system of coreboot. The developer "stepan" checked in revision 4175 to the coreboot repository. This caused the following changes: Change Log: no duplicate names in cmos.layout allowed. (fixes a bunch of boards) Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Build Log: Compilation of dell:s1850 has been fixed Compilation of intel:jarrell has been fixed Compilation of msi:ms9282 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4175&device=ms9282&vendor=… Compilation of supermicro:x6dai_g has been fixed Compilation of supermicro:x6dhe_g has been fixed Compilation of supermicro:x6dhe_g2 has been fixed Compilation of supermicro:x6dhr_ig has been fixed Compilation of supermicro:x6dhr_ig2 has been fixed If something broke during this checkin please be a pain in stepan's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

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[v2] r4177 - trunk/util/flashrom
by svn＠coreboot.org 22 Apr '09

22 Apr '09

Author: hailfinger Date: 2009-04-22 15:33:43 +0200 (Wed, 22 Apr 2009) New Revision: 4177 Modified: trunk/util/flashrom/flashchips.c Log: All "unknown xy SPI chip" entries claim to have status UNTESTED for probe/read/erase/write. That is incorrect. A bit of confusion comes from how the #defines are named. We call them TEST_BAD_*, but the message printed by flashrom says: "This flash part has status NOT WORKING for operations:" Something that is unimplemented is definitely not working. Neither of the chip entries mentioned above has erase or write functions implemented, so erase and write are not working. Since their size is unknown, we can't read them in. That means read is not working as well. Probing is a different matter. If a chip-specific probe function had matched, we wouldn't have to handle the chip with the "unknown xy SPI chip" fallback. I'm tempted to call that "not working" as well, but I'm open to discussion on this point. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Modified: trunk/util/flashrom/flashchips.c =================================================================== --- trunk/util/flashrom/flashchips.c 2009-04-22 12:38:23 UTC (rev 4176) +++ trunk/util/flashrom/flashchips.c 2009-04-22 13:33:43 UTC (rev 4177) @@ -2167,7 +2167,7 @@ .model_id = GENERIC_DEVICE_ID, .total_size = 0, .page_size = 256, - .tested = TEST_UNTESTED, + .tested = TEST_BAD_PREW, .probe = probe_spi_rdid, .erase = NULL, .write = NULL, @@ -2180,7 +2180,7 @@ .model_id = GENERIC_DEVICE_ID, .total_size = 0, .page_size = 256, - .tested = TEST_UNTESTED, + .tested = TEST_BAD_PREW, .probe = probe_spi_rdid, .erase = NULL, .write = NULL, @@ -2193,7 +2193,7 @@ .model_id = GENERIC_DEVICE_ID, .total_size = 0, .page_size = 256, - .tested = TEST_UNTESTED, + .tested = TEST_BAD_PREW, .probe = probe_spi_rdid, .erase = NULL, .write = NULL, @@ -2206,7 +2206,7 @@ .model_id = GENERIC_DEVICE_ID, .total_size = 0, .page_size = 256, - .tested = TEST_UNTESTED, + .tested = TEST_BAD_PREW, .probe = probe_spi_rdid, .erase = NULL, .write = NULL, @@ -2219,7 +2219,7 @@ .model_id = GENERIC_DEVICE_ID, .total_size = 0, .page_size = 256, - .tested = TEST_UNTESTED, + .tested = TEST_BAD_PREW, .probe = probe_spi_rdid, .erase = NULL, .write = NULL, @@ -2232,7 +2232,7 @@ .model_id = GENERIC_DEVICE_ID, .total_size = 0, .page_size = 256, - .tested = TEST_UNTESTED, + .tested = TEST_BAD_PREW, .probe = probe_spi_rdid, .erase = NULL, .write = NULL,

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[PATCH] inteltool: E7505 and XEON (F2) support
by Raphaël Doursenaud 22 Apr '09

22 Apr '09

-----BEGIN PGP SIGNED MESSAGE----- Hash: SHA1 Hi, This will be my first contribution to the coreboot project. I have a bunch of HP xw8000 workstations lying around and I want to give it a try. This patch hopefully adds support for the E7505 northbridge and the Xeon (F2 model Pentium 4 like) processor to inteltool. Everything comes directly from Intel's datasheets. Please review it. Regards, - -- Raphaël Doursenaud -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.9 (GNU/Linux) Comment: Using GnuPG with Mozilla - http://enigmail.mozdev.org iEYEARECAAYFAknvGzAACgkQaZKmNAdXaVWUwwCgrgOMpBn/J6hFzm13DCEc7jME C/gAoIvfpT/f1vC1XFjnZ+n04S5jtBUC =/qaC -----END PGP SIGNATURE-----

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build service results for r4174
by coreboot information 22 Apr '09

22 Apr '09

Dear coreboot readers! This is the automatic build system of coreboot. The developer "uwe" checked in revision 4174 to the coreboot repository. This caused the following changes: Change Log: Quick 'indent' run on ectool with some additional manual cosmetic fixes. Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Build Log: Compilation of dell:s1850 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4174&device=s1850&vendor=d… Compilation of intel:jarrell is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4174&device=jarrell&vendor… Compilation of msi:ms9282 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4174&device=ms9282&vendor=… Compilation of supermicro:x6dai_g is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4174&device=x6dai_g&vendor… Compilation of supermicro:x6dhe_g is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4174&device=x6dhe_g&vendor… Compilation of supermicro:x6dhe_g2 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4174&device=x6dhe_g2&vendo… Compilation of supermicro:x6dhr_ig is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4174&device=x6dhr_ig&vendo… Compilation of supermicro:x6dhr_ig2 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4174&device=x6dhr_ig2&vend… If something broke during this checkin please be a pain in uwe's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

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build service results for r4173
by coreboot information 22 Apr '09

22 Apr '09

Dear coreboot readers! This is the automatic build system of coreboot. The developer "stepan" checked in revision 4173 to the coreboot repository. This caused the following changes: Change Log: don't ignore return values (trivial) Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Build Log: Compilation of dell:s1850 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4173&device=s1850&vendor=d… Compilation of intel:jarrell is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4173&device=jarrell&vendor… Compilation of msi:ms9282 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4173&device=ms9282&vendor=… Compilation of supermicro:x6dai_g is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4173&device=x6dai_g&vendor… Compilation of supermicro:x6dhe_g is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4173&device=x6dhe_g&vendor… Compilation of supermicro:x6dhe_g2 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4173&device=x6dhe_g2&vendo… Compilation of supermicro:x6dhr_ig is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4173&device=x6dhr_ig&vendo… Compilation of supermicro:x6dhr_ig2 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4173&device=x6dhr_ig2&vend… If something broke during this checkin please be a pain in stepan's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

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#128: Improve email user interface for trac
by coreboot 22 Apr '09

22 Apr '09

#128: Improve email user interface for trac ------------------------------------+--------------------------------------- Reporter: stuge | Owner: somebody Type: enhancement | Status: new Priority: major | Milestone: Component: wiki/website/tracker | Version: Keywords: trac email | Dependencies: Patchstatus: there is no patch | ------------------------------------+--------------------------------------- There is a tendency to try to use the mailing list for tracking issues and patches among many members of the project. To avoid that issues are forgotten after a few weeks it makes a lot of sense to file tickets for them in the tracker. Any web based tracker is however available only when online, and that does not fit everyone's workflow. It would be mighty nice to improve the tracker (maybe there are plugins to solve this already) so that email could be used for most tracker tasks: * Create new ticket and handle attachments (important for patches) * Add attachments to existing tickets * Comment on existing tickets * Change ticket properties (type/prio/mile/keywords/cc/deps/patch status/assign) I believe some of this works already, but I don't know how. Help? Does someone know where to find a reference or manual? Thanks! -- Ticket URL: <http://tracker.coreboot.org/trac/coreboot/ticket/128> coreboot <http://www.coreboot.org/>

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[v2] r4176 - trunk/coreboot-v2/src/arch/i386/boot
by svn＠coreboot.org 22 Apr '09

22 Apr '09

Author: stepan Date: 2009-04-22 14:38:23 +0200 (Wed, 22 Apr 2009) New Revision: 4176 Modified: trunk/coreboot-v2/src/arch/i386/boot/boot.c Log: drop unused variable. Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/coreboot-v2/src/arch/i386/boot/boot.c =================================================================== --- trunk/coreboot-v2/src/arch/i386/boot/boot.c 2009-04-22 12:35:57 UTC (rev 4175) +++ trunk/coreboot-v2/src/arch/i386/boot/boot.c 2009-04-22 12:38:23 UTC (rev 4176) @@ -73,12 +73,10 @@ extern unsigned char _ram_seg, _eram_seg; unsigned long lb_start, lb_size; unsigned long adjust, adjusted_boot_notes; - unsigned long type; elf_boot_notes.hdr.b_checksum = compute_ip_checksum(&elf_boot_notes, sizeof(elf_boot_notes)); - type = 0x0E1FB007; lb_start = (unsigned long)&_ram_seg; lb_size = (unsigned long)(&_eram_seg - &_ram_seg); adjust = buffer + lb_size - lb_start;

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coreboot April 2009