coreboot April 2009

coreboot@coreboot.org

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583 discussions

[v2] r4170 - in trunk/coreboot-v2: src/include/boot src/pc80 util/options
by svn＠coreboot.org 22 Apr '09

22 Apr '09

Author: stepan Date: 2009-04-22 11:03:08 +0200 (Wed, 22 Apr 2009) New Revision: 4170 Modified: trunk/coreboot-v2/src/include/boot/coreboot_tables.h trunk/coreboot-v2/src/pc80/mc146818rtc.c trunk/coreboot-v2/src/pc80/mc146818rtc_early.c trunk/coreboot-v2/util/options/build_opt_tbl.c Log: * Allow coreboot to use the full 256 bytes of CMOS memory * Make functions out of the accessor macros in mc146818rtc.c * don't hide reserved cmos entries from coreboot, only from the user. Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Modified: trunk/coreboot-v2/src/include/boot/coreboot_tables.h =================================================================== --- trunk/coreboot-v2/src/include/boot/coreboot_tables.h 2009-04-22 08:56:50 UTC (rev 4169) +++ trunk/coreboot-v2/src/include/boot/coreboot_tables.h 2009-04-22 09:03:08 UTC (rev 4170) @@ -223,7 +223,7 @@ uint32_t size; /* length of this record */ uint32_t name_length; /* length of the following name field */ uint8_t name[CMOS_MAX_NAME_LENGTH]; /* name identifying the default */ -#define CMOS_IMAGE_BUFFER_SIZE 128 +#define CMOS_IMAGE_BUFFER_SIZE 256 uint8_t default_set[CMOS_IMAGE_BUFFER_SIZE]; /* default settings */ }; Modified: trunk/coreboot-v2/src/pc80/mc146818rtc.c =================================================================== --- trunk/coreboot-v2/src/pc80/mc146818rtc.c 2009-04-22 08:56:50 UTC (rev 4169) +++ trunk/coreboot-v2/src/pc80/mc146818rtc.c 2009-04-22 09:03:08 UTC (rev 4170) @@ -4,16 +4,6 @@ #include <boot/coreboot_tables.h> #include <string.h> -#define CMOS_READ(addr) ({ \ -outb((addr),RTC_PORT(0)); \ -inb(RTC_PORT(1)); \ -}) - -#define CMOS_WRITE(val, addr) ({ \ -outb((addr),RTC_PORT(0)); \ -outb((val),RTC_PORT(1)); \ -}) - /* control registers - Moto names */ #define RTC_REG_A 10 @@ -83,7 +73,27 @@ # define RTC_VRT 0x80 /* valid RAM and time */ /**********************************************************************/ +static inline unsigned char cmos_read(unsigned char addr) +{ + int offs = 0; + if (addr >= 128) { + offs = 2; + addr -= 128; + } + outb(addr, RTC_BASE_PORT + offs + 0); + return inb(RTC_BASE_PORT + offs + 1); +} +static inline void cmos_write(unsigned char val, unsigned char addr) +{ + int offs = 0; + if (addr >= 128) { + offs = 2; + addr -= 128; + } + outb(addr, RTC_BASE_PORT + offs + 0); + outb(val, RTC_BASE_PORT + offs + 1); +} static int rtc_checksum_valid(int range_start, int range_end, int cks_loc) { @@ -91,10 +101,10 @@ unsigned sum, old_sum; sum = 0; for(i = range_start; i <= range_end; i++) { - sum += CMOS_READ(i); + sum += cmos_read(i); } sum = (~sum)&0x0ffff; - old_sum = ((CMOS_READ(cks_loc)<<8) | CMOS_READ(cks_loc+1))&0x0ffff; + old_sum = ((cmos_read(cks_loc)<<8) | cmos_read(cks_loc+1))&0x0ffff; return sum == old_sum; } @@ -104,11 +114,11 @@ unsigned sum; sum = 0; for(i = range_start; i <= range_end; i++) { - sum += CMOS_READ(i); + sum += cmos_read(i); } sum = ~(sum & 0x0ffff); - CMOS_WRITE(((sum >> 8) & 0x0ff), cks_loc); - CMOS_WRITE(((sum >> 0) & 0x0ff), cks_loc+1); + cmos_write(((sum >> 8) & 0x0ff), cks_loc); + cmos_write(((sum >> 0) & 0x0ff), cks_loc+1); } #define RTC_CONTROL_DEFAULT (RTC_24H) @@ -130,7 +140,7 @@ #if HAVE_OPTION_TABLE /* See if there has been a CMOS power problem. */ - x = CMOS_READ(RTC_VALID); + x = cmos_read(RTC_VALID); cmos_invalid = !(x & RTC_VRT); /* See if there is a CMOS checksum error */ @@ -143,31 +153,31 @@ cmos_invalid?" Power Problem":"", checksum_invalid?" Checksum invalid":""); #if 0 - CMOS_WRITE(0, 0x01); - CMOS_WRITE(0, 0x03); - CMOS_WRITE(0, 0x05); + cmos_write(0, 0x01); + cmos_write(0, 0x03); + cmos_write(0, 0x05); for(i = 10; i < 48; i++) { - CMOS_WRITE(0, i); + cmos_write(0, i); } if (cmos_invalid) { /* Now setup a default date of Sat 1 January 2000 */ - CMOS_WRITE(0, 0x00); /* seconds */ - CMOS_WRITE(0, 0x02); /* minutes */ - CMOS_WRITE(1, 0x04); /* hours */ - CMOS_WRITE(7, 0x06); /* day of week */ - CMOS_WRITE(1, 0x07); /* day of month */ - CMOS_WRITE(1, 0x08); /* month */ - CMOS_WRITE(0, 0x09); /* year */ + cmos_write(0, 0x00); /* seconds */ + cmos_write(0, 0x02); /* minutes */ + cmos_write(1, 0x04); /* hours */ + cmos_write(7, 0x06); /* day of week */ + cmos_write(1, 0x07); /* day of month */ + cmos_write(1, 0x08); /* month */ + cmos_write(0, 0x09); /* year */ } #endif } #endif /* Setup the real time clock */ - CMOS_WRITE(RTC_CONTROL_DEFAULT, RTC_CONTROL); + cmos_write(RTC_CONTROL_DEFAULT, RTC_CONTROL); /* Setup the frequency it operates at */ - CMOS_WRITE(RTC_FREQ_SELECT_DEFAULT, RTC_FREQ_SELECT); + cmos_write(RTC_FREQ_SELECT_DEFAULT, RTC_FREQ_SELECT); #if HAVE_OPTION_TABLE /* See if there is a LB CMOS checksum error */ @@ -182,7 +192,7 @@ #endif /* Clear any pending interrupts */ - (void) CMOS_READ(RTC_INTR_FLAGS); + (void) cmos_read(RTC_INTR_FLAGS); } @@ -207,7 +217,7 @@ byte=bit/8; /* find the byte where the data starts */ byte_bit=bit%8; /* find the bit in the byte where the data starts */ if(length<9) { /* one byte or less */ - uchar = CMOS_READ(byte); /* load the byte */ + uchar = cmos_read(byte); /* load the byte */ uchar >>= byte_bit; /* shift the bits to byte align */ /* clear unspecified bits */ ret[0] = uchar & ((1 << length) -1); @@ -215,7 +225,7 @@ else { /* more that one byte so transfer the whole bytes */ for(i=0;length;i++,length-=8,byte++) { /* load the byte */ - ret[i]=CMOS_READ(byte); + ret[i]=cmos_read(byte); } } return 0; Modified: trunk/coreboot-v2/src/pc80/mc146818rtc_early.c =================================================================== --- trunk/coreboot-v2/src/pc80/mc146818rtc_early.c 2009-04-22 08:56:50 UTC (rev 4169) +++ trunk/coreboot-v2/src/pc80/mc146818rtc_early.c 2009-04-22 09:03:08 UTC (rev 4170) @@ -10,14 +10,24 @@ static unsigned char cmos_read(unsigned char addr) { - outb(addr, RTC_BASE_PORT + 0); - return inb(RTC_BASE_PORT + 1); + int offs = 0; + if (addr >= 128) { + offs = 2; + addr -= 128; + } + outb(addr, RTC_BASE_PORT + offs + 0); + return inb(RTC_BASE_PORT + offs + 1); } static void cmos_write(unsigned char val, unsigned char addr) { - outb(addr, RTC_BASE_PORT + 0); - outb(val, RTC_BASE_PORT + 1); + int offs = 0; + if (addr >= 128) { + offs = 2; + addr -= 128; + } + outb(addr, RTC_BASE_PORT + offs + 0); + outb(val, RTC_BASE_PORT + offs + 1); } static int cmos_error(void) Modified: trunk/coreboot-v2/util/options/build_opt_tbl.c =================================================================== --- trunk/coreboot-v2/util/options/build_opt_tbl.c 2009-04-22 08:56:50 UTC (rev 4169) +++ trunk/coreboot-v2/util/options/build_opt_tbl.c 2009-04-22 09:03:08 UTC (rev 4170) @@ -8,7 +8,7 @@ #include "../../src/include/pc80/mc146818rtc.h" #include "../../src/include/boot/coreboot_tables.h" -#define CMOS_IMAGE_BUFFER_SIZE 128 +#define CMOS_IMAGE_BUFFER_SIZE 256 #define INPUT_LINE_MAX 256 #define MAX_VALUE_BYTE_LENGTH 64 @@ -563,9 +563,7 @@ continue; } ce = (struct cmos_entries *)ptr; - if (ce->config == 'r') { - continue; - } + if (!is_ident((char *)ce->name)) { fprintf(stderr, "Invalid identifier: %s\n", ce->name);

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[v2] r4169 - in trunk/coreboot-v2/src: cpu/intel cpu/intel/socket_mPGA604 mainboard/dell/s1850 mainboard/intel/jarrell mainboard/intel/xe7501devkit mainboard/supermicro/x6dai_g mainboard/supermicro/x6dhe_g mainboard/supermicro/x6dhe_g2 mainboard/supermicro/x6dhr_ig mainboard/supermicro/x6dhr_ig2 mainboard/tyan/s2735
by svn＠coreboot.org 22 Apr '09

22 Apr '09

Author: stepan Date: 2009-04-22 10:56:50 +0200 (Wed, 22 Apr 2009) New Revision: 4169 Added: trunk/coreboot-v2/src/cpu/intel/socket_mPGA604/ trunk/coreboot-v2/src/cpu/intel/socket_mPGA604/Config.lb trunk/coreboot-v2/src/cpu/intel/socket_mPGA604/chip.h trunk/coreboot-v2/src/cpu/intel/socket_mPGA604/socket_mPGA604.c Removed: trunk/coreboot-v2/src/cpu/intel/socket_mPGA604_533Mhz/ trunk/coreboot-v2/src/cpu/intel/socket_mPGA604_800Mhz/ Modified: trunk/coreboot-v2/src/mainboard/dell/s1850/Config.lb trunk/coreboot-v2/src/mainboard/intel/jarrell/Config.lb trunk/coreboot-v2/src/mainboard/intel/xe7501devkit/Config.lb trunk/coreboot-v2/src/mainboard/supermicro/x6dai_g/Config.lb trunk/coreboot-v2/src/mainboard/supermicro/x6dhe_g/Config.lb trunk/coreboot-v2/src/mainboard/supermicro/x6dhe_g2/Config.lb trunk/coreboot-v2/src/mainboard/supermicro/x6dhr_ig/Config.lb trunk/coreboot-v2/src/mainboard/supermicro/x6dhr_ig2/Config.lb trunk/coreboot-v2/src/mainboard/tyan/s2735/Config.lb Log: This patch unifies the socket_mPGA604_800Mhz and socket_mPGA604_533Mhz to a combined socket_mPGA604. No other sockets come with clock rates, and there is no difference in code, except for the number of microcode patches included in a build. Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Added: trunk/coreboot-v2/src/cpu/intel/socket_mPGA604/Config.lb =================================================================== --- trunk/coreboot-v2/src/cpu/intel/socket_mPGA604/Config.lb (rev 0) +++ trunk/coreboot-v2/src/cpu/intel/socket_mPGA604/Config.lb 2009-04-22 08:56:50 UTC (rev 4169) @@ -0,0 +1,5 @@ +config chip.h +object socket_mPGA604.o +dir /cpu/intel/model_f2x +dir /cpu/intel/model_f3x +dir /cpu/intel/model_f4x Added: trunk/coreboot-v2/src/cpu/intel/socket_mPGA604/chip.h =================================================================== --- trunk/coreboot-v2/src/cpu/intel/socket_mPGA604/chip.h (rev 0) +++ trunk/coreboot-v2/src/cpu/intel/socket_mPGA604/chip.h 2009-04-22 08:56:50 UTC (rev 4169) @@ -0,0 +1,4 @@ +extern struct chip_operations cpu_intel_socket_mPGA604_800Mhz_ops; + +struct cpu_intel_socket_mPGA604_800Mhz_config { +}; Added: trunk/coreboot-v2/src/cpu/intel/socket_mPGA604/socket_mPGA604.c =================================================================== --- trunk/coreboot-v2/src/cpu/intel/socket_mPGA604/socket_mPGA604.c (rev 0) +++ trunk/coreboot-v2/src/cpu/intel/socket_mPGA604/socket_mPGA604.c 2009-04-22 08:56:50 UTC (rev 4169) @@ -0,0 +1,7 @@ +#include <device/device.h> +#include "chip.h" + + +struct chip_operations cpu_intel_socket_mPGA604_800Mhz_ops = { + CHIP_NAME("Socket mPGA604 CPU") +}; Modified: trunk/coreboot-v2/src/mainboard/dell/s1850/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/dell/s1850/Config.lb 2009-04-22 08:18:37 UTC (rev 4168) +++ trunk/coreboot-v2/src/mainboard/dell/s1850/Config.lb 2009-04-22 08:56:50 UTC (rev 4169) @@ -193,10 +193,10 @@ device pci 06.0 on end end device apic_cluster 0 on - chip cpu/intel/socket_mPGA604_800Mhz # cpu 0 + chip cpu/intel/socket_mPGA604 # cpu 0 device apic 0 on end end - chip cpu/intel/socket_mPGA604_800Mhz # cpu 1 + chip cpu/intel/socket_mPGA604 # cpu 1 device apic 6 on end end end Modified: trunk/coreboot-v2/src/mainboard/intel/jarrell/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/intel/jarrell/Config.lb 2009-04-22 08:18:37 UTC (rev 4168) +++ trunk/coreboot-v2/src/mainboard/intel/jarrell/Config.lb 2009-04-22 08:56:50 UTC (rev 4169) @@ -203,10 +203,10 @@ end end device apic_cluster 0 on - chip cpu/intel/socket_mPGA604_800Mhz # cpu 0 + chip cpu/intel/socket_mPGA604 # cpu 0 device apic 0 on end end - chip cpu/intel/socket_mPGA604_800Mhz # cpu 1 + chip cpu/intel/socket_mPGA604 # cpu 1 device apic 6 on end end end Modified: trunk/coreboot-v2/src/mainboard/intel/xe7501devkit/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/intel/xe7501devkit/Config.lb 2009-04-22 08:18:37 UTC (rev 4168) +++ trunk/coreboot-v2/src/mainboard/intel/xe7501devkit/Config.lb 2009-04-22 08:56:50 UTC (rev 4169) @@ -212,10 +212,10 @@ end # SB end # PCI_DOMAIN device apic_cluster 0 on - chip cpu/intel/socket_mPGA604_533Mhz + chip cpu/intel/socket_mPGA604 device apic 0 on end end - chip cpu/intel/socket_mPGA604_533Mhz + chip cpu/intel/socket_mPGA604 device apic 6 on end end end Modified: trunk/coreboot-v2/src/mainboard/supermicro/x6dai_g/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/supermicro/x6dai_g/Config.lb 2009-04-22 08:18:37 UTC (rev 4168) +++ trunk/coreboot-v2/src/mainboard/supermicro/x6dai_g/Config.lb 2009-04-22 08:56:50 UTC (rev 4169) @@ -187,10 +187,10 @@ device pci 08.0 on end end device apic_cluster 0 on - chip cpu/intel/socket_mPGA604_800Mhz # cpu0 + chip cpu/intel/socket_mPGA604 # cpu0 device apic 0 on end end - chip cpu/intel/socket_mPGA604_800Mhz # cpu1 + chip cpu/intel/socket_mPGA604 # cpu1 device apic 6 on end end end Modified: trunk/coreboot-v2/src/mainboard/supermicro/x6dhe_g/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/supermicro/x6dhe_g/Config.lb 2009-04-22 08:18:37 UTC (rev 4168) +++ trunk/coreboot-v2/src/mainboard/supermicro/x6dhe_g/Config.lb 2009-04-22 08:56:50 UTC (rev 4169) @@ -210,10 +210,10 @@ end device apic_cluster 0 on - chip cpu/intel/socket_mPGA604_800Mhz # CPU 0 + chip cpu/intel/socket_mPGA604 # CPU 0 device apic 0 on end end - chip cpu/intel/socket_mPGA604_800Mhz # CPU 1 + chip cpu/intel/socket_mPGA604 # CPU 1 device apic 6 on end end end Modified: trunk/coreboot-v2/src/mainboard/supermicro/x6dhe_g2/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/supermicro/x6dhe_g2/Config.lb 2009-04-22 08:18:37 UTC (rev 4168) +++ trunk/coreboot-v2/src/mainboard/supermicro/x6dhe_g2/Config.lb 2009-04-22 08:56:50 UTC (rev 4169) @@ -210,10 +210,10 @@ end device apic_cluster 0 on - chip cpu/intel/socket_mPGA604_800Mhz # CPU 0 + chip cpu/intel/socket_mPGA604 # CPU 0 device apic 0 on end end - chip cpu/intel/socket_mPGA604_800Mhz # CPU 1 + chip cpu/intel/socket_mPGA604 # CPU 1 device apic 6 on end end end Modified: trunk/coreboot-v2/src/mainboard/supermicro/x6dhr_ig/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/supermicro/x6dhr_ig/Config.lb 2009-04-22 08:18:37 UTC (rev 4168) +++ trunk/coreboot-v2/src/mainboard/supermicro/x6dhr_ig/Config.lb 2009-04-22 08:56:50 UTC (rev 4169) @@ -206,10 +206,10 @@ device pci 06.0 on end end device apic_cluster 0 on - chip cpu/intel/socket_mPGA604_800Mhz # cpu 0 + chip cpu/intel/socket_mPGA604 # cpu 0 device apic 0 on end end - chip cpu/intel/socket_mPGA604_800Mhz # cpu 1 + chip cpu/intel/socket_mPGA604 # cpu 1 device apic 6 on end end end Modified: trunk/coreboot-v2/src/mainboard/supermicro/x6dhr_ig2/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/supermicro/x6dhr_ig2/Config.lb 2009-04-22 08:18:37 UTC (rev 4168) +++ trunk/coreboot-v2/src/mainboard/supermicro/x6dhr_ig2/Config.lb 2009-04-22 08:56:50 UTC (rev 4169) @@ -197,10 +197,10 @@ device pci 06.0 on end end device apic_cluster 0 on - chip cpu/intel/socket_mPGA604_800Mhz # cpu 0 + chip cpu/intel/socket_mPGA604 # cpu 0 device apic 0 on end end - chip cpu/intel/socket_mPGA604_800Mhz # cpu 1 + chip cpu/intel/socket_mPGA604 # cpu 1 device apic 6 on end end end Modified: trunk/coreboot-v2/src/mainboard/tyan/s2735/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s2735/Config.lb 2009-04-22 08:18:37 UTC (rev 4168) +++ trunk/coreboot-v2/src/mainboard/tyan/s2735/Config.lb 2009-04-22 08:56:50 UTC (rev 4169) @@ -172,10 +172,10 @@ end # SB end # PCI_DOMAIN device apic_cluster 0 on - chip cpu/intel/socket_mPGA604_533Mhz + chip cpu/intel/socket_mPGA604 device apic 0 on end end - chip cpu/intel/socket_mPGA604_533Mhz + chip cpu/intel/socket_mPGA604 device apic 6 on end end end

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[PATCH] unify socket_mPGA604_800Mhz and socket_mPGA604_533Mhz
by Stefan Reinauer 22 Apr '09

22 Apr '09

See patch. -- coresystems GmbH • Brahmsstr. 16 • D-79104 Freiburg i. Br. Tel.: +49 761 7668825 • Fax: +49 761 7664613 Email: info(a)coresystems.de • http://www.coresystems.de/ Registergericht: Amtsgericht Freiburg • HRB 7656 Geschäftsführer: Stefan Reinauer • Ust-IdNr.: DE245674866

2 1

Linux Bios in A8js
by João Mamede 22 Apr '09

22 Apr '09

Hello. I want/need to make linuxbios to work with my asus a8js. I'll explain the why's. My gforce 7700 fried and needed replacement. So I bought a gforce 9500 from an asus f8sn. The card fits perfectly to the socket and thermal module. However when bios loads it starts beeping like there is no graphics card. Is there anyway to make it work so that it supports my new graphics? A8js specs page and bios dl: http://www.asus.com/product.aspx?P_ID=pNLo...=specifications http://dlcdnet.asus.com/pub/ASUS/nb/A8Js/A8Jsv213AS.zip F8SN specs page and bios dl: http://www.asus.com/product.aspx?P_ID=qftS...=specifications http://dlcdnet.asus.com/pub/ASUS/nb/F8Sn/F8SNG304AS.zip Thank you Joao

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[PATCH] factor out acpi_create_madt_lapics
by Stefan Reinauer 22 Apr '09

22 Apr '09

See patch -- coresystems GmbH • Brahmsstr. 16 • D-79104 Freiburg i. Br. Tel.: +49 761 7668825 • Fax: +49 761 7664613 Email: info(a)coresystems.de • http://www.coresystems.de/ Registergericht: Amtsgericht Freiburg • HRB 7656 Geschäftsführer: Stefan Reinauer • Ust-IdNr.: DE245674866

3 3

[v2] r4168 - in trunk/coreboot-v2/src: arch/i386/boot northbridge/amd/amdfam10 northbridge/amd/amdk8
by svn＠coreboot.org 22 Apr '09

22 Apr '09

Author: stepan Date: 2009-04-22 10:18:37 +0200 (Wed, 22 Apr 2009) New Revision: 4168 Modified: trunk/coreboot-v2/src/arch/i386/boot/acpi.c trunk/coreboot-v2/src/northbridge/amd/amdfam10/amdfam10_acpi.c trunk/coreboot-v2/src/northbridge/amd/amdk8/amdk8_acpi.c Log: Factor out acpi_create_madt_lapics. It can be used on all ACPI boards. Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Patrick Georgi <patrick.georgi(a)coresystems.de> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Modified: trunk/coreboot-v2/src/arch/i386/boot/acpi.c =================================================================== --- trunk/coreboot-v2/src/arch/i386/boot/acpi.c 2009-04-22 08:17:38 UTC (rev 4167) +++ trunk/coreboot-v2/src/arch/i386/boot/acpi.c 2009-04-22 08:18:37 UTC (rev 4168) @@ -88,6 +88,25 @@ return(lapic->length); } +unsigned long acpi_create_madt_lapics(unsigned long current) +{ + device_t cpu; + int cpu_index = 0; + + for(cpu = all_devices; cpu; cpu = cpu->next) { + if ((cpu->path.type != DEVICE_PATH_APIC) || + (cpu->bus->dev->path.type != DEVICE_PATH_APIC_CLUSTER)) { + continue; + } + if (!cpu->enabled) { + continue; + } + current += acpi_create_madt_lapic((acpi_madt_lapic_t *)current, cpu_index, cpu->path.apic.apic_id); + cpu_index++; + } + return current; +} + int acpi_create_madt_ioapic(acpi_madt_ioapic_t *ioapic, u8 id, u32 addr,u32 gsi_base) { ioapic->type=1; Modified: trunk/coreboot-v2/src/northbridge/amd/amdfam10/amdfam10_acpi.c =================================================================== --- trunk/coreboot-v2/src/northbridge/amd/amdfam10/amdfam10_acpi.c 2009-04-22 08:17:38 UTC (rev 4167) +++ trunk/coreboot-v2/src/northbridge/amd/amdfam10/amdfam10_acpi.c 2009-04-22 08:18:37 UTC (rev 4168) @@ -28,25 +28,6 @@ //it seems some functions can be moved arch/i386/boot/acpi.c -unsigned long acpi_create_madt_lapics(unsigned long current) -{ - device_t cpu; - int cpu_index = 0; - - for(cpu = all_devices; cpu; cpu = cpu->next) { - if ((cpu->path.type != DEVICE_PATH_APIC) || - (cpu->bus->dev->path.type != DEVICE_PATH_APIC_CLUSTER)) { - continue; - } - if (!cpu->enabled) { - continue; - } - current += acpi_create_madt_lapic((acpi_madt_lapic_t *)current, cpu_index, cpu->path.apic.apic_id); - cpu_index++; - } - return current; -} - unsigned long acpi_create_madt_lapic_nmis(unsigned long current, u16 flags, u8 lint) { device_t cpu; Modified: trunk/coreboot-v2/src/northbridge/amd/amdk8/amdk8_acpi.c =================================================================== --- trunk/coreboot-v2/src/northbridge/amd/amdk8/amdk8_acpi.c 2009-04-22 08:17:38 UTC (rev 4167) +++ trunk/coreboot-v2/src/northbridge/amd/amdk8/amdk8_acpi.c 2009-04-22 08:18:37 UTC (rev 4168) @@ -48,25 +48,6 @@ //it seems some functions can be moved arch/i386/boot/acpi.c -unsigned long acpi_create_madt_lapics(unsigned long current) -{ - device_t cpu; - int cpu_index = 0; - - for(cpu = all_devices; cpu; cpu = cpu->next) { - if ((cpu->path.type != DEVICE_PATH_APIC) || - (cpu->bus->dev->path.type != DEVICE_PATH_APIC_CLUSTER)) { - continue; - } - if (!cpu->enabled) { - continue; - } - current += acpi_create_madt_lapic((acpi_madt_lapic_t *)current, cpu_index, cpu->path.apic.apic_id); - cpu_index++; - } - return current; -} - unsigned long acpi_create_madt_lapic_nmis(unsigned long current, u16 flags, u8 lint) { device_t cpu;

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[v2] r4167 - in trunk/coreboot-v2/src: arch/i386/boot arch/i386/include/arch boot
by svn＠coreboot.org 22 Apr '09

22 Apr '09

Author: stepan Date: 2009-04-22 10:17:38 +0200 (Wed, 22 Apr 2009) New Revision: 4167 Modified: trunk/coreboot-v2/src/arch/i386/boot/acpi.c trunk/coreboot-v2/src/arch/i386/include/arch/acpi.h trunk/coreboot-v2/src/boot/hardwaremain.c Log: * move i386 / ACPI dependent code out of hardwaremain.c and into the i386 acpi code. * add some defines for FADT flags Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Patrick Georgi <patrick.georgi(a)coresystems.de> Modified: trunk/coreboot-v2/src/arch/i386/boot/acpi.c =================================================================== --- trunk/coreboot-v2/src/arch/i386/boot/acpi.c 2009-04-22 08:12:05 UTC (rev 4166) +++ trunk/coreboot-v2/src/arch/i386/boot/acpi.c 2009-04-22 08:17:38 UTC (rev 4167) @@ -1,8 +1,8 @@ /* * coreboot ACPI Table support * written by Stefan Reinauer <stepan(a)openbios.org> - * (C) 2004 SUSE LINUX AG - * (C) 2005 Stefan Reinauer + * Copyright (C) 2004 SUSE LINUX AG + * Copyright (C) 2005-2009 coresystems GmbH * * ACPI FADT, FACS, and DSDT table support added by * Nick Barker <nick.barker9(a)btinternet.com>, and those portions @@ -27,11 +27,6 @@ #include <arch/acpigen.h> #include <device/pci.h> -#if HAVE_ACPI_RESUME == 1 -/* this is to be filled by SB code - startup value what was found */ -u8 acpi_slp_type; -#endif - u8 acpi_checksum(u8 *table, u32 length) { u8 ret=0; @@ -81,7 +76,6 @@ return (sizeof(acpi_mcfg_mmconfig_t)); } - int acpi_create_madt_lapic(acpi_madt_lapic_t *lapic, u8 cpu, u8 apic) { lapic->type=0; @@ -378,7 +372,30 @@ } #if HAVE_ACPI_RESUME == 1 +void suspend_resume(void) +{ + void *wake_vec; +#if 0 +#if MEM_TRAIN_SEQ != 0 + #error "So far it works on AMD and MEM_TRAIN_SEQ == 0" +#endif + +#if _RAMBASE < 0x1F00000 + #error "For ACPI RESUME you need to have _RAMBASE at least 31MB" + #error "Chipset support (S3_NVRAM_EARLY and ACPI_IS_WAKEUP_EARLY functions and memory ctrl)" + #error "And coreboot memory reserved in mainboard.c" +#endif +#endif + /* if we happen to be resuming find wakeup vector and jump to OS */ + wake_vec = acpi_find_wakeup_vector(); + if (wake_vec) + acpi_jump_to_wakeup(wake_vec); +} + +/* this is to be filled by SB code - startup value what was found */ +u8 acpi_slp_type = 0; + int acpi_get_sleep_type(void) { return acpi_slp_type; @@ -461,8 +478,10 @@ printk_debug("FADT found at %p\n", fadt); facs = fadt->firmware_ctrl; - if (facs == NULL) + if (facs == NULL) { + printk_debug("No FACS found, wake up from S3 not possible.\n"); return NULL; + } printk_debug("FACS found at %p\n", facs); wake_vec = (void *) facs->firmware_waking_vector; Modified: trunk/coreboot-v2/src/arch/i386/include/arch/acpi.h =================================================================== --- trunk/coreboot-v2/src/arch/i386/include/arch/acpi.h 2009-04-22 08:12:05 UTC (rev 4166) +++ trunk/coreboot-v2/src/arch/i386/include/arch/acpi.h 2009-04-22 08:17:38 UTC (rev 4167) @@ -17,8 +17,10 @@ #include <stdint.h> +#if HAVE_ACPI_RESUME /* 0 = S0, 1 = S1 ...*/ extern u8 acpi_slp_type; +#endif #define RSDP_SIG "RSD PTR " /* RSDT Pointer signature */ #define RSDP_NAME "RSDP" @@ -277,6 +279,37 @@ struct acpi_gen_regaddr x_gpe1_blk; } __attribute__ ((packed)) acpi_fadt_t; +#define ACPI_FADT_WBINVD (1 << 0) +#define ACPI_FADT_WBINVD_FLUSH (1 << 1) +#define ACPI_FADT_C1_SUPPORTED (1 << 2) +#define ACPI_FADT_C2_MP_SUPPORTED (1 << 3) +#define ACPI_FADT_POWER_BUTTON (1 << 4) +#define ACPI_FADT_SLEEP_BUTTON (1 << 5) +#define ACPI_FADT_FIXED_RTC (1 << 6) +#define ACPI_FADT_S4_RTC_WAKE (1 << 7) +#define ACPI_FADT_32BIT_TIMER (1 << 8) +#define ACPI_FADT_DOCKING_SUPPORTED (1 << 9) +#define ACPI_FADT_RESET_REGISTER (1 << 10) +#define ACPI_FADT_SEALED_CASE (1 << 11) +#define ACPI_FADT_HEADLESS (1 << 12) +#define ACPI_FADT_SLEEP_TYPE (1 << 13) +#define ACPI_FADT_PCI_EXPRESS_WAKE (1 << 14) +#define ACPI_FADT_PLATFORM_CLOCK (1 << 15) +#define ACPI_FADT_S4_RTC_VALID (1 << 16) +#define ACPI_FADT_REMOTE_POWER_ON (1 << 17) +#define ACPI_FADT_APIC_CLUSTER (1 << 18) +#define ACPI_FADT_APIC_PHYSICAL (1 << 19) + +enum acpi_preferred_pm_profiles { + PM_UNSPECIFIED = 0, + PM_DESKTOP = 1, + PM_MOBILE = 2, + PM_WORKSTATION = 3, + PM_ENTERPRISE = 4, + PM_SOHO_SERVER = 5, + PM_APPLIANCE_PC = 6 +}; + /* FACS */ typedef struct acpi_facs { char signature[4]; @@ -333,10 +366,14 @@ void acpi_write_rsdt(acpi_rsdt_t *rsdt); void acpi_write_rsdp(acpi_rsdp_t *rsdp, acpi_rsdt_t *rsdt); + +#if HAVE_ACPI_RESUME +void suspend_resume(void); void *acpi_find_wakeup_vector(void); void *acpi_get_wakeup_rsdp(void); -extern void acpi_jmp_to_realm_wakeup(u32 linear_addr); +void acpi_jmp_to_realm_wakeup(u32 linear_addr); void acpi_jump_to_wakeup(void *wakeup_addr); +#endif unsigned long acpi_add_ssdt_pstates(acpi_rsdt_t *rsdt, unsigned long current); Modified: trunk/coreboot-v2/src/boot/hardwaremain.c =================================================================== --- trunk/coreboot-v2/src/boot/hardwaremain.c 2009-04-22 08:12:05 UTC (rev 4166) +++ trunk/coreboot-v2/src/boot/hardwaremain.c 2009-04-22 08:17:38 UTC (rev 4167) @@ -28,16 +28,16 @@ #include <console/console.h> #include <version.h> -#include <boot/tables.h> #include <device/device.h> #include <device/pci.h> #include <delay.h> #include <stdlib.h> #include <part/hard_reset.h> #include <part/init_timer.h> +#include <boot/tables.h> #include <boot/elf.h> #include <cbfs.h> -#if HAVE_ACPI_RESUME == 1 +#if HAVE_ACPI_RESUME #include <arch/acpi.h> #endif @@ -54,9 +54,6 @@ void hardwaremain(int boot_complete) { struct lb_memory *lb_mem; -#if HAVE_ACPI_RESUME == 1 - void *wake_vec; -#endif post_code(0x80); @@ -92,22 +89,10 @@ post_code(0x89); #if HAVE_ACPI_RESUME == 1 - -#if MEM_TRAIN_SEQ != 0 - #error "So far it works on AMD and MEM_TRAIN_SEQ == 0" + suspend_resume(); + post_code(0x8a); #endif -#if _RAMBASE < 0x1F00000 - #error "For ACPI RESUME you need to have _RAMBASE at least 31MB" - #error "Chipset support (S3_NVRAM_EARLY and ACPI_IS_WAKEUP_EARLY functions and memory ctrl)" - #error "And coreboot memory reserved in mainboard.c" -#endif - /* if we happen to be resuming find wakeup vector and jump to OS */ - wake_vec = acpi_find_wakeup_vector(); - if (wake_vec) - acpi_jump_to_wakeup(wake_vec); -#endif - /* Now that we have collected all of our information * write our configuration tables. */

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[v2] r4166 - trunk/coreboot-v2/util
by svn＠coreboot.org 22 Apr '09

22 Apr '09

Author: stepan Date: 2009-04-22 10:12:05 +0200 (Wed, 22 Apr 2009) New Revision: 4166 Modified: trunk/coreboot-v2/util/ Log: add svn:externals for ectool (trivial) Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Property changes on: trunk/coreboot-v2/util ___________________________________________________________________ Modified: svn:externals - flashrom svn://coreboot.org/repos/trunk/util/flashrom nvramtool svn://coreboot.org/repos/trunk/util/nvramtool superiotool svn://coreboot.org/repos/trunk/util/superiotool getpir svn://coreboot.org/repos/trunk/util/getpir mptable svn://coreboot.org/repos/trunk/util/mptable inteltool svn://coreboot.org/repos/trunk/util/inteltool msrtool svn://coreboot.org/repos/trunk/util/msrtool x86emu svn://coreboot.org/repository/coreboot-v3/util/x86emu + flashrom svn://coreboot.org/repos/trunk/util/flashrom nvramtool svn://coreboot.org/repos/trunk/util/nvramtool superiotool svn://coreboot.org/repos/trunk/util/superiotool getpir svn://coreboot.org/repos/trunk/util/getpir mptable svn://coreboot.org/repos/trunk/util/mptable inteltool svn://coreboot.org/repos/trunk/util/inteltool msrtool svn://coreboot.org/repos/trunk/util/msrtool ectool svn://coreboot.org/repos/trunk/util/ectool x86emu svn://coreboot.org/repository/coreboot-v3/util/x86emu

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[v2] r4165 - trunk/coreboot-v2/util/abuild
by svn＠coreboot.org 22 Apr '09

22 Apr '09

Author: oxygene Date: 2009-04-22 10:10:48 +0200 (Wed, 22 Apr 2009) New Revision: 4165 Modified: trunk/coreboot-v2/util/abuild/abuild Log: Remove the requirement for payload.sh files to be executable. This helps if the file is generated from patches, esp. if that happens often (eg. with quilt) Signed-off-by: Patrick Georgi <patrick.georgi(a)coresystems.de> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Modified: trunk/coreboot-v2/util/abuild/abuild =================================================================== --- trunk/coreboot-v2/util/abuild/abuild 2009-04-22 08:07:31 UTC (rev 4164) +++ trunk/coreboot-v2/util/abuild/abuild 2009-04-22 08:10:48 UTC (rev 4165) @@ -127,12 +127,12 @@ # get a working payload for the board if we have one. # the --payload option expects a directory containing - # an executable shell script payload.sh + # a shell script payload.sh # Usage: payload.sh [VENDOR] [DEVICE] # the script returns an absolute path to the payload binary. - if [ -x $payloads/payload.sh ]; then - PAYLOAD=`$payloads/payload.sh $VENDOR $MAINBOARD` + if [ -f $payloads/payload.sh ]; then + PAYLOAD=`sh $payloads/payload.sh $VENDOR $MAINBOARD` printf "Using payload $PAYLOAD\n" fi

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[v2] r4164 - trunk/coreboot-v2/src/cpu/intel/hyperthreading
by svn＠coreboot.org 22 Apr '09

22 Apr '09

Author: oxygene Date: 2009-04-22 10:07:31 +0200 (Wed, 22 Apr 2009) New Revision: 4164 Modified: trunk/coreboot-v2/src/cpu/intel/hyperthreading/intel_sibling.c Log: Trivial removal of a freudian slip. Signed-off-by: Patrick Georgi <patrick.georgi(a)coresystems.de> Acked-by: Patrick Georgi <patrick.georgi(a)coresystems.de> Modified: trunk/coreboot-v2/src/cpu/intel/hyperthreading/intel_sibling.c =================================================================== --- trunk/coreboot-v2/src/cpu/intel/hyperthreading/intel_sibling.c 2009-04-22 07:23:00 UTC (rev 4163) +++ trunk/coreboot-v2/src/cpu/intel/hyperthreading/intel_sibling.c 2009-04-22 08:07:31 UTC (rev 4164) @@ -20,7 +20,7 @@ get_option(&disable_siblings, "hyper_threading"); } result = cpuid(1); - /* Is hypethreading supported */ + /* Is hyperthreading supported */ if (!(result.edx & (1 << 28))) { return; }

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coreboot April 2009