coreboot March 2009

coreboot@coreboot.org

64 participants
316 discussions

r3980 - in trunk/coreboot-v2/src/southbridge: amd/cs5536 via/vt8235 via/vt8237r
by svn＠coreboot.org 06 Mar '09

06 Mar '09

Author: stepan Date: 2009-03-06 19:39:54 +0100 (Fri, 06 Mar 2009) New Revision: 3980 Modified: trunk/coreboot-v2/src/southbridge/amd/cs5536/cs5536.c trunk/coreboot-v2/src/southbridge/via/vt8235/vt8235.c trunk/coreboot-v2/src/southbridge/via/vt8237r/vt8237r_lpc.c Log: use include file for i8259 where appropriate (trivial) Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/coreboot-v2/src/southbridge/amd/cs5536/cs5536.c =================================================================== --- trunk/coreboot-v2/src/southbridge/amd/cs5536/cs5536.c 2009-03-06 18:38:28 UTC (rev 3979) +++ trunk/coreboot-v2/src/southbridge/amd/cs5536/cs5536.c 2009-03-06 18:39:54 UTC (rev 3980) @@ -26,6 +26,7 @@ #include <stdint.h> #include <pc80/isa-dma.h> #include <pc80/mc146818rtc.h> +#include <pc80/i8259.h> #include <cpu/x86/msr.h> #include <cpu/amd/vr.h> #include <cpu/amd/geode_post_code.h> @@ -33,8 +34,6 @@ #include "chip.h" #include "cs5536.h" -extern void setup_i8259(void); - struct msrinit { uint32_t msrnum; msr_t msr; Modified: trunk/coreboot-v2/src/southbridge/via/vt8235/vt8235.c =================================================================== --- trunk/coreboot-v2/src/southbridge/via/vt8235/vt8235.c 2009-03-06 18:38:28 UTC (rev 3979) +++ trunk/coreboot-v2/src/southbridge/via/vt8235/vt8235.c 2009-03-06 18:39:54 UTC (rev 3980) @@ -4,6 +4,7 @@ #include <device/pci_ops.h> #include <device/pci_ids.h> #include <pc80/keyboard.h> +#include <pc80/i8259.h> #include "vt8235.h" #include "chip.h" Modified: trunk/coreboot-v2/src/southbridge/via/vt8237r/vt8237r_lpc.c =================================================================== --- trunk/coreboot-v2/src/southbridge/via/vt8237r/vt8237r_lpc.c 2009-03-06 18:38:28 UTC (rev 3979) +++ trunk/coreboot-v2/src/southbridge/via/vt8237r/vt8237r_lpc.c 2009-03-06 18:39:54 UTC (rev 3980) @@ -27,6 +27,7 @@ #include <pc80/mc146818rtc.h> #include <cpu/x86/lapic.h> #include <pc80/keyboard.h> +#include <pc80/i8259.h> #include <stdlib.h> #include "vt8237r.h" #include "chip.h" @@ -47,7 +48,6 @@ #define INT (1 << 8) extern void dump_south(device_t dev); -extern void setup_i8259(void); static struct ioapicreg { u32 reg;

1 0

r3979 - in trunk/coreboot-v2: src/mainboard/emulation/qemu-x86 targets/emulation/qemu-x86
by svn＠coreboot.org 06 Mar '09

06 Mar '09

Author: stepan Date: 2009-03-06 19:38:28 +0100 (Fri, 06 Mar 2009) New Revision: 3979 Modified: trunk/coreboot-v2/src/mainboard/emulation/qemu-x86/Options.lb trunk/coreboot-v2/targets/emulation/qemu-x86/Config-abuild.lb Log: clean up qemu target config (trivial) Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/coreboot-v2/src/mainboard/emulation/qemu-x86/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/emulation/qemu-x86/Options.lb 2009-03-06 17:43:20 UTC (rev 3978) +++ trunk/coreboot-v2/src/mainboard/emulation/qemu-x86/Options.lb 2009-03-06 18:38:28 UTC (rev 3979) @@ -70,9 +70,8 @@ ## ## Build code to export a programmable irq routing table ## -default HAVE_PIRQ_TABLE=0 -default IRQ_SLOT_COUNT=5 -#object irq_tables.o +default HAVE_PIRQ_TABLE=1 +default IRQ_SLOT_COUNT=6 ## ## Build code to export a CMOS option table Modified: trunk/coreboot-v2/targets/emulation/qemu-x86/Config-abuild.lb =================================================================== --- trunk/coreboot-v2/targets/emulation/qemu-x86/Config-abuild.lb 2009-03-06 17:43:20 UTC (rev 3978) +++ trunk/coreboot-v2/targets/emulation/qemu-x86/Config-abuild.lb 2009-03-06 18:38:28 UTC (rev 3979) @@ -1,22 +1,20 @@ -# This will make a target directory of ./emulation_qemu-x86 +target VENDOR_MAINBOARD +mainboard VENDOR/MAINBOARD -target emulation_qemu-x86 -mainboard emulation/qemu-x86 +option CC="CROSSCC" +option CROSS_COMPILE="CROSS_PREFIX" +option HOSTCC="CROSS_HOSTCC" __COMPRESSION__ option ROM_SIZE=256*1024 -option CC="gcc -m32" - -option HAVE_PIRQ_TABLE=1 -option IRQ_SLOT_COUNT=6 - -romimage "image" +romimage "fallback" + option USE_FALLBACK_IMAGE=1 option ROM_IMAGE_SIZE=0x10000 - option COREBOOT_EXTRA_VERSION="-OpenBIOS" + option COREBOOT_EXTRA_VERSION=".0" payload __PAYLOAD__ end -buildrom ./coreboot.rom ROM_SIZE "image" +buildrom ./coreboot.rom ROM_SIZE "fallback"

1 0

r3978 - trunk/payloads/libpayload/libc
by svn＠coreboot.org 06 Mar '09

06 Mar '09

Author: stepan Date: 2009-03-06 18:43:20 +0100 (Fri, 06 Mar 2009) New Revision: 3978 Modified: trunk/payloads/libpayload/libc/string.c Log: fix strstr. Seems the function never worked before, except the searched substring is at the end. Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/payloads/libpayload/libc/string.c =================================================================== --- trunk/payloads/libpayload/libc/string.c 2009-03-06 17:24:29 UTC (rev 3977) +++ trunk/payloads/libpayload/libc/string.c 2009-03-06 17:43:20 UTC (rev 3978) @@ -234,7 +234,7 @@ int i; for (i = 0; i <= hn - nn; i++) - if (!strcmp(&h[i], n)) + if (!memcmp(&h[i], n, nn)) return (char *)&h[i]; return NULL;

1 0

r3977 - in trunk/coreboot-v2/src: arch/i386/boot arch/i386/smp cpu/x86/lapic cpu/x86/tsc devices
by svn＠coreboot.org 06 Mar '09

06 Mar '09

Author: stepan Date: 2009-03-06 18:24:29 +0100 (Fri, 06 Mar 2009) New Revision: 3977 Modified: trunk/coreboot-v2/src/arch/i386/boot/acpi.c trunk/coreboot-v2/src/arch/i386/boot/multiboot.c trunk/coreboot-v2/src/arch/i386/boot/tables.c trunk/coreboot-v2/src/arch/i386/smp/ioapic.c trunk/coreboot-v2/src/cpu/x86/lapic/lapic_cpu_init.c trunk/coreboot-v2/src/cpu/x86/tsc/delay_tsc.c trunk/coreboot-v2/src/devices/device.c Log: fix a bunch of cast and type warnings and don't call the apic "nvram", that doesn't make no sense. (trivial) Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/coreboot-v2/src/arch/i386/boot/acpi.c =================================================================== --- trunk/coreboot-v2/src/arch/i386/boot/acpi.c 2009-03-06 17:22:35 UTC (rev 3976) +++ trunk/coreboot-v2/src/arch/i386/boot/acpi.c 2009-03-06 17:24:29 UTC (rev 3977) @@ -202,7 +202,7 @@ ssdt->asl_compiler_revision = 42; ssdt->length = sizeof(acpi_header_t); - acpigen_set_current((unsigned char *) current); + acpigen_set_current((char *) current); current = acpi_fill_ssdt_generator(current, oem_table_id); /* recalculate length */ Modified: trunk/coreboot-v2/src/arch/i386/boot/multiboot.c =================================================================== --- trunk/coreboot-v2/src/arch/i386/boot/multiboot.c 2009-03-06 17:22:35 UTC (rev 3976) +++ trunk/coreboot-v2/src/arch/i386/boot/multiboot.c 2009-03-06 17:24:29 UTC (rev 3977) @@ -72,7 +72,7 @@ build_mb_mem_range_nooverlap(res->base, res->size); } -#define ROUND(_r,_a) ((_r) + (((_a) - 1)) & ~((_a) - 1)) +#define ROUND(_r,_a) (((_r) + (((_a) - 1))) & ~((_a) - 1)) unsigned long write_multiboot_info( unsigned long low_table_start, unsigned long low_table_end, @@ -81,12 +81,12 @@ struct multiboot_info *mbi; int i; - mbi = rom_table_end; + mbi = (struct multiboot_info *)rom_table_end; memset(mbi, 0, sizeof(*mbi)); rom_table_end += sizeof(*mbi); mbi->mmap_addr = (u32) rom_table_end; - mb_mem = rom_table_end; + mb_mem = (struct multiboot_mmap_entry *)rom_table_end; /* reserved regions */ reserved_mem[0].addr = low_table_start; @@ -111,5 +111,5 @@ printk_info("Multiboot Information structure has been written.\n"); - return mb_mem; + return (unsigned long)mb_mem; } Modified: trunk/coreboot-v2/src/arch/i386/boot/tables.c =================================================================== --- trunk/coreboot-v2/src/arch/i386/boot/tables.c 2009-03-06 17:22:35 UTC (rev 3976) +++ trunk/coreboot-v2/src/arch/i386/boot/tables.c 2009-03-06 17:24:29 UTC (rev 3977) @@ -182,7 +182,7 @@ #if CONFIG_MULTIBOOT /* The Multiboot information structure */ - mbi = rom_table_end; + mbi = (struct multiboot_info *)rom_table_end; rom_table_end = write_multiboot_info( low_table_start, low_table_end, rom_table_start, rom_table_end); Modified: trunk/coreboot-v2/src/arch/i386/smp/ioapic.c =================================================================== --- trunk/coreboot-v2/src/arch/i386/smp/ioapic.c 2009-03-06 17:22:35 UTC (rev 3976) +++ trunk/coreboot-v2/src/arch/i386/smp/ioapic.c 2009-03-06 17:24:29 UTC (rev 3977) @@ -55,11 +55,11 @@ { int i; unsigned long value_low, value_high; - unsigned long nvram = 0xfec00000; + unsigned long ioapicaddr = 0xfec00000; volatile unsigned long *l; struct ioapicreg *a = ioapicregvalues; - l = (unsigned long *) nvram; + l = (unsigned long *) ioapicaddr; #if defined(i786) /* For the pentium 4 and above apic deliver their interrupts * on the front side bus, enable that. Modified: trunk/coreboot-v2/src/cpu/x86/lapic/lapic_cpu_init.c =================================================================== --- trunk/coreboot-v2/src/cpu/x86/lapic/lapic_cpu_init.c 2009-03-06 17:22:35 UTC (rev 3976) +++ trunk/coreboot-v2/src/cpu/x86/lapic/lapic_cpu_init.c 2009-03-06 17:24:29 UTC (rev 3977) @@ -295,7 +295,7 @@ lapicid = lapic_read(LAPIC_ID) >> 24; - printk_debug("CPU %d going down...\n", lapicid); + printk_debug("CPU %ld going down...\n", lapicid); /* send an LAPIC INIT to myself */ lapic_write_around(LAPIC_ICR2, SET_LAPIC_DEST_FIELD(lapicid)); Modified: trunk/coreboot-v2/src/cpu/x86/tsc/delay_tsc.c =================================================================== --- trunk/coreboot-v2/src/cpu/x86/tsc/delay_tsc.c 2009-03-06 17:22:35 UTC (rev 3976) +++ trunk/coreboot-v2/src/cpu/x86/tsc/delay_tsc.c 2009-03-06 17:24:29 UTC (rev 3977) @@ -104,6 +104,7 @@ unsigned long long start, end, delta; unsigned long result, count; + printk_spew("Calibrating delay loop...\n"); start = rdtscll(); // no udivdi3, dammit. // so we count to 1<< 20 and then right shift 20 @@ -127,10 +128,10 @@ delta >>= 20; // save this for microsecond timing. result = delta; - printk_spew("end %x, start %x\n", end, start); - printk_spew("32-bit delta %d\n", (unsigned long) delta); + printk_spew("end %llx, start %llx\n", end, start); + printk_spew("32-bit delta %ld\n", (unsigned long) delta); - printk_spew("%s 32-bit result is %d\n", + printk_spew("%s 32-bit result is %ld\n", __func__, result); return delta; @@ -143,7 +144,7 @@ { if (!clocks_per_usec) { clocks_per_usec = calibrate_tsc(); - printk_info("clocks_per_usec: %u\n", clocks_per_usec); + printk_info("clocks_per_usec: %lu\n", clocks_per_usec); } } Modified: trunk/coreboot-v2/src/devices/device.c =================================================================== --- trunk/coreboot-v2/src/devices/device.c 2009-03-06 17:22:35 UTC (rev 3976) +++ trunk/coreboot-v2/src/devices/device.c 2009-03-06 17:24:29 UTC (rev 3977) @@ -357,8 +357,7 @@ resource->flags &= ~IORESOURCE_STORED; base += size; - printk_spew( - "%s %02lx * [0x%08Lx - 0x%08Lx] %s\n", + printk_spew("%s %02lx * [0x%08Lx - 0x%08Lx] %s\n", dev_path(dev), resource->index, resource->base,

1 0

r3976 - trunk/coreboot-v2/src/lib
by svn＠coreboot.org 06 Mar '09

06 Mar '09

Author: stepan Date: 2009-03-06 18:22:35 +0100 (Fri, 06 Mar 2009) New Revision: 3976 Modified: trunk/coreboot-v2/src/lib/malloc.c Log: use pointers instead of size_t when dealing with pointers. Also fix a few warnings (trivial) Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/coreboot-v2/src/lib/malloc.c =================================================================== --- trunk/coreboot-v2/src/lib/malloc.c 2009-03-06 17:21:23 UTC (rev 3975) +++ trunk/coreboot-v2/src/lib/malloc.c 2009-03-06 17:22:35 UTC (rev 3976) @@ -4,36 +4,36 @@ #if 0 #define MALLOCDBG(x) #else -#define MALLOCDBG(x) printk_spew x +#define MALLOCDBG(x...) printk_spew(x) #endif extern unsigned char _heap, _eheap; -static size_t free_mem_ptr = (size_t)&_heap; /* Start of heap */ -static size_t free_mem_end_ptr = (size_t)&_eheap; /* End of heap */ +static void *free_mem_ptr = &_heap; /* Start of heap */ +static void *free_mem_end_ptr = &_eheap; /* End of heap */ void malloc_mark(malloc_mark_t *place) { - *place = free_mem_ptr; - printk_spew("malloc_mark 0x%08lx\n", (unsigned long)free_mem_ptr); + *place = (malloc_mark_t)free_mem_ptr; + printk_spew("malloc_mark %p\n", free_mem_ptr); } void malloc_release(malloc_mark_t *ptr) { - free_mem_ptr = *ptr; - printk_spew("malloc_release 0x%08lx\n", (unsigned long)free_mem_ptr); + free_mem_ptr = (void *)*ptr; + printk_spew("malloc_release %p\n", free_mem_ptr); } void *malloc(size_t size) { void *p; - MALLOCDBG(("%s Enter, size %ld, free_mem_ptr 0x%08lx\n", __func__, size, free_mem_ptr)); + MALLOCDBG("%s Enter, size %ld, free_mem_ptr %p\n", __func__, size, free_mem_ptr); if (size < 0) die("Error! malloc: Size < 0"); if (free_mem_ptr <= 0) die("Error! malloc: Free_mem_ptr <= 0"); - free_mem_ptr = (free_mem_ptr + 3) & ~3; /* Align */ + free_mem_ptr = (void *)(((unsigned long)free_mem_ptr + 3) & ~3); /* Align */ p = (void *) free_mem_ptr; free_mem_ptr += size; @@ -41,7 +41,7 @@ if (free_mem_ptr >= free_mem_end_ptr) die("Error! malloc: free_mem_ptr >= free_mem_end_ptr"); - MALLOCDBG(("malloc 0x%08lx\n", (unsigned long)p)); + MALLOCDBG("malloc %p\n", p); return p; }

1 0

r3975 - trunk/coreboot-v2/src/lib
by svn＠coreboot.org 06 Mar '09

06 Mar '09

Author: stepan Date: 2009-03-06 18:21:23 +0100 (Fri, 06 Mar 2009) New Revision: 3975 Modified: trunk/coreboot-v2/src/lib/usbdebug_direct.c Log: use inb instead of outb for delays in usb debug code (trivial) Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/coreboot-v2/src/lib/usbdebug_direct.c =================================================================== --- trunk/coreboot-v2/src/lib/usbdebug_direct.c 2009-03-06 17:20:17 UTC (rev 3974) +++ trunk/coreboot-v2/src/lib/usbdebug_direct.c 2009-03-06 17:21:23 UTC (rev 3975) @@ -92,7 +92,7 @@ int i; while (ms--) { for (i = 0; i < 1000; i++) - outb(0x1, 0x80); + inb(0x80); } }

1 0

r3974 - trunk/coreboot-v2/src/config
by svn＠coreboot.org 06 Mar '09

06 Mar '09

Author: stepan Date: 2009-03-06 18:20:17 +0100 (Fri, 06 Mar 2009) New Revision: 3974 Modified: trunk/coreboot-v2/src/config/Config.lb Log: really clean out all compile time generated files (trivial) Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/coreboot-v2/src/config/Config.lb =================================================================== --- trunk/coreboot-v2/src/config/Config.lb 2009-03-06 00:40:25 UTC (rev 3973) +++ trunk/coreboot-v2/src/config/Config.lb 2009-03-06 17:20:17 UTC (rev 3974) @@ -204,7 +204,10 @@ action "rm -f a.out *.s *.l *.o *.E *.inc" action "rm -f TAGS tags romcc*" action "rm -f docipl buildrom* chips.c *chip.c coreboot_apc* coreboot_ram* coreboot_pay*" - action "rm -f build_opt_tbl* nrv2b* option_table.c crt0.S" + action "rm -f build_opt_tbl* nrv2b* option_table.c option_table.h crt0.S crt0.disasm" + action "rm -f smm smm.elf smm.map smm_bin.c" + action "rm -f dsdt.aml dsdt.c" + action "rm -f payload" end # do standard config files that the user need not specify

1 0

Source Discrepancy Between QA Version and Snapshot Version
by Lim, Vincent 06 Mar '09

06 Mar '09

Hi All: >From http://www.coreboot.org/Download_coreboot page, I discovered that snapshot version http://tracker.coreboot.org/trac/coreboot/changeset/latest/trunk/coreboo t-v2?old_path=%2F&format=zip (text: ... You can also download the most current snapshot directly.) does not contain the complete source thus is causing 'buildingtarget' to fail. I just did a file diff, it is missing 91 files from the util directory. Meanwhile, If I get it from http://qa.coreboot.org/ -> http://qa.coreboot.org/snapshots/coreboot-v2-3973.tar.bz2 <http://qa.coreboot.org/snapshots/coreboot-v2-3972.tar.bz2> , I am was able to do 'buildtarget' and 'gmake' for example, on serengeti_cheetah_fam10 fine. Is there a reason to keep both mechanism ? It seems like http://qa.coreboot.org/ is a better way to go, since it also doing regression build on every svn checkin. Best Regards, Vincent Lim SimNow Team Performance CoE Central Engineering T 512.602.1618 F 512.602.7745

1 0

Re: [coreboot] coreboot+seabios+gpxe
by Kevin O'Connor 05 Mar '09

05 Mar '09

Hi Joe, I'm CC'ing the coreboot mailing list. On Tue, Mar 03, 2009 at 03:21:00PM -0800, Joe Julian wrote: > I'm attempting to duplicate your results and was wondering about the > OPTIONROM defines you mentioned on the coreboot mailing list: > > #define OPTIONROM_BDF_1 0x0100 > #define OPTIONROM_MEM_1 0xfffc0000 > #define OPTIONROM_BDF_2 0x0048 > #define OPTIONROM_MEM_2 0xfffcf800 > > Where do those addresses come from? The values are where the rom can be found in physical memory, and which PCI device they correspond to. It's now possible to use a helper function when setting the BDF values, so an equivalent of the above is: #define OPTIONROM_BDF_1 pci_to_bdf(0x01, 0x00, 0) #define OPTIONROM_MEM_1 0xfffc0000 #define OPTIONROM_BDF_2 pci_to_bdf(0x00, 0x09, 0) #define OPTIONROM_MEM_2 0xfffcf800 To find the PCI addresses, look at the lspci and find the device ids. On my machine they are from: 01:00.0 VGA compatible controller: VIA Technologies, Inc... 00:09.0 Ethernet controller: Realtek Semiconductor Co... For the memory addresses, I have a 256KiB chip, and the first rom is located at the start of the chip - so it is 0x100000000 - 0x40000 = 0xfffc0000. > Do you still load the video bios in coreboot? No - I have SeaBIOS load and execute all the roms. -Kevin

4 6

[PATCH] flashrom: Remove superfluous volatile
by Carl-Daniel Hailfinger 05 Mar '09

05 Mar '09

During the conversion of flash chip accesses to helper functions, I spotted assignments to volatile variables which were neither placed inside the mmapped ROM area nor were they counters. Due to the use of accessor functions, volatile usage can be reduced significantly because the accessor functions take care of actually performing the reads/writes correctly. The following semantic patch spotted them: r exists@ expression b; typedef uint8_t; volatile uint8_t a; position p1; @@ a@p1 = readb(b); @script:python@ p1 << r.p1; a << r.a; b << r.b; @@ print "* file: %s line %s has assignment to unnecessarily volatile variable: %s = readb(%s);" % (p1[0].file, p1[0].line, a, b) Result was: HANDLING: sst28sf040.c * file: sst28sf040.c line 44 has assignment to unnecessarily volatile variable: tmp = readb(TODO: Binary); * file: sst28sf040.c line 43 has assignment to unnecessarily volatile variable: tmp = readb(TODO: Binary); * file: sst28sf040.c line 42 has assignment to unnecessarily volatile variable: tmp = readb(TODO: Binary); * file: sst28sf040.c line 41 has assignment to unnecessarily volatile variable: tmp = readb(TODO: Binary); * file: sst28sf040.c line 40 has assignment to unnecessarily volatile variable: tmp = readb(TODO: Binary); * file: sst28sf040.c line 39 has assignment to unnecessarily volatile variable: tmp = readb(TODO: Binary); * file: sst28sf040.c line 38 has assignment to unnecessarily volatile variable: tmp = readb(TODO: Binary); * file: sst28sf040.c line 58 has assignment to unnecessarily volatile variable: tmp = readb(TODO: Binary); * file: sst28sf040.c line 57 has assignment to unnecessarily volatile variable: tmp = readb(TODO: Binary); * file: sst28sf040.c line 56 has assignment to unnecessarily volatile variable: tmp = readb(TODO: Binary); * file: sst28sf040.c line 55 has assignment to unnecessarily volatile variable: tmp = readb(TODO: Binary); * file: sst28sf040.c line 54 has assignment to unnecessarily volatile variable: tmp = readb(TODO: Binary); * file: sst28sf040.c line 53 has assignment to unnecessarily volatile variable: tmp = readb(TODO: Binary); * file: sst28sf040.c line 52 has assignment to unnecessarily volatile variable: tmp = readb(TODO: Binary); >From that result, the fix was obvious: Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: flashrom-unneeded_volatile/sst28sf040.c =================================================================== --- flashrom-unneeded_volatile/sst28sf040.c (Revision 3971) +++ flashrom-unneeded_volatile/sst28sf040.c (Arbeitskopie) @@ -32,8 +32,7 @@ static __inline__ void protect_28sf040(volatile uint8_t *bios) { - /* ask compiler not to optimize this */ - volatile uint8_t tmp; + uint8_t tmp; tmp = readb(bios + 0x1823); tmp = readb(bios + 0x1820); @@ -46,8 +45,7 @@ static __inline__ void unprotect_28sf040(volatile uint8_t *bios) { - /* ask compiler not to optimize this */ - volatile uint8_t tmp; + uint8_t tmp; tmp = readb(bios + 0x1823); tmp = readb(bios + 0x1820); -- http://www.hailfinger.org/ Index: flashrom-unneeded_volatile/sst28sf040.c =================================================================== --- flashrom-unneeded_volatile/sst28sf040.c (Revision 3971) +++ flashrom-unneeded_volatile/sst28sf040.c (Arbeitskopie) @@ -32,8 +32,7 @@ static __inline__ void protect_28sf040(volatile uint8_t *bios) { - /* ask compiler not to optimize this */ - volatile uint8_t tmp; + uint8_t tmp; tmp = readb(bios + 0x1823); tmp = readb(bios + 0x1820); @@ -46,8 +45,7 @@ static __inline__ void unprotect_28sf040(volatile uint8_t *bios) { - /* ask compiler not to optimize this */ - volatile uint8_t tmp; + uint8_t tmp; tmp = readb(bios + 0x1823); tmp = readb(bios + 0x1820);

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coreboot March 2009