coreboot March 2009

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r3985 - trunk/util/msrtool
by svn＠coreboot.org 08 Mar '09

08 Mar '09

Author: mjones Date: 2009-03-08 05:37:39 +0100 (Sun, 08 Mar 2009) New Revision: 3985 Added: trunk/util/msrtool/k8.c Modified: trunk/util/msrtool/Makefile.in trunk/util/msrtool/configure trunk/util/msrtool/msrtool.c trunk/util/msrtool/msrtool.h trunk/util/msrtool/msrutils.c Log: Add some basic K8 MSRs. Fix bash script type. Removed const return type on msraddrbyname() to fix gcc warning/error. Signed-off-by: Marc Jones <marcj303(a)gmail.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Peter Stuge <peter(a)stuge.se> Modified: trunk/util/msrtool/Makefile.in =================================================================== --- trunk/util/msrtool/Makefile.in 2009-03-06 22:26:00 UTC (rev 3984) +++ trunk/util/msrtool/Makefile.in 2009-03-08 04:37:39 UTC (rev 3985) @@ -26,7 +26,7 @@ CFLAGS = @CFLAGS@ LDFLAGS = @LDFLAGS@ -TARGETS = geodelx.o cs5536.o +TARGETS = geodelx.o cs5536.o k8.o SYSTEMS = linux.o OBJS = $(PROGRAM).o msrutils.o sys.o $(SYSTEMS) $(TARGETS) Modified: trunk/util/msrtool/configure =================================================================== --- trunk/util/msrtool/configure 2009-03-06 22:26:00 UTC (rev 3984) +++ trunk/util/msrtool/configure 2009-03-08 04:37:39 UTC (rev 3985) @@ -1,4 +1,4 @@ -#!/bin/sh +#!/bin/bash # # This file is part of msrtool. # Added: trunk/util/msrtool/k8.c =================================================================== --- trunk/util/msrtool/k8.c (rev 0) +++ trunk/util/msrtool/k8.c 2009-03-08 04:37:39 UTC (rev 3985) @@ -0,0 +1,366 @@ +/* + * This file is part of msrtool. + * + * Copyright (c) 2009 Marc Jones <marcj303(a)gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include "msrtool.h" + +int k8_probe(const struct targetdef *target) { + struct cpuid_t *id = cpuid(); + return 0xF == id->family; +} + +/* + * AMD BKDG Publication # 32559 Revision: 3.08 Issue Date: July 2007 + */ +const struct msrdef k8_msrs[] = { + { 0xC0000080, MSRTYPE_RDWR, MSR2(0, 0), "EFER Register", "Extended Feature Enable Register", { + { 63, 32, RESERVED }, + { 31, 18, RESERVED }, + { 14, 1, "FFXSR:", "Fast FXSAVE/FRSTOR Enable", PRESENT_DEC, { + { MSR1(0), "FXSAVE/FRSTOR disabled" }, + { MSR1(1), "FXSAVE/FRSTOR enabled" }, + { BITVAL_EOT } + }}, + { 13, 1, "LMSLE:", "Long Mode Segment Limit Enable", PRESENT_DEC, { + { MSR1(0), "Long mode segment limit check disabled" }, + { MSR1(1), "Long mode segment limit check enalbed" }, + { BITVAL_EOT } + }}, + { 12, 1, "SVME:", "SVM Enable", PRESENT_DEC, { + { MSR1(0), "SVM features disabled" }, + { MSR1(1), "SVM features enabled" }, + { BITVAL_EOT } + }}, + { 11, 1, "NXE:", "No-Execute Page Enable", PRESENT_DEC, { + { MSR1(0), "NXE features disabled" }, + { MSR1(1), "NXE features enabled" }, + { BITVAL_EOT } + }}, + { 10, 1, "LMA:", "Long Mode Active", PRESENT_DEC, { + { MSR1(0), "Long Mode feature not active" }, + { MSR1(1), "Long Mode feature active" }, + { BITVAL_EOT } + }}, + { 9, 1, RESERVED }, + { 8, 1, "LME:", "Long Mode Enable", PRESENT_DEC, { + { MSR1(0), "Long Mode feature disabled" }, + { MSR1(1), "Long Mode feature enabled" }, + { BITVAL_EOT } + }}, + { 7, 7, RESERVED }, + { 0, 1, "SYSCALL:", "System Call Extension Enable", PRESENT_DEC, { + { MSR1(0), "System Call feature disabled" }, + { MSR1(1), "System Call feature enabled" }, + { BITVAL_EOT } + }}, + { BITS_EOT } + }}, + + { 0xC0010010, MSRTYPE_RDWR, MSR2(0, 0), "SYSCFG Register", "This register controls the system configuration", { + { 63, 32, RESERVED }, + { 31, 9, RESERVED }, + { 22, 1, "Tom2ForceMemTypeWB:", "Top of Memory 2 Memory Type Write Back", PRESENT_DEC, { + { MSR1(0), "Tom2ForceMemTypeWB disabled" }, + { MSR1(1), "Tom2ForceMemTypeWB enabled" }, + { BITVAL_EOT } + }}, + { 21, 1, "MtrrTom2En:", "Top of Memory Address Register 2 Enable", PRESENT_DEC, { + { MSR1(0), "MtrrTom2En disabled" }, + { MSR1(1), "MtrrTom2En enabled" }, + { BITVAL_EOT } + }}, + { 20, 1, "MtrrVarDramEn:", "Top of Memory Address Register and I/O Range Register Enable", PRESENT_DEC, { + { MSR1(0), "MtrrVarDramEn disabled" }, + { MSR1(1), "MtrrVarDramEn enabled" }, + { BITVAL_EOT } + }}, + { 19, 1, "MtrrFixDramModEn:", "RdDram and WrDram Bits Modification Enable", PRESENT_DEC, { + { MSR1(0), "MtrrFixDramModEn disabled" }, + { MSR1(1), "MtrrFixDramModEn enabled" }, + { BITVAL_EOT } + }}, + { 18, 1, "MtrrFixDramEn:", "Fixed RdDram and WrDram Attributes Enable", PRESENT_DEC, { + { MSR1(0), "MtrrFixDramEn disabled" }, + { MSR1(1), "MtrrFixDramEn enabled" }, + { BITVAL_EOT } + }}, + { 17, 1, "SysUcLockEn:", "System Interface Lock Command Enable", PRESENT_DEC, { + { MSR1(0), "SysUcLockEn disabled" }, + { MSR1(1), "SysUcLockEn enabled" }, + { BITVAL_EOT } + }}, + { 16, 1, "ChxToDirtyDis:", "Change to Dirty Command Disable", PRESENT_DEC, { + { MSR1(0), "ChxToDirtyDis disabled" }, + { MSR1(1), "ChxToDirtyDis enabled" }, + { BITVAL_EOT } + }}, + { 15, 5, RESERVED }, + { 10, 1, "SetDirtyEnO:", "SharedToDirty Command for O->M State Transition Enable", PRESENT_DEC, { + { MSR1(0), "SetDirtyEnO disabled" }, + { MSR1(1), "SetDirtyEnO enabled" }, + { BITVAL_EOT } + }}, + { 9, 1, "SetDirtyEnS:", "SharedToDirty Command for S->M State Transition Enable", PRESENT_DEC, { + { MSR1(0), "SetDirtyEnS disabled" }, + { MSR1(1), "SetDirtyEnS enabled" }, + { BITVAL_EOT } + }}, + { 8, 1, "SetDirtyEnE:", "CleanToDirty Command for E->M State Transition Enable", PRESENT_DEC, { + { MSR1(0), "SetDirtyEnE disabled" }, + { MSR1(1), "SetDirtyEnE enabled" }, + { BITVAL_EOT } + }}, + { 7, 3, "SysVicLimit:", "Outstanding Victim Bus Command Limit", PRESENT_HEX, { + { BITVAL_EOT } + }}, + { 4, 5, "SysAckLimit:", "Outstanding Bus Command Limit", PRESENT_HEX, { + { BITVAL_EOT } + }}, + { BITS_EOT } + }}, + + { 0xC0010015, MSRTYPE_RDWR, MSR2(0, 0), "HWCR Register", "This register controls the harware configuration", { + { 63, 32, RESERVED }, + { 31, 2, RESERVED }, + { 29, 6, "START_FID:", "Status of the startup FID", PRESENT_HEX, { + { BITVAL_EOT } + }}, + { 23, 5, RESERVED }, + { 18, 1, "MCi_STATUS_WREN:", "MCi Status Write Enable", PRESENT_DEC, { + { MSR1(0), "MCi_STATUS_WREN disabled" }, + { MSR1(1), "MCi_STATUS_WREN enabled" }, + { BITVAL_EOT } + }}, + { 17, 1, "WRAP32DIS:", "32-bit Address Wrap Disable", PRESENT_DEC, { + { MSR1(0), "WRAP32DIS clear" }, + { MSR1(1), "WRAP32DIS set" }, + { BITVAL_EOT } + }}, + { 16, 1, RESERVED }, + { 15, 1, "SSEDIS:", "SSE Instructions Disable", PRESENT_DEC, { + { MSR1(0), "SSEDIS clear" }, + { MSR1(1), "SSEDIS set" }, + { BITVAL_EOT } + }}, + { 14, 1, "RSMSPCYCDIS:", "Special Bus Cycle On RSM Disable", PRESENT_DEC, { + { MSR1(0), "RSMSPCYCDIS clear" }, + { MSR1(1), "RSMSPCYCDIS set" }, + { BITVAL_EOT } + }}, + { 13, 1, "SMISPCYCDIS:", "Special Bus Cycle On SMI Disable", PRESENT_DEC, { + { MSR1(0), "SMISPCYCDIS clear" }, + { MSR1(1), "SMISPCYCDIS set" }, + { BITVAL_EOT } + }}, + { 12, 1, "HLTXSPCYCEN:", "Enable Special Bus Cycle On Exit From HLT", PRESENT_DEC, { + { MSR1(0), "HLTXSPCYCEN disabled" }, + { MSR1(1), "HLTXSPCYCEN enabled" }, + { BITVAL_EOT } + }}, + { 11, 4, RESERVED }, + { 8, 1, "IGNNE_EM:", "IGNNE Port Emulation Enable", PRESENT_DEC, { + { MSR1(0), "IGNNE_EM disabled" }, + { MSR1(1), "IGNNE_EM enabled" }, + { BITVAL_EOT } + }}, + { 7, 1, "DISLOCK:", "Disable x86 LOCK prefix functionality", PRESENT_DEC, { + { MSR1(0), "DISLOCK clear" }, + { MSR1(1), "DISLOCK set" }, + { BITVAL_EOT } + }}, + { 6, 1, "FFDIS:", "TLB Flush Filter Disable", PRESENT_DEC, { + { MSR1(0), "FFDIS clear" }, + { MSR1(1), "FFDIS set" }, + { BITVAL_EOT } + }}, + { 5, 1, RESERVED }, + { 4, 1, "INVD_WBINVD:", "INVD to WBINVD Conversion", PRESENT_DEC, { + { MSR1(0), "INVD_WBINVD disabled" }, + { MSR1(1), "INVD_WBINVD enabled" }, + { BITVAL_EOT } + }}, + { 3, 1, "TLBCACHEDIS:", "TLB Cacheable Memory Disable", PRESENT_DEC, { + { MSR1(0), "TLBCACHEDIS clear" }, + { MSR1(1), "TLBCACHEDIS set" }, + { BITVAL_EOT } + }}, + { 2, 1, RESERVED }, + { 1, 1, "SLOWFENCE:", "Slow SFENCE Enable", PRESENT_DEC, { + { MSR1(0), "SLOWFENCE disabled" }, + { MSR1(1), "SLOWFENCE enabled" }, + { BITVAL_EOT } + }}, + { 0, 1, "SMMLOCK:", "SMM Configuration Lock", PRESENT_DEC, { + { MSR1(0), "SMMLOCK disabled" }, + { MSR1(1), "SMMLOCK enabled" }, + { BITVAL_EOT } + }}, + { BITS_EOT } + }}, + + { 0xC001001F, MSRTYPE_RDWR, MSR2(0, 0), "NB_CFG Register", "", { + { 63, 9, RESERVED }, + { 54, 1, "InitApicIdCpuIdLo:", "CpuId and NodeId[2:0] bit field positions are swapped in the APICID", PRESENT_DEC, { + { MSR1(0), "CpuId and NodeId not swapped" }, + { MSR1(1), "CpuId and NodeId swapped" }, + { BITVAL_EOT } + }}, + { 53, 8, RESERVED }, + { 45, 1, "DisUsSysMgtRqToNLdt:", "Disable Upstream System Management Rebroadcast", PRESENT_DEC, { + { MSR1(0), "Upstream Rebroadcast disabled" }, + { MSR1(1), "Upstream Rebroadcast enabled" }, + { BITVAL_EOT } + }}, + { 44, 1, RESERVED }, + { 43, 1, "DisThmlPfMonSmiInt:", "Disable Performance Monitor SMI", PRESENT_DEC, { + { MSR1(0), "Performance Monitor SMI enabled" }, + { MSR1(1), "Performance Monitor SMI disabled" }, + { BITVAL_EOT } + }}, + { 42, 6, RESERVED }, + { 36, 1, "DisDatMsk:", "Disables DRAM data masking function", PRESENT_DEC, { + { MSR1(0), "DRAM data masking enabled" }, + { MSR1(1), "DRAM data masking disabled" }, + { BITVAL_EOT } + }}, + { 35, 4, RESERVED }, + { 31, 1, "DisCohLdtCfg:", "Disable Coherent HyperTransport Configuration Accesses", PRESENT_DEC, { + { MSR1(0), "Coherent HyperTransport Configuration enabled" }, + { MSR1(1), "Coherent HyperTransport Configuration disabled" }, + { BITVAL_EOT } + }}, + { 30, 21, RESERVED }, + { 9, 1, "DisRefUseFreeBuf:", "Disable Display Refresh from Using Free List Buffers", PRESENT_DEC, { + { MSR1(0), "Display refresh requests enabled" }, + { MSR1(1), "Display refresh requests disabled" }, + { BITVAL_EOT } + }}, + { BITS_EOT } + }}, + + { 0xC001001A, MSRTYPE_RDWR, MSR2(0, 0), "TOP_MEM Register", "This register indicates the first byte of I/O above DRAM", { + { 63, 24, RESERVED }, + { 39, 8, "TOM 39-32", "", PRESENT_HEX, { + { BITVAL_EOT } + }}, + { 31, 9, "TOM 31-23", "", PRESENT_HEX, { + { BITVAL_EOT } + }}, + { 22, 23, RESERVED }, + { BITS_EOT } + }}, + + { 0xC001001D, MSRTYPE_RDWR, MSR2(0, 0), "TOP_MEM2 Register", "This register indicates the Top of Memory above 4GB", { + { 63, 24, RESERVED }, + { 39, 8, "TOM2 39-32", "", PRESENT_HEX, { + { BITVAL_EOT } + }}, + { 31, 9, "TOM2 31-23", "", PRESENT_HEX, { + { BITVAL_EOT } + }}, + { 22, 23, RESERVED }, + { BITS_EOT } + }}, + + { 0xC0010016, MSRTYPE_RDWR, MSR2(0, 0), "IORRBase0", "This register holds the base of the variable I/O range", { + { 63, 24, RESERVED }, + { 39, 8, "BASE 27-20", "", PRESENT_HEX, { + { BITVAL_EOT } + }}, + { 31, 20, "BASE 20-0", "", PRESENT_HEX, { + { BITVAL_EOT } + }}, + { 11, 6, RESERVED }, + { 5, 1, "RdDram:", "Read from DRAM", PRESENT_DEC, { + { MSR1(0), "RdDram disabled" }, + { MSR1(1), "RdDram enabled" }, + { BITVAL_EOT } + }}, + { 4, 1, "WrDram:", "Write to DRAM", PRESENT_DEC, { + { MSR1(0), "WrDram disabled" }, + { MSR1(1), "WrDram enabled" }, + { BITVAL_EOT } + }}, + { BITS_EOT } + }}, + + { 0xC0010017, MSRTYPE_RDWR, MSR2(0, 0), "IORRMask0", "This register holds the mask of the variable I/O range", { + { 63, 24, RESERVED }, + { 39, 8, "MASK 27-20", "", PRESENT_HEX, { + { BITVAL_EOT } + }}, + { 31, 20, "MASK 20-0", "", PRESENT_HEX, { + { BITVAL_EOT } + }}, + { 11, 1, "V:", "Enables variable I/O range registers", PRESENT_DEC, { + { MSR1(0), "V I/O range disabled" }, + { MSR1(1), "V I/O range enabled" }, + { BITVAL_EOT } + }}, + { 10, 11, RESERVED }, + { BITS_EOT } + }}, + + { 0xC0010018, MSRTYPE_RDWR, MSR2(0, 0), "IORRBase1", "This register holds the base of the variable I/O range", { + { 63, 24, RESERVED }, + { 39, 8, "BASE 27-20", "", PRESENT_HEX, { + { BITVAL_EOT } + }}, + { 31, 20, "BASE 20-0", "", PRESENT_HEX, { + { BITVAL_EOT } + }}, + { 11, 6, RESERVED }, + { 5, 1, "RdDram:", "Read from DRAM", PRESENT_DEC, { + { MSR1(0), "RdDram disabled" }, + { MSR1(1), "RdDram enabled" }, + { BITVAL_EOT } + }}, + { 4, 1, "WrDram:", "Write to DRAM", PRESENT_DEC, { + { MSR1(0), "WrDram disabled" }, + { MSR1(1), "WrDram enabled" }, + { BITVAL_EOT } + }}, + { BITS_EOT } + }}, + + { 0xC0010019, MSRTYPE_RDWR, MSR2(0, 0), "IORRMask1", "This register holds the mask of the variable I/O range", { + { 63, 24, RESERVED }, + { 39, 8, "MASK 27-20", "", PRESENT_HEX, { + { BITVAL_EOT } + }}, + { 31, 20, "MASK 20-0", "", PRESENT_HEX, { + { BITVAL_EOT } + }}, + { 11, 1, "V:", "Enables variable I/O range registers", PRESENT_DEC, { + { MSR1(0), "V I/O range disabled" }, + { MSR1(1), "V I/O range enabled" }, + { BITVAL_EOT } + }}, + { 10, 11, RESERVED }, + { BITS_EOT } + }}, + +/* + { 0, MSRTYPE_RDONLY, MSR2(0, 0), "TEMPLATE", "Template MSR", { + { 63, 64, RESERVED }, + { BITS_EOT } + }}, +*/ + + { MSR_EOT } +}; Modified: trunk/util/msrtool/msrtool.c =================================================================== --- trunk/util/msrtool/msrtool.c 2009-03-06 22:26:00 UTC (rev 3984) +++ trunk/util/msrtool/msrtool.c 2009-03-08 04:37:39 UTC (rev 3985) @@ -42,6 +42,7 @@ static struct targetdef alltargets[] = { { "geodelx", "AMD Geode(tm) LX", geodelx_probe, geodelx_msrs }, { "cs5536", "AMD Geode(tm) CS5536", cs5536_probe, cs5536_msrs }, + { "K8", "AMD K8 Family", k8_probe, k8_msrs }, { TARGET_EOT } }; Modified: trunk/util/msrtool/msrtool.h =================================================================== --- trunk/util/msrtool/msrtool.h 2009-03-06 22:26:00 UTC (rev 3984) +++ trunk/util/msrtool/msrtool.h 2009-03-08 04:37:39 UTC (rev 3985) @@ -157,7 +157,7 @@ struct msr msr_shr(const struct msr a, const uint8_t bits); void msr_and(struct msr *a, const struct msr b); const struct msrdef *findmsrdef(const uint32_t addr); -const uint32_t msraddrbyname(const char *name); +uint32_t msraddrbyname(const char *name); void dumpmsrdefs(const struct targetdef *t); int dumpmsrdefsvals(FILE *f, const struct targetdef *t, const uint8_t cpu); uint8_t str2msr(char *str, struct msr *msr); @@ -185,4 +185,8 @@ extern int cs5536_probe(const struct targetdef *t); extern const struct msrdef cs5536_msrs[]; +/* k8.c */ +extern int k8_probe(const struct targetdef *t); +extern const struct msrdef k8_msrs[]; + #endif /* MSRTOOL_H */ Modified: trunk/util/msrtool/msrutils.c =================================================================== --- trunk/util/msrtool/msrutils.c 2009-03-06 22:26:00 UTC (rev 3984) +++ trunk/util/msrtool/msrutils.c 2009-03-08 04:37:39 UTC (rev 3985) @@ -137,7 +137,7 @@ return NULL; } -const uint32_t msraddrbyname(const char *name) { +uint32_t msraddrbyname(const char *name) { uint8_t t; const uint32_t addr = strtoul(name, NULL, 16); const struct msrdef *m;

1 0

GA-P31-ES3G motherboard support
by Roman Mindalev 07 Mar '09

07 Mar '09

Hi! Recently I'm get this PC: Intel E2200 Dual Core processor Gigabyte GA-P31-ES3G motherboard (P31 northbridge, ICH7 southbridge) flashrom r3844 with PAT disabled successfully made BIOS backup: Found chipset "Intel ICH7/ICH7R", enabling flash write... OK. Found chip "Macronix MX25L4005" (512 KB) at physical address 0xfff80000 lspci output: 00:00.0 Host bridge: Intel Corporation 82G33/G31/P35/P31 Express DRAM Controller (rev 10) 00:01.0 PCI bridge: Intel Corporation 82G33/G31/P35/P31 Express PCI Express Root Port (rev 10) 00:1b.0 Audio device: Intel Corporation 82801G (ICH7 Family) High Definition Audio Controller (rev 01) 00:1c.0 PCI bridge: Intel Corporation 82801G (ICH7 Family) PCI Express Port 1 (rev 01) 00:1c.1 PCI bridge: Intel Corporation 82801G (ICH7 Family) PCI Express Port 2 (rev 01) 00:1d.0 USB Controller: Intel Corporation 82801G (ICH7 Family) USB UHCI Controller #1 (rev 01) 00:1d.1 USB Controller: Intel Corporation 82801G (ICH7 Family) USB UHCI Controller #2 (rev 01) 00:1d.2 USB Controller: Intel Corporation 82801G (ICH7 Family) USB UHCI Controller #3 (rev 01) 00:1d.3 USB Controller: Intel Corporation 82801G (ICH7 Family) USB UHCI Controller #4 (rev 01) 00:1d.7 USB Controller: Intel Corporation 82801G (ICH7 Family) USB2 EHCI Controller (rev 01) 00:1e.0 PCI bridge: Intel Corporation 82801 PCI Bridge (rev e1) 00:1f.0 ISA bridge: Intel Corporation 82801GB/GR (ICH7 Family) LPC Interface Bridge (rev 01) 00:1f.1 IDE interface: Intel Corporation 82801G (ICH7 Family) IDE Controller (rev 01) 00:1f.2 IDE interface: Intel Corporation 82801GB/GR/GH (ICH7 Family) SATA IDE Controller (rev 01) 00:1f.3 SMBus: Intel Corporation 82801G (ICH7 Family) SMBus Controller (rev 01) 01:00.0 VGA compatible controller: nVidia Corporation GeForce 8400 GS (rev a1) 03:00.0 Ethernet controller: Realtek Semiconductor Co., Ltd. RTL8111/8168B PCI Express Gigabit Ethernet controller (rev 02) Any chance for this hardware to be supported by coreboot?

2 2

Re: [coreboot] seaBIOS config options "for emulators"
by Joe Julian 07 Mar '09

07 Mar '09

Kevin O'Connor wrote: > On Fri, Mar 06, 2009 at 05:18:15PM -0800, Joe Julian wrote: > >> I find this patch >> http://www.coreboot.org/pipermail/coreboot/2009-February/045068.html >> > > Yes. You need to apply that patch. (Please confirm your machine has > at least 1GiB of memory.) > > The next thing you need to do is setup your SeaBIOS src/config.h. It > should have CONFIG_COREBOOT set, CONFIG_DEBUG_SERIAL set, > CONFIG_OPTIONROMS_DEPLOYED unset, and OPTIONROM_BDF/MEM_* set. I > think you've already done this. > > Then, one compiles the above, and flashes the chip. > > If you're not seeing the correct output, something must be wrong. > You'll need to capture the serial output and send the log. With the > log, we'll be able to figure out what went wrong. > Thanks for your help. I can't directly apply that patch because it's been superseded by this one http://tracker.coreboot.org/trac/coreboot/changeset/3960 which works for me so far, with the following changes. There's a little bit of workaround there, as I don't know how to patch the HAVE_HIGH_TABLES into src/northbridge/amd/amdfam10/northbridge.c Here's a link to my log: http://www.privatepaste.com/04ilD2DoPH And yes, the machine has more than 1Gb. It has 8. --- src/arch/i386/boot/tables.c (revision 3981) +++ src/arch/i386/boot/tables.c (working copy) @@ -58,7 +58,7 @@ } #if HAVE_HIGH_TABLES == 1 -uint64_t high_tables_base = 0; +uint64_t high_tables_base = 0x3dff0000; uint64_t high_tables_size; #endif @@ -188,11 +187,12 @@ rom_table_start, rom_table_end); #endif +#if 0 /* The coreboot table must be in 0-4K or 960K-1M */ write_coreboot_table(low_table_start, low_table_end, rom_table_start, rom_table_end); -#if 0 && HAVE_HIGH_TABLES == 1 +#else // HAVE_HIGH_TABLES == 1 /* This is currently broken and should be severely refactored. Ideally * we only have a pointer to the coreboot table in the low memory, so * anyone can find the real position. @@ -205,8 +205,8 @@ * corrupted */ if (high_tables_base) { - write_coreboot_table(high_table_start, high_table_end, - high_table_start, high_table_end); + write_coreboot_table(low_table_start, low_table_end, + high_table_start, high_table_end); } #endif --- src/mainboard/tyan/s2912_fam10/mainboard.c (revision 3981) +++ src/mainboard/tyan/s2912_fam10/mainboard.c (working copy) @@ -24,6 +24,7 @@ #include <device/pci.h> #include <device/pci_ids.h> #include <device/pci_ops.h> +#include <boot/tables.h> #include "chip.h" #if CONFIG_CHIP_NAME == 1 @@ -31,3 +32,15 @@ CHIP_NAME("Tyan S2912 Mainboard (Family 10)") }; #endif +/* in arch/i386/boot/tables.c */ +extern uint64_t high_tables_base, high_tables_size; + +int add_mainboard_resources(struct lb_memory *mem) +{ +#if HAVE_HIGH_TABLES == 1 + printk_debug("Adding high table area\n"); + lb_add_memory_range(mem, LB_MEM_TABLE, + high_tables_base, high_tables_size); +#endif +return 0; +} Index: src/mainboard/tyan/s2912_fam10/Options.lb =================================================================== --- src/mainboard/tyan/s2912_fam10/Options.lb (revision 3981) +++ src/mainboard/tyan/s2912_fam10/Options.lb (working copy) @@ -22,6 +22,8 @@ uses HAVE_MP_TABLE uses HAVE_PIRQ_TABLE uses HAVE_ACPI_TABLES +uses HAVE_MAINBOARD_RESOURCES +uses HAVE_HIGH_TABLES uses ACPI_SSDTX_NUM uses USE_FALLBACK_IMAGE uses USE_FAILOVER_IMAGE @@ -166,6 +168,8 @@ ## ACPI tables will be included default HAVE_ACPI_TABLES=0 +default HAVE_MAINBOARD_RESOURCES=0 +default HAVE_HIGH_TABLES=1 ## extra SSDT num default ACPI_SSDTX_NUM=31 @@ -211,8 +215,8 @@ #default HW_MEM_HOLE_SIZE_AUTO_INC=1 #VGA Console -default CONFIG_CONSOLE_VGA=1 -default CONFIG_PCI_ROM_RUN=1 +default CONFIG_CONSOLE_VGA=0 +default CONFIG_PCI_ROM_RUN=0 #default CONFIG_USBDEBUG_DIRECT=1

2 1

965/ICH8 ?
by Peter Stuge 07 Mar '09

07 Mar '09

How different are they from 945/ICH7? Target: http://www.commell.com.tw/Product/SBC/LV-679.HTM Am thinking to try the Kontron port to see what happens. Hobby project though. //Peter

2 1

FILO failure
by ron minnich 07 Mar '09

07 Mar '09

This is on the kontron with a USB drive. It's very consistent. We might need a slightly more informative error message than "panic". thanks ron FILO version 0.6.0rc1 (rminnich(a)xcpu2.sandia.gov) Fri Mar 6 23:31:02 PST 2009 00:1d.0 27c8:8086.0 UHCI controller fullspeed device maxPacketSize0: 40 device version: 2.0 device has 1 configurations device has 1 interfaces #0 has 2 endpoints, interface 8:6, protocol 50 #1: Endpoint 1 (in), max packet size 40, type bulk #2: Endpoint 2 (out), max packet size 40, type bulk device of class 8 found MSC found it uses SCSI transparent command set it uses Bulk-Only Transport protocol using endpoint 81 as in, 2 as out has 1 luns Waiting for device to become ready... .........timeout. Device not ready. Sti. spin up. OK. has 3963904 blocks sized 512b 00:1d.1 27c9:8086.1 UHCI controller warning: device 0 reassigned? 00:1d.2 27ca:8086.2 UHCI controller 00:1d.3 27cb:8086.3 UHCI controller memory allocator panic.

1 0

ACPI/APIC related questions in coreboot.
by Harald Gutmann 06 Mar '09

06 Mar '09

Hello, at the moment i try to get acpi support running with the gigabyte m57sli mainboard. a few things are allready done (fill fadt, dsdt.asl and a pretty "raw" acpi_tables.c). Now my problem is, that i can't figure out the right values to set up the madt and mcfg acpi tables. On the coreboot wiki page according to acpi it's listed to check the source of asus/m2v-mx_se how to fill/create the madt tables. My problem for now is just, where do i find the right values to fill that table correctly? The values which are used in the example are alled #defined somewhere, but for mcp55 i couldn't find values which are defined somewhere and named the same style like those for via. Trying to set up the mcfg table i tried to "guess" the right value for finding the right "dev" to set it up at the correct address base. Here is my guessed suggest for the right values: dev = dev_find_device(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_MCP55_PCI, 0); //or is PCI_DEVICE_ID_NVIDIA_MCP55_LPC correct if (!dev) return current; res = find_resource(dev, K8T890_MMCONFIG_MBAR); /*where to find the right value for mcp55 instead of k8t890? (guessing is not a really good idea, coreboot fails on bootup if that value doesn't exist.*/ if (res) { current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *) current, res->base, 0x0, 0x0, 0xff); } What does work until now, nothing "great" but it seems that fadt is filled correctly and that the dsdt.asl file is also fine, but it's hard to verify when linux hangs after wring an error message that no lapic entries are present and that mmconfig has no entries. I'd be really glad to get some hints how/where i could find out the needed values. Kind regards, Harald Gutmann

2 3

proposed cpu startup change
by ron minnich 06 Mar '09

06 Mar '09

This is a proposal for cpu startup on v3. It is motivated by the needs of SMP. The idea is that we introduce cpu phases to parallel the device phases. Because, on modern CPUs, we can dynamically probe pretty much everything, we don't use the device tree for CPUs; that was always a point of confusion on v2 anyway. Rather, in this example, we define cpu_phase1 and cpu_phase 6 (for example) and define weak symbols for them. These functions can be over-ridden by platform or cpu functions. Here's the patch. Comments welcome. ron Index: lib/stage2.c =================================================================== --- lib/stage2.c (revision 1143) +++ lib/stage2.c (working copy) @@ -28,6 +28,18 @@ #include <device/device.h> #include <tables.h> +void __attribute__((weak)) unsigned int cpu_phase1(unsigned int coldboot, + struct sys_info *sysinfo) +{ + printk(BIOS_SPEW, "cpu_phase1: nothing to do\n"); +} + +void __attribute__((weak)) unsigned int cpu_phase6(unsigned int coldboot, + struct sys_info *sysinfo) +{ + printk(BIOS_SPEW, "cpu_phase6: nothing to do\n"); +} + /** * Main function of the DRAM part of coreboot. * @@ -44,8 +56,10 @@ void *stage2(void) { void *mbi; + struct sys_info *sysinfo = &(global_vars()->sys_info); post_code(POST_STAGE2_BEGIN); + cpu_phase1(is_coldboot(), sysinfo); dev_init(); /* Phase 1 was console init and making printk work. Both functions are @@ -85,6 +99,11 @@ dev_phase6(); show_all_devs(BIOS_DEBUG, "After phase 6."); + /* final cleanup: do any remaining CPU setup. This can include memory + * init, or not, depending on the CPU; it may have been done in phase 1. + */ + cpu_phase6(is_coldboot(), sysinfo); + /* Write tables to pass information to the payloads. */ post_code(POST_STAGE2_WRITE_TABLES); mbi = write_tables();

2 6

[PATCH] flashrom: Rename chip accessor functions
by Carl-Daniel Hailfinger 06 Mar '09

06 Mar '09

FreeBSD definitions of (read|write)[bwl] collide with our own. Before we attempt trickery, we can simply rename the accessor functions. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: flashrom-rename_chip_accessors/flash.h =================================================================== --- flashrom-rename_chip_accessors/flash.h (Revision 3973) +++ flashrom-rename_chip_accessors/flash.h (Arbeitskopie) @@ -58,32 +58,32 @@ #define INL inl #endif -static inline void writeb(uint8_t b, volatile void *addr) +static inline void chip_writeb(uint8_t b, volatile void *addr) { *(volatile uint8_t *) addr = b; } -static inline void writew(uint16_t b, volatile void *addr) +static inline void chip_writew(uint16_t b, volatile void *addr) { *(volatile uint16_t *) addr = b; } -static inline void writel(uint32_t b, volatile void *addr) +static inline void chip_writel(uint32_t b, volatile void *addr) { *(volatile uint32_t *) addr = b; } -static inline uint8_t readb(const volatile void *addr) +static inline uint8_t chip_readb(const volatile void *addr) { return *(volatile uint8_t *) addr; } -static inline uint16_t readw(const volatile void *addr) +static inline uint16_t chip_readw(const volatile void *addr) { return *(volatile uint16_t *) addr; } -static inline uint32_t readl(const volatile void *addr) +static inline uint32_t chip_readl(const volatile void *addr) { return *(volatile uint32_t *) addr; } Index: flashrom-rename_chip_accessors/pm49fl00x.c =================================================================== --- flashrom-rename_chip_accessors/pm49fl00x.c (Revision 3973) +++ flashrom-rename_chip_accessors/pm49fl00x.c (Arbeitskopie) @@ -35,7 +35,7 @@ if (block_size == 16384 && i % 2) continue; - writeb(bits, bios + (i * block_size) + 2); + chip_writeb(bits, bios + (i * block_size) + 2); } } Index: flashrom-rename_chip_accessors/en29f002a.c =================================================================== --- flashrom-rename_chip_accessors/en29f002a.c (Revision 3973) +++ flashrom-rename_chip_accessors/en29f002a.c (Arbeitskopie) @@ -35,19 +35,19 @@ volatile uint8_t *bios = flash->virtual_memory; uint8_t id1, id2; - writeb(0xAA, bios + 0x555); - writeb(0x55, bios + 0x2AA); - writeb(0x90, bios + 0x555); + chip_writeb(0xAA, bios + 0x555); + chip_writeb(0x55, bios + 0x2AA); + chip_writeb(0x90, bios + 0x555); myusec_delay(10); - id1 = readb(bios + 0x100); - id2 = readb(bios + 0x101); + id1 = chip_readb(bios + 0x100); + id2 = chip_readb(bios + 0x101); /* exit by writing F0 anywhere? or the code below */ - writeb(0xAA, bios + 0x555); - writeb(0x55, bios + 0x2AA); - writeb(0xF0, bios + 0x555); + chip_writeb(0xAA, bios + 0x555); + chip_writeb(0x55, bios + 0x2AA); + chip_writeb(0xF0, bios + 0x555); printf_debug("%s: id1 0x%02x, id2 0x%02x\n", __FUNCTION__, id1, id2); @@ -68,19 +68,19 @@ volatile uint8_t *bios = flash->virtual_memory; uint8_t id1, id2; - writeb(0xAA, bios + 0x555); - writeb(0x55, bios + 0xAAA); - writeb(0x90, bios + 0x555); + chip_writeb(0xAA, bios + 0x555); + chip_writeb(0x55, bios + 0xAAA); + chip_writeb(0x90, bios + 0x555); myusec_delay(10); - id1 = readb(bios + 0x100); - id2 = readb(bios + 0x101); + id1 = chip_readb(bios + 0x100); + id2 = chip_readb(bios + 0x101); /* exit by writing F0 anywhere? or the code below */ - writeb(0xAA, bios + 0x555); - writeb(0x55, bios + 0xAAA); - writeb(0xF0, bios + 0x555); + chip_writeb(0xAA, bios + 0x555); + chip_writeb(0x55, bios + 0xAAA); + chip_writeb(0xF0, bios + 0x555); printf_debug("%s: id1 0x%x, id2 0x%x\n", __FUNCTION__, id1, id2); @@ -107,10 +107,10 @@ /* write to the sector */ if ((i & 0xfff) == 0) printf("address: 0x%08lx", (unsigned long)i); - writeb(0xAA, bios + 0x5555); - writeb(0x55, bios + 0x2AAA); - writeb(0xA0, bios + 0x5555); - writeb(*buf++, dst++); + chip_writeb(0xAA, bios + 0x5555); + chip_writeb(0x55, bios + 0x2AAA); + chip_writeb(0xA0, bios + 0x5555); + chip_writeb(*buf++, dst++); /* wait for Toggle bit ready */ toggle_ready_jedec(dst); Index: flashrom-rename_chip_accessors/jedec.c =================================================================== --- flashrom-rename_chip_accessors/jedec.c (Revision 3973) +++ flashrom-rename_chip_accessors/jedec.c (Arbeitskopie) @@ -40,10 +40,10 @@ unsigned int i = 0; uint8_t tmp1, tmp2; - tmp1 = readb(dst) & 0x40; + tmp1 = chip_readb(dst) & 0x40; while (i++ < 0xFFFFFFF) { - tmp2 = readb(dst) & 0x40; + tmp2 = chip_readb(dst) & 0x40; if (tmp1 == tmp2) { break; } @@ -59,7 +59,7 @@ data &= 0x80; while (i++ < 0xFFFFFFF) { - tmp = readb(dst) & 0x80; + tmp = chip_readb(dst) & 0x80; if (tmp == data) { break; } @@ -68,21 +68,21 @@ void unprotect_jedec(volatile uint8_t *bios) { - writeb(0xAA, bios + 0x5555); - writeb(0x55, bios + 0x2AAA); - writeb(0x80, bios + 0x5555); - writeb(0xAA, bios + 0x5555); - writeb(0x55, bios + 0x2AAA); - writeb(0x20, bios + 0x5555); + chip_writeb(0xAA, bios + 0x5555); + chip_writeb(0x55, bios + 0x2AAA); + chip_writeb(0x80, bios + 0x5555); + chip_writeb(0xAA, bios + 0x5555); + chip_writeb(0x55, bios + 0x2AAA); + chip_writeb(0x20, bios + 0x5555); usleep(200); } void protect_jedec(volatile uint8_t *bios) { - writeb(0xAA, bios + 0x5555); - writeb(0x55, bios + 0x2AAA); - writeb(0xA0, bios + 0x5555); + chip_writeb(0xAA, bios + 0x5555); + chip_writeb(0x55, bios + 0x2AAA); + chip_writeb(0xA0, bios + 0x5555); usleep(200); } @@ -94,40 +94,40 @@ uint32_t largeid1, largeid2; /* Issue JEDEC Product ID Entry command */ - writeb(0xAA, bios + 0x5555); + chip_writeb(0xAA, bios + 0x5555); myusec_delay(10); - writeb(0x55, bios + 0x2AAA); + chip_writeb(0x55, bios + 0x2AAA); myusec_delay(10); - writeb(0x90, bios + 0x5555); + chip_writeb(0x90, bios + 0x5555); /* Older chips may need up to 100 us to respond. The ATMEL 29C020 * needs 10 ms according to the data sheet. */ myusec_delay(10000); /* Read product ID */ - id1 = readb(bios); - id2 = readb(bios + 0x01); + id1 = chip_readb(bios); + id2 = chip_readb(bios + 0x01); largeid1 = id1; largeid2 = id2; /* Check if it is a continuation ID, this should be a while loop. */ if (id1 == 0x7F) { largeid1 <<= 8; - id1 = readb(bios + 0x100); + id1 = chip_readb(bios + 0x100); largeid1 |= id1; } if (id2 == 0x7F) { largeid2 <<= 8; - id2 = readb(bios + 0x101); + id2 = chip_readb(bios + 0x101); largeid2 |= id2; } /* Issue JEDEC Product ID Exit command */ - writeb(0xAA, bios + 0x5555); + chip_writeb(0xAA, bios + 0x5555); myusec_delay(10); - writeb(0x55, bios + 0x2AAA); + chip_writeb(0x55, bios + 0x2AAA); myusec_delay(10); - writeb(0xF0, bios + 0x5555); + chip_writeb(0xF0, bios + 0x5555); myusec_delay(40); printf_debug("%s: id1 0x%02x, id2 0x%02x", __FUNCTION__, largeid1, largeid2); @@ -143,18 +143,18 @@ int erase_sector_jedec(volatile uint8_t *bios, unsigned int page) { /* Issue the Sector Erase command */ - writeb(0xAA, bios + 0x5555); + chip_writeb(0xAA, bios + 0x5555); myusec_delay(10); - writeb(0x55, bios + 0x2AAA); + chip_writeb(0x55, bios + 0x2AAA); myusec_delay(10); - writeb(0x80, bios + 0x5555); + chip_writeb(0x80, bios + 0x5555); myusec_delay(10); - writeb(0xAA, bios + 0x5555); + chip_writeb(0xAA, bios + 0x5555); myusec_delay(10); - writeb(0x55, bios + 0x2AAA); + chip_writeb(0x55, bios + 0x2AAA); myusec_delay(10); - writeb(0x30, bios + page); + chip_writeb(0x30, bios + page); myusec_delay(10); /* wait for Toggle bit ready */ @@ -166,18 +166,18 @@ int erase_block_jedec(volatile uint8_t *bios, unsigned int block) { /* Issue the Sector Erase command */ - writeb(0xAA, bios + 0x5555); + chip_writeb(0xAA, bios + 0x5555); myusec_delay(10); - writeb(0x55, bios + 0x2AAA); + chip_writeb(0x55, bios + 0x2AAA); myusec_delay(10); - writeb(0x80, bios + 0x5555); + chip_writeb(0x80, bios + 0x5555); myusec_delay(10); - writeb(0xAA, bios + 0x5555); + chip_writeb(0xAA, bios + 0x5555); myusec_delay(10); - writeb(0x55, bios + 0x2AAA); + chip_writeb(0x55, bios + 0x2AAA); myusec_delay(10); - writeb(0x50, bios + block); + chip_writeb(0x50, bios + block); myusec_delay(10); /* wait for Toggle bit ready */ @@ -191,18 +191,18 @@ volatile uint8_t *bios = flash->virtual_memory; /* Issue the JEDEC Chip Erase command */ - writeb(0xAA, bios + 0x5555); + chip_writeb(0xAA, bios + 0x5555); myusec_delay(10); - writeb(0x55, bios + 0x2AAA); + chip_writeb(0x55, bios + 0x2AAA); myusec_delay(10); - writeb(0x80, bios + 0x5555); + chip_writeb(0x80, bios + 0x5555); myusec_delay(10); - writeb(0xAA, bios + 0x5555); + chip_writeb(0xAA, bios + 0x5555); myusec_delay(10); - writeb(0x55, bios + 0x2AAA); + chip_writeb(0x55, bios + 0x2AAA); myusec_delay(10); - writeb(0x10, bios + 0x5555); + chip_writeb(0x10, bios + 0x5555); myusec_delay(10); toggle_ready_jedec(bios); @@ -219,15 +219,15 @@ retry: /* Issue JEDEC Data Unprotect comand */ - writeb(0xAA, bios + 0x5555); - writeb(0x55, bios + 0x2AAA); - writeb(0xA0, bios + 0x5555); + chip_writeb(0xAA, bios + 0x5555); + chip_writeb(0x55, bios + 0x2AAA); + chip_writeb(0xA0, bios + 0x5555); /* transfer data from source to destination */ for (i = start_index; i < page_size; i++) { /* If the data is 0xFF, don't program it */ if (*src != 0xFF) - writeb(*src, dst); + chip_writeb(*src, dst); dst++; src++; } @@ -238,7 +238,7 @@ src = s; ok = 1; for (i = 0; i < page_size; i++) { - if (readb(dst) != *src) { + if (chip_readb(dst) != *src) { ok = 0; break; } @@ -269,15 +269,15 @@ retry: /* Issue JEDEC Byte Program command */ - writeb(0xAA, bios + 0x5555); - writeb(0x55, bios + 0x2AAA); - writeb(0xA0, bios + 0x5555); + chip_writeb(0xAA, bios + 0x5555); + chip_writeb(0x55, bios + 0x2AAA); + chip_writeb(0xA0, bios + 0x5555); /* transfer data from source to destination */ - writeb(*src, dst); + chip_writeb(*src, dst); toggle_ready_jedec(bios); - if (readb(dst) != *src && tried++ < MAX_REFLASH_TRIES) { + if (chip_readb(dst) != *src && tried++ < MAX_REFLASH_TRIES) { goto retry; } Index: flashrom-rename_chip_accessors/w29ee011.c =================================================================== --- flashrom-rename_chip_accessors/w29ee011.c (Revision 3973) +++ flashrom-rename_chip_accessors/w29ee011.c (Arbeitskopie) @@ -37,29 +37,29 @@ } /* Issue JEDEC Product ID Entry command */ - writeb(0xAA, bios + 0x5555); + chip_writeb(0xAA, bios + 0x5555); myusec_delay(10); - writeb(0x55, bios + 0x2AAA); + chip_writeb(0x55, bios + 0x2AAA); myusec_delay(10); - writeb(0x80, bios + 0x5555); + chip_writeb(0x80, bios + 0x5555); myusec_delay(10); - writeb(0xAA, bios + 0x5555); + chip_writeb(0xAA, bios + 0x5555); myusec_delay(10); - writeb(0x55, bios + 0x2AAA); + chip_writeb(0x55, bios + 0x2AAA); myusec_delay(10); - writeb(0x60, bios + 0x5555); + chip_writeb(0x60, bios + 0x5555); myusec_delay(10); /* Read product ID */ - id1 = readb(bios); - id2 = readb(bios + 0x01); + id1 = chip_readb(bios); + id2 = chip_readb(bios + 0x01); /* Issue JEDEC Product ID Exit command */ - writeb(0xAA, bios + 0x5555); + chip_writeb(0xAA, bios + 0x5555); myusec_delay(10); - writeb(0x55, bios + 0x2AAA); + chip_writeb(0x55, bios + 0x2AAA); myusec_delay(10); - writeb(0xF0, bios + 0x5555); + chip_writeb(0xF0, bios + 0x5555); myusec_delay(10); printf_debug("%s: id1 0x%02x, id2 0x%02x\n", __FUNCTION__, id1, id2); Index: flashrom-rename_chip_accessors/sst49lfxxxc.c =================================================================== --- flashrom-rename_chip_accessors/sst49lfxxxc.c (Revision 3973) +++ flashrom-rename_chip_accessors/sst49lfxxxc.c (Arbeitskopie) @@ -50,20 +50,20 @@ //printf("bios=0x%08lx\n", (unsigned long)bios); for (i = 0; left > 65536; i++, left -= 65536) { //printf("lockbits at address=0x%08lx is 0x%01x\n", (unsigned long)0xFFC00000 - size + (i * 65536) + 2, *(bios + (i * 65536) + 2) ); - writeb(bits, bios + (i * 65536) + 2); + chip_writeb(bits, bios + (i * 65536) + 2); } address = i * 65536; //printf("lockbits at address=0x%08lx is 0x%01x\n", (unsigned long)0xFFc00000 - size + address + 2, *(bios + address + 2) ); - writeb(bits, bios + address + 2); + chip_writeb(bits, bios + address + 2); address += 32768; //printf("lockbits at address=0x%08lx is 0x%01x\n", (unsigned long)0xFFc00000 - size + address + 2, *(bios + address + 2) ); - writeb(bits, bios + address + 2); + chip_writeb(bits, bios + address + 2); address += 8192; //printf("lockbits at address=0x%08lx is 0x%01x\n", (unsigned long)0xFFc00000 - size + address + 2, *(bios + address + 2) ); - writeb(bits, bios + address + 2); + chip_writeb(bits, bios + address + 2); address += 8192; //printf("lockbits at address=0x%08lx is 0x%01x\n", (unsigned long)0xFFc00000 - size + address + 2, *(bios + address + 2) ); - writeb(bits, bios + address + 2); + chip_writeb(bits, bios + address + 2); return 0; } @@ -73,14 +73,14 @@ { unsigned char status; - writeb(SECTOR_ERASE, bios); - writeb(ERASE, bios + address); + chip_writeb(SECTOR_ERASE, bios); + chip_writeb(ERASE, bios + address); do { - status = readb(bios); + status = chip_readb(bios); if (status & (STATUS_ESS | STATUS_BPS)) { printf("sector erase FAILED at address=0x%08lx status=0x%01x\n", (unsigned long)bios + address, status); - writeb(CLEAR_STATUS, bios); + chip_writeb(CLEAR_STATUS, bios); return (-1); } } while (!(status & STATUS_WSMS)); @@ -96,7 +96,7 @@ int i; unsigned char status; - writeb(CLEAR_STATUS, bios); + chip_writeb(CLEAR_STATUS, bios); for (i = 0; i < page_size; i++) { /* transfer data from source to destination */ if (*src == 0xFF) { @@ -105,14 +105,14 @@ continue; } /*issue AUTO PROGRAM command */ - writeb(AUTO_PGRM, bios); - writeb(*src++, dst++); + chip_writeb(AUTO_PGRM, bios); + chip_writeb(*src++, dst++); do { - status = readb(bios); + status = chip_readb(bios); if (status & (STATUS_ESS | STATUS_BPS)) { printf("sector write FAILED at address=0x%08lx status=0x%01x\n", (unsigned long)dst, status); - writeb(CLEAR_STATUS, bios); + chip_writeb(CLEAR_STATUS, bios); return (-1); } } while (!(status & STATUS_WSMS)); @@ -127,13 +127,13 @@ uint8_t id1, id2; - writeb(RESET, bios); + chip_writeb(RESET, bios); - writeb(READ_ID, bios); - id1 = readb(bios); - id2 = readb(bios + 0x01); + chip_writeb(READ_ID, bios); + id1 = chip_readb(bios); + id2 = chip_readb(bios + 0x01); - writeb(RESET, bios); + chip_writeb(RESET, bios); printf_debug("%s: id1 0x%02x, id2 0x%02x\n", __FUNCTION__, id1, id2); @@ -157,7 +157,7 @@ if (erase_sector_49lfxxxc(bios, i) != 0) return (-1); - writeb(RESET, bios); + chip_writeb(RESET, bios); return 0; } @@ -183,7 +183,7 @@ } printf("\n"); - writeb(RESET, bios); + chip_writeb(RESET, bios); return 0; } Index: flashrom-rename_chip_accessors/sharplhf00l04.c =================================================================== --- flashrom-rename_chip_accessors/sharplhf00l04.c (Revision 3973) +++ flashrom-rename_chip_accessors/sharplhf00l04.c (Arbeitskopie) @@ -41,23 +41,23 @@ #if 0 /* Enter ID mode */ - writeb(0xAA, bios + 0x5555); - writeb(0x55, bios + 0x2AAA); - writeb(0x90, bios + 0x5555); + chip_writeb(0xAA, bios + 0x5555); + chip_writeb(0x55, bios + 0x2AAA); + chip_writeb(0x90, bios + 0x5555); #endif - writeb(0xff, bios); + chip_writeb(0xff, bios); myusec_delay(10); - writeb(0x90, bios); + chip_writeb(0x90, bios); myusec_delay(10); - id1 = readb(bios); - id2 = readb(bios + 0x01); + id1 = chip_readb(bios); + id2 = chip_readb(bios + 0x01); /* Leave ID mode */ - writeb(0xAA, bios + 0x5555); - writeb(0x55, bios + 0x2AAA); - writeb(0xF0, bios + 0x5555); + chip_writeb(0xAA, bios + 0x5555); + chip_writeb(0x55, bios + 0x2AAA); + chip_writeb(0xF0, bios + 0x5555); myusec_delay(10); @@ -76,25 +76,25 @@ uint8_t status; uint8_t id1, id2; - writeb(0x70, bios); - if ((readb(bios) & 0x80) == 0) { // it's busy - while ((readb(bios) & 0x80) == 0) ; + chip_writeb(0x70, bios); + if ((chip_readb(bios) & 0x80) == 0) { // it's busy + while ((chip_readb(bios) & 0x80) == 0) ; } - status = readb(bios); + status = chip_readb(bios); // put another command to get out of status register mode - writeb(0x90, bios); + chip_writeb(0x90, bios); myusec_delay(10); - id1 = readb(bios); - id2 = readb(bios + 0x01); + id1 = chip_readb(bios); + id2 = chip_readb(bios + 0x01); // this is needed to jam it out of "read id" mode - writeb(0xAA, bios + 0x5555); - writeb(0x55, bios + 0x2AAA); - writeb(0xF0, bios + 0x5555); + chip_writeb(0xAA, bios + 0x5555); + chip_writeb(0x55, bios + 0x2AAA); + chip_writeb(0xF0, bios + 0x5555); return status; } @@ -106,19 +106,19 @@ uint8_t status; // clear status register - writeb(0x50, bios); + chip_writeb(0x50, bios); printf("Erase at %p\n", bios); status = wait_lhf00l04(flash->virtual_memory); print_lhf00l04_status(status); // clear write protect printf("write protect is at %p\n", (wrprotect)); - printf("write protect is 0x%x\n", readb(wrprotect)); - writeb(0, wrprotect); - printf("write protect is 0x%x\n", readb(wrprotect)); + printf("write protect is 0x%x\n", chip_readb(wrprotect)); + chip_writeb(0, wrprotect); + printf("write protect is 0x%x\n", chip_readb(wrprotect)); // now start it - writeb(0x20, bios); - writeb(0xd0, bios); + chip_writeb(0x20, bios); + chip_writeb(0xd0, bios); myusec_delay(10); // now let's see what the register is status = wait_lhf00l04(flash->virtual_memory); @@ -149,8 +149,8 @@ for (i = 0; i < page_size; i++) { /* transfer data from source to destination */ - writeb(0x40, dst); - writeb(*src++, dst++); + chip_writeb(0x40, dst); + chip_writeb(*src++, dst++); wait_lhf00l04(bios); } } @@ -163,7 +163,7 @@ volatile uint8_t *bios = flash->virtual_memory; erase_lhf00l04(flash); - if (readb(bios) != 0xff) { + if (chip_readb(bios) != 0xff) { printf("ERASE FAILED!\n"); return -1; } Index: flashrom-rename_chip_accessors/m29f002.c =================================================================== --- flashrom-rename_chip_accessors/m29f002.c (Revision 3973) +++ flashrom-rename_chip_accessors/m29f002.c (Arbeitskopie) @@ -22,12 +22,12 @@ int erase_m29f002(struct flashchip *flash) { volatile uint8_t *bios = flash->virtual_memory; - writeb(0xaa, bios + 0x555); - writeb(0x55, bios + 0xaaa); - writeb(0x80, bios + 0x555); - writeb(0xaa, bios + 0x555); - writeb(0x55, bios + 0xaaa); - writeb(0x10, bios + 0x555); + chip_writeb(0xaa, bios + 0x555); + chip_writeb(0x55, bios + 0xaaa); + chip_writeb(0x80, bios + 0x555); + chip_writeb(0xaa, bios + 0x555); + chip_writeb(0x55, bios + 0xaaa); + chip_writeb(0x10, bios + 0x555); myusec_delay(10); toggle_ready_jedec(bios); return 0; @@ -35,21 +35,21 @@ static void rewrite_block(volatile uint8_t *bios, uint8_t *src, volatile uint8_t *dst, int size) { /* erase */ - writeb(0xaa, bios + 0x555); - writeb(0x55, bios + 0xaaa); - writeb(0x80, bios + 0x555); - writeb(0xaa, bios + 0x555); - writeb(0x55, bios + 0xaaa); - writeb(0x30, dst); + chip_writeb(0xaa, bios + 0x555); + chip_writeb(0x55, bios + 0xaaa); + chip_writeb(0x80, bios + 0x555); + chip_writeb(0xaa, bios + 0x555); + chip_writeb(0x55, bios + 0xaaa); + chip_writeb(0x30, dst); myusec_delay(10); toggle_ready_jedec(bios); /* program */ while (size--) { - writeb(0xaa, bios + 0x555); - writeb(0x55, bios + 0xaaa); - writeb(0xa0, bios + 0x555); - writeb(*src, dst); + chip_writeb(0xaa, bios + 0x555); + chip_writeb(0x55, bios + 0xaaa); + chip_writeb(0xa0, bios + 0x555); + chip_writeb(*src, dst); toggle_ready_jedec(dst); dst++; src++; Index: flashrom-rename_chip_accessors/w39v040c.c =================================================================== --- flashrom-rename_chip_accessors/w39v040c.c (Revision 3973) +++ flashrom-rename_chip_accessors/w39v040c.c (Arbeitskopie) @@ -26,22 +26,22 @@ volatile uint8_t *bios = flash->virtual_memory; uint8_t id1, id2, lock; - writeb(0xAA, bios + 0x5555); + chip_writeb(0xAA, bios + 0x5555); myusec_delay(10); - writeb(0x55, bios + 0x2AAA); + chip_writeb(0x55, bios + 0x2AAA); myusec_delay(10); - writeb(0x90, bios + 0x5555); + chip_writeb(0x90, bios + 0x5555); myusec_delay(10); - id1 = readb(bios); - id2 = readb(bios + 1); - lock = readb(bios + 0xfff2); + id1 = chip_readb(bios); + id2 = chip_readb(bios + 1); + lock = chip_readb(bios + 0xfff2); - writeb(0xAA, bios + 0x5555); + chip_writeb(0xAA, bios + 0x5555); myusec_delay(10); - writeb(0x55, bios + 0x2AAA); + chip_writeb(0x55, bios + 0x2AAA); myusec_delay(10); - writeb(0xF0, bios + 0x5555); + chip_writeb(0xF0, bios + 0x5555); myusec_delay(40); printf_debug("%s: id1 0x%02x, id2 0x%02x", __func__, id1, id2); Index: flashrom-rename_chip_accessors/sst28sf040.c =================================================================== --- flashrom-rename_chip_accessors/sst28sf040.c (Revision 3973) +++ flashrom-rename_chip_accessors/sst28sf040.c (Arbeitskopie) @@ -34,33 +34,33 @@ { uint8_t tmp; - tmp = readb(bios + 0x1823); - tmp = readb(bios + 0x1820); - tmp = readb(bios + 0x1822); - tmp = readb(bios + 0x0418); - tmp = readb(bios + 0x041B); - tmp = readb(bios + 0x0419); - tmp = readb(bios + 0x040A); + tmp = chip_readb(bios + 0x1823); + tmp = chip_readb(bios + 0x1820); + tmp = chip_readb(bios + 0x1822); + tmp = chip_readb(bios + 0x0418); + tmp = chip_readb(bios + 0x041B); + tmp = chip_readb(bios + 0x0419); + tmp = chip_readb(bios + 0x040A); } static __inline__ void unprotect_28sf040(volatile uint8_t *bios) { uint8_t tmp; - tmp = readb(bios + 0x1823); - tmp = readb(bios + 0x1820); - tmp = readb(bios + 0x1822); - tmp = readb(bios + 0x0418); - tmp = readb(bios + 0x041B); - tmp = readb(bios + 0x0419); - tmp = readb(bios + 0x041A); + tmp = chip_readb(bios + 0x1823); + tmp = chip_readb(bios + 0x1820); + tmp = chip_readb(bios + 0x1822); + tmp = chip_readb(bios + 0x0418); + tmp = chip_readb(bios + 0x041B); + tmp = chip_readb(bios + 0x0419); + tmp = chip_readb(bios + 0x041A); } static __inline__ int erase_sector_28sf040(volatile uint8_t *bios, unsigned long address) { - writeb(AUTO_PG_ERASE1, bios); - writeb(AUTO_PG_ERASE2, bios + address); + chip_writeb(AUTO_PG_ERASE1, bios); + chip_writeb(AUTO_PG_ERASE2, bios + address); /* wait for Toggle bit ready */ toggle_ready_jedec(bios); @@ -83,8 +83,8 @@ continue; } /*issue AUTO PROGRAM command */ - writeb(AUTO_PGRM, dst); - writeb(*src++, dst++); + chip_writeb(AUTO_PGRM, dst); + chip_writeb(*src++, dst++); /* wait for Toggle bit ready */ toggle_ready_jedec(bios); @@ -98,16 +98,16 @@ volatile uint8_t *bios = flash->virtual_memory; uint8_t id1, id2; - writeb(RESET, bios); + chip_writeb(RESET, bios); myusec_delay(10); - writeb(READ_ID, bios); + chip_writeb(READ_ID, bios); myusec_delay(10); - id1 = readb(bios); + id1 = chip_readb(bios); myusec_delay(10); - id2 = readb(bios + 0x01); + id2 = chip_readb(bios + 0x01); - writeb(RESET, bios); + chip_writeb(RESET, bios); myusec_delay(10); printf_debug("%s: id1 0x%02x, id2 0x%02x\n", __FUNCTION__, id1, id2); @@ -122,8 +122,8 @@ volatile uint8_t *bios = flash->virtual_memory; unprotect_28sf040(bios); - writeb(CHIP_ERASE, bios); - writeb(CHIP_ERASE, bios); + chip_writeb(CHIP_ERASE, bios); + chip_writeb(CHIP_ERASE, bios); protect_28sf040(bios); myusec_delay(10); Index: flashrom-rename_chip_accessors/stm50flw0x0x.c =================================================================== --- flashrom-rename_chip_accessors/stm50flw0x0x.c (Revision 3973) +++ flashrom-rename_chip_accessors/stm50flw0x0x.c (Arbeitskopie) @@ -33,9 +33,9 @@ void protect_stm50flw0x0x(volatile uint8_t *bios) { - writeb(0xAA, bios + 0x5555); - writeb(0x55, bios + 0x2AAA); - writeb(0xA0, bios + 0x5555); + chip_writeb(0xAA, bios + 0x5555); + chip_writeb(0x55, bios + 0x2AAA); + chip_writeb(0xA0, bios + 0x5555); usleep(200); } @@ -47,37 +47,37 @@ uint32_t largeid1, largeid2; /* Issue JEDEC Product ID Entry command */ - writeb(0xAA, bios + 0x5555); + chip_writeb(0xAA, bios + 0x5555); myusec_delay(10); - writeb(0x55, bios + 0x2AAA); + chip_writeb(0x55, bios + 0x2AAA); myusec_delay(10); - writeb(0x90, bios + 0x5555); + chip_writeb(0x90, bios + 0x5555); myusec_delay(40); /* Read product ID */ - id1 = readb(bios); - id2 = readb(bios + 0x01); + id1 = chip_readb(bios); + id2 = chip_readb(bios + 0x01); largeid1 = id1; largeid2 = id2; /* Check if it is a continuation ID, this should be a while loop. */ if (id1 == 0x7F) { largeid1 <<= 8; - id1 = readb(bios + 0x100); + id1 = chip_readb(bios + 0x100); largeid1 |= id1; } if (id2 == 0x7F) { largeid2 <<= 8; - id2 = readb(bios + 0x101); + id2 = chip_readb(bios + 0x101); largeid2 |= id2; } /* Issue JEDEC Product ID Exit command */ - writeb(0xAA, bios + 0x5555); + chip_writeb(0xAA, bios + 0x5555); myusec_delay(10); - writeb(0x55, bios + 0x2AAA); + chip_writeb(0x55, bios + 0x2AAA); myusec_delay(10); - writeb(0xF0, bios + 0x5555); + chip_writeb(0xF0, bios + 0x5555); myusec_delay(40); printf_debug("%s: id1 0x%02x, id2 0x%02x\n", __FUNCTION__, largeid1, @@ -96,21 +96,21 @@ uint8_t id1; // id2; - writeb(0x70, bios); - if ((readb(bios) & 0x80) == 0) { // it's busy - while ((readb(bios) & 0x80) == 0) ; + chip_writeb(0x70, bios); + if ((chip_readb(bios) & 0x80) == 0) { // it's busy + while ((chip_readb(bios) & 0x80) == 0) ; } // put another command to get out of status register mode - writeb(0x90, bios); + chip_writeb(0x90, bios); myusec_delay(10); - id1 = readb(bios); + id1 = chip_readb(bios); // this is needed to jam it out of "read id" mode - writeb(0xAA, bios + 0x5555); - writeb(0x55, bios + 0x2AAA); - writeb(0xF0, bios + 0x5555); + chip_writeb(0xAA, bios + 0x5555); + chip_writeb(0x55, bios + 0x2AAA); + chip_writeb(0xF0, bios + 0x5555); } /* @@ -142,8 +142,8 @@ // unlock each 4k-sector for (j = 0; j < 0x10000; j += 0x1000) { printf_debug("unlocking at 0x%x\n", offset + j); - writeb(unlock_sector, flash_addr + offset + j); - if (readb(flash_addr + offset + j) != unlock_sector) { + chip_writeb(unlock_sector, flash_addr + offset + j); + if (chip_readb(flash_addr + offset + j) != unlock_sector) { printf("Cannot unlock sector @ 0x%x\n", offset + j); return -1; @@ -151,8 +151,8 @@ } } else { printf_debug("unlocking at 0x%x\n", offset); - writeb(unlock_sector, flash_addr + offset); - if (readb(flash_addr + offset) != unlock_sector) { + chip_writeb(unlock_sector, flash_addr + offset); + if (chip_readb(flash_addr + offset) != unlock_sector) { printf("Cannot unlock sector @ 0x%x\n", offset); return -1; } @@ -167,17 +167,17 @@ int j; // clear status register - writeb(0x50, bios); + chip_writeb(0x50, bios); printf_debug("Erase at %p\n", bios); // now start it - writeb(0x20, bios); - writeb(0xd0, bios); + chip_writeb(0x20, bios); + chip_writeb(0xd0, bios); myusec_delay(10); wait_stm50flw0x0x(flash->virtual_memory); for (j = 0; j < flash->page_size; j++) { - if (readb(bios + j) != 0xFF) { + if (chip_readb(bios + j) != 0xFF) { printf("Erase failed at 0x%x\n", offset + j); return -1; } @@ -197,8 +197,8 @@ /* transfer data from source to destination */ for (i = 0; i < page_size; i++) { - writeb(0x40, dst); - writeb(*src++, dst++); + chip_writeb(0x40, dst); + chip_writeb(*src++, dst++); wait_stm50flw0x0x(bios); } @@ -210,7 +210,7 @@ dst = d; src = s; for (i = 0; i < page_size; i++) { - if (readb(dst) != *src) { + if (chip_readb(dst) != *src) { rc = -1; break; } Index: flashrom-rename_chip_accessors/am29f040b.c =================================================================== --- flashrom-rename_chip_accessors/am29f040b.c (Revision 3973) +++ flashrom-rename_chip_accessors/am29f040b.c (Arbeitskopie) @@ -25,12 +25,12 @@ static __inline__ int erase_sector_29f040b(volatile uint8_t *bios, unsigned long address) { - writeb(0xAA, bios + 0x555); - writeb(0x55, bios + 0x2AA); - writeb(0x80, bios + 0x555); - writeb(0xAA, bios + 0x555); - writeb(0x55, bios + 0x2AA); - writeb(0x30, bios + address); + chip_writeb(0xAA, bios + 0x555); + chip_writeb(0x55, bios + 0x2AA); + chip_writeb(0x80, bios + 0x555); + chip_writeb(0xAA, bios + 0x555); + chip_writeb(0x55, bios + 0x2AA); + chip_writeb(0x30, bios + address); sleep(2); @@ -52,10 +52,10 @@ printf("0x%08lx", (unsigned long)dst - (unsigned long)bios); - writeb(0xAA, bios + 0x555); - writeb(0x55, bios + 0x2AA); - writeb(0xA0, bios + 0x555); - writeb(*src++, dst++); + chip_writeb(0xAA, bios + 0x555); + chip_writeb(0x55, bios + 0x2AA); + chip_writeb(0xA0, bios + 0x555); + chip_writeb(*src++, dst++); /* wait for Toggle bit ready */ toggle_ready_jedec(bios); @@ -72,14 +72,14 @@ volatile uint8_t *bios = flash->virtual_memory; uint8_t id1, id2; - writeb(0xAA, bios + 0x555); - writeb(0x55, bios + 0x2AA); - writeb(0x90, bios + 0x555); + chip_writeb(0xAA, bios + 0x555); + chip_writeb(0x55, bios + 0x2AA); + chip_writeb(0x90, bios + 0x555); - id1 = readb(bios); - id2 = readb(bios + 0x01); + id1 = chip_readb(bios); + id2 = chip_readb(bios + 0x01); - writeb(0xF0, bios); + chip_writeb(0xF0, bios); myusec_delay(10); @@ -94,12 +94,12 @@ { volatile uint8_t *bios = flash->virtual_memory; - writeb(0xAA, bios + 0x555); - writeb(0x55, bios + 0x2AA); - writeb(0x80, bios + 0x555); - writeb(0xAA, bios + 0x555); - writeb(0x55, bios + 0x2AA); - writeb(0x10, bios + 0x555); + chip_writeb(0xAA, bios + 0x555); + chip_writeb(0x55, bios + 0x2AA); + chip_writeb(0x80, bios + 0x555); + chip_writeb(0xAA, bios + 0x555); + chip_writeb(0x55, bios + 0x2AA); + chip_writeb(0x10, bios + 0x555); myusec_delay(10); toggle_ready_jedec(bios); Index: flashrom-rename_chip_accessors/sst_fwhub.c =================================================================== --- flashrom-rename_chip_accessors/sst_fwhub.c (Revision 3973) +++ flashrom-rename_chip_accessors/sst_fwhub.c (Arbeitskopie) @@ -51,7 +51,7 @@ volatile uint8_t *wrprotect = flash->virtual_registers + offset + 2; // clear write protect - writeb(0, wrprotect); + chip_writeb(0, wrprotect); erase_block_jedec(flash->virtual_memory, offset); toggle_ready_jedec(flash->virtual_memory); Index: flashrom-rename_chip_accessors/w39v080fa.c =================================================================== --- flashrom-rename_chip_accessors/w39v080fa.c (Revision 3973) +++ flashrom-rename_chip_accessors/w39v080fa.c (Arbeitskopie) @@ -27,19 +27,19 @@ uint8_t vid, did; /* Product Identification Entry */ - writeb(0xAA, bios + 0x5555); - writeb(0x55, bios + 0x2AAA); - writeb(0x90, bios + 0x5555); + chip_writeb(0xAA, bios + 0x5555); + chip_writeb(0x55, bios + 0x2AAA); + chip_writeb(0x90, bios + 0x5555); myusec_delay(10); /* Read product ID */ - vid = readb(bios); - did = readb(bios + 0x01); + vid = chip_readb(bios); + did = chip_readb(bios + 0x01); /* Product Identifixation Exit */ - writeb(0xAA, bios + 0x5555); - writeb(0x55, bios + 0x2AAA); - writeb(0xF0, bios + 0x5555); + chip_writeb(0xAA, bios + 0x5555); + chip_writeb(0x55, bios + 0x2AAA); + chip_writeb(0xF0, bios + 0x5555); myusec_delay(10); printf_debug("%s: vid 0x%x, did 0x%x\n", __FUNCTION__, vid, did); @@ -58,16 +58,16 @@ uint8_t locking; printf_debug("Trying to unlock block @0x%08x = 0x%02x\n", offset, - readb(wrprotect)); + chip_readb(wrprotect)); - locking = readb(wrprotect); + locking = chip_readb(wrprotect); switch (locking & 0x7) { case 0: printf_debug("Full Access.\n"); return 0; case 1: printf_debug("Write Lock (Default State).\n"); - writeb(0, wrprotect); + chip_writeb(0, wrprotect); return 0; case 2: printf_debug("Locked Open (Full Access, Lock Down).\n"); @@ -77,11 +77,11 @@ return -1; case 4: printf_debug("Read Lock.\n"); - writeb(0, wrprotect); + chip_writeb(0, wrprotect); return 0; case 5: printf_debug("Read/Write Lock.\n"); - writeb(0, wrprotect); + chip_writeb(0, wrprotect); return 0; case 6: fprintf(stderr, "Error: Read Lock, Locked Down.\n"); @@ -106,18 +106,18 @@ */ /* Product Identification Entry */ - writeb(0xAA, bios + 0x5555); - writeb(0x55, bios + 0x2AAA); - writeb(0x90, bios + 0x5555); + chip_writeb(0xAA, bios + 0x5555); + chip_writeb(0x55, bios + 0x2AAA); + chip_writeb(0x90, bios + 0x5555); myusec_delay(10); /* Read Hardware Lock Bits */ - locking = readb(bios + 0xffff2); + locking = chip_readb(bios + 0xffff2); /* Product Identification Exit */ - writeb(0xAA, bios + 0x5555); - writeb(0x55, bios + 0x2AAA); - writeb(0xF0, bios + 0x5555); + chip_writeb(0xAA, bios + 0x5555); + chip_writeb(0x55, bios + 0x2AAA); + chip_writeb(0xF0, bios + 0x5555); myusec_delay(10); printf_debug("Lockout bits:\n"); @@ -151,13 +151,13 @@ printf("0x%08x\b\b\b\b\b\b\b\b\b\b", sector); /* Sector Erase */ - writeb(0xAA, bios + 0x5555); - writeb(0x55, bios + 0x2AAA); - writeb(0x80, bios + 0x5555); + chip_writeb(0xAA, bios + 0x5555); + chip_writeb(0x55, bios + 0x2AAA); + chip_writeb(0x80, bios + 0x5555); - writeb(0xAA, bios + 0x5555); - writeb(0x55, bios + 0x2AAA); - writeb(0x30, bios + sector); + chip_writeb(0xAA, bios + 0x5555); + chip_writeb(0x55, bios + 0x2AAA); + chip_writeb(0x30, bios + sector); /* wait for Toggle bit ready */ toggle_ready_jedec(bios); Index: flashrom-rename_chip_accessors/82802ab.c =================================================================== --- flashrom-rename_chip_accessors/82802ab.c (Revision 3973) +++ flashrom-rename_chip_accessors/82802ab.c (Arbeitskopie) @@ -49,23 +49,23 @@ uint8_t id1, id2; #if 0 - writeb(0xAA, bios + 0x5555); - writeb(0x55, bios + 0x2AAA); - writeb(0x90, bios + 0x5555); + chip_writeb(0xAA, bios + 0x5555); + chip_writeb(0x55, bios + 0x2AAA); + chip_writeb(0x90, bios + 0x5555); #endif - writeb(0xff, bios); + chip_writeb(0xff, bios); myusec_delay(10); - writeb(0x90, bios); + chip_writeb(0x90, bios); myusec_delay(10); - id1 = readb(bios); - id2 = readb(bios + 0x01); + id1 = chip_readb(bios); + id2 = chip_readb(bios + 0x01); /* Leave ID mode */ - writeb(0xAA, bios + 0x5555); - writeb(0x55, bios + 0x2AAA); - writeb(0xF0, bios + 0x5555); + chip_writeb(0xAA, bios + 0x5555); + chip_writeb(0x55, bios + 0x2AAA); + chip_writeb(0xF0, bios + 0x5555); myusec_delay(10); @@ -84,25 +84,25 @@ uint8_t status; uint8_t id1, id2; - writeb(0x70, bios); - if ((readb(bios) & 0x80) == 0) { // it's busy - while ((readb(bios) & 0x80) == 0) ; + chip_writeb(0x70, bios); + if ((chip_readb(bios) & 0x80) == 0) { // it's busy + while ((chip_readb(bios) & 0x80) == 0) ; } - status = readb(bios); + status = chip_readb(bios); // put another command to get out of status register mode - writeb(0x90, bios); + chip_writeb(0x90, bios); myusec_delay(10); - id1 = readb(bios); - id2 = readb(bios + 0x01); + id1 = chip_readb(bios); + id2 = chip_readb(bios + 0x01); // this is needed to jam it out of "read id" mode - writeb(0xAA, bios + 0x5555); - writeb(0x55, bios + 0x2AAA); - writeb(0xF0, bios + 0x5555); + chip_writeb(0xAA, bios + 0x5555); + chip_writeb(0x55, bios + 0x2AAA); + chip_writeb(0xF0, bios + 0x5555); return status; } @@ -115,23 +115,23 @@ uint8_t status; // clear status register - writeb(0x50, bios); + chip_writeb(0x50, bios); //printf("Erase at %p\n", bios); // clear write protect //printf("write protect is at %p\n", (wrprotect)); //printf("write protect is 0x%x\n", *(wrprotect)); - writeb(0, wrprotect); + chip_writeb(0, wrprotect); //printf("write protect is 0x%x\n", *(wrprotect)); // now start it - writeb(0x20, bios); - writeb(0xd0, bios); + chip_writeb(0x20, bios); + chip_writeb(0xd0, bios); myusec_delay(10); // now let's see what the register is status = wait_82802ab(flash->virtual_memory); //print_82802ab_status(status); for (j = 0; j < flash->page_size; j++) { - if (readb(bios + j) != 0xFF) { + if (chip_readb(bios + j) != 0xFF) { printf("BLOCK ERASE failed at 0x%x\n", offset); return -1; } @@ -162,8 +162,8 @@ for (i = 0; i < page_size; i++) { /* transfer data from source to destination */ - writeb(0x40, dst); - writeb(*src++, dst++); + chip_writeb(0x40, dst); + chip_writeb(*src++, dst++); wait_82802ab(bios); } } Index: flashrom-rename_chip_accessors/m29f400bt.c =================================================================== --- flashrom-rename_chip_accessors/m29f400bt.c (Revision 3973) +++ flashrom-rename_chip_accessors/m29f400bt.c (Arbeitskopie) @@ -22,9 +22,9 @@ void protect_m29f400bt(volatile uint8_t *bios) { - writeb(0xAA, bios + 0xAAA); - writeb(0x55, bios + 0x555); - writeb(0xA0, bios + 0xAAA); + chip_writeb(0xAA, bios + 0xAAA); + chip_writeb(0x55, bios + 0x555); + chip_writeb(0xA0, bios + 0xAAA); usleep(200); } @@ -35,18 +35,18 @@ int i; for (i = 0; i < page_size; i++) { - writeb(0xAA, bios + 0xAAA); - writeb(0x55, bios + 0x555); - writeb(0xA0, bios + 0xAAA); + chip_writeb(0xAA, bios + 0xAAA); + chip_writeb(0x55, bios + 0x555); + chip_writeb(0xA0, bios + 0xAAA); /* transfer data from source to destination */ - writeb(*src, dst); + chip_writeb(*src, dst); //*(volatile char *) (bios) = 0xF0; //usleep(5); toggle_ready_jedec(dst); printf ("Value in the flash at address %p = %#x, want %#x\n", - (uint8_t *) (dst - bios), readb(dst), *src); + (uint8_t *) (dst - bios), chip_readb(dst), *src); dst++; src++; } @@ -57,21 +57,21 @@ volatile uint8_t *bios = flash->virtual_memory; uint8_t id1, id2; - writeb(0xAA, bios + 0xAAA); - writeb(0x55, bios + 0x555); - writeb(0x90, bios + 0xAAA); + chip_writeb(0xAA, bios + 0xAAA); + chip_writeb(0x55, bios + 0x555); + chip_writeb(0x90, bios + 0xAAA); myusec_delay(10); - id1 = readb(bios); + id1 = chip_readb(bios); /* The data sheet says id2 is at (bios + 0x01) and id2 listed in * flash.h does not match. It should be possible to use JEDEC probe. */ - id2 = readb(bios + 0x02); + id2 = chip_readb(bios + 0x02); - writeb(0xAA, bios + 0xAAA); - writeb(0x55, bios + 0x555); - writeb(0xF0, bios + 0xAAA); + chip_writeb(0xAA, bios + 0xAAA); + chip_writeb(0x55, bios + 0x555); + chip_writeb(0xF0, bios + 0xAAA); myusec_delay(10); @@ -87,13 +87,13 @@ { volatile uint8_t *bios = flash->virtual_memory; - writeb(0xAA, bios + 0xAAA); - writeb(0x55, bios + 0x555); - writeb(0x80, bios + 0xAAA); + chip_writeb(0xAA, bios + 0xAAA); + chip_writeb(0x55, bios + 0x555); + chip_writeb(0x80, bios + 0xAAA); - writeb(0xAA, bios + 0xAAA); - writeb(0x55, bios + 0x555); - writeb(0x10, bios + 0xAAA); + chip_writeb(0xAA, bios + 0xAAA); + chip_writeb(0x55, bios + 0x555); + chip_writeb(0x10, bios + 0xAAA); myusec_delay(10); toggle_ready_jedec(bios); @@ -104,14 +104,14 @@ int block_erase_m29f400bt(volatile uint8_t *bios, volatile uint8_t *dst) { - writeb(0xAA, bios + 0xAAA); - writeb(0x55, bios + 0x555); - writeb(0x80, bios + 0xAAA); + chip_writeb(0xAA, bios + 0xAAA); + chip_writeb(0x55, bios + 0x555); + chip_writeb(0x80, bios + 0xAAA); - writeb(0xAA, bios + 0xAAA); - writeb(0x55, bios + 0x555); + chip_writeb(0xAA, bios + 0xAAA); + chip_writeb(0x55, bios + 0x555); //*(volatile uint8_t *) (bios + 0xAAA) = 0x10; - writeb(0x30, dst); + chip_writeb(0x30, dst); myusec_delay(10); toggle_ready_jedec(bios); Index: flashrom-rename_chip_accessors/mx29f002.c =================================================================== --- flashrom-rename_chip_accessors/mx29f002.c (Revision 3973) +++ flashrom-rename_chip_accessors/mx29f002.c (Arbeitskopie) @@ -27,14 +27,14 @@ volatile uint8_t *bios = flash->virtual_memory; uint8_t id1, id2; - writeb(0xAA, bios + 0x5555); - writeb(0x55, bios + 0x2AAA); - writeb(0x90, bios + 0x5555); + chip_writeb(0xAA, bios + 0x5555); + chip_writeb(0x55, bios + 0x2AAA); + chip_writeb(0x90, bios + 0x5555); - id1 = readb(bios); - id2 = readb(bios + 0x01); + id1 = chip_readb(bios); + id2 = chip_readb(bios + 0x01); - writeb(0xF0, bios); + chip_writeb(0xF0, bios); myusec_delay(10); @@ -49,13 +49,13 @@ { volatile uint8_t *bios = flash->virtual_memory; - writeb(0xF0, bios + 0x555); - writeb(0xAA, bios + 0x555); - writeb(0x55, bios + 0x2AA); - writeb(0x80, bios + 0x555); - writeb(0xAA, bios + 0x555); - writeb(0x55, bios + 0x2AA); - writeb(0x10, bios + 0x555); + chip_writeb(0xF0, bios + 0x555); + chip_writeb(0xAA, bios + 0x555); + chip_writeb(0x55, bios + 0x2AA); + chip_writeb(0x80, bios + 0x555); + chip_writeb(0xAA, bios + 0x555); + chip_writeb(0x55, bios + 0x2AA); + chip_writeb(0x10, bios + 0x555); myusec_delay(100); toggle_ready_jedec(bios); @@ -65,12 +65,12 @@ #if 0 toggle_ready_jedec(bios); - writeb(0x30, bios + 0x0ffff); - writeb(0x30, bios + 0x1ffff); - writeb(0x30, bios + 0x2ffff); - writeb(0x30, bios + 0x37fff); - writeb(0x30, bios + 0x39fff); - writeb(0x30, bios + 0x3bfff); + chip_writeb(0x30, bios + 0x0ffff); + chip_writeb(0x30, bios + 0x1ffff); + chip_writeb(0x30, bios + 0x2ffff); + chip_writeb(0x30, bios + 0x37fff); + chip_writeb(0x30, bios + 0x39fff); + chip_writeb(0x30, bios + 0x3bfff); #endif return 0; @@ -83,7 +83,7 @@ volatile uint8_t *bios = flash->virtual_memory; volatile uint8_t *dst = bios; - writeb(0xF0, bios); + chip_writeb(0xF0, bios); myusec_delay(10); erase_29f002(flash); //*bios = 0xF0; @@ -93,10 +93,10 @@ /* write to the sector */ if ((i & 0xfff) == 0) printf("address: 0x%08lx", (unsigned long)i); - writeb(0xAA, bios + 0x5555); - writeb(0x55, bios + 0x2AAA); - writeb(0xA0, bios + 0x5555); - writeb(*buf++, dst++); + chip_writeb(0xAA, bios + 0x5555); + chip_writeb(0x55, bios + 0x2AAA); + chip_writeb(0xA0, bios + 0x5555); + chip_writeb(*buf++, dst++); /* wait for Toggle bit ready */ toggle_ready_jedec(dst); -- http://www.hailfinger.org/ Index: flashrom-rename_chip_accessors/flash.h =================================================================== --- flashrom-rename_chip_accessors/flash.h (Revision 3973) +++ flashrom-rename_chip_accessors/flash.h (Arbeitskopie) @@ -58,32 +58,32 @@ #define INL inl #endif -static inline void writeb(uint8_t b, volatile void *addr) +static inline void chip_writeb(uint8_t b, volatile void *addr) { *(volatile uint8_t *) addr = b; } -static inline void writew(uint16_t b, volatile void *addr) +static inline void chip_writew(uint16_t b, volatile void *addr) { *(volatile uint16_t *) addr = b; } -static inline void writel(uint32_t b, volatile void *addr) +static inline void chip_writel(uint32_t b, volatile void *addr) { *(volatile uint32_t *) addr = b; } -static inline uint8_t readb(const volatile void *addr) +static inline uint8_t chip_readb(const volatile void *addr) { return *(volatile uint8_t *) addr; } -static inline uint16_t readw(const volatile void *addr) +static inline uint16_t chip_readw(const volatile void *addr) { return *(volatile uint16_t *) addr; } -static inline uint32_t readl(const volatile void *addr) +static inline uint32_t chip_readl(const volatile void *addr) { return *(volatile uint32_t *) addr; } Index: flashrom-rename_chip_accessors/pm49fl00x.c =================================================================== --- flashrom-rename_chip_accessors/pm49fl00x.c (Revision 3973) +++ flashrom-rename_chip_accessors/pm49fl00x.c (Arbeitskopie) @@ -35,7 +35,7 @@ if (block_size == 16384 && i % 2) continue; - writeb(bits, bios + (i * block_size) + 2); + chip_writeb(bits, bios + (i * block_size) + 2); } } Index: flashrom-rename_chip_accessors/en29f002a.c =================================================================== --- flashrom-rename_chip_accessors/en29f002a.c (Revision 3973) +++ flashrom-rename_chip_accessors/en29f002a.c (Arbeitskopie) @@ -35,19 +35,19 @@ volatile uint8_t *bios = flash->virtual_memory; uint8_t id1, id2; - writeb(0xAA, bios + 0x555); - writeb(0x55, bios + 0x2AA); - writeb(0x90, bios + 0x555); + chip_writeb(0xAA, bios + 0x555); + chip_writeb(0x55, bios + 0x2AA); + chip_writeb(0x90, bios + 0x555); myusec_delay(10); - id1 = readb(bios + 0x100); - id2 = readb(bios + 0x101); + id1 = chip_readb(bios + 0x100); + id2 = chip_readb(bios + 0x101); /* exit by writing F0 anywhere? or the code below */ - writeb(0xAA, bios + 0x555); - writeb(0x55, bios + 0x2AA); - writeb(0xF0, bios + 0x555); + chip_writeb(0xAA, bios + 0x555); + chip_writeb(0x55, bios + 0x2AA); + chip_writeb(0xF0, bios + 0x555); printf_debug("%s: id1 0x%02x, id2 0x%02x\n", __FUNCTION__, id1, id2); @@ -68,19 +68,19 @@ volatile uint8_t *bios = flash->virtual_memory; uint8_t id1, id2; - writeb(0xAA, bios + 0x555); - writeb(0x55, bios + 0xAAA); - writeb(0x90, bios + 0x555); + chip_writeb(0xAA, bios + 0x555); + chip_writeb(0x55, bios + 0xAAA); + chip_writeb(0x90, bios + 0x555); myusec_delay(10); - id1 = readb(bios + 0x100); - id2 = readb(bios + 0x101); + id1 = chip_readb(bios + 0x100); + id2 = chip_readb(bios + 0x101); /* exit by writing F0 anywhere? or the code below */ - writeb(0xAA, bios + 0x555); - writeb(0x55, bios + 0xAAA); - writeb(0xF0, bios + 0x555); + chip_writeb(0xAA, bios + 0x555); + chip_writeb(0x55, bios + 0xAAA); + chip_writeb(0xF0, bios + 0x555); printf_debug("%s: id1 0x%x, id2 0x%x\n", __FUNCTION__, id1, id2); @@ -107,10 +107,10 @@ /* write to the sector */ if ((i & 0xfff) == 0) printf("address: 0x%08lx", (unsigned long)i); - writeb(0xAA, bios + 0x5555); - writeb(0x55, bios + 0x2AAA); - writeb(0xA0, bios + 0x5555); - writeb(*buf++, dst++); + chip_writeb(0xAA, bios + 0x5555); + chip_writeb(0x55, bios + 0x2AAA); + chip_writeb(0xA0, bios + 0x5555); + chip_writeb(*buf++, dst++); /* wait for Toggle bit ready */ toggle_ready_jedec(dst); Index: flashrom-rename_chip_accessors/jedec.c =================================================================== --- flashrom-rename_chip_accessors/jedec.c (Revision 3973) +++ flashrom-rename_chip_accessors/jedec.c (Arbeitskopie) @@ -40,10 +40,10 @@ unsigned int i = 0; uint8_t tmp1, tmp2; - tmp1 = readb(dst) & 0x40; + tmp1 = chip_readb(dst) & 0x40; while (i++ < 0xFFFFFFF) { - tmp2 = readb(dst) & 0x40; + tmp2 = chip_readb(dst) & 0x40; if (tmp1 == tmp2) { break; } @@ -59,7 +59,7 @@ data &= 0x80; while (i++ < 0xFFFFFFF) { - tmp = readb(dst) & 0x80; + tmp = chip_readb(dst) & 0x80; if (tmp == data) { break; } @@ -68,21 +68,21 @@ void unprotect_jedec(volatile uint8_t *bios) { - writeb(0xAA, bios + 0x5555); - writeb(0x55, bios + 0x2AAA); - writeb(0x80, bios + 0x5555); - writeb(0xAA, bios + 0x5555); - writeb(0x55, bios + 0x2AAA); - writeb(0x20, bios + 0x5555); + chip_writeb(0xAA, bios + 0x5555); + chip_writeb(0x55, bios + 0x2AAA); + chip_writeb(0x80, bios + 0x5555); + chip_writeb(0xAA, bios + 0x5555); + chip_writeb(0x55, bios + 0x2AAA); + chip_writeb(0x20, bios + 0x5555); usleep(200); } void protect_jedec(volatile uint8_t *bios) { - writeb(0xAA, bios + 0x5555); - writeb(0x55, bios + 0x2AAA); - writeb(0xA0, bios + 0x5555); + chip_writeb(0xAA, bios + 0x5555); + chip_writeb(0x55, bios + 0x2AAA); + chip_writeb(0xA0, bios + 0x5555); usleep(200); } @@ -94,40 +94,40 @@ uint32_t largeid1, largeid2; /* Issue JEDEC Product ID Entry command */ - writeb(0xAA, bios + 0x5555); + chip_writeb(0xAA, bios + 0x5555); myusec_delay(10); - writeb(0x55, bios + 0x2AAA); + chip_writeb(0x55, bios + 0x2AAA); myusec_delay(10); - writeb(0x90, bios + 0x5555); + chip_writeb(0x90, bios + 0x5555); /* Older chips may need up to 100 us to respond. The ATMEL 29C020 * needs 10 ms according to the data sheet. */ myusec_delay(10000); /* Read product ID */ - id1 = readb(bios); - id2 = readb(bios + 0x01); + id1 = chip_readb(bios); + id2 = chip_readb(bios + 0x01); largeid1 = id1; largeid2 = id2; /* Check if it is a continuation ID, this should be a while loop. */ if (id1 == 0x7F) { largeid1 <<= 8; - id1 = readb(bios + 0x100); + id1 = chip_readb(bios + 0x100); largeid1 |= id1; } if (id2 == 0x7F) { largeid2 <<= 8; - id2 = readb(bios + 0x101); + id2 = chip_readb(bios + 0x101); largeid2 |= id2; } /* Issue JEDEC Product ID Exit command */ - writeb(0xAA, bios + 0x5555); + chip_writeb(0xAA, bios + 0x5555); myusec_delay(10); - writeb(0x55, bios + 0x2AAA); + chip_writeb(0x55, bios + 0x2AAA); myusec_delay(10); - writeb(0xF0, bios + 0x5555); + chip_writeb(0xF0, bios + 0x5555); myusec_delay(40); printf_debug("%s: id1 0x%02x, id2 0x%02x", __FUNCTION__, largeid1, largeid2); @@ -143,18 +143,18 @@ int erase_sector_jedec(volatile uint8_t *bios, unsigned int page) { /* Issue the Sector Erase command */ - writeb(0xAA, bios + 0x5555); + chip_writeb(0xAA, bios + 0x5555); myusec_delay(10); - writeb(0x55, bios + 0x2AAA); + chip_writeb(0x55, bios + 0x2AAA); myusec_delay(10); - writeb(0x80, bios + 0x5555); + chip_writeb(0x80, bios + 0x5555); myusec_delay(10); - writeb(0xAA, bios + 0x5555); + chip_writeb(0xAA, bios + 0x5555); myusec_delay(10); - writeb(0x55, bios + 0x2AAA); + chip_writeb(0x55, bios + 0x2AAA); myusec_delay(10); - writeb(0x30, bios + page); + chip_writeb(0x30, bios + page); myusec_delay(10); /* wait for Toggle bit ready */ @@ -166,18 +166,18 @@ int erase_block_jedec(volatile uint8_t *bios, unsigned int block) { /* Issue the Sector Erase command */ - writeb(0xAA, bios + 0x5555); + chip_writeb(0xAA, bios + 0x5555); myusec_delay(10); - writeb(0x55, bios + 0x2AAA); + chip_writeb(0x55, bios + 0x2AAA); myusec_delay(10); - writeb(0x80, bios + 0x5555); + chip_writeb(0x80, bios + 0x5555); myusec_delay(10); - writeb(0xAA, bios + 0x5555); + chip_writeb(0xAA, bios + 0x5555); myusec_delay(10); - writeb(0x55, bios + 0x2AAA); + chip_writeb(0x55, bios + 0x2AAA); myusec_delay(10); - writeb(0x50, bios + block); + chip_writeb(0x50, bios + block); myusec_delay(10); /* wait for Toggle bit ready */ @@ -191,18 +191,18 @@ volatile uint8_t *bios = flash->virtual_memory; /* Issue the JEDEC Chip Erase command */ - writeb(0xAA, bios + 0x5555); + chip_writeb(0xAA, bios + 0x5555); myusec_delay(10); - writeb(0x55, bios + 0x2AAA); + chip_writeb(0x55, bios + 0x2AAA); myusec_delay(10); - writeb(0x80, bios + 0x5555); + chip_writeb(0x80, bios + 0x5555); myusec_delay(10); - writeb(0xAA, bios + 0x5555); + chip_writeb(0xAA, bios + 0x5555); myusec_delay(10); - writeb(0x55, bios + 0x2AAA); + chip_writeb(0x55, bios + 0x2AAA); myusec_delay(10); - writeb(0x10, bios + 0x5555); + chip_writeb(0x10, bios + 0x5555); myusec_delay(10); toggle_ready_jedec(bios); @@ -219,15 +219,15 @@ retry: /* Issue JEDEC Data Unprotect comand */ - writeb(0xAA, bios + 0x5555); - writeb(0x55, bios + 0x2AAA); - writeb(0xA0, bios + 0x5555); + chip_writeb(0xAA, bios + 0x5555); + chip_writeb(0x55, bios + 0x2AAA); + chip_writeb(0xA0, bios + 0x5555); /* transfer data from source to destination */ for (i = start_index; i < page_size; i++) { /* If the data is 0xFF, don't program it */ if (*src != 0xFF) - writeb(*src, dst); + chip_writeb(*src, dst); dst++; src++; } @@ -238,7 +238,7 @@ src = s; ok = 1; for (i = 0; i < page_size; i++) { - if (readb(dst) != *src) { + if (chip_readb(dst) != *src) { ok = 0; break; } @@ -269,15 +269,15 @@ retry: /* Issue JEDEC Byte Program command */ - writeb(0xAA, bios + 0x5555); - writeb(0x55, bios + 0x2AAA); - writeb(0xA0, bios + 0x5555); + chip_writeb(0xAA, bios + 0x5555); + chip_writeb(0x55, bios + 0x2AAA); + chip_writeb(0xA0, bios + 0x5555); /* transfer data from source to destination */ - writeb(*src, dst); + chip_writeb(*src, dst); toggle_ready_jedec(bios); - if (readb(dst) != *src && tried++ < MAX_REFLASH_TRIES) { + if (chip_readb(dst) != *src && tried++ < MAX_REFLASH_TRIES) { goto retry; } Index: flashrom-rename_chip_accessors/w29ee011.c =================================================================== --- flashrom-rename_chip_accessors/w29ee011.c (Revision 3973) +++ flashrom-rename_chip_accessors/w29ee011.c (Arbeitskopie) @@ -37,29 +37,29 @@ } /* Issue JEDEC Product ID Entry command */ - writeb(0xAA, bios + 0x5555); + chip_writeb(0xAA, bios + 0x5555); myusec_delay(10); - writeb(0x55, bios + 0x2AAA); + chip_writeb(0x55, bios + 0x2AAA); myusec_delay(10); - writeb(0x80, bios + 0x5555); + chip_writeb(0x80, bios + 0x5555); myusec_delay(10); - writeb(0xAA, bios + 0x5555); + chip_writeb(0xAA, bios + 0x5555); myusec_delay(10); - writeb(0x55, bios + 0x2AAA); + chip_writeb(0x55, bios + 0x2AAA); myusec_delay(10); - writeb(0x60, bios + 0x5555); + chip_writeb(0x60, bios + 0x5555); myusec_delay(10); /* Read product ID */ - id1 = readb(bios); - id2 = readb(bios + 0x01); + id1 = chip_readb(bios); + id2 = chip_readb(bios + 0x01); /* Issue JEDEC Product ID Exit command */ - writeb(0xAA, bios + 0x5555); + chip_writeb(0xAA, bios + 0x5555); myusec_delay(10); - writeb(0x55, bios + 0x2AAA); + chip_writeb(0x55, bios + 0x2AAA); myusec_delay(10); - writeb(0xF0, bios + 0x5555); + chip_writeb(0xF0, bios + 0x5555); myusec_delay(10); printf_debug("%s: id1 0x%02x, id2 0x%02x\n", __FUNCTION__, id1, id2); Index: flashrom-rename_chip_accessors/sst49lfxxxc.c =================================================================== --- flashrom-rename_chip_accessors/sst49lfxxxc.c (Revision 3973) +++ flashrom-rename_chip_accessors/sst49lfxxxc.c (Arbeitskopie) @@ -50,20 +50,20 @@ //printf("bios=0x%08lx\n", (unsigned long)bios); for (i = 0; left > 65536; i++, left -= 65536) { //printf("lockbits at address=0x%08lx is 0x%01x\n", (unsigned long)0xFFC00000 - size + (i * 65536) + 2, *(bios + (i * 65536) + 2) ); - writeb(bits, bios + (i * 65536) + 2); + chip_writeb(bits, bios + (i * 65536) + 2); } address = i * 65536; //printf("lockbits at address=0x%08lx is 0x%01x\n", (unsigned long)0xFFc00000 - size + address + 2, *(bios + address + 2) ); - writeb(bits, bios + address + 2); + chip_writeb(bits, bios + address + 2); address += 32768; //printf("lockbits at address=0x%08lx is 0x%01x\n", (unsigned long)0xFFc00000 - size + address + 2, *(bios + address + 2) ); - writeb(bits, bios + address + 2); + chip_writeb(bits, bios + address + 2); address += 8192; //printf("lockbits at address=0x%08lx is 0x%01x\n", (unsigned long)0xFFc00000 - size + address + 2, *(bios + address + 2) ); - writeb(bits, bios + address + 2); + chip_writeb(bits, bios + address + 2); address += 8192; //printf("lockbits at address=0x%08lx is 0x%01x\n", (unsigned long)0xFFc00000 - size + address + 2, *(bios + address + 2) ); - writeb(bits, bios + address + 2); + chip_writeb(bits, bios + address + 2); return 0; } @@ -73,14 +73,14 @@ { unsigned char status; - writeb(SECTOR_ERASE, bios); - writeb(ERASE, bios + address); + chip_writeb(SECTOR_ERASE, bios); + chip_writeb(ERASE, bios + address); do { - status = readb(bios); + status = chip_readb(bios); if (status & (STATUS_ESS | STATUS_BPS)) { printf("sector erase FAILED at address=0x%08lx status=0x%01x\n", (unsigned long)bios + address, status); - writeb(CLEAR_STATUS, bios); + chip_writeb(CLEAR_STATUS, bios); return (-1); } } while (!(status & STATUS_WSMS)); @@ -96,7 +96,7 @@ int i; unsigned char status; - writeb(CLEAR_STATUS, bios); + chip_writeb(CLEAR_STATUS, bios); for (i = 0; i < page_size; i++) { /* transfer data from source to destination */ if (*src == 0xFF) { @@ -105,14 +105,14 @@ continue; } /*issue AUTO PROGRAM command */ - writeb(AUTO_PGRM, bios); - writeb(*src++, dst++); + chip_writeb(AUTO_PGRM, bios); + chip_writeb(*src++, dst++); do { - status = readb(bios); + status = chip_readb(bios); if (status & (STATUS_ESS | STATUS_BPS)) { printf("sector write FAILED at address=0x%08lx status=0x%01x\n", (unsigned long)dst, status); - writeb(CLEAR_STATUS, bios); + chip_writeb(CLEAR_STATUS, bios); return (-1); } } while (!(status & STATUS_WSMS)); @@ -127,13 +127,13 @@ uint8_t id1, id2; - writeb(RESET, bios); + chip_writeb(RESET, bios); - writeb(READ_ID, bios); - id1 = readb(bios); - id2 = readb(bios + 0x01); + chip_writeb(READ_ID, bios); + id1 = chip_readb(bios); + id2 = chip_readb(bios + 0x01); - writeb(RESET, bios); + chip_writeb(RESET, bios); printf_debug("%s: id1 0x%02x, id2 0x%02x\n", __FUNCTION__, id1, id2); @@ -157,7 +157,7 @@ if (erase_sector_49lfxxxc(bios, i) != 0) return (-1); - writeb(RESET, bios); + chip_writeb(RESET, bios); return 0; } @@ -183,7 +183,7 @@ } printf("\n"); - writeb(RESET, bios); + chip_writeb(RESET, bios); return 0; } Index: flashrom-rename_chip_accessors/sharplhf00l04.c =================================================================== --- flashrom-rename_chip_accessors/sharplhf00l04.c (Revision 3973) +++ flashrom-rename_chip_accessors/sharplhf00l04.c (Arbeitskopie) @@ -41,23 +41,23 @@ #if 0 /* Enter ID mode */ - writeb(0xAA, bios + 0x5555); - writeb(0x55, bios + 0x2AAA); - writeb(0x90, bios + 0x5555); + chip_writeb(0xAA, bios + 0x5555); + chip_writeb(0x55, bios + 0x2AAA); + chip_writeb(0x90, bios + 0x5555); #endif - writeb(0xff, bios); + chip_writeb(0xff, bios); myusec_delay(10); - writeb(0x90, bios); + chip_writeb(0x90, bios); myusec_delay(10); - id1 = readb(bios); - id2 = readb(bios + 0x01); + id1 = chip_readb(bios); + id2 = chip_readb(bios + 0x01); /* Leave ID mode */ - writeb(0xAA, bios + 0x5555); - writeb(0x55, bios + 0x2AAA); - writeb(0xF0, bios + 0x5555); + chip_writeb(0xAA, bios + 0x5555); + chip_writeb(0x55, bios + 0x2AAA); + chip_writeb(0xF0, bios + 0x5555); myusec_delay(10); @@ -76,25 +76,25 @@ uint8_t status; uint8_t id1, id2; - writeb(0x70, bios); - if ((readb(bios) & 0x80) == 0) { // it's busy - while ((readb(bios) & 0x80) == 0) ; + chip_writeb(0x70, bios); + if ((chip_readb(bios) & 0x80) == 0) { // it's busy + while ((chip_readb(bios) & 0x80) == 0) ; } - status = readb(bios); + status = chip_readb(bios); // put another command to get out of status register mode - writeb(0x90, bios); + chip_writeb(0x90, bios); myusec_delay(10); - id1 = readb(bios); - id2 = readb(bios + 0x01); + id1 = chip_readb(bios); + id2 = chip_readb(bios + 0x01); // this is needed to jam it out of "read id" mode - writeb(0xAA, bios + 0x5555); - writeb(0x55, bios + 0x2AAA); - writeb(0xF0, bios + 0x5555); + chip_writeb(0xAA, bios + 0x5555); + chip_writeb(0x55, bios + 0x2AAA); + chip_writeb(0xF0, bios + 0x5555); return status; } @@ -106,19 +106,19 @@ uint8_t status; // clear status register - writeb(0x50, bios); + chip_writeb(0x50, bios); printf("Erase at %p\n", bios); status = wait_lhf00l04(flash->virtual_memory); print_lhf00l04_status(status); // clear write protect printf("write protect is at %p\n", (wrprotect)); - printf("write protect is 0x%x\n", readb(wrprotect)); - writeb(0, wrprotect); - printf("write protect is 0x%x\n", readb(wrprotect)); + printf("write protect is 0x%x\n", chip_readb(wrprotect)); + chip_writeb(0, wrprotect); + printf("write protect is 0x%x\n", chip_readb(wrprotect)); // now start it - writeb(0x20, bios); - writeb(0xd0, bios); + chip_writeb(0x20, bios); + chip_writeb(0xd0, bios); myusec_delay(10); // now let's see what the register is status = wait_lhf00l04(flash->virtual_memory); @@ -149,8 +149,8 @@ for (i = 0; i < page_size; i++) { /* transfer data from source to destination */ - writeb(0x40, dst); - writeb(*src++, dst++); + chip_writeb(0x40, dst); + chip_writeb(*src++, dst++); wait_lhf00l04(bios); } } @@ -163,7 +163,7 @@ volatile uint8_t *bios = flash->virtual_memory; erase_lhf00l04(flash); - if (readb(bios) != 0xff) { + if (chip_readb(bios) != 0xff) { printf("ERASE FAILED!\n"); return -1; } Index: flashrom-rename_chip_accessors/m29f002.c =================================================================== --- flashrom-rename_chip_accessors/m29f002.c (Revision 3973) +++ flashrom-rename_chip_accessors/m29f002.c (Arbeitskopie) @@ -22,12 +22,12 @@ int erase_m29f002(struct flashchip *flash) { volatile uint8_t *bios = flash->virtual_memory; - writeb(0xaa, bios + 0x555); - writeb(0x55, bios + 0xaaa); - writeb(0x80, bios + 0x555); - writeb(0xaa, bios + 0x555); - writeb(0x55, bios + 0xaaa); - writeb(0x10, bios + 0x555); + chip_writeb(0xaa, bios + 0x555); + chip_writeb(0x55, bios + 0xaaa); + chip_writeb(0x80, bios + 0x555); + chip_writeb(0xaa, bios + 0x555); + chip_writeb(0x55, bios + 0xaaa); + chip_writeb(0x10, bios + 0x555); myusec_delay(10); toggle_ready_jedec(bios); return 0; @@ -35,21 +35,21 @@ static void rewrite_block(volatile uint8_t *bios, uint8_t *src, volatile uint8_t *dst, int size) { /* erase */ - writeb(0xaa, bios + 0x555); - writeb(0x55, bios + 0xaaa); - writeb(0x80, bios + 0x555); - writeb(0xaa, bios + 0x555); - writeb(0x55, bios + 0xaaa); - writeb(0x30, dst); + chip_writeb(0xaa, bios + 0x555); + chip_writeb(0x55, bios + 0xaaa); + chip_writeb(0x80, bios + 0x555); + chip_writeb(0xaa, bios + 0x555); + chip_writeb(0x55, bios + 0xaaa); + chip_writeb(0x30, dst); myusec_delay(10); toggle_ready_jedec(bios); /* program */ while (size--) { - writeb(0xaa, bios + 0x555); - writeb(0x55, bios + 0xaaa); - writeb(0xa0, bios + 0x555); - writeb(*src, dst); + chip_writeb(0xaa, bios + 0x555); + chip_writeb(0x55, bios + 0xaaa); + chip_writeb(0xa0, bios + 0x555); + chip_writeb(*src, dst); toggle_ready_jedec(dst); dst++; src++; Index: flashrom-rename_chip_accessors/w39v040c.c =================================================================== --- flashrom-rename_chip_accessors/w39v040c.c (Revision 3973) +++ flashrom-rename_chip_accessors/w39v040c.c (Arbeitskopie) @@ -26,22 +26,22 @@ volatile uint8_t *bios = flash->virtual_memory; uint8_t id1, id2, lock; - writeb(0xAA, bios + 0x5555); + chip_writeb(0xAA, bios + 0x5555); myusec_delay(10); - writeb(0x55, bios + 0x2AAA); + chip_writeb(0x55, bios + 0x2AAA); myusec_delay(10); - writeb(0x90, bios + 0x5555); + chip_writeb(0x90, bios + 0x5555); myusec_delay(10); - id1 = readb(bios); - id2 = readb(bios + 1); - lock = readb(bios + 0xfff2); + id1 = chip_readb(bios); + id2 = chip_readb(bios + 1); + lock = chip_readb(bios + 0xfff2); - writeb(0xAA, bios + 0x5555); + chip_writeb(0xAA, bios + 0x5555); myusec_delay(10); - writeb(0x55, bios + 0x2AAA); + chip_writeb(0x55, bios + 0x2AAA); myusec_delay(10); - writeb(0xF0, bios + 0x5555); + chip_writeb(0xF0, bios + 0x5555); myusec_delay(40); printf_debug("%s: id1 0x%02x, id2 0x%02x", __func__, id1, id2); Index: flashrom-rename_chip_accessors/sst28sf040.c =================================================================== --- flashrom-rename_chip_accessors/sst28sf040.c (Revision 3973) +++ flashrom-rename_chip_accessors/sst28sf040.c (Arbeitskopie) @@ -34,33 +34,33 @@ { uint8_t tmp; - tmp = readb(bios + 0x1823); - tmp = readb(bios + 0x1820); - tmp = readb(bios + 0x1822); - tmp = readb(bios + 0x0418); - tmp = readb(bios + 0x041B); - tmp = readb(bios + 0x0419); - tmp = readb(bios + 0x040A); + tmp = chip_readb(bios + 0x1823); + tmp = chip_readb(bios + 0x1820); + tmp = chip_readb(bios + 0x1822); + tmp = chip_readb(bios + 0x0418); + tmp = chip_readb(bios + 0x041B); + tmp = chip_readb(bios + 0x0419); + tmp = chip_readb(bios + 0x040A); } static __inline__ void unprotect_28sf040(volatile uint8_t *bios) { uint8_t tmp; - tmp = readb(bios + 0x1823); - tmp = readb(bios + 0x1820); - tmp = readb(bios + 0x1822); - tmp = readb(bios + 0x0418); - tmp = readb(bios + 0x041B); - tmp = readb(bios + 0x0419); - tmp = readb(bios + 0x041A); + tmp = chip_readb(bios + 0x1823); + tmp = chip_readb(bios + 0x1820); + tmp = chip_readb(bios + 0x1822); + tmp = chip_readb(bios + 0x0418); + tmp = chip_readb(bios + 0x041B); + tmp = chip_readb(bios + 0x0419); + tmp = chip_readb(bios + 0x041A); } static __inline__ int erase_sector_28sf040(volatile uint8_t *bios, unsigned long address) { - writeb(AUTO_PG_ERASE1, bios); - writeb(AUTO_PG_ERASE2, bios + address); + chip_writeb(AUTO_PG_ERASE1, bios); + chip_writeb(AUTO_PG_ERASE2, bios + address); /* wait for Toggle bit ready */ toggle_ready_jedec(bios); @@ -83,8 +83,8 @@ continue; } /*issue AUTO PROGRAM command */ - writeb(AUTO_PGRM, dst); - writeb(*src++, dst++); + chip_writeb(AUTO_PGRM, dst); + chip_writeb(*src++, dst++); /* wait for Toggle bit ready */ toggle_ready_jedec(bios); @@ -98,16 +98,16 @@ volatile uint8_t *bios = flash->virtual_memory; uint8_t id1, id2; - writeb(RESET, bios); + chip_writeb(RESET, bios); myusec_delay(10); - writeb(READ_ID, bios); + chip_writeb(READ_ID, bios); myusec_delay(10); - id1 = readb(bios); + id1 = chip_readb(bios); myusec_delay(10); - id2 = readb(bios + 0x01); + id2 = chip_readb(bios + 0x01); - writeb(RESET, bios); + chip_writeb(RESET, bios); myusec_delay(10); printf_debug("%s: id1 0x%02x, id2 0x%02x\n", __FUNCTION__, id1, id2); @@ -122,8 +122,8 @@ volatile uint8_t *bios = flash->virtual_memory; unprotect_28sf040(bios); - writeb(CHIP_ERASE, bios); - writeb(CHIP_ERASE, bios); + chip_writeb(CHIP_ERASE, bios); + chip_writeb(CHIP_ERASE, bios); protect_28sf040(bios); myusec_delay(10); Index: flashrom-rename_chip_accessors/stm50flw0x0x.c =================================================================== --- flashrom-rename_chip_accessors/stm50flw0x0x.c (Revision 3973) +++ flashrom-rename_chip_accessors/stm50flw0x0x.c (Arbeitskopie) @@ -33,9 +33,9 @@ void protect_stm50flw0x0x(volatile uint8_t *bios) { - writeb(0xAA, bios + 0x5555); - writeb(0x55, bios + 0x2AAA); - writeb(0xA0, bios + 0x5555); + chip_writeb(0xAA, bios + 0x5555); + chip_writeb(0x55, bios + 0x2AAA); + chip_writeb(0xA0, bios + 0x5555); usleep(200); } @@ -47,37 +47,37 @@ uint32_t largeid1, largeid2; /* Issue JEDEC Product ID Entry command */ - writeb(0xAA, bios + 0x5555); + chip_writeb(0xAA, bios + 0x5555); myusec_delay(10); - writeb(0x55, bios + 0x2AAA); + chip_writeb(0x55, bios + 0x2AAA); myusec_delay(10); - writeb(0x90, bios + 0x5555); + chip_writeb(0x90, bios + 0x5555); myusec_delay(40); /* Read product ID */ - id1 = readb(bios); - id2 = readb(bios + 0x01); + id1 = chip_readb(bios); + id2 = chip_readb(bios + 0x01); largeid1 = id1; largeid2 = id2; /* Check if it is a continuation ID, this should be a while loop. */ if (id1 == 0x7F) { largeid1 <<= 8; - id1 = readb(bios + 0x100); + id1 = chip_readb(bios + 0x100); largeid1 |= id1; } if (id2 == 0x7F) { largeid2 <<= 8; - id2 = readb(bios + 0x101); + id2 = chip_readb(bios + 0x101); largeid2 |= id2; } /* Issue JEDEC Product ID Exit command */ - writeb(0xAA, bios + 0x5555); + chip_writeb(0xAA, bios + 0x5555); myusec_delay(10); - writeb(0x55, bios + 0x2AAA); + chip_writeb(0x55, bios + 0x2AAA); myusec_delay(10); - writeb(0xF0, bios + 0x5555); + chip_writeb(0xF0, bios + 0x5555); myusec_delay(40); printf_debug("%s: id1 0x%02x, id2 0x%02x\n", __FUNCTION__, largeid1, @@ -96,21 +96,21 @@ uint8_t id1; // id2; - writeb(0x70, bios); - if ((readb(bios) & 0x80) == 0) { // it's busy - while ((readb(bios) & 0x80) == 0) ; + chip_writeb(0x70, bios); + if ((chip_readb(bios) & 0x80) == 0) { // it's busy + while ((chip_readb(bios) & 0x80) == 0) ; } // put another command to get out of status register mode - writeb(0x90, bios); + chip_writeb(0x90, bios); myusec_delay(10); - id1 = readb(bios); + id1 = chip_readb(bios); // this is needed to jam it out of "read id" mode - writeb(0xAA, bios + 0x5555); - writeb(0x55, bios + 0x2AAA); - writeb(0xF0, bios + 0x5555); + chip_writeb(0xAA, bios + 0x5555); + chip_writeb(0x55, bios + 0x2AAA); + chip_writeb(0xF0, bios + 0x5555); } /* @@ -142,8 +142,8 @@ // unlock each 4k-sector for (j = 0; j < 0x10000; j += 0x1000) { printf_debug("unlocking at 0x%x\n", offset + j); - writeb(unlock_sector, flash_addr + offset + j); - if (readb(flash_addr + offset + j) != unlock_sector) { + chip_writeb(unlock_sector, flash_addr + offset + j); + if (chip_readb(flash_addr + offset + j) != unlock_sector) { printf("Cannot unlock sector @ 0x%x\n", offset + j); return -1; @@ -151,8 +151,8 @@ } } else { printf_debug("unlocking at 0x%x\n", offset); - writeb(unlock_sector, flash_addr + offset); - if (readb(flash_addr + offset) != unlock_sector) { + chip_writeb(unlock_sector, flash_addr + offset); + if (chip_readb(flash_addr + offset) != unlock_sector) { printf("Cannot unlock sector @ 0x%x\n", offset); return -1; } @@ -167,17 +167,17 @@ int j; // clear status register - writeb(0x50, bios); + chip_writeb(0x50, bios); printf_debug("Erase at %p\n", bios); // now start it - writeb(0x20, bios); - writeb(0xd0, bios); + chip_writeb(0x20, bios); + chip_writeb(0xd0, bios); myusec_delay(10); wait_stm50flw0x0x(flash->virtual_memory); for (j = 0; j < flash->page_size; j++) { - if (readb(bios + j) != 0xFF) { + if (chip_readb(bios + j) != 0xFF) { printf("Erase failed at 0x%x\n", offset + j); return -1; } @@ -197,8 +197,8 @@ /* transfer data from source to destination */ for (i = 0; i < page_size; i++) { - writeb(0x40, dst); - writeb(*src++, dst++); + chip_writeb(0x40, dst); + chip_writeb(*src++, dst++); wait_stm50flw0x0x(bios); } @@ -210,7 +210,7 @@ dst = d; src = s; for (i = 0; i < page_size; i++) { - if (readb(dst) != *src) { + if (chip_readb(dst) != *src) { rc = -1; break; } Index: flashrom-rename_chip_accessors/am29f040b.c =================================================================== --- flashrom-rename_chip_accessors/am29f040b.c (Revision 3973) +++ flashrom-rename_chip_accessors/am29f040b.c (Arbeitskopie) @@ -25,12 +25,12 @@ static __inline__ int erase_sector_29f040b(volatile uint8_t *bios, unsigned long address) { - writeb(0xAA, bios + 0x555); - writeb(0x55, bios + 0x2AA); - writeb(0x80, bios + 0x555); - writeb(0xAA, bios + 0x555); - writeb(0x55, bios + 0x2AA); - writeb(0x30, bios + address); + chip_writeb(0xAA, bios + 0x555); + chip_writeb(0x55, bios + 0x2AA); + chip_writeb(0x80, bios + 0x555); + chip_writeb(0xAA, bios + 0x555); + chip_writeb(0x55, bios + 0x2AA); + chip_writeb(0x30, bios + address); sleep(2); @@ -52,10 +52,10 @@ printf("0x%08lx", (unsigned long)dst - (unsigned long)bios); - writeb(0xAA, bios + 0x555); - writeb(0x55, bios + 0x2AA); - writeb(0xA0, bios + 0x555); - writeb(*src++, dst++); + chip_writeb(0xAA, bios + 0x555); + chip_writeb(0x55, bios + 0x2AA); + chip_writeb(0xA0, bios + 0x555); + chip_writeb(*src++, dst++); /* wait for Toggle bit ready */ toggle_ready_jedec(bios); @@ -72,14 +72,14 @@ volatile uint8_t *bios = flash->virtual_memory; uint8_t id1, id2; - writeb(0xAA, bios + 0x555); - writeb(0x55, bios + 0x2AA); - writeb(0x90, bios + 0x555); + chip_writeb(0xAA, bios + 0x555); + chip_writeb(0x55, bios + 0x2AA); + chip_writeb(0x90, bios + 0x555); - id1 = readb(bios); - id2 = readb(bios + 0x01); + id1 = chip_readb(bios); + id2 = chip_readb(bios + 0x01); - writeb(0xF0, bios); + chip_writeb(0xF0, bios); myusec_delay(10); @@ -94,12 +94,12 @@ { volatile uint8_t *bios = flash->virtual_memory; - writeb(0xAA, bios + 0x555); - writeb(0x55, bios + 0x2AA); - writeb(0x80, bios + 0x555); - writeb(0xAA, bios + 0x555); - writeb(0x55, bios + 0x2AA); - writeb(0x10, bios + 0x555); + chip_writeb(0xAA, bios + 0x555); + chip_writeb(0x55, bios + 0x2AA); + chip_writeb(0x80, bios + 0x555); + chip_writeb(0xAA, bios + 0x555); + chip_writeb(0x55, bios + 0x2AA); + chip_writeb(0x10, bios + 0x555); myusec_delay(10); toggle_ready_jedec(bios); Index: flashrom-rename_chip_accessors/sst_fwhub.c =================================================================== --- flashrom-rename_chip_accessors/sst_fwhub.c (Revision 3973) +++ flashrom-rename_chip_accessors/sst_fwhub.c (Arbeitskopie) @@ -51,7 +51,7 @@ volatile uint8_t *wrprotect = flash->virtual_registers + offset + 2; // clear write protect - writeb(0, wrprotect); + chip_writeb(0, wrprotect); erase_block_jedec(flash->virtual_memory, offset); toggle_ready_jedec(flash->virtual_memory); Index: flashrom-rename_chip_accessors/w39v080fa.c =================================================================== --- flashrom-rename_chip_accessors/w39v080fa.c (Revision 3973) +++ flashrom-rename_chip_accessors/w39v080fa.c (Arbeitskopie) @@ -27,19 +27,19 @@ uint8_t vid, did; /* Product Identification Entry */ - writeb(0xAA, bios + 0x5555); - writeb(0x55, bios + 0x2AAA); - writeb(0x90, bios + 0x5555); + chip_writeb(0xAA, bios + 0x5555); + chip_writeb(0x55, bios + 0x2AAA); + chip_writeb(0x90, bios + 0x5555); myusec_delay(10); /* Read product ID */ - vid = readb(bios); - did = readb(bios + 0x01); + vid = chip_readb(bios); + did = chip_readb(bios + 0x01); /* Product Identifixation Exit */ - writeb(0xAA, bios + 0x5555); - writeb(0x55, bios + 0x2AAA); - writeb(0xF0, bios + 0x5555); + chip_writeb(0xAA, bios + 0x5555); + chip_writeb(0x55, bios + 0x2AAA); + chip_writeb(0xF0, bios + 0x5555); myusec_delay(10); printf_debug("%s: vid 0x%x, did 0x%x\n", __FUNCTION__, vid, did); @@ -58,16 +58,16 @@ uint8_t locking; printf_debug("Trying to unlock block @0x%08x = 0x%02x\n", offset, - readb(wrprotect)); + chip_readb(wrprotect)); - locking = readb(wrprotect); + locking = chip_readb(wrprotect); switch (locking & 0x7) { case 0: printf_debug("Full Access.\n"); return 0; case 1: printf_debug("Write Lock (Default State).\n"); - writeb(0, wrprotect); + chip_writeb(0, wrprotect); return 0; case 2: printf_debug("Locked Open (Full Access, Lock Down).\n"); @@ -77,11 +77,11 @@ return -1; case 4: printf_debug("Read Lock.\n"); - writeb(0, wrprotect); + chip_writeb(0, wrprotect); return 0; case 5: printf_debug("Read/Write Lock.\n"); - writeb(0, wrprotect); + chip_writeb(0, wrprotect); return 0; case 6: fprintf(stderr, "Error: Read Lock, Locked Down.\n"); @@ -106,18 +106,18 @@ */ /* Product Identification Entry */ - writeb(0xAA, bios + 0x5555); - writeb(0x55, bios + 0x2AAA); - writeb(0x90, bios + 0x5555); + chip_writeb(0xAA, bios + 0x5555); + chip_writeb(0x55, bios + 0x2AAA); + chip_writeb(0x90, bios + 0x5555); myusec_delay(10); /* Read Hardware Lock Bits */ - locking = readb(bios + 0xffff2); + locking = chip_readb(bios + 0xffff2); /* Product Identification Exit */ - writeb(0xAA, bios + 0x5555); - writeb(0x55, bios + 0x2AAA); - writeb(0xF0, bios + 0x5555); + chip_writeb(0xAA, bios + 0x5555); + chip_writeb(0x55, bios + 0x2AAA); + chip_writeb(0xF0, bios + 0x5555); myusec_delay(10); printf_debug("Lockout bits:\n"); @@ -151,13 +151,13 @@ printf("0x%08x\b\b\b\b\b\b\b\b\b\b", sector); /* Sector Erase */ - writeb(0xAA, bios + 0x5555); - writeb(0x55, bios + 0x2AAA); - writeb(0x80, bios + 0x5555); + chip_writeb(0xAA, bios + 0x5555); + chip_writeb(0x55, bios + 0x2AAA); + chip_writeb(0x80, bios + 0x5555); - writeb(0xAA, bios + 0x5555); - writeb(0x55, bios + 0x2AAA); - writeb(0x30, bios + sector); + chip_writeb(0xAA, bios + 0x5555); + chip_writeb(0x55, bios + 0x2AAA); + chip_writeb(0x30, bios + sector); /* wait for Toggle bit ready */ toggle_ready_jedec(bios); Index: flashrom-rename_chip_accessors/82802ab.c =================================================================== --- flashrom-rename_chip_accessors/82802ab.c (Revision 3973) +++ flashrom-rename_chip_accessors/82802ab.c (Arbeitskopie) @@ -49,23 +49,23 @@ uint8_t id1, id2; #if 0 - writeb(0xAA, bios + 0x5555); - writeb(0x55, bios + 0x2AAA); - writeb(0x90, bios + 0x5555); + chip_writeb(0xAA, bios + 0x5555); + chip_writeb(0x55, bios + 0x2AAA); + chip_writeb(0x90, bios + 0x5555); #endif - writeb(0xff, bios); + chip_writeb(0xff, bios); myusec_delay(10); - writeb(0x90, bios); + chip_writeb(0x90, bios); myusec_delay(10); - id1 = readb(bios); - id2 = readb(bios + 0x01); + id1 = chip_readb(bios); + id2 = chip_readb(bios + 0x01); /* Leave ID mode */ - writeb(0xAA, bios + 0x5555); - writeb(0x55, bios + 0x2AAA); - writeb(0xF0, bios + 0x5555); + chip_writeb(0xAA, bios + 0x5555); + chip_writeb(0x55, bios + 0x2AAA); + chip_writeb(0xF0, bios + 0x5555); myusec_delay(10); @@ -84,25 +84,25 @@ uint8_t status; uint8_t id1, id2; - writeb(0x70, bios); - if ((readb(bios) & 0x80) == 0) { // it's busy - while ((readb(bios) & 0x80) == 0) ; + chip_writeb(0x70, bios); + if ((chip_readb(bios) & 0x80) == 0) { // it's busy + while ((chip_readb(bios) & 0x80) == 0) ; } - status = readb(bios); + status = chip_readb(bios); // put another command to get out of status register mode - writeb(0x90, bios); + chip_writeb(0x90, bios); myusec_delay(10); - id1 = readb(bios); - id2 = readb(bios + 0x01); + id1 = chip_readb(bios); + id2 = chip_readb(bios + 0x01); // this is needed to jam it out of "read id" mode - writeb(0xAA, bios + 0x5555); - writeb(0x55, bios + 0x2AAA); - writeb(0xF0, bios + 0x5555); + chip_writeb(0xAA, bios + 0x5555); + chip_writeb(0x55, bios + 0x2AAA); + chip_writeb(0xF0, bios + 0x5555); return status; } @@ -115,23 +115,23 @@ uint8_t status; // clear status register - writeb(0x50, bios); + chip_writeb(0x50, bios); //printf("Erase at %p\n", bios); // clear write protect //printf("write protect is at %p\n", (wrprotect)); //printf("write protect is 0x%x\n", *(wrprotect)); - writeb(0, wrprotect); + chip_writeb(0, wrprotect); //printf("write protect is 0x%x\n", *(wrprotect)); // now start it - writeb(0x20, bios); - writeb(0xd0, bios); + chip_writeb(0x20, bios); + chip_writeb(0xd0, bios); myusec_delay(10); // now let's see what the register is status = wait_82802ab(flash->virtual_memory); //print_82802ab_status(status); for (j = 0; j < flash->page_size; j++) { - if (readb(bios + j) != 0xFF) { + if (chip_readb(bios + j) != 0xFF) { printf("BLOCK ERASE failed at 0x%x\n", offset); return -1; } @@ -162,8 +162,8 @@ for (i = 0; i < page_size; i++) { /* transfer data from source to destination */ - writeb(0x40, dst); - writeb(*src++, dst++); + chip_writeb(0x40, dst); + chip_writeb(*src++, dst++); wait_82802ab(bios); } } Index: flashrom-rename_chip_accessors/m29f400bt.c =================================================================== --- flashrom-rename_chip_accessors/m29f400bt.c (Revision 3973) +++ flashrom-rename_chip_accessors/m29f400bt.c (Arbeitskopie) @@ -22,9 +22,9 @@ void protect_m29f400bt(volatile uint8_t *bios) { - writeb(0xAA, bios + 0xAAA); - writeb(0x55, bios + 0x555); - writeb(0xA0, bios + 0xAAA); + chip_writeb(0xAA, bios + 0xAAA); + chip_writeb(0x55, bios + 0x555); + chip_writeb(0xA0, bios + 0xAAA); usleep(200); } @@ -35,18 +35,18 @@ int i; for (i = 0; i < page_size; i++) { - writeb(0xAA, bios + 0xAAA); - writeb(0x55, bios + 0x555); - writeb(0xA0, bios + 0xAAA); + chip_writeb(0xAA, bios + 0xAAA); + chip_writeb(0x55, bios + 0x555); + chip_writeb(0xA0, bios + 0xAAA); /* transfer data from source to destination */ - writeb(*src, dst); + chip_writeb(*src, dst); //*(volatile char *) (bios) = 0xF0; //usleep(5); toggle_ready_jedec(dst); printf ("Value in the flash at address %p = %#x, want %#x\n", - (uint8_t *) (dst - bios), readb(dst), *src); + (uint8_t *) (dst - bios), chip_readb(dst), *src); dst++; src++; } @@ -57,21 +57,21 @@ volatile uint8_t *bios = flash->virtual_memory; uint8_t id1, id2; - writeb(0xAA, bios + 0xAAA); - writeb(0x55, bios + 0x555); - writeb(0x90, bios + 0xAAA); + chip_writeb(0xAA, bios + 0xAAA); + chip_writeb(0x55, bios + 0x555); + chip_writeb(0x90, bios + 0xAAA); myusec_delay(10); - id1 = readb(bios); + id1 = chip_readb(bios); /* The data sheet says id2 is at (bios + 0x01) and id2 listed in * flash.h does not match. It should be possible to use JEDEC probe. */ - id2 = readb(bios + 0x02); + id2 = chip_readb(bios + 0x02); - writeb(0xAA, bios + 0xAAA); - writeb(0x55, bios + 0x555); - writeb(0xF0, bios + 0xAAA); + chip_writeb(0xAA, bios + 0xAAA); + chip_writeb(0x55, bios + 0x555); + chip_writeb(0xF0, bios + 0xAAA); myusec_delay(10); @@ -87,13 +87,13 @@ { volatile uint8_t *bios = flash->virtual_memory; - writeb(0xAA, bios + 0xAAA); - writeb(0x55, bios + 0x555); - writeb(0x80, bios + 0xAAA); + chip_writeb(0xAA, bios + 0xAAA); + chip_writeb(0x55, bios + 0x555); + chip_writeb(0x80, bios + 0xAAA); - writeb(0xAA, bios + 0xAAA); - writeb(0x55, bios + 0x555); - writeb(0x10, bios + 0xAAA); + chip_writeb(0xAA, bios + 0xAAA); + chip_writeb(0x55, bios + 0x555); + chip_writeb(0x10, bios + 0xAAA); myusec_delay(10); toggle_ready_jedec(bios); @@ -104,14 +104,14 @@ int block_erase_m29f400bt(volatile uint8_t *bios, volatile uint8_t *dst) { - writeb(0xAA, bios + 0xAAA); - writeb(0x55, bios + 0x555); - writeb(0x80, bios + 0xAAA); + chip_writeb(0xAA, bios + 0xAAA); + chip_writeb(0x55, bios + 0x555); + chip_writeb(0x80, bios + 0xAAA); - writeb(0xAA, bios + 0xAAA); - writeb(0x55, bios + 0x555); + chip_writeb(0xAA, bios + 0xAAA); + chip_writeb(0x55, bios + 0x555); //*(volatile uint8_t *) (bios + 0xAAA) = 0x10; - writeb(0x30, dst); + chip_writeb(0x30, dst); myusec_delay(10); toggle_ready_jedec(bios); Index: flashrom-rename_chip_accessors/mx29f002.c =================================================================== --- flashrom-rename_chip_accessors/mx29f002.c (Revision 3973) +++ flashrom-rename_chip_accessors/mx29f002.c (Arbeitskopie) @@ -27,14 +27,14 @@ volatile uint8_t *bios = flash->virtual_memory; uint8_t id1, id2; - writeb(0xAA, bios + 0x5555); - writeb(0x55, bios + 0x2AAA); - writeb(0x90, bios + 0x5555); + chip_writeb(0xAA, bios + 0x5555); + chip_writeb(0x55, bios + 0x2AAA); + chip_writeb(0x90, bios + 0x5555); - id1 = readb(bios); - id2 = readb(bios + 0x01); + id1 = chip_readb(bios); + id2 = chip_readb(bios + 0x01); - writeb(0xF0, bios); + chip_writeb(0xF0, bios); myusec_delay(10); @@ -49,13 +49,13 @@ { volatile uint8_t *bios = flash->virtual_memory; - writeb(0xF0, bios + 0x555); - writeb(0xAA, bios + 0x555); - writeb(0x55, bios + 0x2AA); - writeb(0x80, bios + 0x555); - writeb(0xAA, bios + 0x555); - writeb(0x55, bios + 0x2AA); - writeb(0x10, bios + 0x555); + chip_writeb(0xF0, bios + 0x555); + chip_writeb(0xAA, bios + 0x555); + chip_writeb(0x55, bios + 0x2AA); + chip_writeb(0x80, bios + 0x555); + chip_writeb(0xAA, bios + 0x555); + chip_writeb(0x55, bios + 0x2AA); + chip_writeb(0x10, bios + 0x555); myusec_delay(100); toggle_ready_jedec(bios); @@ -65,12 +65,12 @@ #if 0 toggle_ready_jedec(bios); - writeb(0x30, bios + 0x0ffff); - writeb(0x30, bios + 0x1ffff); - writeb(0x30, bios + 0x2ffff); - writeb(0x30, bios + 0x37fff); - writeb(0x30, bios + 0x39fff); - writeb(0x30, bios + 0x3bfff); + chip_writeb(0x30, bios + 0x0ffff); + chip_writeb(0x30, bios + 0x1ffff); + chip_writeb(0x30, bios + 0x2ffff); + chip_writeb(0x30, bios + 0x37fff); + chip_writeb(0x30, bios + 0x39fff); + chip_writeb(0x30, bios + 0x3bfff); #endif return 0; @@ -83,7 +83,7 @@ volatile uint8_t *bios = flash->virtual_memory; volatile uint8_t *dst = bios; - writeb(0xF0, bios); + chip_writeb(0xF0, bios); myusec_delay(10); erase_29f002(flash); //*bios = 0xF0; @@ -93,10 +93,10 @@ /* write to the sector */ if ((i & 0xfff) == 0) printf("address: 0x%08lx", (unsigned long)i); - writeb(0xAA, bios + 0x5555); - writeb(0x55, bios + 0x2AAA); - writeb(0xA0, bios + 0x5555); - writeb(*buf++, dst++); + chip_writeb(0xAA, bios + 0x5555); + chip_writeb(0x55, bios + 0x2AAA); + chip_writeb(0xA0, bios + 0x5555); + chip_writeb(*buf++, dst++); /* wait for Toggle bit ready */ toggle_ready_jedec(dst);

2 2

r3984 - trunk/util/flashrom
by svn＠coreboot.org 06 Mar '09

06 Mar '09

Author: hailfinger Date: 2009-03-06 23:26:00 +0100 (Fri, 06 Mar 2009) New Revision: 3984 Modified: trunk/util/flashrom/82802ab.c trunk/util/flashrom/am29f040b.c trunk/util/flashrom/en29f002a.c trunk/util/flashrom/flash.h trunk/util/flashrom/jedec.c trunk/util/flashrom/m29f002.c trunk/util/flashrom/m29f400bt.c trunk/util/flashrom/mx29f002.c trunk/util/flashrom/pm49fl00x.c trunk/util/flashrom/sharplhf00l04.c trunk/util/flashrom/sst28sf040.c trunk/util/flashrom/sst49lfxxxc.c trunk/util/flashrom/sst_fwhub.c trunk/util/flashrom/stm50flw0x0x.c trunk/util/flashrom/w29ee011.c trunk/util/flashrom/w39v040c.c trunk/util/flashrom/w39v080fa.c Log: FreeBSD definitions of (read|write)[bwl] collide with our own. Before we attempt trickery, we can simply rename the accessor functions. Patch created with the help of Coccinelle. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Idwer Vollering <idwer_v(a)hotmail.com> Acked-by: Patrick Georgi <patrick(a)georgi-clan.de> Modified: trunk/util/flashrom/82802ab.c =================================================================== --- trunk/util/flashrom/82802ab.c 2009-03-06 19:54:15 UTC (rev 3983) +++ trunk/util/flashrom/82802ab.c 2009-03-06 22:26:00 UTC (rev 3984) @@ -49,23 +49,23 @@ uint8_t id1, id2; #if 0 - writeb(0xAA, bios + 0x5555); - writeb(0x55, bios + 0x2AAA); - writeb(0x90, bios + 0x5555); + chip_writeb(0xAA, bios + 0x5555); + chip_writeb(0x55, bios + 0x2AAA); + chip_writeb(0x90, bios + 0x5555); #endif - writeb(0xff, bios); + chip_writeb(0xff, bios); myusec_delay(10); - writeb(0x90, bios); + chip_writeb(0x90, bios); myusec_delay(10); - id1 = readb(bios); - id2 = readb(bios + 0x01); + id1 = chip_readb(bios); + id2 = chip_readb(bios + 0x01); /* Leave ID mode */ - writeb(0xAA, bios + 0x5555); - writeb(0x55, bios + 0x2AAA); - writeb(0xF0, bios + 0x5555); + chip_writeb(0xAA, bios + 0x5555); + chip_writeb(0x55, bios + 0x2AAA); + chip_writeb(0xF0, bios + 0x5555); myusec_delay(10); @@ -84,25 +84,25 @@ uint8_t status; uint8_t id1, id2; - writeb(0x70, bios); - if ((readb(bios) & 0x80) == 0) { // it's busy - while ((readb(bios) & 0x80) == 0) ; + chip_writeb(0x70, bios); + if ((chip_readb(bios) & 0x80) == 0) { // it's busy + while ((chip_readb(bios) & 0x80) == 0) ; } - status = readb(bios); + status = chip_readb(bios); // put another command to get out of status register mode - writeb(0x90, bios); + chip_writeb(0x90, bios); myusec_delay(10); - id1 = readb(bios); - id2 = readb(bios + 0x01); + id1 = chip_readb(bios); + id2 = chip_readb(bios + 0x01); // this is needed to jam it out of "read id" mode - writeb(0xAA, bios + 0x5555); - writeb(0x55, bios + 0x2AAA); - writeb(0xF0, bios + 0x5555); + chip_writeb(0xAA, bios + 0x5555); + chip_writeb(0x55, bios + 0x2AAA); + chip_writeb(0xF0, bios + 0x5555); return status; } @@ -115,23 +115,23 @@ uint8_t status; // clear status register - writeb(0x50, bios); + chip_writeb(0x50, bios); //printf("Erase at %p\n", bios); // clear write protect //printf("write protect is at %p\n", (wrprotect)); //printf("write protect is 0x%x\n", *(wrprotect)); - writeb(0, wrprotect); + chip_writeb(0, wrprotect); //printf("write protect is 0x%x\n", *(wrprotect)); // now start it - writeb(0x20, bios); - writeb(0xd0, bios); + chip_writeb(0x20, bios); + chip_writeb(0xd0, bios); myusec_delay(10); // now let's see what the register is status = wait_82802ab(flash->virtual_memory); //print_82802ab_status(status); for (j = 0; j < flash->page_size; j++) { - if (readb(bios + j) != 0xFF) { + if (chip_readb(bios + j) != 0xFF) { printf("BLOCK ERASE failed at 0x%x\n", offset); return -1; } @@ -162,8 +162,8 @@ for (i = 0; i < page_size; i++) { /* transfer data from source to destination */ - writeb(0x40, dst); - writeb(*src++, dst++); + chip_writeb(0x40, dst); + chip_writeb(*src++, dst++); wait_82802ab(bios); } } Modified: trunk/util/flashrom/am29f040b.c =================================================================== --- trunk/util/flashrom/am29f040b.c 2009-03-06 19:54:15 UTC (rev 3983) +++ trunk/util/flashrom/am29f040b.c 2009-03-06 22:26:00 UTC (rev 3984) @@ -25,12 +25,12 @@ static __inline__ int erase_sector_29f040b(volatile uint8_t *bios, unsigned long address) { - writeb(0xAA, bios + 0x555); - writeb(0x55, bios + 0x2AA); - writeb(0x80, bios + 0x555); - writeb(0xAA, bios + 0x555); - writeb(0x55, bios + 0x2AA); - writeb(0x30, bios + address); + chip_writeb(0xAA, bios + 0x555); + chip_writeb(0x55, bios + 0x2AA); + chip_writeb(0x80, bios + 0x555); + chip_writeb(0xAA, bios + 0x555); + chip_writeb(0x55, bios + 0x2AA); + chip_writeb(0x30, bios + address); sleep(2); @@ -52,10 +52,10 @@ printf("0x%08lx", (unsigned long)dst - (unsigned long)bios); - writeb(0xAA, bios + 0x555); - writeb(0x55, bios + 0x2AA); - writeb(0xA0, bios + 0x555); - writeb(*src++, dst++); + chip_writeb(0xAA, bios + 0x555); + chip_writeb(0x55, bios + 0x2AA); + chip_writeb(0xA0, bios + 0x555); + chip_writeb(*src++, dst++); /* wait for Toggle bit ready */ toggle_ready_jedec(bios); @@ -72,14 +72,14 @@ volatile uint8_t *bios = flash->virtual_memory; uint8_t id1, id2; - writeb(0xAA, bios + 0x555); - writeb(0x55, bios + 0x2AA); - writeb(0x90, bios + 0x555); + chip_writeb(0xAA, bios + 0x555); + chip_writeb(0x55, bios + 0x2AA); + chip_writeb(0x90, bios + 0x555); - id1 = readb(bios); - id2 = readb(bios + 0x01); + id1 = chip_readb(bios); + id2 = chip_readb(bios + 0x01); - writeb(0xF0, bios); + chip_writeb(0xF0, bios); myusec_delay(10); @@ -94,12 +94,12 @@ { volatile uint8_t *bios = flash->virtual_memory; - writeb(0xAA, bios + 0x555); - writeb(0x55, bios + 0x2AA); - writeb(0x80, bios + 0x555); - writeb(0xAA, bios + 0x555); - writeb(0x55, bios + 0x2AA); - writeb(0x10, bios + 0x555); + chip_writeb(0xAA, bios + 0x555); + chip_writeb(0x55, bios + 0x2AA); + chip_writeb(0x80, bios + 0x555); + chip_writeb(0xAA, bios + 0x555); + chip_writeb(0x55, bios + 0x2AA); + chip_writeb(0x10, bios + 0x555); myusec_delay(10); toggle_ready_jedec(bios); Modified: trunk/util/flashrom/en29f002a.c =================================================================== --- trunk/util/flashrom/en29f002a.c 2009-03-06 19:54:15 UTC (rev 3983) +++ trunk/util/flashrom/en29f002a.c 2009-03-06 22:26:00 UTC (rev 3984) @@ -35,19 +35,19 @@ volatile uint8_t *bios = flash->virtual_memory; uint8_t id1, id2; - writeb(0xAA, bios + 0x555); - writeb(0x55, bios + 0x2AA); - writeb(0x90, bios + 0x555); + chip_writeb(0xAA, bios + 0x555); + chip_writeb(0x55, bios + 0x2AA); + chip_writeb(0x90, bios + 0x555); myusec_delay(10); - id1 = readb(bios + 0x100); - id2 = readb(bios + 0x101); + id1 = chip_readb(bios + 0x100); + id2 = chip_readb(bios + 0x101); /* exit by writing F0 anywhere? or the code below */ - writeb(0xAA, bios + 0x555); - writeb(0x55, bios + 0x2AA); - writeb(0xF0, bios + 0x555); + chip_writeb(0xAA, bios + 0x555); + chip_writeb(0x55, bios + 0x2AA); + chip_writeb(0xF0, bios + 0x555); printf_debug("%s: id1 0x%02x, id2 0x%02x\n", __FUNCTION__, id1, id2); @@ -68,19 +68,19 @@ volatile uint8_t *bios = flash->virtual_memory; uint8_t id1, id2; - writeb(0xAA, bios + 0x555); - writeb(0x55, bios + 0xAAA); - writeb(0x90, bios + 0x555); + chip_writeb(0xAA, bios + 0x555); + chip_writeb(0x55, bios + 0xAAA); + chip_writeb(0x90, bios + 0x555); myusec_delay(10); - id1 = readb(bios + 0x100); - id2 = readb(bios + 0x101); + id1 = chip_readb(bios + 0x100); + id2 = chip_readb(bios + 0x101); /* exit by writing F0 anywhere? or the code below */ - writeb(0xAA, bios + 0x555); - writeb(0x55, bios + 0xAAA); - writeb(0xF0, bios + 0x555); + chip_writeb(0xAA, bios + 0x555); + chip_writeb(0x55, bios + 0xAAA); + chip_writeb(0xF0, bios + 0x555); printf_debug("%s: id1 0x%x, id2 0x%x\n", __FUNCTION__, id1, id2); @@ -107,10 +107,10 @@ /* write to the sector */ if ((i & 0xfff) == 0) printf("address: 0x%08lx", (unsigned long)i); - writeb(0xAA, bios + 0x5555); - writeb(0x55, bios + 0x2AAA); - writeb(0xA0, bios + 0x5555); - writeb(*buf++, dst++); + chip_writeb(0xAA, bios + 0x5555); + chip_writeb(0x55, bios + 0x2AAA); + chip_writeb(0xA0, bios + 0x5555); + chip_writeb(*buf++, dst++); /* wait for Toggle bit ready */ toggle_ready_jedec(dst); Modified: trunk/util/flashrom/flash.h =================================================================== --- trunk/util/flashrom/flash.h 2009-03-06 19:54:15 UTC (rev 3983) +++ trunk/util/flashrom/flash.h 2009-03-06 22:26:00 UTC (rev 3984) @@ -58,32 +58,32 @@ #define INL inl #endif -static inline void writeb(uint8_t b, volatile void *addr) +static inline void chip_writeb(uint8_t b, volatile void *addr) { *(volatile uint8_t *) addr = b; } -static inline void writew(uint16_t b, volatile void *addr) +static inline void chip_writew(uint16_t b, volatile void *addr) { *(volatile uint16_t *) addr = b; } -static inline void writel(uint32_t b, volatile void *addr) +static inline void chip_writel(uint32_t b, volatile void *addr) { *(volatile uint32_t *) addr = b; } -static inline uint8_t readb(const volatile void *addr) +static inline uint8_t chip_readb(const volatile void *addr) { return *(volatile uint8_t *) addr; } -static inline uint16_t readw(const volatile void *addr) +static inline uint16_t chip_readw(const volatile void *addr) { return *(volatile uint16_t *) addr; } -static inline uint32_t readl(const volatile void *addr) +static inline uint32_t chip_readl(const volatile void *addr) { return *(volatile uint32_t *) addr; } Modified: trunk/util/flashrom/jedec.c =================================================================== --- trunk/util/flashrom/jedec.c 2009-03-06 19:54:15 UTC (rev 3983) +++ trunk/util/flashrom/jedec.c 2009-03-06 22:26:00 UTC (rev 3984) @@ -40,10 +40,10 @@ unsigned int i = 0; uint8_t tmp1, tmp2; - tmp1 = readb(dst) & 0x40; + tmp1 = chip_readb(dst) & 0x40; while (i++ < 0xFFFFFFF) { - tmp2 = readb(dst) & 0x40; + tmp2 = chip_readb(dst) & 0x40; if (tmp1 == tmp2) { break; } @@ -59,7 +59,7 @@ data &= 0x80; while (i++ < 0xFFFFFFF) { - tmp = readb(dst) & 0x80; + tmp = chip_readb(dst) & 0x80; if (tmp == data) { break; } @@ -68,21 +68,21 @@ void unprotect_jedec(volatile uint8_t *bios) { - writeb(0xAA, bios + 0x5555); - writeb(0x55, bios + 0x2AAA); - writeb(0x80, bios + 0x5555); - writeb(0xAA, bios + 0x5555); - writeb(0x55, bios + 0x2AAA); - writeb(0x20, bios + 0x5555); + chip_writeb(0xAA, bios + 0x5555); + chip_writeb(0x55, bios + 0x2AAA); + chip_writeb(0x80, bios + 0x5555); + chip_writeb(0xAA, bios + 0x5555); + chip_writeb(0x55, bios + 0x2AAA); + chip_writeb(0x20, bios + 0x5555); usleep(200); } void protect_jedec(volatile uint8_t *bios) { - writeb(0xAA, bios + 0x5555); - writeb(0x55, bios + 0x2AAA); - writeb(0xA0, bios + 0x5555); + chip_writeb(0xAA, bios + 0x5555); + chip_writeb(0x55, bios + 0x2AAA); + chip_writeb(0xA0, bios + 0x5555); usleep(200); } @@ -94,40 +94,40 @@ uint32_t largeid1, largeid2; /* Issue JEDEC Product ID Entry command */ - writeb(0xAA, bios + 0x5555); + chip_writeb(0xAA, bios + 0x5555); myusec_delay(10); - writeb(0x55, bios + 0x2AAA); + chip_writeb(0x55, bios + 0x2AAA); myusec_delay(10); - writeb(0x90, bios + 0x5555); + chip_writeb(0x90, bios + 0x5555); /* Older chips may need up to 100 us to respond. The ATMEL 29C020 * needs 10 ms according to the data sheet. */ myusec_delay(10000); /* Read product ID */ - id1 = readb(bios); - id2 = readb(bios + 0x01); + id1 = chip_readb(bios); + id2 = chip_readb(bios + 0x01); largeid1 = id1; largeid2 = id2; /* Check if it is a continuation ID, this should be a while loop. */ if (id1 == 0x7F) { largeid1 <<= 8; - id1 = readb(bios + 0x100); + id1 = chip_readb(bios + 0x100); largeid1 |= id1; } if (id2 == 0x7F) { largeid2 <<= 8; - id2 = readb(bios + 0x101); + id2 = chip_readb(bios + 0x101); largeid2 |= id2; } /* Issue JEDEC Product ID Exit command */ - writeb(0xAA, bios + 0x5555); + chip_writeb(0xAA, bios + 0x5555); myusec_delay(10); - writeb(0x55, bios + 0x2AAA); + chip_writeb(0x55, bios + 0x2AAA); myusec_delay(10); - writeb(0xF0, bios + 0x5555); + chip_writeb(0xF0, bios + 0x5555); myusec_delay(40); printf_debug("%s: id1 0x%02x, id2 0x%02x", __FUNCTION__, largeid1, largeid2); @@ -143,18 +143,18 @@ int erase_sector_jedec(volatile uint8_t *bios, unsigned int page) { /* Issue the Sector Erase command */ - writeb(0xAA, bios + 0x5555); + chip_writeb(0xAA, bios + 0x5555); myusec_delay(10); - writeb(0x55, bios + 0x2AAA); + chip_writeb(0x55, bios + 0x2AAA); myusec_delay(10); - writeb(0x80, bios + 0x5555); + chip_writeb(0x80, bios + 0x5555); myusec_delay(10); - writeb(0xAA, bios + 0x5555); + chip_writeb(0xAA, bios + 0x5555); myusec_delay(10); - writeb(0x55, bios + 0x2AAA); + chip_writeb(0x55, bios + 0x2AAA); myusec_delay(10); - writeb(0x30, bios + page); + chip_writeb(0x30, bios + page); myusec_delay(10); /* wait for Toggle bit ready */ @@ -166,18 +166,18 @@ int erase_block_jedec(volatile uint8_t *bios, unsigned int block) { /* Issue the Sector Erase command */ - writeb(0xAA, bios + 0x5555); + chip_writeb(0xAA, bios + 0x5555); myusec_delay(10); - writeb(0x55, bios + 0x2AAA); + chip_writeb(0x55, bios + 0x2AAA); myusec_delay(10); - writeb(0x80, bios + 0x5555); + chip_writeb(0x80, bios + 0x5555); myusec_delay(10); - writeb(0xAA, bios + 0x5555); + chip_writeb(0xAA, bios + 0x5555); myusec_delay(10); - writeb(0x55, bios + 0x2AAA); + chip_writeb(0x55, bios + 0x2AAA); myusec_delay(10); - writeb(0x50, bios + block); + chip_writeb(0x50, bios + block); myusec_delay(10); /* wait for Toggle bit ready */ @@ -191,18 +191,18 @@ volatile uint8_t *bios = flash->virtual_memory; /* Issue the JEDEC Chip Erase command */ - writeb(0xAA, bios + 0x5555); + chip_writeb(0xAA, bios + 0x5555); myusec_delay(10); - writeb(0x55, bios + 0x2AAA); + chip_writeb(0x55, bios + 0x2AAA); myusec_delay(10); - writeb(0x80, bios + 0x5555); + chip_writeb(0x80, bios + 0x5555); myusec_delay(10); - writeb(0xAA, bios + 0x5555); + chip_writeb(0xAA, bios + 0x5555); myusec_delay(10); - writeb(0x55, bios + 0x2AAA); + chip_writeb(0x55, bios + 0x2AAA); myusec_delay(10); - writeb(0x10, bios + 0x5555); + chip_writeb(0x10, bios + 0x5555); myusec_delay(10); toggle_ready_jedec(bios); @@ -219,15 +219,15 @@ retry: /* Issue JEDEC Data Unprotect comand */ - writeb(0xAA, bios + 0x5555); - writeb(0x55, bios + 0x2AAA); - writeb(0xA0, bios + 0x5555); + chip_writeb(0xAA, bios + 0x5555); + chip_writeb(0x55, bios + 0x2AAA); + chip_writeb(0xA0, bios + 0x5555); /* transfer data from source to destination */ for (i = start_index; i < page_size; i++) { /* If the data is 0xFF, don't program it */ if (*src != 0xFF) - writeb(*src, dst); + chip_writeb(*src, dst); dst++; src++; } @@ -238,7 +238,7 @@ src = s; ok = 1; for (i = 0; i < page_size; i++) { - if (readb(dst) != *src) { + if (chip_readb(dst) != *src) { ok = 0; break; } @@ -269,15 +269,15 @@ retry: /* Issue JEDEC Byte Program command */ - writeb(0xAA, bios + 0x5555); - writeb(0x55, bios + 0x2AAA); - writeb(0xA0, bios + 0x5555); + chip_writeb(0xAA, bios + 0x5555); + chip_writeb(0x55, bios + 0x2AAA); + chip_writeb(0xA0, bios + 0x5555); /* transfer data from source to destination */ - writeb(*src, dst); + chip_writeb(*src, dst); toggle_ready_jedec(bios); - if (readb(dst) != *src && tried++ < MAX_REFLASH_TRIES) { + if (chip_readb(dst) != *src && tried++ < MAX_REFLASH_TRIES) { goto retry; } Modified: trunk/util/flashrom/m29f002.c =================================================================== --- trunk/util/flashrom/m29f002.c 2009-03-06 19:54:15 UTC (rev 3983) +++ trunk/util/flashrom/m29f002.c 2009-03-06 22:26:00 UTC (rev 3984) @@ -22,12 +22,12 @@ int erase_m29f002(struct flashchip *flash) { volatile uint8_t *bios = flash->virtual_memory; - writeb(0xaa, bios + 0x555); - writeb(0x55, bios + 0xaaa); - writeb(0x80, bios + 0x555); - writeb(0xaa, bios + 0x555); - writeb(0x55, bios + 0xaaa); - writeb(0x10, bios + 0x555); + chip_writeb(0xaa, bios + 0x555); + chip_writeb(0x55, bios + 0xaaa); + chip_writeb(0x80, bios + 0x555); + chip_writeb(0xaa, bios + 0x555); + chip_writeb(0x55, bios + 0xaaa); + chip_writeb(0x10, bios + 0x555); myusec_delay(10); toggle_ready_jedec(bios); return 0; @@ -35,21 +35,21 @@ static void rewrite_block(volatile uint8_t *bios, uint8_t *src, volatile uint8_t *dst, int size) { /* erase */ - writeb(0xaa, bios + 0x555); - writeb(0x55, bios + 0xaaa); - writeb(0x80, bios + 0x555); - writeb(0xaa, bios + 0x555); - writeb(0x55, bios + 0xaaa); - writeb(0x30, dst); + chip_writeb(0xaa, bios + 0x555); + chip_writeb(0x55, bios + 0xaaa); + chip_writeb(0x80, bios + 0x555); + chip_writeb(0xaa, bios + 0x555); + chip_writeb(0x55, bios + 0xaaa); + chip_writeb(0x30, dst); myusec_delay(10); toggle_ready_jedec(bios); /* program */ while (size--) { - writeb(0xaa, bios + 0x555); - writeb(0x55, bios + 0xaaa); - writeb(0xa0, bios + 0x555); - writeb(*src, dst); + chip_writeb(0xaa, bios + 0x555); + chip_writeb(0x55, bios + 0xaaa); + chip_writeb(0xa0, bios + 0x555); + chip_writeb(*src, dst); toggle_ready_jedec(dst); dst++; src++; Modified: trunk/util/flashrom/m29f400bt.c =================================================================== --- trunk/util/flashrom/m29f400bt.c 2009-03-06 19:54:15 UTC (rev 3983) +++ trunk/util/flashrom/m29f400bt.c 2009-03-06 22:26:00 UTC (rev 3984) @@ -22,9 +22,9 @@ void protect_m29f400bt(volatile uint8_t *bios) { - writeb(0xAA, bios + 0xAAA); - writeb(0x55, bios + 0x555); - writeb(0xA0, bios + 0xAAA); + chip_writeb(0xAA, bios + 0xAAA); + chip_writeb(0x55, bios + 0x555); + chip_writeb(0xA0, bios + 0xAAA); usleep(200); } @@ -35,18 +35,18 @@ int i; for (i = 0; i < page_size; i++) { - writeb(0xAA, bios + 0xAAA); - writeb(0x55, bios + 0x555); - writeb(0xA0, bios + 0xAAA); + chip_writeb(0xAA, bios + 0xAAA); + chip_writeb(0x55, bios + 0x555); + chip_writeb(0xA0, bios + 0xAAA); /* transfer data from source to destination */ - writeb(*src, dst); + chip_writeb(*src, dst); //*(volatile char *) (bios) = 0xF0; //usleep(5); toggle_ready_jedec(dst); printf ("Value in the flash at address %p = %#x, want %#x\n", - (uint8_t *) (dst - bios), readb(dst), *src); + (uint8_t *) (dst - bios), chip_readb(dst), *src); dst++; src++; } @@ -57,21 +57,21 @@ volatile uint8_t *bios = flash->virtual_memory; uint8_t id1, id2; - writeb(0xAA, bios + 0xAAA); - writeb(0x55, bios + 0x555); - writeb(0x90, bios + 0xAAA); + chip_writeb(0xAA, bios + 0xAAA); + chip_writeb(0x55, bios + 0x555); + chip_writeb(0x90, bios + 0xAAA); myusec_delay(10); - id1 = readb(bios); + id1 = chip_readb(bios); /* The data sheet says id2 is at (bios + 0x01) and id2 listed in * flash.h does not match. It should be possible to use JEDEC probe. */ - id2 = readb(bios + 0x02); + id2 = chip_readb(bios + 0x02); - writeb(0xAA, bios + 0xAAA); - writeb(0x55, bios + 0x555); - writeb(0xF0, bios + 0xAAA); + chip_writeb(0xAA, bios + 0xAAA); + chip_writeb(0x55, bios + 0x555); + chip_writeb(0xF0, bios + 0xAAA); myusec_delay(10); @@ -87,13 +87,13 @@ { volatile uint8_t *bios = flash->virtual_memory; - writeb(0xAA, bios + 0xAAA); - writeb(0x55, bios + 0x555); - writeb(0x80, bios + 0xAAA); + chip_writeb(0xAA, bios + 0xAAA); + chip_writeb(0x55, bios + 0x555); + chip_writeb(0x80, bios + 0xAAA); - writeb(0xAA, bios + 0xAAA); - writeb(0x55, bios + 0x555); - writeb(0x10, bios + 0xAAA); + chip_writeb(0xAA, bios + 0xAAA); + chip_writeb(0x55, bios + 0x555); + chip_writeb(0x10, bios + 0xAAA); myusec_delay(10); toggle_ready_jedec(bios); @@ -104,14 +104,14 @@ int block_erase_m29f400bt(volatile uint8_t *bios, volatile uint8_t *dst) { - writeb(0xAA, bios + 0xAAA); - writeb(0x55, bios + 0x555); - writeb(0x80, bios + 0xAAA); + chip_writeb(0xAA, bios + 0xAAA); + chip_writeb(0x55, bios + 0x555); + chip_writeb(0x80, bios + 0xAAA); - writeb(0xAA, bios + 0xAAA); - writeb(0x55, bios + 0x555); + chip_writeb(0xAA, bios + 0xAAA); + chip_writeb(0x55, bios + 0x555); //*(volatile uint8_t *) (bios + 0xAAA) = 0x10; - writeb(0x30, dst); + chip_writeb(0x30, dst); myusec_delay(10); toggle_ready_jedec(bios); Modified: trunk/util/flashrom/mx29f002.c =================================================================== --- trunk/util/flashrom/mx29f002.c 2009-03-06 19:54:15 UTC (rev 3983) +++ trunk/util/flashrom/mx29f002.c 2009-03-06 22:26:00 UTC (rev 3984) @@ -27,14 +27,14 @@ volatile uint8_t *bios = flash->virtual_memory; uint8_t id1, id2; - writeb(0xAA, bios + 0x5555); - writeb(0x55, bios + 0x2AAA); - writeb(0x90, bios + 0x5555); + chip_writeb(0xAA, bios + 0x5555); + chip_writeb(0x55, bios + 0x2AAA); + chip_writeb(0x90, bios + 0x5555); - id1 = readb(bios); - id2 = readb(bios + 0x01); + id1 = chip_readb(bios); + id2 = chip_readb(bios + 0x01); - writeb(0xF0, bios); + chip_writeb(0xF0, bios); myusec_delay(10); @@ -49,13 +49,13 @@ { volatile uint8_t *bios = flash->virtual_memory; - writeb(0xF0, bios + 0x555); - writeb(0xAA, bios + 0x555); - writeb(0x55, bios + 0x2AA); - writeb(0x80, bios + 0x555); - writeb(0xAA, bios + 0x555); - writeb(0x55, bios + 0x2AA); - writeb(0x10, bios + 0x555); + chip_writeb(0xF0, bios + 0x555); + chip_writeb(0xAA, bios + 0x555); + chip_writeb(0x55, bios + 0x2AA); + chip_writeb(0x80, bios + 0x555); + chip_writeb(0xAA, bios + 0x555); + chip_writeb(0x55, bios + 0x2AA); + chip_writeb(0x10, bios + 0x555); myusec_delay(100); toggle_ready_jedec(bios); @@ -65,12 +65,12 @@ #if 0 toggle_ready_jedec(bios); - writeb(0x30, bios + 0x0ffff); - writeb(0x30, bios + 0x1ffff); - writeb(0x30, bios + 0x2ffff); - writeb(0x30, bios + 0x37fff); - writeb(0x30, bios + 0x39fff); - writeb(0x30, bios + 0x3bfff); + chip_writeb(0x30, bios + 0x0ffff); + chip_writeb(0x30, bios + 0x1ffff); + chip_writeb(0x30, bios + 0x2ffff); + chip_writeb(0x30, bios + 0x37fff); + chip_writeb(0x30, bios + 0x39fff); + chip_writeb(0x30, bios + 0x3bfff); #endif return 0; @@ -83,7 +83,7 @@ volatile uint8_t *bios = flash->virtual_memory; volatile uint8_t *dst = bios; - writeb(0xF0, bios); + chip_writeb(0xF0, bios); myusec_delay(10); erase_29f002(flash); //*bios = 0xF0; @@ -93,10 +93,10 @@ /* write to the sector */ if ((i & 0xfff) == 0) printf("address: 0x%08lx", (unsigned long)i); - writeb(0xAA, bios + 0x5555); - writeb(0x55, bios + 0x2AAA); - writeb(0xA0, bios + 0x5555); - writeb(*buf++, dst++); + chip_writeb(0xAA, bios + 0x5555); + chip_writeb(0x55, bios + 0x2AAA); + chip_writeb(0xA0, bios + 0x5555); + chip_writeb(*buf++, dst++); /* wait for Toggle bit ready */ toggle_ready_jedec(dst); Modified: trunk/util/flashrom/pm49fl00x.c =================================================================== --- trunk/util/flashrom/pm49fl00x.c 2009-03-06 19:54:15 UTC (rev 3983) +++ trunk/util/flashrom/pm49fl00x.c 2009-03-06 22:26:00 UTC (rev 3984) @@ -35,7 +35,7 @@ if (block_size == 16384 && i % 2) continue; - writeb(bits, bios + (i * block_size) + 2); + chip_writeb(bits, bios + (i * block_size) + 2); } } Modified: trunk/util/flashrom/sharplhf00l04.c =================================================================== --- trunk/util/flashrom/sharplhf00l04.c 2009-03-06 19:54:15 UTC (rev 3983) +++ trunk/util/flashrom/sharplhf00l04.c 2009-03-06 22:26:00 UTC (rev 3984) @@ -41,23 +41,23 @@ #if 0 /* Enter ID mode */ - writeb(0xAA, bios + 0x5555); - writeb(0x55, bios + 0x2AAA); - writeb(0x90, bios + 0x5555); + chip_writeb(0xAA, bios + 0x5555); + chip_writeb(0x55, bios + 0x2AAA); + chip_writeb(0x90, bios + 0x5555); #endif - writeb(0xff, bios); + chip_writeb(0xff, bios); myusec_delay(10); - writeb(0x90, bios); + chip_writeb(0x90, bios); myusec_delay(10); - id1 = readb(bios); - id2 = readb(bios + 0x01); + id1 = chip_readb(bios); + id2 = chip_readb(bios + 0x01); /* Leave ID mode */ - writeb(0xAA, bios + 0x5555); - writeb(0x55, bios + 0x2AAA); - writeb(0xF0, bios + 0x5555); + chip_writeb(0xAA, bios + 0x5555); + chip_writeb(0x55, bios + 0x2AAA); + chip_writeb(0xF0, bios + 0x5555); myusec_delay(10); @@ -76,25 +76,25 @@ uint8_t status; uint8_t id1, id2; - writeb(0x70, bios); - if ((readb(bios) & 0x80) == 0) { // it's busy - while ((readb(bios) & 0x80) == 0) ; + chip_writeb(0x70, bios); + if ((chip_readb(bios) & 0x80) == 0) { // it's busy + while ((chip_readb(bios) & 0x80) == 0) ; } - status = readb(bios); + status = chip_readb(bios); // put another command to get out of status register mode - writeb(0x90, bios); + chip_writeb(0x90, bios); myusec_delay(10); - id1 = readb(bios); - id2 = readb(bios + 0x01); + id1 = chip_readb(bios); + id2 = chip_readb(bios + 0x01); // this is needed to jam it out of "read id" mode - writeb(0xAA, bios + 0x5555); - writeb(0x55, bios + 0x2AAA); - writeb(0xF0, bios + 0x5555); + chip_writeb(0xAA, bios + 0x5555); + chip_writeb(0x55, bios + 0x2AAA); + chip_writeb(0xF0, bios + 0x5555); return status; } @@ -106,19 +106,19 @@ uint8_t status; // clear status register - writeb(0x50, bios); + chip_writeb(0x50, bios); printf("Erase at %p\n", bios); status = wait_lhf00l04(flash->virtual_memory); print_lhf00l04_status(status); // clear write protect printf("write protect is at %p\n", (wrprotect)); - printf("write protect is 0x%x\n", readb(wrprotect)); - writeb(0, wrprotect); - printf("write protect is 0x%x\n", readb(wrprotect)); + printf("write protect is 0x%x\n", chip_readb(wrprotect)); + chip_writeb(0, wrprotect); + printf("write protect is 0x%x\n", chip_readb(wrprotect)); // now start it - writeb(0x20, bios); - writeb(0xd0, bios); + chip_writeb(0x20, bios); + chip_writeb(0xd0, bios); myusec_delay(10); // now let's see what the register is status = wait_lhf00l04(flash->virtual_memory); @@ -149,8 +149,8 @@ for (i = 0; i < page_size; i++) { /* transfer data from source to destination */ - writeb(0x40, dst); - writeb(*src++, dst++); + chip_writeb(0x40, dst); + chip_writeb(*src++, dst++); wait_lhf00l04(bios); } } @@ -163,7 +163,7 @@ volatile uint8_t *bios = flash->virtual_memory; erase_lhf00l04(flash); - if (readb(bios) != 0xff) { + if (chip_readb(bios) != 0xff) { printf("ERASE FAILED!\n"); return -1; } Modified: trunk/util/flashrom/sst28sf040.c =================================================================== --- trunk/util/flashrom/sst28sf040.c 2009-03-06 19:54:15 UTC (rev 3983) +++ trunk/util/flashrom/sst28sf040.c 2009-03-06 22:26:00 UTC (rev 3984) @@ -34,33 +34,33 @@ { uint8_t tmp; - tmp = readb(bios + 0x1823); - tmp = readb(bios + 0x1820); - tmp = readb(bios + 0x1822); - tmp = readb(bios + 0x0418); - tmp = readb(bios + 0x041B); - tmp = readb(bios + 0x0419); - tmp = readb(bios + 0x040A); + tmp = chip_readb(bios + 0x1823); + tmp = chip_readb(bios + 0x1820); + tmp = chip_readb(bios + 0x1822); + tmp = chip_readb(bios + 0x0418); + tmp = chip_readb(bios + 0x041B); + tmp = chip_readb(bios + 0x0419); + tmp = chip_readb(bios + 0x040A); } static __inline__ void unprotect_28sf040(volatile uint8_t *bios) { uint8_t tmp; - tmp = readb(bios + 0x1823); - tmp = readb(bios + 0x1820); - tmp = readb(bios + 0x1822); - tmp = readb(bios + 0x0418); - tmp = readb(bios + 0x041B); - tmp = readb(bios + 0x0419); - tmp = readb(bios + 0x041A); + tmp = chip_readb(bios + 0x1823); + tmp = chip_readb(bios + 0x1820); + tmp = chip_readb(bios + 0x1822); + tmp = chip_readb(bios + 0x0418); + tmp = chip_readb(bios + 0x041B); + tmp = chip_readb(bios + 0x0419); + tmp = chip_readb(bios + 0x041A); } static __inline__ int erase_sector_28sf040(volatile uint8_t *bios, unsigned long address) { - writeb(AUTO_PG_ERASE1, bios); - writeb(AUTO_PG_ERASE2, bios + address); + chip_writeb(AUTO_PG_ERASE1, bios); + chip_writeb(AUTO_PG_ERASE2, bios + address); /* wait for Toggle bit ready */ toggle_ready_jedec(bios); @@ -83,8 +83,8 @@ continue; } /*issue AUTO PROGRAM command */ - writeb(AUTO_PGRM, dst); - writeb(*src++, dst++); + chip_writeb(AUTO_PGRM, dst); + chip_writeb(*src++, dst++); /* wait for Toggle bit ready */ toggle_ready_jedec(bios); @@ -98,16 +98,16 @@ volatile uint8_t *bios = flash->virtual_memory; uint8_t id1, id2; - writeb(RESET, bios); + chip_writeb(RESET, bios); myusec_delay(10); - writeb(READ_ID, bios); + chip_writeb(READ_ID, bios); myusec_delay(10); - id1 = readb(bios); + id1 = chip_readb(bios); myusec_delay(10); - id2 = readb(bios + 0x01); + id2 = chip_readb(bios + 0x01); - writeb(RESET, bios); + chip_writeb(RESET, bios); myusec_delay(10); printf_debug("%s: id1 0x%02x, id2 0x%02x\n", __FUNCTION__, id1, id2); @@ -122,8 +122,8 @@ volatile uint8_t *bios = flash->virtual_memory; unprotect_28sf040(bios); - writeb(CHIP_ERASE, bios); - writeb(CHIP_ERASE, bios); + chip_writeb(CHIP_ERASE, bios); + chip_writeb(CHIP_ERASE, bios); protect_28sf040(bios); myusec_delay(10); Modified: trunk/util/flashrom/sst49lfxxxc.c =================================================================== --- trunk/util/flashrom/sst49lfxxxc.c 2009-03-06 19:54:15 UTC (rev 3983) +++ trunk/util/flashrom/sst49lfxxxc.c 2009-03-06 22:26:00 UTC (rev 3984) @@ -50,20 +50,20 @@ //printf("bios=0x%08lx\n", (unsigned long)bios); for (i = 0; left > 65536; i++, left -= 65536) { //printf("lockbits at address=0x%08lx is 0x%01x\n", (unsigned long)0xFFC00000 - size + (i * 65536) + 2, *(bios + (i * 65536) + 2) ); - writeb(bits, bios + (i * 65536) + 2); + chip_writeb(bits, bios + (i * 65536) + 2); } address = i * 65536; //printf("lockbits at address=0x%08lx is 0x%01x\n", (unsigned long)0xFFc00000 - size + address + 2, *(bios + address + 2) ); - writeb(bits, bios + address + 2); + chip_writeb(bits, bios + address + 2); address += 32768; //printf("lockbits at address=0x%08lx is 0x%01x\n", (unsigned long)0xFFc00000 - size + address + 2, *(bios + address + 2) ); - writeb(bits, bios + address + 2); + chip_writeb(bits, bios + address + 2); address += 8192; //printf("lockbits at address=0x%08lx is 0x%01x\n", (unsigned long)0xFFc00000 - size + address + 2, *(bios + address + 2) ); - writeb(bits, bios + address + 2); + chip_writeb(bits, bios + address + 2); address += 8192; //printf("lockbits at address=0x%08lx is 0x%01x\n", (unsigned long)0xFFc00000 - size + address + 2, *(bios + address + 2) ); - writeb(bits, bios + address + 2); + chip_writeb(bits, bios + address + 2); return 0; } @@ -73,14 +73,14 @@ { unsigned char status; - writeb(SECTOR_ERASE, bios); - writeb(ERASE, bios + address); + chip_writeb(SECTOR_ERASE, bios); + chip_writeb(ERASE, bios + address); do { - status = readb(bios); + status = chip_readb(bios); if (status & (STATUS_ESS | STATUS_BPS)) { printf("sector erase FAILED at address=0x%08lx status=0x%01x\n", (unsigned long)bios + address, status); - writeb(CLEAR_STATUS, bios); + chip_writeb(CLEAR_STATUS, bios); return (-1); } } while (!(status & STATUS_WSMS)); @@ -96,7 +96,7 @@ int i; unsigned char status; - writeb(CLEAR_STATUS, bios); + chip_writeb(CLEAR_STATUS, bios); for (i = 0; i < page_size; i++) { /* transfer data from source to destination */ if (*src == 0xFF) { @@ -105,14 +105,14 @@ continue; } /*issue AUTO PROGRAM command */ - writeb(AUTO_PGRM, bios); - writeb(*src++, dst++); + chip_writeb(AUTO_PGRM, bios); + chip_writeb(*src++, dst++); do { - status = readb(bios); + status = chip_readb(bios); if (status & (STATUS_ESS | STATUS_BPS)) { printf("sector write FAILED at address=0x%08lx status=0x%01x\n", (unsigned long)dst, status); - writeb(CLEAR_STATUS, bios); + chip_writeb(CLEAR_STATUS, bios); return (-1); } } while (!(status & STATUS_WSMS)); @@ -127,13 +127,13 @@ uint8_t id1, id2; - writeb(RESET, bios); + chip_writeb(RESET, bios); - writeb(READ_ID, bios); - id1 = readb(bios); - id2 = readb(bios + 0x01); + chip_writeb(READ_ID, bios); + id1 = chip_readb(bios); + id2 = chip_readb(bios + 0x01); - writeb(RESET, bios); + chip_writeb(RESET, bios); printf_debug("%s: id1 0x%02x, id2 0x%02x\n", __FUNCTION__, id1, id2); @@ -157,7 +157,7 @@ if (erase_sector_49lfxxxc(bios, i) != 0) return (-1); - writeb(RESET, bios); + chip_writeb(RESET, bios); return 0; } @@ -183,7 +183,7 @@ } printf("\n"); - writeb(RESET, bios); + chip_writeb(RESET, bios); return 0; } Modified: trunk/util/flashrom/sst_fwhub.c =================================================================== --- trunk/util/flashrom/sst_fwhub.c 2009-03-06 19:54:15 UTC (rev 3983) +++ trunk/util/flashrom/sst_fwhub.c 2009-03-06 22:26:00 UTC (rev 3984) @@ -51,7 +51,7 @@ volatile uint8_t *wrprotect = flash->virtual_registers + offset + 2; // clear write protect - writeb(0, wrprotect); + chip_writeb(0, wrprotect); erase_block_jedec(flash->virtual_memory, offset); toggle_ready_jedec(flash->virtual_memory); Modified: trunk/util/flashrom/stm50flw0x0x.c =================================================================== --- trunk/util/flashrom/stm50flw0x0x.c 2009-03-06 19:54:15 UTC (rev 3983) +++ trunk/util/flashrom/stm50flw0x0x.c 2009-03-06 22:26:00 UTC (rev 3984) @@ -33,9 +33,9 @@ void protect_stm50flw0x0x(volatile uint8_t *bios) { - writeb(0xAA, bios + 0x5555); - writeb(0x55, bios + 0x2AAA); - writeb(0xA0, bios + 0x5555); + chip_writeb(0xAA, bios + 0x5555); + chip_writeb(0x55, bios + 0x2AAA); + chip_writeb(0xA0, bios + 0x5555); usleep(200); } @@ -47,37 +47,37 @@ uint32_t largeid1, largeid2; /* Issue JEDEC Product ID Entry command */ - writeb(0xAA, bios + 0x5555); + chip_writeb(0xAA, bios + 0x5555); myusec_delay(10); - writeb(0x55, bios + 0x2AAA); + chip_writeb(0x55, bios + 0x2AAA); myusec_delay(10); - writeb(0x90, bios + 0x5555); + chip_writeb(0x90, bios + 0x5555); myusec_delay(40); /* Read product ID */ - id1 = readb(bios); - id2 = readb(bios + 0x01); + id1 = chip_readb(bios); + id2 = chip_readb(bios + 0x01); largeid1 = id1; largeid2 = id2; /* Check if it is a continuation ID, this should be a while loop. */ if (id1 == 0x7F) { largeid1 <<= 8; - id1 = readb(bios + 0x100); + id1 = chip_readb(bios + 0x100); largeid1 |= id1; } if (id2 == 0x7F) { largeid2 <<= 8; - id2 = readb(bios + 0x101); + id2 = chip_readb(bios + 0x101); largeid2 |= id2; } /* Issue JEDEC Product ID Exit command */ - writeb(0xAA, bios + 0x5555); + chip_writeb(0xAA, bios + 0x5555); myusec_delay(10); - writeb(0x55, bios + 0x2AAA); + chip_writeb(0x55, bios + 0x2AAA); myusec_delay(10); - writeb(0xF0, bios + 0x5555); + chip_writeb(0xF0, bios + 0x5555); myusec_delay(40); printf_debug("%s: id1 0x%02x, id2 0x%02x\n", __FUNCTION__, largeid1, @@ -96,21 +96,21 @@ uint8_t id1; // id2; - writeb(0x70, bios); - if ((readb(bios) & 0x80) == 0) { // it's busy - while ((readb(bios) & 0x80) == 0) ; + chip_writeb(0x70, bios); + if ((chip_readb(bios) & 0x80) == 0) { // it's busy + while ((chip_readb(bios) & 0x80) == 0) ; } // put another command to get out of status register mode - writeb(0x90, bios); + chip_writeb(0x90, bios); myusec_delay(10); - id1 = readb(bios); + id1 = chip_readb(bios); // this is needed to jam it out of "read id" mode - writeb(0xAA, bios + 0x5555); - writeb(0x55, bios + 0x2AAA); - writeb(0xF0, bios + 0x5555); + chip_writeb(0xAA, bios + 0x5555); + chip_writeb(0x55, bios + 0x2AAA); + chip_writeb(0xF0, bios + 0x5555); } /* @@ -142,8 +142,8 @@ // unlock each 4k-sector for (j = 0; j < 0x10000; j += 0x1000) { printf_debug("unlocking at 0x%x\n", offset + j); - writeb(unlock_sector, flash_addr + offset + j); - if (readb(flash_addr + offset + j) != unlock_sector) { + chip_writeb(unlock_sector, flash_addr + offset + j); + if (chip_readb(flash_addr + offset + j) != unlock_sector) { printf("Cannot unlock sector @ 0x%x\n", offset + j); return -1; @@ -151,8 +151,8 @@ } } else { printf_debug("unlocking at 0x%x\n", offset); - writeb(unlock_sector, flash_addr + offset); - if (readb(flash_addr + offset) != unlock_sector) { + chip_writeb(unlock_sector, flash_addr + offset); + if (chip_readb(flash_addr + offset) != unlock_sector) { printf("Cannot unlock sector @ 0x%x\n", offset); return -1; } @@ -167,17 +167,17 @@ int j; // clear status register - writeb(0x50, bios); + chip_writeb(0x50, bios); printf_debug("Erase at %p\n", bios); // now start it - writeb(0x20, bios); - writeb(0xd0, bios); + chip_writeb(0x20, bios); + chip_writeb(0xd0, bios); myusec_delay(10); wait_stm50flw0x0x(flash->virtual_memory); for (j = 0; j < flash->page_size; j++) { - if (readb(bios + j) != 0xFF) { + if (chip_readb(bios + j) != 0xFF) { printf("Erase failed at 0x%x\n", offset + j); return -1; } @@ -197,8 +197,8 @@ /* transfer data from source to destination */ for (i = 0; i < page_size; i++) { - writeb(0x40, dst); - writeb(*src++, dst++); + chip_writeb(0x40, dst); + chip_writeb(*src++, dst++); wait_stm50flw0x0x(bios); } @@ -210,7 +210,7 @@ dst = d; src = s; for (i = 0; i < page_size; i++) { - if (readb(dst) != *src) { + if (chip_readb(dst) != *src) { rc = -1; break; } Modified: trunk/util/flashrom/w29ee011.c =================================================================== --- trunk/util/flashrom/w29ee011.c 2009-03-06 19:54:15 UTC (rev 3983) +++ trunk/util/flashrom/w29ee011.c 2009-03-06 22:26:00 UTC (rev 3984) @@ -37,29 +37,29 @@ } /* Issue JEDEC Product ID Entry command */ - writeb(0xAA, bios + 0x5555); + chip_writeb(0xAA, bios + 0x5555); myusec_delay(10); - writeb(0x55, bios + 0x2AAA); + chip_writeb(0x55, bios + 0x2AAA); myusec_delay(10); - writeb(0x80, bios + 0x5555); + chip_writeb(0x80, bios + 0x5555); myusec_delay(10); - writeb(0xAA, bios + 0x5555); + chip_writeb(0xAA, bios + 0x5555); myusec_delay(10); - writeb(0x55, bios + 0x2AAA); + chip_writeb(0x55, bios + 0x2AAA); myusec_delay(10); - writeb(0x60, bios + 0x5555); + chip_writeb(0x60, bios + 0x5555); myusec_delay(10); /* Read product ID */ - id1 = readb(bios); - id2 = readb(bios + 0x01); + id1 = chip_readb(bios); + id2 = chip_readb(bios + 0x01); /* Issue JEDEC Product ID Exit command */ - writeb(0xAA, bios + 0x5555); + chip_writeb(0xAA, bios + 0x5555); myusec_delay(10); - writeb(0x55, bios + 0x2AAA); + chip_writeb(0x55, bios + 0x2AAA); myusec_delay(10); - writeb(0xF0, bios + 0x5555); + chip_writeb(0xF0, bios + 0x5555); myusec_delay(10); printf_debug("%s: id1 0x%02x, id2 0x%02x\n", __FUNCTION__, id1, id2); Modified: trunk/util/flashrom/w39v040c.c =================================================================== --- trunk/util/flashrom/w39v040c.c 2009-03-06 19:54:15 UTC (rev 3983) +++ trunk/util/flashrom/w39v040c.c 2009-03-06 22:26:00 UTC (rev 3984) @@ -26,22 +26,22 @@ volatile uint8_t *bios = flash->virtual_memory; uint8_t id1, id2, lock; - writeb(0xAA, bios + 0x5555); + chip_writeb(0xAA, bios + 0x5555); myusec_delay(10); - writeb(0x55, bios + 0x2AAA); + chip_writeb(0x55, bios + 0x2AAA); myusec_delay(10); - writeb(0x90, bios + 0x5555); + chip_writeb(0x90, bios + 0x5555); myusec_delay(10); - id1 = readb(bios); - id2 = readb(bios + 1); - lock = readb(bios + 0xfff2); + id1 = chip_readb(bios); + id2 = chip_readb(bios + 1); + lock = chip_readb(bios + 0xfff2); - writeb(0xAA, bios + 0x5555); + chip_writeb(0xAA, bios + 0x5555); myusec_delay(10); - writeb(0x55, bios + 0x2AAA); + chip_writeb(0x55, bios + 0x2AAA); myusec_delay(10); - writeb(0xF0, bios + 0x5555); + chip_writeb(0xF0, bios + 0x5555); myusec_delay(40); printf_debug("%s: id1 0x%02x, id2 0x%02x", __func__, id1, id2); Modified: trunk/util/flashrom/w39v080fa.c =================================================================== --- trunk/util/flashrom/w39v080fa.c 2009-03-06 19:54:15 UTC (rev 3983) +++ trunk/util/flashrom/w39v080fa.c 2009-03-06 22:26:00 UTC (rev 3984) @@ -27,19 +27,19 @@ uint8_t vid, did; /* Product Identification Entry */ - writeb(0xAA, bios + 0x5555); - writeb(0x55, bios + 0x2AAA); - writeb(0x90, bios + 0x5555); + chip_writeb(0xAA, bios + 0x5555); + chip_writeb(0x55, bios + 0x2AAA); + chip_writeb(0x90, bios + 0x5555); myusec_delay(10); /* Read product ID */ - vid = readb(bios); - did = readb(bios + 0x01); + vid = chip_readb(bios); + did = chip_readb(bios + 0x01); /* Product Identifixation Exit */ - writeb(0xAA, bios + 0x5555); - writeb(0x55, bios + 0x2AAA); - writeb(0xF0, bios + 0x5555); + chip_writeb(0xAA, bios + 0x5555); + chip_writeb(0x55, bios + 0x2AAA); + chip_writeb(0xF0, bios + 0x5555); myusec_delay(10); printf_debug("%s: vid 0x%x, did 0x%x\n", __FUNCTION__, vid, did); @@ -58,16 +58,16 @@ uint8_t locking; printf_debug("Trying to unlock block @0x%08x = 0x%02x\n", offset, - readb(wrprotect)); + chip_readb(wrprotect)); - locking = readb(wrprotect); + locking = chip_readb(wrprotect); switch (locking & 0x7) { case 0: printf_debug("Full Access.\n"); return 0; case 1: printf_debug("Write Lock (Default State).\n"); - writeb(0, wrprotect); + chip_writeb(0, wrprotect); return 0; case 2: printf_debug("Locked Open (Full Access, Lock Down).\n"); @@ -77,11 +77,11 @@ return -1; case 4: printf_debug("Read Lock.\n"); - writeb(0, wrprotect); + chip_writeb(0, wrprotect); return 0; case 5: printf_debug("Read/Write Lock.\n"); - writeb(0, wrprotect); + chip_writeb(0, wrprotect); return 0; case 6: fprintf(stderr, "Error: Read Lock, Locked Down.\n"); @@ -106,18 +106,18 @@ */ /* Product Identification Entry */ - writeb(0xAA, bios + 0x5555); - writeb(0x55, bios + 0x2AAA); - writeb(0x90, bios + 0x5555); + chip_writeb(0xAA, bios + 0x5555); + chip_writeb(0x55, bios + 0x2AAA); + chip_writeb(0x90, bios + 0x5555); myusec_delay(10); /* Read Hardware Lock Bits */ - locking = readb(bios + 0xffff2); + locking = chip_readb(bios + 0xffff2); /* Product Identification Exit */ - writeb(0xAA, bios + 0x5555); - writeb(0x55, bios + 0x2AAA); - writeb(0xF0, bios + 0x5555); + chip_writeb(0xAA, bios + 0x5555); + chip_writeb(0x55, bios + 0x2AAA); + chip_writeb(0xF0, bios + 0x5555); myusec_delay(10); printf_debug("Lockout bits:\n"); @@ -151,13 +151,13 @@ printf("0x%08x\b\b\b\b\b\b\b\b\b\b", sector); /* Sector Erase */ - writeb(0xAA, bios + 0x5555); - writeb(0x55, bios + 0x2AAA); - writeb(0x80, bios + 0x5555); + chip_writeb(0xAA, bios + 0x5555); + chip_writeb(0x55, bios + 0x2AAA); + chip_writeb(0x80, bios + 0x5555); - writeb(0xAA, bios + 0x5555); - writeb(0x55, bios + 0x2AAA); - writeb(0x30, bios + sector); + chip_writeb(0xAA, bios + 0x5555); + chip_writeb(0x55, bios + 0x2AAA); + chip_writeb(0x30, bios + sector); /* wait for Toggle bit ready */ toggle_ready_jedec(bios);

1 0

[patch] ACPI support on M57SLI
by Harald Gutmann 06 Mar '09

06 Mar '09

Hello, the result of the past two/three days work/interest on coreboot is a big part of ACPI support on M57SLI which works on my revision (v2). Soft-Power-Off works, and that's what i missed really hard in coreboot for m57sli. The other parts of ACPI support should work (mostly) also fine. (except setting up MMCONFIG in acpi_fill_mcfg, and the powernow features which hopefully can be done with the recently commited patch "AMD boards to use new Power Now infrastructure" from Rudolf Marek). I think i'll get the time this weekend or at the beginning of the next week to address those remaining problems. In the mean time i hope that someone can test the code which i didn't originally write, but modified, to work at M57SLI. For myself I own an M57SLI with hardware rev.2, maybe Ward can test if that code will work on v1 too. One other "problem" with the actual code is, that most of the interesting parts are hardcoded (numbers where variables should be/could be). The attached patch is quite complete, except the problems mentioned above and the copyright informations are missing in the patch. This one is just for testing, and i'll try to get the remaining problems fixed, and i also will add copyright information when the work is finally done. I think it's not the time to add this patch into svn because of the above mentioned missing parts. But it's a great time to test and enjoy this patch. Kind regards, Harald Gutmann

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coreboot March 2009