Kevin O'Connor wrote:
On Fri, Mar 06, 2009 at 05:18:15PM -0800, Joe Julian wrote:
I find this patch http://www.coreboot.org/pipermail/coreboot/2009-February/045068.html
Yes. You need to apply that patch. (Please confirm your machine has at least 1GiB of memory.)
The next thing you need to do is setup your SeaBIOS src/config.h. It should have CONFIG_COREBOOT set, CONFIG_DEBUG_SERIAL set, CONFIG_OPTIONROMS_DEPLOYED unset, and OPTIONROM_BDF/MEM_* set. I think you've already done this.
Then, one compiles the above, and flashes the chip.
If you're not seeing the correct output, something must be wrong. You'll need to capture the serial output and send the log. With the log, we'll be able to figure out what went wrong.
Thanks for your help. I can't directly apply that patch because it's been superseded by this one http://tracker.coreboot.org/trac/coreboot/changeset/3960 which works for me so far, with the following changes. There's a little bit of workaround there, as I don't know how to patch the HAVE_HIGH_TABLES into src/northbridge/amd/amdfam10/northbridge.c
Here's a link to my log: http://www.privatepaste.com/04ilD2DoPH
And yes, the machine has more than 1Gb. It has 8.
--- src/arch/i386/boot/tables.c (revision 3981) +++ src/arch/i386/boot/tables.c (working copy) @@ -58,7 +58,7 @@ }
#if HAVE_HIGH_TABLES == 1 -uint64_t high_tables_base = 0; +uint64_t high_tables_base = 0x3dff0000; uint64_t high_tables_size; #endif
@@ -188,11 +187,12 @@ rom_table_start, rom_table_end); #endif
+#if 0 /* The coreboot table must be in 0-4K or 960K-1M */ write_coreboot_table(low_table_start, low_table_end, rom_table_start, rom_table_end);
-#if 0 && HAVE_HIGH_TABLES == 1 +#else // HAVE_HIGH_TABLES == 1 /* This is currently broken and should be severely refactored. Ideally * we only have a pointer to the coreboot table in the low memory, so * anyone can find the real position. @@ -205,8 +205,8 @@ * corrupted */ if (high_tables_base) { - write_coreboot_table(high_table_start, high_table_end, - high_table_start, high_table_end); + write_coreboot_table(low_table_start, low_table_end, + high_table_start, high_table_end); } #endif
--- src/mainboard/tyan/s2912_fam10/mainboard.c (revision 3981) +++ src/mainboard/tyan/s2912_fam10/mainboard.c (working copy) @@ -24,6 +24,7 @@ #include <device/pci.h> #include <device/pci_ids.h> #include <device/pci_ops.h> +#include <boot/tables.h> #include "chip.h"
#if CONFIG_CHIP_NAME == 1 @@ -31,3 +32,15 @@ CHIP_NAME("Tyan S2912 Mainboard (Family 10)") }; #endif +/* in arch/i386/boot/tables.c */ +extern uint64_t high_tables_base, high_tables_size; + +int add_mainboard_resources(struct lb_memory *mem) +{ +#if HAVE_HIGH_TABLES == 1 + printk_debug("Adding high table area\n"); + lb_add_memory_range(mem, LB_MEM_TABLE, + high_tables_base, high_tables_size); +#endif +return 0; +} Index: src/mainboard/tyan/s2912_fam10/Options.lb =================================================================== --- src/mainboard/tyan/s2912_fam10/Options.lb (revision 3981) +++ src/mainboard/tyan/s2912_fam10/Options.lb (working copy) @@ -22,6 +22,8 @@ uses HAVE_MP_TABLE uses HAVE_PIRQ_TABLE uses HAVE_ACPI_TABLES +uses HAVE_MAINBOARD_RESOURCES +uses HAVE_HIGH_TABLES uses ACPI_SSDTX_NUM uses USE_FALLBACK_IMAGE uses USE_FAILOVER_IMAGE @@ -166,6 +168,8 @@
## ACPI tables will be included default HAVE_ACPI_TABLES=0 +default HAVE_MAINBOARD_RESOURCES=0 +default HAVE_HIGH_TABLES=1 ## extra SSDT num default ACPI_SSDTX_NUM=31
@@ -211,8 +215,8 @@ #default HW_MEM_HOLE_SIZE_AUTO_INC=1
#VGA Console -default CONFIG_CONSOLE_VGA=1 -default CONFIG_PCI_ROM_RUN=1 +default CONFIG_CONSOLE_VGA=0 +default CONFIG_PCI_ROM_RUN=0
#default CONFIG_USBDEBUG_DIRECT=1
On Fri, Mar 06, 2009 at 09:46:01PM -0800, Joe Julian wrote:
Kevin O'Connor wrote:
If you're not seeing the correct output, something must be wrong. You'll need to capture the serial output and send the log. With the log, we'll be able to figure out what went wrong.
Thanks for your help. I can't directly apply that patch because it's been superseded by this one http://tracker.coreboot.org/trac/coreboot/changeset/3960 which works for me so far, with the following changes. There's a little bit of workaround there, as I don't know how to patch the HAVE_HIGH_TABLES into src/northbridge/amd/amdfam10/northbridge.c
Here's a link to my log: http://www.privatepaste.com/04ilD2DoPH
Okay. Looks like your tables are being relocated and SeaBIOS is finding them properly. It also looks like gPXE is succesfully running.
Unfortunately, your coreboot mainboard doesn't have any ACPI definitions. (So, the problem isn't SeaBIOS not finding it - instead coreboot is not providing it.)
Extending coreboot to provide acpi definitions is a bit out of my expertise. Someone from the list should be able to suggest a starting point. You are getting very close though.
-Kevin
-
Joe Julian -
Kevin O'Connor