coreboot March 2009

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316 discussions

r4019 - trunk/coreboot-v2/src/config
by svn＠coreboot.org 19 Mar '09

19 Mar '09

Author: stepan Date: 2009-03-19 02:30:16 +0100 (Thu, 19 Mar 2009) New Revision: 4019 Modified: trunk/coreboot-v2/src/config/Options.lb Log: fix the following warning on all boards that don't have PIRQ_ROUTE enabled In file included from coreboot-v2-4017//src/arch/i386/boot/pirq_routing.c:2: coreboot-v2-4017/src/arch/i386/include/arch/pirq_routing.h:45:5: warning: "PIRQ_ROUTE" is not defined coreboot-v2-4017//src/arch/i386/boot/pirq_routing.c:103:6: warning: "PIRQ_ROUTE" is not defined Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/coreboot-v2/src/config/Options.lb =================================================================== --- trunk/coreboot-v2/src/config/Options.lb 2009-03-19 01:13:01 UTC (rev 4018) +++ trunk/coreboot-v2/src/config/Options.lb 2009-03-19 01:30:16 UTC (rev 4019) @@ -738,7 +738,7 @@ end define PIRQ_ROUTE default 0 - export used + export always comment "Define if we have a PIRQ table and want routing IRQs" end define IRQ_SLOT_COUNT

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warnings about shadowed variables
by Stefan Reinauer 19 Mar '09

19 Mar '09

Hi, besides the Ubuntu breakage, commit 4000 brought a couple of interesting warnings that were not available before, such as those about the shadowing of variables. This happens when a global variable is "overwritten" with a local definition so that the global version is no longer available in that scope, such as this one: coreboot-v2-4017/src/arch/i386/boot/multiboot.c: In function 'write_multiboot_info': coreboot-v2-4017/src/arch/i386/boot/multiboot.c:81: warning: declaration of 'mbi' shadows a global declaration coreboot-v2-4017/src/arch/i386/boot/multiboot.c:27: warning: shadowed declaration is here If you see these warnings in your builds, please attempt to fix them as they might mean that your code is accessing the wrong variables.. Stefan -- coresystems GmbH • Brahmsstr. 16 • D-79104 Freiburg i. Br. Tel.: +49 761 7668825 • Fax: +49 761 7664613 Email: info(a)coresystems.de • http://www.coresystems.de/ Registergericht: Amtsgericht Freiburg • HRB 7656 Geschäftsführer: Stefan Reinauer • Ust-IdNr.: DE245674866

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r4018 - trunk/coreboot-v2/src/cpu/ppc/ppc7xx
by svn＠coreboot.org 19 Mar '09

19 Mar '09

Author: stepan Date: 2009-03-19 02:13:01 +0100 (Thu, 19 Mar 2009) New Revision: 4018 Modified: trunk/coreboot-v2/src/cpu/ppc/ppc7xx/Config.lb Log: fix totalimpact briq compilation. the target had a cpu specific and a mainboard specific clock.c. Since no other target uses the same cpu, I commented out the CPU's clock.c. Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/coreboot-v2/src/cpu/ppc/ppc7xx/Config.lb =================================================================== --- trunk/coreboot-v2/src/cpu/ppc/ppc7xx/Config.lb 2009-03-18 16:25:34 UTC (rev 4017) +++ trunk/coreboot-v2/src/cpu/ppc/ppc7xx/Config.lb 2009-03-19 01:13:01 UTC (rev 4018) @@ -17,9 +17,11 @@ initinclude "FAMILY_INIT" cpu/ppc/ppc7xx/ppc7xx.inc -object clock.o +# Only TotalImpact Briq uses the ppc7xx and it brings its own clock.o +# so we comment this out for now: +# object clock.o object cache.S -initobject clock.o +#initobject clock.o initobject cache.S dir /cpu/simple_init

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Asus M2A-VM status
by Carl-Daniel Hailfinger 19 Mar '09

19 Mar '09

The Asus M2A-VM is working pretty well, but there is still lots of stuff to fix before the board is production ready. I added some info to the wiki page: http://www.coreboot.org/ASUS_M2A-VM#Other_issues Help to fix the remaining issues is appreciated. Once the MMCONFIG bug has been fixed, I plan to commit the M2A-VM as new target to the svn tree. Regards, Carl-Daniel -- http://www.hailfinger.org/

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Strange failure - help?
by Myles Watson 19 Mar '09

19 Mar '09

I have two coreboot trees. As far as I can tell they're identical. One produces working ROM images, and the other reboots when it jumps to the payload. These are the only differences from the .map files: Broken: 0000b03d A _binary_coreboot_ram_rom_size 0010b03d A _eiseg fffeb03d A _x fffeb03d D _binary_coreboot_ram_rom_end fffeb03d D _eliseg fffeb03d D _eram Works: 0000b222 A _binary_coreboot_ram_rom_size 0010b222 A _eiseg fffeb222 A _x fffeb222 D _binary_coreboot_ram_rom_end fffeb222 D _eliseg fffeb222 D _eram The broken one has a path of: /home/myles/try/buildrom-devel/work/coreboot/svn/ The working one's path is: /home/myles/buildrom-devel/work/coreboot/svn/ They were both working until yesterday. I've tried everything I can think of. I've removed the non-functional one's build directory completely. The payloads are bit-for-bit identical. The only difference in the boot log before the reboot is this line: Works: Wrote coreboot table at: 00000500 - 00000788 checksum 5385 Broken: Wrote coreboot table at: 00000500 - 0000076c checksum 4fd2 diffing the hexdump of the ROM files shows that the payload is identical. Any ideas? It is true that I have a working tree, but if I didn't I'd be hosed so I'd like to know the real cause. Thanks, Myles

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Re: [coreboot] r1145 - in coreboot-v3: arch/x86 arch/x86/intel/core2 device include lib mainboard/kontron/986lcd-m
by Pattrick Hueper 18 Mar '09

18 Mar '09

Hi, On Wed, Mar 11, 2009 at 5:17 PM, <svn(a)coreboot.org> wrote: ... > > + cpu_phase2(is_coldboot(), sysinfo); > + This breaks the qemu-x86 build for me... is_coldboot() is undefined, it is only defined in northbridge/intel/i945/reset_test.c I have changed the CFLAGS to include -g to make debugging in qemu-x86 with gdb possible, dont know if that has anything to do with it... Cheers, Patty

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build service results for r4017
by coreboot information 18 Mar '09

18 Mar '09

Dear coreboot readers! This is the automatic build system of coreboot. The developer "phueper" checked in revision 4017 to the coreboot repository. This caused the following changes: Change Log: add YABEL flag to options to decide wether access to devices other than the one yabel is running for is possible Signed-off-by: Pattrick Hueper <phueper(a)hueper.net> Tested and Acked-by: Joseph Smith <joe(a)settoplinux.org> Build Log: Compilation of totalimpact:briq is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4017&device=briq&vendor=to… If something broke during this checkin please be a pain in phueper's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

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[PATCH] YABEL support PCI accesses to other devices than the one yabel is running for
by Pattrick Hueper 18 Mar '09

18 Mar '09

Hi, Joseph and Stefan have had some fun using yabel on devices with (intel?) onboard graphics cards. We found that those devices want to read config space of other devices than the one yabel is running for. This was previously impossible. These patches introduce a yabel option CONFIG_YABEL_ACCESS_OTHER_DEVICES that when set to 1/true allows Option ROMs to find and access (read-only) other devices' config space. Both through INT1A functions and cf8/cfc IO ports. This allows the mentioned onboard graphics cards to be initialized by yabel. The two 0001 patches add the corresponding Option to Kconfig/Options.lb for v3/v2, the 0002 patch adds the functionality to yabel. Signed-off-by: Pattrick Hueper <phueper(a)hueper.net> Patty

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r1155 - coreboot-v3/util/x86emu/yabel
by svn＠coreboot.org 18 Mar '09

18 Mar '09

Author: phueper Date: 2009-03-18 17:27:01 +0100 (Wed, 18 Mar 2009) New Revision: 1155 Modified: coreboot-v3/util/x86emu/yabel/interrupt.c coreboot-v3/util/x86emu/yabel/io.c Log: "other device" support for YABEL PCI Config Space Accesses This patch makes it possible for Option ROMs to access devices other than the one YABEL is running for. This is needed for some onboard Graphics Cards Option ROMs. Signed-off-by: Pattrick Hueper <phueper(a)hueper.net> Tested and Acked-by: Joseph Smith <joe(a)settoplinux.org> Modified: coreboot-v3/util/x86emu/yabel/interrupt.c =================================================================== --- coreboot-v3/util/x86emu/yabel/interrupt.c 2009-03-18 16:26:56 UTC (rev 1154) +++ coreboot-v3/util/x86emu/yabel/interrupt.c 2009-03-18 16:27:01 UTC (rev 1155) @@ -330,6 +330,7 @@ { // function number in AX u8 bus, devfn, offs; + struct device* dev; switch (M.x86.R_AX) { case 0xb101: // Installation check @@ -341,30 +342,46 @@ break; case 0xb102: // Find PCI Device - // NOTE: we currently only allow the device to find itself... - // it SHOULD be all we ever need... // device_id in CX, vendor_id in DX // device index in SI (i.e. if multiple devices with same vendor/device id // are connected). We currently only support device index 0 + // DEBUG_PRINTF_INTR("%s(): function: %x: PCI Find Device\n", __func__, M.x86.R_AX); + /* FixME: support SI != 0 */ +#if defined(CONFIG_YABEL_PCI_ACCESS_OTHER_DEVICES) && CONFIG_YABEL_PCI_ACCESS_OTHER_DEVICES==1 +#ifdef COREBOOT_V2 + dev = dev_find_device(M.x86.R_DX, M.x86.R_CX, 0); +#else + dev = dev_find_pci_device(M.x86.R_DX, M.x86.R_CX, 0); +#endif + if (dev != 0) { + DEBUG_PRINTF_INTR + ("%s(): function %x: PCI Find Device --> 0x%04x\n", + __func__, M.x86.R_AX, M.x86.R_BX); + + M.x86.R_BH = dev->bus->secondary; + M.x86.R_BL = dev->path.pci.devfn; + M.x86.R_AH = 0x00; // return code: success + CLEAR_FLAG(F_CF); +#else + // only allow the device to find itself... if ((M.x86.R_CX == bios_device.pci_device_id) - && (M.x86.R_DX == bios_device.pci_vendor_id) - // device index must be 0 - && (M.x86.R_SI == 0)) { + && (M.x86.R_DX == bios_device.pci_vendor_id) + // device index must be 0 + && (M.x86.R_SI == 0)) { CLEAR_FLAG(F_CF); - M.x86.R_AH = 0x00; // return code: success + M.x86.R_AH = 0x00; // return code: success M.x86.R_BH = bios_device.bus; M.x86.R_BL = bios_device.devfn; - DEBUG_PRINTF_INTR - ("%s(): function %x: PCI Find Device --> 0x%04x\n", - __func__, M.x86.R_AX, M.x86.R_BX); +#endif } else { DEBUG_PRINTF_INTR - ("%s(): function %x: invalid device/vendor/device index! (%04x/%04x/%02x expected: %04x/%04x/0) \n", + ("%s(): function %x: invalid device/vendor/device index! (%04x/%04x/%02x expected: %04x/%04x/00) \n", __func__, M.x86.R_AX, M.x86.R_CX, M.x86.R_DX, M.x86.R_SI, bios_device.pci_device_id, bios_device.pci_vendor_id); + SET_FLAG(F_CF); M.x86.R_AH = 0x86; // return code: device not found } @@ -375,11 +392,22 @@ bus = M.x86.R_BH; devfn = M.x86.R_BL; offs = M.x86.R_DI; + DEBUG_PRINTF_INTR("%s(): function: %x: PCI Config Read from device: bus: %02x, devfn: %02x, offset: %02x\n", + __func__, M.x86.R_AX, bus, devfn, offs); +#if defined(CONFIG_YABEL_PCI_ACCESS_OTHER_DEVICES) && CONFIG_YABEL_PCI_ACCESS_OTHER_DEVICES==1 + dev = dev_find_slot(bus, devfn); + DEBUG_PRINTF_INTR("%s(): function: %x: dev_find_slot() returned: %s\n", + __func__, M.x86.R_AX, dev_path(dev)); + if (dev == 0) { + // fail accesses to non-existent devices... +#else + dev = bios_device.dev; if ((bus != bios_device.bus) - || (devfn != bios_device.devfn)) { + || (devfn != bios_device.devfn)) { // fail accesses to any device but ours... +#endif printf - ("%s(): Config read access invalid! bus: %x (%x), devfn: %x (%x), offs: %x\n", + ("%s(): Config read access invalid device! bus: %02x (%02x), devfn: %02x (%02x), offs: %02x\n", __func__, bus, bios_device.bus, devfn, bios_device.devfn, offs); SET_FLAG(F_CF); @@ -391,7 +419,7 @@ case 0xb108: M.x86.R_CL = #ifdef CONFIG_PCI_OPTION_ROM_RUN_YABEL - pci_read_config8(bios_device.dev, offs); + pci_read_config8(dev, offs); #else (u8) rtas_pci_config_read(bios_device. puid, 1, @@ -406,7 +434,7 @@ case 0xb109: M.x86.R_CX = #ifdef CONFIG_PCI_OPTION_ROM_RUN_YABEL - pci_read_config16(bios_device.dev, offs); + pci_read_config16(dev, offs); #else (u16) rtas_pci_config_read(bios_device. puid, 2, @@ -421,7 +449,7 @@ case 0xb10a: M.x86.R_ECX = #ifdef CONFIG_PCI_OPTION_ROM_RUN_YABEL - pci_read_config32(bios_device.dev, offs); + pci_read_config32(dev, offs); #else (u32) rtas_pci_config_read(bios_device. puid, 4, Modified: coreboot-v3/util/x86emu/yabel/io.c =================================================================== --- coreboot-v3/util/x86emu/yabel/io.c 2009-03-18 16:26:56 UTC (rev 1154) +++ coreboot-v3/util/x86emu/yabel/io.c 2009-03-18 16:27:01 UTC (rev 1155) @@ -349,6 +349,7 @@ pci_cfg_read(X86EMU_pioAddr addr, u8 size) { u32 rval = 0xFFFFFFFF; + struct device * dev; if ((addr >= 0xCFC) && ((addr + size) <= 0xD00)) { // PCI Configuration Mechanism 1 step 1 // write to 0xCF8, sets bus, device, function and Config Space offset @@ -361,29 +362,38 @@ devfn = (port_cf8_val & 0x0000FF00) >> 8; offs = (port_cf8_val & 0x000000FF); offs += (addr - 0xCFC); // if addr is not 0xcfc, the offset is moved accordingly + DEBUG_PRINTF_INTR("%s(): PCI Config Read from device: bus: %02x, devfn: %02x, offset: %02x\n", + __func__, bus, devfn, offs); +#if defined(CONFIG_YABEL_PCI_ACCESS_OTHER_DEVICES) && CONFIG_YABEL_PCI_ACCESS_OTHER_DEVICES==1 + dev = dev_find_slot(bus, devfn); + DEBUG_PRINTF_INTR("%s(): dev_find_slot() returned: %s\n", + __func__, dev_path(dev)); + if (dev == 0) { + // fail accesses to non-existent devices... +#else + dev = bios_device.dev; if ((bus != bios_device.bus) - || (devfn != bios_device.devfn)) { + || (devfn != bios_device.devfn)) { // fail accesses to any device but ours... +#endif printf - ("Config read access invalid! PCI device %x:%x.%x, offs: %x\n", - bus, devfn >> 3, devfn & 7, offs); -#ifdef CONFIG_YABEL_NO_ILLEGAL_ACCESS + ("%s(): Config read access invalid device! bus: %02x (%02x), devfn: %02x (%02x), offs: %02x\n", + __func__, bus, bios_device.bus, devfn, + bios_device.devfn, offs); + SET_FLAG(F_CF); HALT_SYS(); + return 0; } else { -#else - } - { -#endif #ifdef CONFIG_PCI_OPTION_ROM_RUN_YABEL switch (size) { case 1: - rval = pci_read_config8(bios_device.dev, offs); + rval = pci_read_config8(dev, offs); break; case 2: - rval = pci_read_config16(bios_device.dev, offs); + rval = pci_read_config16(dev, offs); break; case 4: - rval = pci_read_config32(bios_device.dev, offs); + rval = pci_read_config32(dev, offs); break; } #else

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r1154 - coreboot-v3/device
by svn＠coreboot.org 18 Mar '09

18 Mar '09

Author: phueper Date: 2009-03-18 17:26:56 +0100 (Wed, 18 Mar 2009) New Revision: 1154 Modified: coreboot-v3/device/Kconfig Log: add YABEL flag to options to decide wether access to devices other than the one yabel is running for is possible Signed-off-by: Pattrick Hueper <phueper(a)hueper.net> Tested and Acked-by: Joseph Smith <joe(a)settoplinux.org> Modified: coreboot-v3/device/Kconfig =================================================================== --- coreboot-v3/device/Kconfig 2009-03-18 14:58:03 UTC (rev 1153) +++ coreboot-v3/device/Kconfig 2009-03-18 16:26:56 UTC (rev 1154) @@ -111,6 +111,14 @@ help Set YABEL debug flags, for possible values, see util/x86emu/yabel/debug.h + config YABEL_PCI_ACCESS_OTHER_DEVICES + bool "Allow PCI Config Access to other devices" + default n + help + Allow Option ROMs executed by YABEL to access the config + space of devices other than the one YABEL is running for. + This may be needed by some onboard Graphics cards ROMs. + endmenu # TODO: This should probably become a CMOS option.

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coreboot March 2009