coreboot March 2009

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[PATCH] mkelfimage: add support for high coreboot tables
by Stefan Reinauer 17 Mar '09

17 Mar '09

See patch -- coresystems GmbH • Brahmsstr. 16 • D-79104 Freiburg i. Br. Tel.: +49 761 7668825 • Fax: +49 761 7664613 Email: info(a)coresystems.de • http://www.coresystems.de/ Registergericht: Amtsgericht Freiburg • HRB 7656 Geschäftsführer: Stefan Reinauer • Ust-IdNr.: DE245674866

2 2

r4015 - in trunk/util/mkelfImage: include linux-i386
by svn＠coreboot.org 17 Mar '09

17 Mar '09

Author: stepan Date: 2009-03-17 16:33:41 +0100 (Tue, 17 Mar 2009) New Revision: 4015 Modified: trunk/util/mkelfImage/include/linuxbios_tables.h trunk/util/mkelfImage/linux-i386/convert_params.c Log: Add support for high coreboot table to mkelfimage Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Myles Watson <mylesgw(a)gmail.com> Modified: trunk/util/mkelfImage/include/linuxbios_tables.h =================================================================== --- trunk/util/mkelfImage/include/linuxbios_tables.h 2009-03-17 15:15:15 UTC (rev 4014) +++ trunk/util/mkelfImage/include/linuxbios_tables.h 2009-03-17 15:33:41 UTC (rev 4015) @@ -79,4 +79,13 @@ uint64_t hwrpb; }; +#define LB_TAG_FORWARD 0x0011 +struct lb_forward { + uint32_t tag; + uint32_t size; + uint64_t forward; +}; + + + #endif /* LINUXBIOS_TABLES_H */ Modified: trunk/util/mkelfImage/linux-i386/convert_params.c =================================================================== --- trunk/util/mkelfImage/linux-i386/convert_params.c 2009-03-17 15:15:15 UTC (rev 4014) +++ trunk/util/mkelfImage/linux-i386/convert_params.c 2009-03-17 15:33:41 UTC (rev 4015) @@ -978,6 +978,13 @@ head = __find_lb_table((void *)0xf0000, (void *)0x100000); } if (head) { + struct lb_forward *forward = (struct lb_forward *)(((char *)head) + head->header_bytes); + if (forward->tag == LB_TAG_FORWARD) { + head = __find_lb_table(forward->forward, + forward->forward + 0x1000); + } + } + if (head) { info->has_linuxbios = 1; info->lb_table = head; return 1;

1 0

build service results for r4012
by coreboot information 17 Mar '09

17 Mar '09

Dear coreboot readers! This is the automatic build system of coreboot. The developer "stepan" checked in revision 4012 to the coreboot repository. This caused the following changes: Change Log: This patch adds "high coreboot table support" to coreboot version 2. Some bootloaders seem to overwrite memory starting at 0x600, thus destroying the coreboot table integrity, rendering the table useless. By moving the table to the high tables area (if it's activated), this problem is fixed. In order to move the table, a 40 bytes mini coreboot table with a single sub table is placed at 0x500/0x530 that points to the real coreboot table. This is comparable to the ACPI RSDT or the MP floating table. This patch also adds "table forward" support to flashrom and nvramtool. Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Peter Stuge <peter(a)stuge.se> Build Log: Compilation of embeddedplanet:ep405pc is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4012&device=ep405pc&vendor… Compilation of motorola:sandpointx3_altimus_mpc7410 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4012&device=sandpointx3_al… Compilation of totalimpact:briq is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4012&device=briq&vendor=to… If something broke during this checkin please be a pain in stepan's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

1 0

r4014 - in trunk/coreboot-v2/src: arch/ppc/init config
by svn＠coreboot.org 17 Mar '09

17 Mar '09

Author: stepan Date: 2009-03-17 16:15:15 +0100 (Tue, 17 Mar 2009) New Revision: 4014 Modified: trunk/coreboot-v2/src/arch/ppc/init/ldscript.lb trunk/coreboot-v2/src/config/coreboot_ram.ld Log: Don't know if this is the correct fix, but it fixes compilation of the PPC targets. Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/coreboot-v2/src/arch/ppc/init/ldscript.lb =================================================================== --- trunk/coreboot-v2/src/arch/ppc/init/ldscript.lb 2009-03-17 14:39:36 UTC (rev 4013) +++ trunk/coreboot-v2/src/arch/ppc/init/ldscript.lb 2009-03-17 15:15:15 UTC (rev 4014) @@ -79,6 +79,18 @@ _eram = . ; } + .sdata : { + _SDA_BASE_ = .; + *(.sdata) + } + + .sdata2 : { + _SDA2_BASE_ = .; + *(.sdata2) + } + + + /* * Absolute location of where coreboot will be relocated in RAM. */ Modified: trunk/coreboot-v2/src/config/coreboot_ram.ld =================================================================== --- trunk/coreboot-v2/src/config/coreboot_ram.ld 2009-03-17 14:39:36 UTC (rev 4013) +++ trunk/coreboot-v2/src/config/coreboot_ram.ld 2009-03-17 15:15:15 UTC (rev 4014) @@ -75,6 +75,17 @@ *(.data) _edata = .; } + + .sdata : { + _SDA_BASE_ = .; + *(.sdata) + } + + .sdata2 : { + _SDA2_BASE_ = .; + *(.sdata2) + } + /* * bss does not contain data, it is just a space that should be zero * initialized on startup. (typically uninitialized global variables)

1 0

build service results for r4011
by coreboot information 17 Mar '09

17 Mar '09

Dear coreboot readers! This is the automatic build system of coreboot. The developer "stepan" checked in revision 4011 to the coreboot repository. This caused the following changes: Change Log: This patch adds "high coreboot table support" to coreboot version 2. Some bootloaders seem to overwrite memory starting at 0x600, thus destroying the coreboot table integrity, rendering the table useless. By moving the table to the high tables area (if it's activated), this problem is fixed. In order to move the table, a 40 bytes mini coreboot table with a single sub table is placed at 0x500/0x530 that points to the real coreboot table. This is comparable to the ACPI RSDT or the MP floating table. This patch also adds "table forward" support to flashrom and nvramtool. Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Peter Stuge <peter(a)stuge.se> Build Log: Compilation of embeddedplanet:ep405pc is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4011&device=ep405pc&vendor… Compilation of motorola:sandpointx3_altimus_mpc7410 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4011&device=sandpointx3_al… Compilation of totalimpact:briq is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4011&device=briq&vendor=to… If something broke during this checkin please be a pain in stepan's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

1 0

AMD 690 board with dual 88e8056
by Daniel Toussaint 17 Mar '09

17 Mar '09

Dear All, I am working on an mother board with AMD 690 chipset (lspci at the bottom of this mail). All works perfectly , using mainboards/amd/dbm6990t. The only thing is that the two on board 88E8056 - they are not detected at all. If I plugin a PCI card with a wireless lan chip, it works fine. Is there anything specific I still need to do in the Config.lb for the mainboard - I was under the assumption that these kind of devices would work out of the box. Thanks for any debug tips you could give me. ---lspci of my board (boot under Award). 00:00.0 Host bridge: ATI Technologies Inc RS690 Host Bridge 00:01.0 PCI bridge: ATI Technologies Inc RS690 PCI to PCI Bridge (Internal gfx) 00:04.0 PCI bridge: ATI Technologies Inc Device 7914 00:05.0 PCI bridge: ATI Technologies Inc RS690 PCI to PCI Bridge (PCI Express Port 1) 00:12.0 SATA controller: ATI Technologies Inc SB600 Non-Raid-5 SATA 00:13.0 USB Controller: ATI Technologies Inc SB600 USB (OHCI0) 00:13.1 USB Controller: ATI Technologies Inc SB600 USB (OHCI1) 00:13.2 USB Controller: ATI Technologies Inc SB600 USB (OHCI2) 00:13.3 USB Controller: ATI Technologies Inc SB600 USB (OHCI3) 00:13.4 USB Controller: ATI Technologies Inc SB600 USB (OHCI4) 00:13.5 USB Controller: ATI Technologies Inc SB600 USB Controller (EHCI) 00:14.0 SMBus: ATI Technologies Inc SBx00 SMBus Controller (rev 14) 00:14.1 IDE interface: ATI Technologies Inc SB600 IDE 00:14.2 Audio device: ATI Technologies Inc SBx00 Azalia (Intel HDA) 00:14.3 ISA bridge: ATI Technologies Inc SB600 PCI to LPC Bridge 00:14.4 PCI bridge: ATI Technologies Inc SBx00 PCI to PCI Bridge 00:18.0 Host bridge: Advanced Micro Devices [AMD] K8 [Athlon64/Opteron] HyperTransport Technology Configuration 00:18.1 Host bridge: Advanced Micro Devices [AMD] K8 [Athlon64/Opteron] Address Map 00:18.2 Host bridge: Advanced Micro Devices [AMD] K8 [Athlon64/Opteron] DRAM Controller 00:18.3 Host bridge: Advanced Micro Devices [AMD] K8 [Athlon64/Opteron] Miscellaneous Control 01:05.0 VGA compatible controller: ATI Technologies Inc RS690M [Radeon X1200 Series] 02:00.0 Ethernet controller: Marvell Technology Group Ltd. 88E8056 PCI-E Gigabit Ethernet Controller (rev 12) 03:00.0 Ethernet controller: Marvell Technology Group Ltd. 88E8056 PCI-E Gigabit Ethernet Controller (rev 12) 00:00.0 0600: 1002:7910 00:01.0 0604: 1002:7912 00:04.0 0604: 1002:7914 00:05.0 0604: 1002:7915 00:12.0 0106: 1002:4380 00:13.0 0c03: 1002:4387 00:13.1 0c03: 1002:4388 00:13.2 0c03: 1002:4389 00:13.3 0c03: 1002:438a 00:13.4 0c03: 1002:438b 00:13.5 0c03: 1002:4386 00:14.0 0c05: 1002:4385 (rev 14) 00:14.1 0101: 1002:438c 00:14.2 0403: 1002:4383 00:14.3 0601: 1002:438d 00:14.4 0604: 1002:4384 00:18.0 0600: 1022:1100 00:18.1 0600: 1022:1101 00:18.2 0600: 1022:1102 00:18.3 0600: 1022:1103 01:05.0 0300: 1002:791f 02:00.0 0200: 11ab:4364 (rev 12) 03:00.0 0200: 11ab:4364 (rev 12)

4 7

r4013 - trunk/util/nvramtool
by svn＠coreboot.org 17 Mar '09

17 Mar '09

Author: stepan Date: 2009-03-17 15:39:36 +0100 (Tue, 17 Mar 2009) New Revision: 4013 Modified: trunk/util/nvramtool/coreboot_tables.h trunk/util/nvramtool/lbtable.c Log: This patch adds "high coreboot table support" to coreboot version 2. Some bootloaders seem to overwrite memory starting at 0x600, thus destroying the coreboot table integrity, rendering the table useless. By moving the table to the high tables area (if it's activated), this problem is fixed. In order to move the table, a 40 bytes mini coreboot table with a single sub table is placed at 0x500/0x530 that points to the real coreboot table. This is comparable to the ACPI RSDT or the MP floating table. This patch also adds "table forward" support to flashrom and nvramtool. Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Peter Stuge <peter(a)stuge.se> Modified: trunk/util/nvramtool/coreboot_tables.h =================================================================== --- trunk/util/nvramtool/coreboot_tables.h 2009-03-17 14:39:25 UTC (rev 4012) +++ trunk/util/nvramtool/coreboot_tables.h 2009-03-17 14:39:36 UTC (rev 4013) @@ -146,6 +146,14 @@ uint32_t size; uint8_t string[0]; }; +#define LB_TAG_SERIAL 0x000f +#define LB_TAG_CONSOLE 0x0010 +#define LB_TAG_FORWARD 0x0011 +struct lb_forward { + uint32_t tag; + uint32_t size; + uint64_t forward; +}; /* The following structures are for the cmos definitions table */ #define LB_TAG_CMOS_OPTION_TABLE 200 Modified: trunk/util/nvramtool/lbtable.c =================================================================== --- trunk/util/nvramtool/lbtable.c 2009-03-17 14:39:25 UTC (rev 4012) +++ trunk/util/nvramtool/lbtable.c 2009-03-17 14:39:36 UTC (rev 4013) @@ -149,6 +149,8 @@ "%s: Item %s not found in coreboot table. Apparently, you are " "using coreboot v1.\n"; +int fd; + /* This is the number of items from the coreboot table that may be displayed * using the -l option. */ @@ -240,6 +242,7 @@ * /dev/mem. */ static const void *low_phys_mem; +static unsigned long low_phys_base = 0; /* Pointer to coreboot table. */ static const struct lb_header *lbtable = NULL; @@ -261,7 +264,7 @@ * /dev/mem. This macro converts 'vaddr' to a physical address. ****************************************************************************/ #define vtophys(vaddr) (((unsigned long) vaddr) - \ - ((unsigned long) low_phys_mem)) + ((unsigned long) low_phys_mem) + low_phys_base) /**************************************************************************** * phystov @@ -272,7 +275,7 @@ * by calling mmap() on /dev/mem. ****************************************************************************/ #define phystov(paddr) (((unsigned long) low_phys_mem) + \ - ((unsigned long) paddr)) + ((unsigned long) paddr) - low_phys_base) /**************************************************************************** * get_lbtable @@ -280,7 +283,7 @@ * Find the coreboot table and set global variable lbtable to point to it. ****************************************************************************/ void get_lbtable (void) - { int fd, i, bad_header_count, bad_table_count, bad_headers, bad_tables; + { int i, bad_header_count, bad_table_count, bad_headers, bad_tables; if (lbtable != NULL) return; @@ -494,6 +497,7 @@ int *bad_table_count) { static const char signature[] = { 'L', 'B', 'I', 'O' }; const struct lb_header *table; + const struct lb_forward *forward; const uint32_t *p; uint32_t sig; @@ -534,6 +538,25 @@ } /* checksums are ok: we found it! */ + /* But it may just be a forwarding table, so look if there's a forwarder */ + lbtable = table; + forward = (struct lb_forward *)find_lbrec(LB_TAG_FORWARD); + lbtable = NULL; + + if (forward) { + uint64_t new_phys = forward->forward; + + new_phys &= ~(getpagesize()-1); + + munmap((void *)low_phys_mem, BYTES_TO_MAP); + if ((low_phys_mem = mmap(NULL, BYTES_TO_MAP, PROT_READ, MAP_SHARED, fd, (off_t)new_phys)) == MAP_FAILED) + { fprintf(stderr, "%s: Failed to mmap /dev/mem: %s\n", prog_name, + strerror(errno)); + exit(1); + } + low_phys_base = new_phys; + table = lbtable_scan(phystov(low_phys_base), phystov(low_phys_base + BYTES_TO_MAP), bad_header_count, bad_table_count); + } return table; } @@ -865,6 +888,15 @@ case LB_TAG_ASSEMBLER: return "ASSEMBLER"; + case LB_TAG_SERIAL: + return "SERIAL"; + + case LB_TAG_CONSOLE: + return "CONSOLE"; + + case LB_TAG_FORWARD: + return "FORWARD"; + case LB_TAG_CMOS_OPTION_TABLE: return "CMOS_OPTION_TABLE";

1 0

r4012 - trunk/util/flashrom
by svn＠coreboot.org 17 Mar '09

17 Mar '09

Author: stepan Date: 2009-03-17 15:39:25 +0100 (Tue, 17 Mar 2009) New Revision: 4012 Modified: trunk/util/flashrom/cbtable.c trunk/util/flashrom/coreboot_tables.h Log: This patch adds "high coreboot table support" to coreboot version 2. Some bootloaders seem to overwrite memory starting at 0x600, thus destroying the coreboot table integrity, rendering the table useless. By moving the table to the high tables area (if it's activated), this problem is fixed. In order to move the table, a 40 bytes mini coreboot table with a single sub table is placed at 0x500/0x530 that points to the real coreboot table. This is comparable to the ACPI RSDT or the MP floating table. This patch also adds "table forward" support to flashrom and nvramtool. Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Peter Stuge <peter(a)stuge.se> Modified: trunk/util/flashrom/cbtable.c =================================================================== --- trunk/util/flashrom/cbtable.c 2009-03-17 14:38:48 UTC (rev 4011) +++ trunk/util/flashrom/cbtable.c 2009-03-17 14:39:25 UTC (rev 4012) @@ -4,7 +4,7 @@ * Copyright (C) 2002 Steven James <pyro(a)linuxlabs.com> * Copyright (C) 2002 Linux Networx * (Written by Eric Biederman <ebiederman(a)lnxi.com> for Linux Networx) - * Copyright (C) 2006-2007 coresystems GmbH + * Copyright (C) 2006-2009 coresystems GmbH * (Written by Stefan Reinauer <stepan(a)coresystems.de> for coresystems GmbH) * * This program is free software; you can redistribute it and/or modify @@ -124,7 +124,7 @@ head->table_checksum); continue; } - fprintf(stdout, "Found coreboot table at 0x%08lx.\n", addr); + printf_debug("Found coreboot table at 0x%08lx.\n", addr); return head; }; @@ -181,9 +181,10 @@ } } +#define BYTES_TO_MAP (1024*1024) int coreboot_init(void) { - uint8_t *low_1MB; + uint8_t *table_area; unsigned long addr, start; struct lb_header *lb_table; struct lb_record *rec, *last; @@ -196,18 +197,31 @@ #else start = 0x0; #endif - low_1MB = physmap("low megabyte", start, 1024*1024); + table_area = physmap("low megabyte", start, BYTES_TO_MAP); - lb_table = find_lb_table(low_1MB, 0x00000, 0x1000); + lb_table = find_lb_table(table_area, 0x00000, 0x1000); if (!lb_table) - lb_table = find_lb_table(low_1MB, 0xf0000, 1024*1024); + lb_table = find_lb_table(table_area, 0xf0000, BYTES_TO_MAP); + if (lb_table) { + struct lb_forward *forward = (struct lb_forward *) + (((char *)lb_table) + lb_table->header_bytes); + if (forward->tag == LB_TAG_FORWARD) { + start = forward->forward; + start &= ~(getpagesize()-1); + physunmap(table_area, BYTES_TO_MAP); + table_area = physmap("high tables", start, BYTES_TO_MAP); + lb_table = find_lb_table(table_area, 0x00000, 0x1000); + } + } + if (!lb_table) { printf("No coreboot table found.\n"); return -1; } - addr = ((char *)lb_table) - ((char *)low_1MB) + start; - printf_debug("coreboot table found at %p.\n", lb_table + start); + addr = ((char *)lb_table) - ((char *)table_area) + start; + fprintf(stdout, "coreboot table found at 0x%lx.\n", + (unsigned long)lb_table - (unsigned long)table_area + start); rec = (struct lb_record *)(((char *)lb_table) + lb_table->header_bytes); last = (struct lb_record *)(((char *)rec) + lb_table->table_bytes); printf_debug("coreboot header(%d) checksum: %04x table(%d) checksum: %04x entries: %d\n", Modified: trunk/util/flashrom/coreboot_tables.h =================================================================== --- trunk/util/flashrom/coreboot_tables.h 2009-03-17 14:38:48 UTC (rev 4011) +++ trunk/util/flashrom/coreboot_tables.h 2009-03-17 14:39:25 UTC (rev 4012) @@ -135,6 +135,13 @@ uint8_t string[0]; }; +#define LB_TAG_FORWARD 0x0011 +struct lb_forward { + uint32_t tag; + uint32_t size; + uint64_t forward; +}; + /* The following structures are for the cmos definitions table */ #define LB_TAG_CMOS_OPTION_TABLE 200 /* cmos header record */

1 0

r4011 - in trunk/coreboot-v2/src: arch/i386/boot include/boot
by svn＠coreboot.org 17 Mar '09

17 Mar '09

Author: stepan Date: 2009-03-17 15:38:48 +0100 (Tue, 17 Mar 2009) New Revision: 4011 Modified: trunk/coreboot-v2/src/arch/i386/boot/coreboot_table.c trunk/coreboot-v2/src/arch/i386/boot/coreboot_table.h trunk/coreboot-v2/src/arch/i386/boot/tables.c trunk/coreboot-v2/src/include/boot/coreboot_tables.h Log: This patch adds "high coreboot table support" to coreboot version 2. Some bootloaders seem to overwrite memory starting at 0x600, thus destroying the coreboot table integrity, rendering the table useless. By moving the table to the high tables area (if it's activated), this problem is fixed. In order to move the table, a 40 bytes mini coreboot table with a single sub table is placed at 0x500/0x530 that points to the real coreboot table. This is comparable to the ACPI RSDT or the MP floating table. This patch also adds "table forward" support to flashrom and nvramtool. Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Peter Stuge <peter(a)stuge.se> Modified: trunk/coreboot-v2/src/arch/i386/boot/coreboot_table.c =================================================================== --- trunk/coreboot-v2/src/arch/i386/boot/coreboot_table.c 2009-03-17 01:47:25 UTC (rev 4010) +++ trunk/coreboot-v2/src/arch/i386/boot/coreboot_table.c 2009-03-17 14:38:48 UTC (rev 4011) @@ -196,6 +196,18 @@ } +struct lb_forward *lb_forward(struct lb_header *header, struct lb_header *next_header) +{ + struct lb_record *rec; + struct lb_forward *forward; + rec = lb_new_record(header); + forward = (struct lb_forward *)rec; + forward->tag = LB_TAG_FORWARD; + forward->size = sizeof(*forward); + forward->forward = (uint64_t) next_header; + return forward; +} + void lb_memory_range(struct lb_memory *mem, uint32_t type, uint64_t start, uint64_t size) { @@ -239,14 +251,17 @@ } } -unsigned long lb_table_fini(struct lb_header *head) +static unsigned long lb_table_fini(struct lb_header *head, int fixup) { struct lb_record *rec, *first_rec; rec = lb_last_record(head); if (head->table_entries) { head->table_bytes += rec->size; } - lb_reserve_table_memory(head); + + if (fixup) + lb_reserve_table_memory(head); + first_rec = lb_first_record(head); head->table_checksum = compute_ip_checksum(first_rec, head->table_bytes); head->header_checksum = 0; @@ -406,6 +421,22 @@ struct lb_header *head; struct lb_memory *mem; +#if HAVE_HIGH_TABLES == 1 + printk_debug("Writing high table forward entry at 0x%08lx\n", + low_table_end); + head = lb_table_init(low_table_end); + lb_forward(head, rom_table_end); + lb_table_fini(head, 0); + + low_table_end = (unsigned long)head; + printk_debug("New low_table_end: 0x%08lx\n", low_table_end); + printk_debug("Now going to write high coreboot table at 0x%08lx\n", + rom_table_end); + + head = lb_table_init(rom_table_end); + rom_table_end = (unsigned long)head; + printk_debug("rom_table_end = 0x%08lx\n", rom_table_end); +#else if(low_table_end > (0x1000 - sizeof(struct lb_header))) { /* after 4K */ /* We need to put lbtable on to [0xf0000,0x100000) */ head = lb_table_init(rom_table_end); @@ -414,6 +445,7 @@ head = lb_table_init(low_table_end); low_table_end = (unsigned long)head; } +#endif printk_debug("Adjust low_table_end from 0x%08lx to ", low_table_end); low_table_end += 0xfff; // 4K aligned @@ -469,6 +501,6 @@ lb_strings(head); /* Remember where my valid memory ranges are */ - return lb_table_fini(head); + return lb_table_fini(head, 1); } Modified: trunk/coreboot-v2/src/arch/i386/boot/coreboot_table.h =================================================================== --- trunk/coreboot-v2/src/arch/i386/boot/coreboot_table.h 2009-03-17 01:47:25 UTC (rev 4010) +++ trunk/coreboot-v2/src/arch/i386/boot/coreboot_table.h 2009-03-17 14:38:48 UTC (rev 4011) @@ -17,7 +17,6 @@ void lb_memory_range(struct lb_memory *mem, uint32_t type, uint64_t start, uint64_t size); struct lb_mainboard *lb_mainboard(struct lb_header *header); -unsigned long lb_table_fini(struct lb_header *header); /* Routines to extract part so the coreboot table or information * from the coreboot table. Modified: trunk/coreboot-v2/src/arch/i386/boot/tables.c =================================================================== --- trunk/coreboot-v2/src/arch/i386/boot/tables.c 2009-03-17 01:47:25 UTC (rev 4010) +++ trunk/coreboot-v2/src/arch/i386/boot/tables.c 2009-03-17 14:38:48 UTC (rev 4011) @@ -75,7 +75,7 @@ unsigned long high_table_start, high_table_end=0; if (high_tables_base) { - printk_debug("High Tables Base is %lx.\n", high_tables_base); + printk_debug("High Tables Base is %llx.\n", high_tables_base); high_table_start = high_tables_base; high_table_end = high_tables_base; } else { @@ -189,26 +189,19 @@ rom_table_start, rom_table_end); #endif +#if HAVE_HIGH_TABLES == 1 + if (high_tables_base) { + write_coreboot_table(low_table_start, low_table_end, + high_table_start, high_table_end); + } else { + printk_err("ERROR: No high_tables_base.\n"); + write_coreboot_table(low_table_start, low_table_end, + rom_table_start, rom_table_end); + } +#else /* The coreboot table must be in 0-4K or 960K-1M */ write_coreboot_table(low_table_start, low_table_end, rom_table_start, rom_table_end); - -#if 0 && HAVE_HIGH_TABLES == 1 - /* This is currently broken and should be severely refactored. Ideally - * we only have a pointer to the coreboot table in the low memory, so - * anyone can find the real position. - * write_coreboot_table does a lot more than just writing the coreboot - * table. It magically decides where the table should go, and therefore - * it consumes two base addresses. If we call write_coreboot_table like - * below, we get weird effects. - */ - /* And we want another copy in high area because the low area might be - * corrupted - */ - if (high_tables_base) { - write_coreboot_table(high_table_start, high_table_end, - high_table_start, high_table_end); - } #endif return get_lb_mem(); Modified: trunk/coreboot-v2/src/include/boot/coreboot_tables.h =================================================================== --- trunk/coreboot-v2/src/include/boot/coreboot_tables.h 2009-03-17 01:47:25 UTC (rev 4010) +++ trunk/coreboot-v2/src/include/boot/coreboot_tables.h 2009-03-17 14:38:48 UTC (rev 4011) @@ -155,6 +155,13 @@ uint16_t type; }; +#define LB_TAG_FORWARD 0x0011 +struct lb_forward { + uint32_t tag; + uint32_t size; + uint64_t forward; +}; + #define LB_TAG_CONSOLE_SERIAL8250 0 #define LB_TAG_CONSOLE_VGA 1 #define LB_TAG_CONSOLE_BTEXT 2

1 0

DBM690T booting windows xp
by Wang, Qingpei 17 Mar '09

17 Mar '09

Hi all, I am stilling trying to booting windows xp with dbm690t. It still did no progress now. I attached the dmesg from linux and full Coreboot log and the acpidumpfile data.txt.I just hardcoded the high table to (((1024-128)*1024*1024)-64*1024) for there is 1GB memory and Top 128M are reserved for video. Jason Wang BeiJing Technology Development Center Advanced Micro Devices (AMD)

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coreboot March 2009