coreboot December 2009

coreboot@coreboot.org

49 participants
169 discussions

[commit] r4994 - in trunk: src/arch/i386 src/arch/i386/init src/arch/i386/lib src/cpu/amd/model_10xxx src/cpu/amd/model_fxx src/mainboard/amd/serengeti_cheetah_fam10 src/northbridge/amd/amdfam10 src/southbridge/amd/amd8111 util/compareboard util/romcc
by svn＠coreboot.org 31 Dec '09

31 Dec '09

Author: oxygene Date: 2009-12-31 13:56:53 +0100 (Thu, 31 Dec 2009) New Revision: 4994 Added: trunk/src/northbridge/amd/amdfam10/bootblock.c trunk/src/southbridge/amd/amd8111/bootblock.c Modified: trunk/src/arch/i386/Kconfig trunk/src/arch/i386/Makefile.tinybootblock.inc trunk/src/arch/i386/init/bootblock.c trunk/src/arch/i386/lib/walkcbfs.S trunk/src/cpu/amd/model_10xxx/Kconfig trunk/src/cpu/amd/model_fxx/Kconfig trunk/src/mainboard/amd/serengeti_cheetah_fam10/Kconfig trunk/src/mainboard/amd/serengeti_cheetah_fam10/Makefile.inc trunk/src/northbridge/amd/amdfam10/Kconfig trunk/src/northbridge/amd/amdfam10/Makefile.inc trunk/src/southbridge/amd/amd8111/Kconfig trunk/util/compareboard/compareboard trunk/util/romcc/romcc.c Log: romcc: - Set __PRE_RAM__ define per default - Properly handle ignored (#ifdef'd out) #include lines amd/serengeti_cheetah_fam10: - write ACPI files to $(obj) instead of the top dir (alias $(CURDIR)) tinybootblock: - provide a way to define code that should be added to the bootblock, to map the entire ROM for use by CBFS amd/model_fxx, amd/model_10xxx: - add CONFIG_SSE walkcbfs.S: - eliminate the use of two registers, to make space for romcc to wiggle amd/serengeti_cheetah_fam10: - use the enable_rom framework. not entirely functional yet Boot-tested on emulation/qemu-x86 Build-tested on amd/serengeti_cheetah_fam10 amd/serengeti_cheetah_fam10 fails in amdht/ somewhere, but builds Signed-off-by: Patrick Georgi <patrick.georgi(a)coresystems.de> Acked-by: Ronald G. Minnich <rminnich(a)gmail.com> Modified: trunk/src/arch/i386/Kconfig =================================================================== --- trunk/src/arch/i386/Kconfig 2009-12-28 09:59:44 UTC (rev 4993) +++ trunk/src/arch/i386/Kconfig 2009-12-31 12:56:53 UTC (rev 4994) @@ -43,3 +43,9 @@ config TINY_BOOTBLOCK bool default n + +config BOOTBLOCK_NORTHBRIDGE_INIT + string + +config BOOTBLOCK_SOUTHBRIDGE_INIT + string Modified: trunk/src/arch/i386/Makefile.tinybootblock.inc =================================================================== --- trunk/src/arch/i386/Makefile.tinybootblock.inc 2009-12-28 09:59:44 UTC (rev 4993) +++ trunk/src/arch/i386/Makefile.tinybootblock.inc 2009-12-31 12:56:53 UTC (rev 4994) @@ -30,9 +30,17 @@ bootblock_inc += $(src)/cpu/x86/16bit/reset16.inc bootblock_inc += $(src)/cpu/x86/32bit/entry32.inc bootblock_inc += $(src)/arch/i386/lib/id.inc +ifeq ($(CONFIG_SSE),y) +bootblock_inc += $(src)/cpu/x86/sse_enable.inc +endif bootblock_inc += $(obj)/mainboard/$(MAINBOARDDIR)/bootblock.inc bootblock_inc += $(src)/arch/i386/lib/walkcbfs.S +bootblock_romccflags := -mcpu=i386 +ifeq ($(CONFIG_SSE),y) +bootblock_romccflags := -mcpu=k7 -msse +endif + $(obj)/bootblock/ldscript.ld: $(bootblock_ldscripts) $(obj)/ldoptions mkdir -p $(obj)/bootblock printf '$(foreach ldscript,ldoptions $(bootblock_lds),INCLUDE "$(ldscript)"\n)' > $@ @@ -48,7 +56,7 @@ $(CC) -x assembler-with-cpp -DASSEMBLY -E -I$(src)/include -I$(src)/arch/i386/include -I$(obj) -I$(obj)/bootblock -include $(obj)/config.h -I. -I$(src) $< > $@.new && mv $@.new $@ $(obj)/mainboard/$(MAINBOARDDIR)/bootblock.inc: $(obj)/romcc $(src)/arch/i386/init/bootblock.c - $(obj)/romcc $(ROMCCFLAGS) $(INCLUDES) $(src)/arch/i386/init/bootblock.c -o $@ + $(obj)/romcc $(bootblock_romccflags) -O2 $(ROMCCFLAGS) $(INCLUDES) $(src)/arch/i386/init/bootblock.c -o $@ $(obj)/bootblock.elf: $(obj)/mainboard/$(MAINBOARDDIR)/bootblock.o $(obj)/bootblock/ldscript.ld @printf " LINK $(subst $(obj)/,,$(@))\n" Modified: trunk/src/arch/i386/init/bootblock.c =================================================================== --- trunk/src/arch/i386/init/bootblock.c 2009-12-28 09:59:44 UTC (rev 4993) +++ trunk/src/arch/i386/init/bootblock.c 2009-12-31 12:56:53 UTC (rev 4994) @@ -1,3 +1,21 @@ +#if CONFIG_LOGICAL_CPUS && \ + (defined(CONFIG_BOOTBLOCK_NORTHBRIDGE_INIT) || defined(CONFIG_BOOTBLOCK_SOUTHBRIDGE_INIT)) +#include <cpu/x86/lapic/boot_cpu.c> +#else +#define boot_cpu(x) 1 +#endif + +#ifdef CONFIG_BOOTBLOCK_NORTHBRIDGE_INIT +#include CONFIG_BOOTBLOCK_NORTHBRIDGE_INIT +#else +static void bootblock_northbridge_init(void) { } +#endif +#ifdef CONFIG_BOOTBLOCK_SOUTHBRIDGE_INIT +#include CONFIG_BOOTBLOCK_SOUTHBRIDGE_INIT +#else +static void bootblock_southbridge_init(void) { } +#endif + static unsigned long findstage(char* target) { unsigned long entry; @@ -4,21 +22,25 @@ asm volatile ( "mov $1f, %%esp\n\t" "jmp walkcbfs\n\t" - "1:\n\t" : "=a" (entry) : "S" (target) : "ebx", "ecx", "edx", "edi", "ebp", "esp"); + "1:\n\t" : "=a" (entry) : "S" (target) : "ebx", "ecx", "edi", "esp"); return entry; } -static void call(unsigned long addr) +static void call(unsigned long addr, unsigned long bist) { - asm volatile ("jmp %0\n\t" : : "r" (addr)); + asm volatile ("jmp %0\n\t" : : "r" (addr), "a" (bist)); } -static void main(void) +static void main(unsigned long bist) { + if (boot_cpu()) { + bootblock_northbridge_init(); + bootblock_southbridge_init(); + } const char* target1 = "fallback/romstage"; unsigned long entry; entry = findstage(target1); - if (entry) call(entry); + if (entry) call(entry, bist); asm volatile ("1:\n\thlt\n\tjmp 1b\n\t"); } Modified: trunk/src/arch/i386/lib/walkcbfs.S =================================================================== --- trunk/src/arch/i386/lib/walkcbfs.S 2009-12-28 09:59:44 UTC (rev 4993) +++ trunk/src/arch/i386/lib/walkcbfs.S 2009-12-31 12:56:53 UTC (rev 4994) @@ -25,18 +25,9 @@ input %esi: filename input %esp: return address (not pointer to return address!) output %eax: entry point - clobbers %ebx, %ecx, %edx, %edi, %ebp + clobbers %ebx, %ecx, %edi */ walkcbfs: - mov %esi, %ebp /* stash away filename pointer */ - mov $0, %edx -1: - cmpb $0, (%edx,%esi) - jz 2f - add $1, %edx - jmp 1b -2: - add $1, %edx mov CBFS_HEADER_PTR, %eax mov CBFS_HEADER_ROMSIZE(%eax), %ecx bswap %ecx @@ -45,15 +36,20 @@ mov CBFS_HEADER_OFFSET(%eax), %ecx bswap %ecx add %ecx, %ebx - mov CBFS_HEADER_ALIGN(%eax), %eax - bswap %eax - sub $1, %eax + /* determine filename length */ + mov $0, %eax +1: + cmpb $0, (%eax,%esi) + jz 2f + add $1, %eax + jmp 1b +2: + add $1, %eax walker: - mov %ebp, %esi mov %ebx, %edi add $CBFS_FILE_STRUCTSIZE, %edi /* edi = address of first byte after struct cbfs_file */ - mov %edx, %ecx + mov %eax, %ecx repe cmpsb # zero flag set if strings are equal jnz tryharder @@ -67,21 +63,29 @@ jmp *%esp tryharder: + sub %ebx, %edi /* edi = # of walked bytes */ + sub %edi, %esi /* esi = start of filename */ + + /* ebx = ecx = (current+offset+len+ALIGN-1) & ~(ALIGN-1) */ mov CBFS_FILE_OFFSET(%ebx), %ecx bswap %ecx add %ebx, %ecx mov CBFS_FILE_LEN(%ebx), %edi bswap %edi add %edi, %ecx - add %eax, %ecx - mov %eax, %edi + mov CBFS_HEADER_PTR, %ebx + mov CBFS_HEADER_ALIGN(%ebx), %ebx + bswap %ebx + sub $1, %ebx + add %ebx, %ecx + mov %ebx, %edi not %edi and %edi, %ecx mov %ecx, %ebx /* look if we should exit */ - mov CBFS_HEADER_PTR, %esi - mov CBFS_HEADER_ROMSIZE(%esi), %ecx + mov CBFS_HEADER_PTR, %ecx + mov CBFS_HEADER_ROMSIZE(%ecx), %ecx bswap %ecx not %ecx add $1, %ecx Modified: trunk/src/cpu/amd/model_10xxx/Kconfig =================================================================== --- trunk/src/cpu/amd/model_10xxx/Kconfig 2009-12-28 09:59:44 UTC (rev 4993) +++ trunk/src/cpu/amd/model_10xxx/Kconfig 2009-12-31 12:56:53 UTC (rev 4994) @@ -3,6 +3,7 @@ select HAVE_MOVNTI select USE_PRINTK_IN_CAR select USE_DCACHE_RAM + select SSE config CPU_ADDR_BITS int Modified: trunk/src/cpu/amd/model_fxx/Kconfig =================================================================== --- trunk/src/cpu/amd/model_fxx/Kconfig 2009-12-28 09:59:44 UTC (rev 4993) +++ trunk/src/cpu/amd/model_fxx/Kconfig 2009-12-31 12:56:53 UTC (rev 4994) @@ -3,6 +3,7 @@ select HAVE_MOVNTI select USE_PRINTK_IN_CAR select USE_DCACHE_RAM + select SSE config CPU_ADDR_BITS int Modified: trunk/src/mainboard/amd/serengeti_cheetah_fam10/Kconfig =================================================================== --- trunk/src/mainboard/amd/serengeti_cheetah_fam10/Kconfig 2009-12-28 09:59:44 UTC (rev 4993) +++ trunk/src/mainboard/amd/serengeti_cheetah_fam10/Kconfig 2009-12-31 12:56:53 UTC (rev 4994) @@ -20,6 +20,7 @@ select BOARD_ROMSIZE_KB_1024 select ENABLE_APIC_EXT_ID select LIFT_BSP_APIC_ID + select TINY_BOOTBLOCK config MAINBOARD_DIR string @@ -127,3 +128,12 @@ default 0x1022 depends on BOARD_AMD_SERENGETI_CHEETAH_FAM10 +config RAMBASE + hex + default 0x200000 + depends on BOARD_AMD_SERENGETI_CHEETAH_FAM10 + +config ID_SECTION_OFFSET + hex + default 0x80 + depends on BOARD_AMD_SERENGETI_CHEETAH_FAM10 Modified: trunk/src/mainboard/amd/serengeti_cheetah_fam10/Makefile.inc =================================================================== --- trunk/src/mainboard/amd/serengeti_cheetah_fam10/Makefile.inc 2009-12-28 09:59:44 UTC (rev 4993) +++ trunk/src/mainboard/amd/serengeti_cheetah_fam10/Makefile.inc 2009-12-31 12:56:53 UTC (rev 4994) @@ -41,17 +41,12 @@ initobj-y += crt0.o # FIXME in $(top)/Makefile -crt0-y += ../../../../src/cpu/x86/16bit/entry16.inc crt0-y += ../../../../src/cpu/x86/32bit/entry32.inc -crt0-y += ../../../../src/cpu/x86/16bit/reset16.inc -crt0-y += ../../../../src/arch/i386/lib/id.inc crt0-y += ../../../../src/cpu/amd/car/cache_as_ram.inc crt0-y += auto.inc ldscript-y += ../../../../src/arch/i386/init/ldscript_fallback_cbfs.lb -ldscript-y += ../../../../src/cpu/x86/16bit/entry16.lds -ldscript-y += ../../../../src/cpu/x86/16bit/reset16.lds -ldscript-y += ../../../../src/arch/i386/lib/id.lds +ldscript-y += ../../../../src/cpu/x86/32bit/entry32.lds ldscript-y += ../../../../src/arch/i386/lib/failover.lds ifdef POST_EVALUATION Modified: trunk/src/northbridge/amd/amdfam10/Kconfig =================================================================== --- trunk/src/northbridge/amd/amdfam10/Kconfig 2009-12-28 09:59:44 UTC (rev 4993) +++ trunk/src/northbridge/amd/amdfam10/Kconfig 2009-12-31 12:56:53 UTC (rev 4994) @@ -52,4 +52,9 @@ default n depends on NORTHBRIDGE_AMD_AMDFAM10 +config BOOTBLOCK_NORTHBRIDGE_INIT + string + default "northbridge/amd/amdfam10/bootblock.c" + depends on NORTHBRIDGE_AMD_AMDFAM10 + source src/northbridge/amd/amdfam10/root_complex/Kconfig Modified: trunk/src/northbridge/amd/amdfam10/Makefile.inc =================================================================== --- trunk/src/northbridge/amd/amdfam10/Makefile.inc 2009-12-28 09:59:44 UTC (rev 4993) +++ trunk/src/northbridge/amd/amdfam10/Makefile.inc 2009-12-31 12:56:53 UTC (rev 4994) @@ -13,33 +13,33 @@ ifdef POST_EVALUATION $(obj)/northbridge/amd/amdfam10/ssdt.c: $(src)/northbridge/amd/amdfam10/ssdt.dsl - iasl -p $(CURDIR)/ssdt -tc $< - perl -pi -e 's/AmlCode/AmlCode_ssdt/g' ssdt.hex - mv ssdt.hex $@ + iasl -p $(obj)/ssdt -tc $< + perl -pi -e 's/AmlCode/AmlCode_ssdt/g' $(obj)/ssdt.hex + mv $(obj)/ssdt.hex $@ $(obj)/northbridge/amd/amdfam10/sspr1.c: $(src)/northbridge/amd/amdfam10/sspr1.dsl - iasl -p $(CURDIR)/sspr1 -tc $< - perl -pi -e 's/AmlCode/AmlCode_sspr1/g' sspr1.hex - mv sspr1.hex $@ + iasl -p $(obj)/sspr1 -tc $< + perl -pi -e 's/AmlCode/AmlCode_sspr1/g' $(obj)/sspr1.hex + mv $(obj)/sspr1.hex $@ $(obj)/northbridge/amd/amdfam10/sspr2.c: $(src)/northbridge/amd/amdfam10/sspr2.dsl - iasl -p $(CURDIR)/sspr2 -tc $< - perl -pi -e 's/AmlCode/AmlCode_sspr2/g' sspr2.hex - mv sspr2.hex $@ + iasl -p $(obj)/sspr2 -tc $< + perl -pi -e 's/AmlCode/AmlCode_sspr2/g' $(obj)/sspr2.hex + mv $(obj)/sspr2.hex $@ $(obj)/northbridge/amd/amdfam10/sspr3.c: $(src)/northbridge/amd/amdfam10/sspr3.dsl - iasl -p $(CURDIR)/sspr3 -tc $< - perl -pi -e 's/AmlCode/AmlCode_sspr3/g' sspr3.hex - mv sspr3.hex $@ + iasl -p $(obj)/sspr3 -tc $< + perl -pi -e 's/AmlCode/AmlCode_sspr3/g' $(obj)/sspr3.hex + mv $(obj)/sspr3.hex $@ $(obj)/northbridge/amd/amdfam10/sspr4.c: $(src)/northbridge/amd/amdfam10/sspr4.dsl - iasl -p $(CURDIR)/sspr4 -tc $< - perl -pi -e 's/AmlCode/AmlCode_sspr4/g' sspr4.hex - mv sspr4.hex $@ + iasl -p $(obj)/sspr4 -tc $< + perl -pi -e 's/AmlCode/AmlCode_sspr4/g' $(obj)/sspr4.hex + mv $(obj)/sspr4.hex $@ $(obj)/northbridge/amd/amdfam10/sspr5.c: $(src)/northbridge/amd/amdfam10/sspr5.dsl - iasl -p $(CURDIR)/sspr5 -tc $< - perl -pi -e 's/AmlCode/AmlCode_sspr5/g' sspr5.hex - mv sspr5.hex $@ + iasl -p $(obj)/sspr5 -tc $< + perl -pi -e 's/AmlCode/AmlCode_sspr5/g' $(obj)/sspr5.hex + mv $(obj)/sspr5.hex $@ endif Added: trunk/src/northbridge/amd/amdfam10/bootblock.c =================================================================== --- trunk/src/northbridge/amd/amdfam10/bootblock.c (rev 0) +++ trunk/src/northbridge/amd/amdfam10/bootblock.c 2009-12-31 12:56:53 UTC (rev 4994) @@ -0,0 +1,12 @@ +#include <arch/io.h> +#include <arch/romcc_io.h> +#include <device/pci_def.h> +#include "northbridge/amd/amdfam10/early_ht.c" + +static void bootblock_northbridge_init(void) { + /* Nothing special needs to be done to find bus 0 */ + /* Allow the HT devices to be found */ + /* mov bsp to bus 0xff when > 8 nodes */ + set_bsp_node_CHtExtNodeCfgEn(); + enumerate_ht_chain(); +} Modified: trunk/src/southbridge/amd/amd8111/Kconfig =================================================================== --- trunk/src/southbridge/amd/amd8111/Kconfig 2009-12-28 09:59:44 UTC (rev 4993) +++ trunk/src/southbridge/amd/amd8111/Kconfig 2009-12-31 12:56:53 UTC (rev 4994) @@ -20,3 +20,7 @@ config SOUTHBRIDGE_AMD_AMD8111 bool +config BOOTBLOCK_SOUTHBRIDGE_INIT + string + default "southbridge/amd/amd8111/bootblock.c" + depends on SOUTHBRIDGE_AMD_AMD8111 Added: trunk/src/southbridge/amd/amd8111/bootblock.c =================================================================== --- trunk/src/southbridge/amd/amd8111/bootblock.c (rev 0) +++ trunk/src/southbridge/amd/amd8111/bootblock.c 2009-12-31 12:56:53 UTC (rev 4994) @@ -0,0 +1,6 @@ +#include "southbridge/amd/amd8111/amd8111_enable_rom.c" + +static void bootblock_southbridge_init(void) { + /* Setup the rom access for 4M */ + amd8111_enable_rom(); +} Modified: trunk/util/compareboard/compareboard =================================================================== --- trunk/util/compareboard/compareboard 2009-12-28 09:59:44 UTC (rev 4993) +++ trunk/util/compareboard/compareboard 2009-12-31 12:56:53 UTC (rev 4994) @@ -103,8 +103,12 @@ -e "/^CONFIG_GDB_STUB / d" \ -e "/^CONFIG_VIDEO_MB / d" \ -e "/^CONFIG_EXPERT / d" \ + -e "/^CONFIG_SSE / d" \ -e "/^CONFIG_VGA_BIOS / d" \ -e "/^CONFIG_WARNINGS_ARE_ERRORS / d" \ + -e "/^CONFIG_TINY_BOOTBLOCK / d" \ + -e "/^CONFIG_BOOTBLOCK_NORTHBRIDGE_INIT / d" \ + -e "/^CONFIG_BOOTBLOCK_SOUTHBRIDGE_INIT / d" \ $A/new > $A/new.filtered normalize $A/old.filtered > $A/old.normalized Modified: trunk/util/romcc/romcc.c =================================================================== --- trunk/util/romcc/romcc.c 2009-12-28 09:59:44 UTC (rev 4993) +++ trunk/util/romcc/romcc.c 2009-12-31 12:56:53 UTC (rev 4994) @@ -3616,6 +3616,7 @@ tm = localtime(&now); register_builtin_macro(state, "__ROMCC__", VERSION_MAJOR); + register_builtin_macro(state, "__PRE_RAM__", VERSION_MAJOR); register_builtin_macro(state, "__ROMCC_MINOR__", VERSION_MINOR); register_builtin_macro(state, "__FILE__", "\"This should be the filename\""); register_builtin_macro(state, "__LINE__", "54321"); @@ -5453,6 +5454,13 @@ name = 0; pp_eat(state, TOK_MINCLUDE); + if (if_eat(state)) { + /* Find the end of the line */ + while((tok = raw_peek(state)) != TOK_EOL) { + raw_eat(state, tok); + } + break; + } tok = peek(state); if (tok == TOK_LIT_STRING) { struct token *tk;

1 0

[PATCH]Implement per chipset rom enable sequence framework, and enable Fam10 build with Kconfig
by Patrick Georgi 31 Dec '09

31 Dec '09

Hi, attached patch implements a framework to do rom enable sequences for the tinybootblock system and implements the rom enable for Fam10. Changes: - Pass BIST through the bootblock (AMD wants this) - Rework walkcbfs to leave two registers unused, so BIST doesn't break romcc on non-mmx/sse systems - Provide enable_rom code for Fam10 northbridge and AMD8111 southbridge and hook it up in amd/serengeti_cheetah_fam10 Build tested on amd/serengeti_cheetah_fam10 and emulation/qemu-x86. QEmu is also boot-tested, the AMD board failed in my last tests. As I'm out of ideas on what might be wrong in Fam10 init, I decided to publish it - it's an improvement over what we have now, right? ;-) Signed-off-by: Patrick Georgi <patrick.georgi(a)coresystems.de> Regards, Patrick

2 2

Coreboot support for FSC D2264
by Bernhard Weiss 29 Dec '09

29 Dec '09

Hi, may someone can help me to get my FSC 2264 board supported by coreboot? The chipset of this board seems to be supported by coreboot v2 Just the board itself is unknown or not listed so far. Any advice where to start is appreciated. Please find below the listings of lspci -tvnn, superiotool -dV, flashrom -V. Additional information can be found in the attached listing of dmidecode. Base Board Information Manufacturer: FUJITSU SIEMENS Product Name: D2264-A1 Version: S26361-D2264-A1 lspci -tvnn: -[0000:00]-+-00.0 Silicon Integrated Systems [SiS] 761/M761 Host [1039:0761] +-01.0-[0000:01]----00.0 Silicon Integrated Systems [SiS] 661/741/760 PCI/AGP or 662/761Gx PCIE VGA Display Adapter [1039:6330] +-02.0 Silicon Integrated Systems [SiS] SiS965 [MuTIOL Media IO] [1039:0965] +-05.0 Silicon Integrated Systems [SiS] 182 SATA/RAID Controller [1039:0182] +-18.0 Advanced Micro Devices [AMD] K8 [Athlon64/Opteron] HyperTransport Technology Configuration [1022:1100] +-18.1 Advanced Micro Devices [AMD] K8 [Athlon64/Opteron] Address Map [1022:1101] +-18.2 Advanced Micro Devices [AMD] K8 [Athlon64/Opteron] DRAM Controller [1022:1102] +-18.3 Advanced Micro Devices [AMD] K8 [Athlon64/Opteron] Miscellaneous Control [1022:1103] \-1f.0-[0000:03]-- superiotool -dV: Found SMSC DME1737 (id=0x78, rev=0x03) at 0x2e flashrom -V: Found chip "SST SST49LF004A/B" (512 KB) at physical address 0xfff80000 Thanks in advance. Greetings Bernhard ___________________________________________________________ Preisknaller: WEB.DE DSL Flatrate für nur 16,99 Euro/mtl.! http://produkte.web.de/go/02/

1 0

Re: [coreboot] M2v-mx_se asus : s3 sleeping broken since rev4625 ruik
by congedete＠voila.fr 29 Dec '09

29 Dec '09

Hello Rudolf, You are right. It works with your patch using buildtarget instead of kconfig. But now, I'm back to the first problem I found: when using kconfig, S3 resume doesn't work and when using buildtarget, I can't boot opensuse because I get the error: initrd is too big. You don't seem to have such a problem, do you ? I really appreciate your help and you (and coreboot team) are a god for me at this time because I come from high level language ie csharp and it's difficult to switch to low level language,asm or linux but I try. Regards. > Message du 28/12/09 à 10h44 > De : "Rudolf Marek" <r.marek(a)assembler.cz> > A : congedete(a)voila.fr > Copie à : coreboot(a)coreboot.org > Objet : Re: [coreboot] M2v-mx_se asus : s3 sleeping broken since rev4625 ruik > > > Hi, > > I can confirm the patch works fine. The board reserves the memory on 31MB as > hole. So, the saving stuff can be left unimplemented for now. > > [ 0.000000] BIOS-e820: 0000000000000000 - 000000000009f000 (usable) > [ 0.000000] BIOS-e820: 000000000009f000 - 00000000000a0000 (reserved) > [ 0.000000] BIOS-e820: 00000000000f0000 - 0000000000100000 (reserved) > [ 0.000000] BIOS-e820: 0000000000100000 - 0000000001f00000 (usable) > [ 0.000000] BIOS-e820: 0000000001f00000 - 0000000002000000 (reserved) > [ 0.000000] BIOS-e820: 0000000002000000 - 0000000017fe7000 (usable) > [ 0.000000] BIOS-e820: 0000000017fe7000 - 0000000018000000 (reserved) > [ 0.000000] BIOS-e820: 00000000e0000000 - 00000000f0000000 (reserved) > > High Tables Base is 17ff0000, but that little missing stuff 0000000017fe7000 - > 17ff0000 is from SeaBIOS I think. > > I used classic buildtarget/abuild method beccause I think Kconfig has bit > different configuration. > > I'm glad that you have chosen this board! It was a lot of work to get it running ;) > > Thanks, > Rudolf > > -- > coreboot mailing list: coreboot(a)coreboot.org > http://www.coreboot.org/mailman/listinfo/coreboot > > ____________________________________________________ Adressez gratuitement vos cartes de voeux virtuelles avec Voila.fr sur http://carte-de-voeux.voila.fr

3 2

KBuild Report [r4993]
by coresystems autobuild service 28 Dec '09

28 Dec '09

[1/116] a-trend/atc-6220 ok. Processing mainboard/a-trend/atc-6220 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_INTEL_SLOT_2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 +CONFIG_TINY_BOOTBLOCK = 0x0 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [2/116] a-trend/atc-6240 ok. Processing mainboard/a-trend/atc-6240 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_INTEL_SLOT_2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 +CONFIG_TINY_BOOTBLOCK = 0x0 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [3/116] abit/be6-ii_v2_0 ok. Processing mainboard/abit/be6-ii_v2_0 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_INTEL_SLOT_2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 +CONFIG_TINY_BOOTBLOCK = 0x0 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [4/116] advantech/pcm-5820 ok. Processing mainboard/advantech/pcm-5820 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_GX1 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x0 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 +CONFIG_TINY_BOOTBLOCK = 0x0 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WRITE_HIGH_TABLES = 0x1 +CONFIG_WRITE_HIGH_TABLES = 0x0 [5/116] amd/db800 ok. Processing mainboard/amd/db800 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_LX = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_IRQ_SLOT_COUNT = 0x4 +CONFIG_IRQ_SLOT_COUNT = 0x6 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 +CONFIG_TINY_BOOTBLOCK = 0x0 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [6/116] amd/dbm690t ok. Processing mainboard/amd/dbm690t (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-4993/targets/amd/dbm690t/Config-abuild.lb ok Creating builddir...ok -CONFIG_GFXUMA = 0x1 +CONFIG_GFXUMA = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_ROM_SIZE = 0x100000 +CONFIG_ROM_SIZE = 0x80000 +CONFIG_TINY_BOOTBLOCK = 0x0 [7/116] amd/norwich ok. Processing mainboard/amd/norwich (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_LX = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 +CONFIG_TINY_BOOTBLOCK = 0x0 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [8/116] amd/pistachio ok. Processing mainboard/amd/pistachio (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-4993/targets/amd/pistachio/Config-abuild.lb ok Creating builddir...ok -CONFIG_APIC_ID_OFFSET = 0x0 +CONFIG_APIC_ID_OFFSET = 0x8 -CONFIG_GFXUMA = 0x1 +CONFIG_GFXUMA = 0x0 +CONFIG_HAVE_ACPI_TABLES = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 -CONFIG_HAVE_MAINBOARD_RESOURCES = 0x1 +CONFIG_HAVE_MAINBOARD_RESOURCES = 0x0 +CONFIG_HAVE_MP_TABLE = 0x1 -CONFIG_HAVE_OPTION_TABLE = 0x0 +CONFIG_HAVE_OPTION_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x1 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x6 -CONFIG_HT_CHAIN_UNITID_BASE = 0x0 +CONFIG_HT_CHAIN_UNITID_BASE = 0xa -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_ROM_SIZE = 0x100000 +CONFIG_ROM_SIZE = 0x80000 -CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x1 +CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x2 +CONFIG_TINY_BOOTBLOCK = 0x0 -CONFIG_WAIT_BEFORE_CPUS_INIT = 0x0 +CONFIG_WAIT_BEFORE_CPUS_INIT = 0x1 [9/116] amd/rumba ok. Processing mainboard/amd/rumba (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_GX2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_HAVE_HIGH_TABLES = 0x0 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 +CONFIG_TINY_BOOTBLOCK = 0x0 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WRITE_HIGH_TABLES = 0x1 +CONFIG_WRITE_HIGH_TABLES = 0x0 [10/116] amd/serengeti_cheetah ok. Processing mainboard/amd/serengeti_cheetah (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-4993/targets/amd/serengeti_cheetah/Config-abuild.lb ok Creating builddir...ok -CONFIG_ACPI_SSDTX_NUM = 0x1 +CONFIG_ACPI_SSDTX_NUM = 0x0 +CONFIG_HAVE_ACPI_TABLES = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_TINY_BOOTBLOCK = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [11/116] amd/serengeti_cheetah_fam10 fail. [12/116] arima/hdama ok. Processing mainboard/arima/hdama (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-4993/targets/arima/hdama/Config-abuild.lb ok Creating builddir...ok -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DCACHE_RAM_BASE = 0xcf000 +CONFIG_DCACHE_RAM_BASE = 0xc8000 -CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0 +CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_DCACHE_RAM_SIZE = 0x8000 -CONFIG_DIMM_SUPPORT = 0x108 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0 +CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x0 +CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x1 +CONFIG_TINY_BOOTBLOCK = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [13/116] artecgroup/dbe61 ok. Processing mainboard/artecgroup/dbe61 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_LX = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 +CONFIG_TINY_BOOTBLOCK = 0x0 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [14/116] asi/mb_5blgp ok. Processing mainboard/asi/mb_5blgp (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_GX1 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x0 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 +CONFIG_TINY_BOOTBLOCK = 0x0 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WRITE_HIGH_TABLES = 0x1 +CONFIG_WRITE_HIGH_TABLES = 0x0 [15/116] asi/mb_5blmp ok. Processing mainboard/asi/mb_5blmp (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_GX1 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_GENERATE_MP_TABLE = 0x0 +CONFIG_GX1_VIDEO = 0x1 +CONFIG_GX1_VIDEOMODE = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x0 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 +CONFIG_SPLASH_GRAPHIC = 0x1 +CONFIG_TINY_BOOTBLOCK = 0x0 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WRITE_HIGH_TABLES = 0x1 +CONFIG_WRITE_HIGH_TABLES = 0x0 [16/116] asus/a8n_e ok. Processing mainboard/asus/a8n_e (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-4993/targets/asus/a8n_e/Config-abuild.lb ok Creating builddir...ok -CONFIG_APIC_ID_OFFSET = 0x0 +CONFIG_APIC_ID_OFFSET = 0x10 -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DCACHE_RAM_BASE = 0xc8000 +CONFIG_DCACHE_RAM_BASE = 0xcf000 -CONFIG_DCACHE_RAM_SIZE = 0x8000 +CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DIMM_SUPPORT = 0x108 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x0 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 +CONFIG_TINY_BOOTBLOCK = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [17/116] asus/a8v-e_se ok. Processing mainboard/asus/a8v-e_se (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DIMM_SUPPORT = 0x108 +CONFIG_EPIA_VT8237R_INIT = 0x0 +CONFIG_HAVE_ACPI_TABLES = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_IRQ_SLOT_COUNT = 0xd -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 +CONFIG_TINY_BOOTBLOCK = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [18/116] asus/m2v-mx_se ok. Processing mainboard/asus/m2v-mx_se (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-4993/targets/asus/m2v-mx_se/Config-abuild.lb ok Creating builddir...ok -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_EPIA_VT8237R_INIT = 0x0 -CONFIG_HAVE_ACPI_RESUME = 0x1 +CONFIG_HAVE_ACPI_RESUME = 0x0 +CONFIG_HAVE_ACPI_TABLES = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 -CONFIG_HAVE_LOW_TABLES = 0x0 +CONFIG_HAVE_LOW_TABLES = 0x1 -CONFIG_HAVE_MAINBOARD_RESOURCES = 0x1 +CONFIG_HAVE_MAINBOARD_RESOURCES = 0x0 -CONFIG_HW_MEM_HOLE_SIZEK = 0x0 +CONFIG_HW_MEM_HOLE_SIZEK = 0x100000 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x1f00000 +CONFIG_RAMBASE = 0x100000 -CONFIG_RAMTOP = 0x2000000 +CONFIG_RAMTOP = 0x200000 +CONFIG_TINY_BOOTBLOCK = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [19/116] asus/mew-am ok. Processing mainboard/asus/mew-am (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 +CONFIG_I810_VIDEO_MB_1MB = 0x1 +CONFIG_I810_VIDEO_MB_512KB = 0x0 +CONFIG_I810_VIDEO_MB_OFF = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 +CONFIG_MMX = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 +CONFIG_TINY_BOOTBLOCK = 0x0 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [20/116] asus/mew-vm ok. Processing mainboard/asus/mew-vm (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 -CONFIG_HAVE_OPTION_TABLE = 0x0 +CONFIG_HAVE_OPTION_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 +CONFIG_I810_VIDEO_MB_1MB = 0x1 +CONFIG_I810_VIDEO_MB_512KB = 0x0 +CONFIG_I810_VIDEO_MB_OFF = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 +CONFIG_MMX = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 +CONFIG_TINY_BOOTBLOCK = 0x0 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [21/116] asus/p2b-d ok. Processing mainboard/asus/p2b-d (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_INTEL_SLOT_2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 +CONFIG_TINY_BOOTBLOCK = 0x0 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [22/116] asus/p2b-ds ok. Processing mainboard/asus/p2b-ds (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_AGP_APERTURE_SIZE = 0x4000000 -CONFIG_APIC_ID_OFFSET = 0x0 +CONFIG_APIC_ID_OFFSET = 0x10 -CONFIG_CPU_ADDR_BITS = 0x24 +CONFIG_CPU_ADDR_BITS = 0x28 -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DCACHE_RAM_BASE = 0xc0000 +CONFIG_DCACHE_RAM_BASE = 0xcf000 -CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0 +CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 -CONFIG_DIMM_SUPPORT = 0x108 -CONFIG_HAVE_HARD_RESET = 0x0 +CONFIG_HAVE_HARD_RESET = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 -CONFIG_HAVE_MOVNTI = 0x0 +CONFIG_HAVE_MOVNTI = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 -CONFIG_HAVE_OPTION_TABLE = 0x0 +CONFIG_HAVE_OPTION_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x0 -CONFIG_HT_CHAIN_UNITID_BASE = 0x1 +CONFIG_HT_CHAIN_UNITID_BASE = 0x0 -CONFIG_HW_MEM_HOLE_SIZEK = 0x0 +CONFIG_HW_MEM_HOLE_SIZEK = 0x100000 -CONFIG_ID_SECTION_OFFSET = 0x10 +CONFIG_ID_SECTION_OFFSET = 0x80 -CONFIG_IRQ_SLOT_COUNT = 0x7 +CONFIG_IRQ_SLOT_COUNT = 0xd -CONFIG_LB_CKS_LOC = 0x7e +CONFIG_LB_CKS_LOC = 0x7b -CONFIG_LB_CKS_RANGE_END = 0x7d +CONFIG_LB_CKS_RANGE_END = 0x7a -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID = 0x0 +CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID = 0x815a -CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x0 +CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1043 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_MEM_TRAIN_SEQ = 0x0 +CONFIG_MEM_TRAIN_SEQ = 0x2 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_ROM_SIZE = 0x40000 +CONFIG_ROM_SIZE = 0x80000 -CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x0 +CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x2 -CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x1 +CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0 +CONFIG_TINY_BOOTBLOCK = 0x0 -CONFIG_UDELAY_TSC = 0x1 +CONFIG_UDELAY_TSC = 0x0 -CONFIG_USE_DCACHE_RAM = 0x0 +CONFIG_USE_DCACHE_RAM = 0x1 -CONFIG_USE_PRINTK_IN_CAR = 0x0 +CONFIG_USE_PRINTK_IN_CAR = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [23/116] asus/p2b-f ok. Processing mainboard/asus/p2b-f (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_INTEL_SLOT_2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 +CONFIG_TINY_BOOTBLOCK = 0x0 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [24/116] asus/p2b ok. Processing mainboard/asus/p2b (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_INTEL_SLOT_2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 +CONFIG_TINY_BOOTBLOCK = 0x0 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [25/116] asus/p3b-f ok. Processing mainboard/asus/p3b-f (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_INTEL_SLOT_2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 +CONFIG_TINY_BOOTBLOCK = 0x0 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [26/116] axus/tc320 ok. Processing mainboard/axus/tc320 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_GX1 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x6 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x0 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x6 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 +CONFIG_TINY_BOOTBLOCK = 0x0 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WRITE_HIGH_TABLES = 0x1 +CONFIG_WRITE_HIGH_TABLES = 0x0 [27/116] azza/pt-6ibd ok. Processing mainboard/azza/pt-6ibd (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_INTEL_SLOT_2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 +CONFIG_TINY_BOOTBLOCK = 0x0 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [28/116] bcom/winnet100 ok. Processing mainboard/bcom/winnet100 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_GX1 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x6 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x0 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x6 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 +CONFIG_TINY_BOOTBLOCK = 0x0 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WRITE_HIGH_TABLES = 0x1 +CONFIG_WRITE_HIGH_TABLES = 0x0 [29/116] bcom/winnetp680 ok. Processing mainboard/bcom/winnetp680 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-4993/targets/bcom/winnetp680/Config-abuild.lb ok Creating builddir...ok +CONFIG_CN700_VIDEO_MB_128MB = 0x0 +CONFIG_CN700_VIDEO_MB_16MB = 0x0 +CONFIG_CN700_VIDEO_MB_32MB = 0x1 +CONFIG_CN700_VIDEO_MB_64MB = 0x0 +CONFIG_CN700_VIDEO_MB_8MB = 0x0 +CONFIG_CN700_VIDEO_MB_OFF = 0x0 +CONFIG_CPU_VIA_C7 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x7 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_EPIA_VT8237R_INIT = 0x0 +CONFIG_FALLBACK_SIZE = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_TINY_BOOTBLOCK = 0x0 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 [30/116] biostar/m6tba ok. Processing mainboard/biostar/m6tba (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_INTEL_SLOT_2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 +CONFIG_TINY_BOOTBLOCK = 0x0 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [31/116] broadcom/blast ok. Processing mainboard/broadcom/blast (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_APIC_ID_OFFSET = 0x0 +CONFIG_APIC_ID_OFFSET = 0x10 -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DIMM_SUPPORT = 0x108 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x1 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x0 -CONFIG_HT_CHAIN_UNITID_BASE = 0x6 +CONFIG_HT_CHAIN_UNITID_BASE = 0x0 -CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0 +CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x1 +CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x2 -CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x1 +CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0 +CONFIG_TINY_BOOTBLOCK = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [32/116] compaq/deskpro_en_sff_p600 ok. Processing mainboard/compaq/deskpro_en_sff_p600 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_INTEL_SLOT_2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 +CONFIG_TINY_BOOTBLOCK = 0x0 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [33/116] dell/s1850 ok. Processing mainboard/dell/s1850 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_HAVE_HARD_RESET = 0x1 +CONFIG_HAVE_HARD_RESET = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 -CONFIG_HAVE_MOVNTI = 0x1 +CONFIG_HAVE_MOVNTI = 0x0 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_IOAPIC = 0x1 +CONFIG_IOAPIC = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAX_CPUS = 0x4 +CONFIG_MAX_CPUS = 0x2 -CONFIG_MAX_PHYSICAL_CPUS = 0x1 +CONFIG_MAX_PHYSICAL_CPUS = 0x2 +CONFIG_MMX = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 +CONFIG_SSE = 0x1 +CONFIG_TINY_BOOTBLOCK = 0x0 -CONFIG_TTYS0_BAUD = 0x4b00 +CONFIG_TTYS0_BAUD = 0x1c200 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [34/116] digitallogic/adl855pc ok. Processing mainboard/digitallogic/adl855pc (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HARD_RESET = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 +CONFIG_MMX = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_SMP = 0x0 +CONFIG_SMP = 0x1 +CONFIG_SSE = 0x1 +CONFIG_TINY_BOOTBLOCK = 0x0 -CONFIG_UDELAY_IO = 0x1 +CONFIG_UDELAY_IO = 0x0 -CONFIG_UDELAY_TSC = 0x0 +CONFIG_UDELAY_TSC = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [35/116] digitallogic/msm586seg ok. Processing mainboard/digitallogic/msm586seg (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-4993/targets/digitallogic/msm586seg/Config-abuild.lb ok Creating builddir...ok +CONFIG_CPU_AMD_SC520 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x0 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_ROM_SIZE = 0x80000 +CONFIG_ROM_SIZE = 0x40000 +CONFIG_TINY_BOOTBLOCK = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_UDELAY_LAPIC = 0x0 +CONFIG_UDELAY_TSC = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [36/116] digitallogic/msm800sev ok. Processing mainboard/digitallogic/msm800sev (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_LX = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_IRQ_SLOT_COUNT = 0x9 +CONFIG_IRQ_SLOT_COUNT = 0x7 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 +CONFIG_TINY_BOOTBLOCK = 0x0 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [37/116] eaglelion/5bcm ok. Processing mainboard/eaglelion/5bcm (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_GX1 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_GX1_VIDEO = 0x1 +CONFIG_GX1_VIDEOMODE = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x0 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 +CONFIG_SPLASH_GRAPHIC = 0x1 +CONFIG_TINY_BOOTBLOCK = 0x0 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WRITE_HIGH_TABLES = 0x1 +CONFIG_WRITE_HIGH_TABLES = 0x0 [38/116] emulation/qemu-x86 ok. Processing mainboard/emulation/qemu-x86 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-4993/targets/emulation/qemu-x86/Config-abuild.lb ok Creating builddir...ok +CONFIG_CPU_EMULATION_QEMU_X86 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0x8f000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_HAVE_HIGH_TABLES = 0x0 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 +CONFIG_TINY_BOOTBLOCK = 0x1 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_UDELAY_LAPIC = 0x0 +CONFIG_UDELAY_TSC = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WRITE_HIGH_TABLES = 0x1 +CONFIG_WRITE_HIGH_TABLES = 0x0 [39/116] gigabyte/ga-6bxc ok. Processing mainboard/gigabyte/ga-6bxc (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_INTEL_SLOT_2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_IRQ_SLOT_COUNT = 0x6 +CONFIG_IRQ_SLOT_COUNT = 0x5 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 +CONFIG_TINY_BOOTBLOCK = 0x0 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [40/116] gigabyte/ga_2761gxdk ok. Processing mainboard/gigabyte/ga_2761gxdk (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-4993/targets/gigabyte/ga_2761gxdk/Config-abuild.lb ok Creating builddir...ok -CONFIG_APIC_ID_OFFSET = 0x10 +CONFIG_APIC_ID_OFFSET = 0x16 -CONFIG_HAVE_FALLBACK_BOOT = 0x1 +CONFIG_HAVE_FALLBACK_BOOT = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x0 -CONFIG_MEM_TRAIN_SEQ = 0x2 +CONFIG_MEM_TRAIN_SEQ = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0 +CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x1 -CONFIG_SERIAL_CPU_INIT = 0x1 +CONFIG_SERIAL_CPU_INIT = 0x0 -CONFIG_SMP = 0x0 +CONFIG_SMP = 0x1 +CONFIG_TINY_BOOTBLOCK = 0x0 -CONFIG_USE_FALLBACK_IMAGE = 0x1 +CONFIG_USE_FALLBACK_IMAGE = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [41/116] gigabyte/m57sli ok. Processing mainboard/gigabyte/m57sli (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-4993/targets/gigabyte/m57sli/Config-abuild.lb ok Creating builddir...ok -CONFIG_APIC_ID_OFFSET = 0x10 +CONFIG_APIC_ID_OFFSET = 0x16 +CONFIG_HAVE_ACPI_TABLES = 0x1 -CONFIG_HAVE_FALLBACK_BOOT = 0x1 +CONFIG_HAVE_FALLBACK_BOOT = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x0 -CONFIG_MEM_TRAIN_SEQ = 0x2 +CONFIG_MEM_TRAIN_SEQ = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0 +CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x1 -CONFIG_SERIAL_CPU_INIT = 0x1 +CONFIG_SERIAL_CPU_INIT = 0x0 -CONFIG_SUPERIO_ITE_IT8716F_OVERRIDE_FANCTL = 0x1 +CONFIG_TINY_BOOTBLOCK = 0x0 -CONFIG_USE_FALLBACK_IMAGE = 0x1 +CONFIG_USE_FALLBACK_IMAGE = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [42/116] hp/dl145_g3 ok. Processing mainboard/hp/dl145_g3 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_APIC_ID_OFFSET = 0x8 +CONFIG_APIC_ID_OFFSET = 0x10 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x1 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x0 -CONFIG_HT_CHAIN_UNITID_BASE = 0x6 +CONFIG_HT_CHAIN_UNITID_BASE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x1 +CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0 -CONFIG_SERIAL_CPU_INIT = 0x0 +CONFIG_SERIAL_CPU_INIT = 0x1 +CONFIG_TINY_BOOTBLOCK = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [43/116] hp/e_vectra_p2706t ok. Processing mainboard/hp/e_vectra_p2706t (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 +CONFIG_I810_VIDEO_MB_1MB = 0x1 +CONFIG_I810_VIDEO_MB_512KB = 0x0 +CONFIG_I810_VIDEO_MB_OFF = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 +CONFIG_MMX = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 +CONFIG_TINY_BOOTBLOCK = 0x0 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 [44/116] ibm/e325 ok. Processing mainboard/ibm/e325 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_APIC_ID_OFFSET = 0x0 +CONFIG_APIC_ID_OFFSET = 0x8 -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DIMM_SUPPORT = 0x108 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x6 -CONFIG_HT_CHAIN_UNITID_BASE = 0x1 +CONFIG_HT_CHAIN_UNITID_BASE = 0xa -CONFIG_HW_MEM_HOLE_SIZEK = 0x0 +CONFIG_HW_MEM_HOLE_SIZEK = 0x100000 -CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0 +CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x0 +CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x2 -CONFIG_SERIAL_CPU_INIT = 0x1 +CONFIG_SERIAL_CPU_INIT = 0x0 -CONFIG_SMP = 0x1 +CONFIG_SMP = 0x0 +CONFIG_TINY_BOOTBLOCK = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WAIT_BEFORE_CPUS_INIT = 0x0 +CONFIG_WAIT_BEFORE_CPUS_INIT = 0x1 [45/116] ibm/e326 ok. Processing mainboard/ibm/e326 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-4993/targets/ibm/e326/Config-abuild.lb ok Creating builddir...ok -CONFIG_APIC_ID_OFFSET = 0x0 +CONFIG_APIC_ID_OFFSET = 0x8 -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DIMM_SUPPORT = 0x108 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x6 -CONFIG_HT_CHAIN_UNITID_BASE = 0x1 +CONFIG_HT_CHAIN_UNITID_BASE = 0xa -CONFIG_HW_MEM_HOLE_SIZEK = 0x0 +CONFIG_HW_MEM_HOLE_SIZEK = 0x100000 -CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0 +CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x0 +CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x2 -CONFIG_SERIAL_CPU_INIT = 0x1 +CONFIG_SERIAL_CPU_INIT = 0x0 +CONFIG_TINY_BOOTBLOCK = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WAIT_BEFORE_CPUS_INIT = 0x0 +CONFIG_WAIT_BEFORE_CPUS_INIT = 0x1 [46/116] iei/juki-511p ok. Processing mainboard/iei/juki-511p (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-4993/targets/iei/juki-511p/Config-abuild.lb ok Creating builddir...ok +CONFIG_CPU_AMD_GX1 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_GX1_VIDEO = 0x1 +CONFIG_GX1_VIDEOMODE = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x0 -CONFIG_HAVE_INIT_TIMER = 0x0 +CONFIG_HAVE_INIT_TIMER = 0x1 -CONFIG_HAVE_OPTION_TABLE = 0x0 +CONFIG_HAVE_OPTION_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 +CONFIG_SPLASH_GRAPHIC = 0x1 +CONFIG_TINY_BOOTBLOCK = 0x0 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_UDELAY_IO = 0x1 +CONFIG_UDELAY_IO = 0x0 -CONFIG_UDELAY_TSC = 0x0 +CONFIG_UDELAY_TSC = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WRITE_HIGH_TABLES = 0x1 +CONFIG_WRITE_HIGH_TABLES = 0x0 [47/116] iei/nova4899r ok. Processing mainboard/iei/nova4899r (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_GX1 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_GX1_VIDEO = 0x1 +CONFIG_GX1_VIDEOMODE = 0x0 -CONFIG_HAVE_FALLBACK_BOOT = 0x0 +CONFIG_HAVE_FALLBACK_BOOT = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x0 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 +CONFIG_SPLASH_GRAPHIC = 0x1 +CONFIG_TINY_BOOTBLOCK = 0x0 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WRITE_HIGH_TABLES = 0x1 +CONFIG_WRITE_HIGH_TABLES = 0x0 [48/116] iei/pcisa-lx-800-r10 ok. Processing mainboard/iei/pcisa-lx-800-r10 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_LX = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 -CONFIG_HAVE_INIT_TIMER = 0x0 +CONFIG_HAVE_INIT_TIMER = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 +CONFIG_TINY_BOOTBLOCK = 0x0 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_UDELAY_IO = 0x1 +CONFIG_UDELAY_IO = 0x0 -CONFIG_UDELAY_TSC = 0x0 +CONFIG_UDELAY_TSC = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [49/116] intel/d945gclf ok. Processing mainboard/intel/d945gclf (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-4993/targets/intel/d945gclf/Config-abuild.lb ok Creating builddir...ok +CONFIG_CPU_INTEL_CORE = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xffed8000 +CONFIG_DCACHE_RAM_BASE = 0xffdf8000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x5 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 -CONFIG_GENERATE_ACPI_TABLES = 0x1 +CONFIG_GENERATE_ACPI_TABLES = 0x0 -CONFIG_GFXUMA = 0x1 +CONFIG_GFXUMA = 0x0 -CONFIG_HAVE_ACPI_RESUME = 0x1 +CONFIG_HAVE_ACPI_RESUME = 0x0 -CONFIG_HAVE_HARD_RESET = 0x1 +CONFIG_HAVE_HARD_RESET = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 -CONFIG_HAVE_INIT_TIMER = 0x1 +CONFIG_HAVE_INIT_TIMER = 0x0 -CONFIG_HAVE_MAINBOARD_RESOURCES = 0x1 +CONFIG_HAVE_MAINBOARD_RESOURCES = 0x0 -CONFIG_HAVE_MOVNTI = 0x1 +CONFIG_HAVE_MOVNTI = 0x0 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HAVE_SMI_HANDLER = 0x1 +CONFIG_HAVE_SMI_HANDLER = 0x0 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_IOAPIC = 0x1 +CONFIG_IOAPIC = 0x0 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_MAX_CPUS = 0x4 +CONFIG_MAX_CPUS = 0x1 +CONFIG_MMX = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_ROM_SIZE = 0x80000 +CONFIG_ROM_SIZE = 0x100000 +CONFIG_SSE = 0x1 +CONFIG_TINY_BOOTBLOCK = 0x0 -CONFIG_USE_DCACHE_RAM = 0x1 +CONFIG_USE_DCACHE_RAM = 0x0 [50/116] intel/eagleheights ok. Processing mainboard/intel/eagleheights (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_INTEL_CORE2 = 0x1 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x7 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_ACPI_TABLES = 0x1 -CONFIG_HAVE_HARD_RESET = 0x1 +CONFIG_HAVE_HARD_RESET = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 -CONFIG_HAVE_MAINBOARD_RESOURCES = 0x1 +CONFIG_HAVE_MAINBOARD_RESOURCES = 0x0 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_IOAPIC = 0x1 +CONFIG_IOAPIC = 0x0 -CONFIG_IRQ_SLOT_COUNT = 0x9 +CONFIG_IRQ_SLOT_COUNT = 0x12 -CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x0 +CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x8086 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_MAX_CPUS = 0x4 +CONFIG_MAX_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 +CONFIG_TINY_BOOTBLOCK = 0x0 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_USE_DCACHE_RAM = 0x1 +CONFIG_USE_DCACHE_RAM = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [51/116] intel/jarrell ok. Processing mainboard/intel/jarrell (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_ATI_RAGE_XL = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_HAVE_HARD_RESET = 0x1 +CONFIG_HAVE_HARD_RESET = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 -CONFIG_HAVE_MOVNTI = 0x1 +CONFIG_HAVE_MOVNTI = 0x0 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_IOAPIC = 0x1 +CONFIG_IOAPIC = 0x0 -CONFIG_IRQ_SLOT_COUNT = 0x12 +CONFIG_IRQ_SLOT_COUNT = 0x9 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAX_REBOOT_CNT = 0x8 +CONFIG_MAX_REBOOT_CNT = 0x3 +CONFIG_MMX = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 +CONFIG_SSE = 0x1 +CONFIG_TINY_BOOTBLOCK = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [52/116] intel/mtarvon ok. Processing mainboard/intel/mtarvon (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x5 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 -CONFIG_HAVE_HARD_RESET = 0x1 +CONFIG_HAVE_HARD_RESET = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_IOAPIC = 0x1 +CONFIG_IOAPIC = 0x0 -CONFIG_LB_CKS_LOC = 0x7e +CONFIG_LB_CKS_LOC = 0x7b -CONFIG_LB_CKS_RANGE_END = 0x7d +CONFIG_LB_CKS_RANGE_END = 0x7a -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x5 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_MAX_CPUS = 0x4 +CONFIG_MAX_CPUS = 0x1 +CONFIG_MMX = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 +CONFIG_SSE = 0x1 +CONFIG_TINY_BOOTBLOCK = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [53/116] intel/truxton ok. Processing mainboard/intel/truxton (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_INTEL_EP80579 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x5 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 -CONFIG_HAVE_HARD_RESET = 0x1 +CONFIG_HAVE_HARD_RESET = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_IOAPIC = 0x1 +CONFIG_IOAPIC = 0x0 -CONFIG_LB_CKS_LOC = 0x7e +CONFIG_LB_CKS_LOC = 0x7b -CONFIG_LB_CKS_RANGE_END = 0x7d +CONFIG_LB_CKS_RANGE_END = 0x7a -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x5 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_MAX_CPUS = 0x4 +CONFIG_MAX_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_SMP = 0x1 +CONFIG_SMP = 0x0 +CONFIG_TINY_BOOTBLOCK = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [54/116] intel/xe7501devkit ok. Processing mainboard/intel/xe7501devkit (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEBUG = 0x1 +CONFIG_DEBUG = 0x0 +CONFIG_HAVE_ACPI_TABLES = 0x1 -CONFIG_HAVE_HARD_RESET = 0x1 +CONFIG_HAVE_HARD_RESET = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 -CONFIG_HAVE_MOVNTI = 0x1 +CONFIG_HAVE_MOVNTI = 0x0 +CONFIG_HAVE_MP_TABLE = 0x1 -CONFIG_HAVE_OPTION_TABLE = 0x0 +CONFIG_HAVE_OPTION_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_IOAPIC = 0x1 +CONFIG_IOAPIC = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_MMX = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 +CONFIG_SSE = 0x1 +CONFIG_TINY_BOOTBLOCK = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [55/116] iwill/dk8_htx ok. Processing mainboard/iwill/dk8_htx (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-4993/targets/iwill/dk8_htx/Config-abuild.lb ok Creating builddir...ok -CONFIG_ACPI_SSDTX_NUM = 0x3 +CONFIG_ACPI_SSDTX_NUM = 0x0 -CONFIG_APIC_ID_OFFSET = 0x10 +CONFIG_APIC_ID_OFFSET = 0x8 -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DCACHE_RAM_BASE = 0xc4000 +CONFIG_DCACHE_RAM_BASE = 0xc8000 -CONFIG_DCACHE_RAM_SIZE = 0xc000 +CONFIG_DCACHE_RAM_SIZE = 0x8000 -CONFIG_DIMM_SUPPORT = 0x108 +CONFIG_HAVE_ACPI_TABLES = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HW_MEM_HOLE_SIZEK = 0x80000 +CONFIG_HW_MEM_HOLE_SIZEK = 0x100000 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_TINY_BOOTBLOCK = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WAIT_BEFORE_CPUS_INIT = 0x0 +CONFIG_WAIT_BEFORE_CPUS_INIT = 0x1 [56/116] iwill/dk8s2 ok. Processing mainboard/iwill/dk8s2 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_APIC_ID_OFFSET = 0x0 +CONFIG_APIC_ID_OFFSET = 0x8 +CONFIG_ATI_RAGE_XL = 0x1 -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DCACHE_RAM_BASE = 0xcf000 +CONFIG_DCACHE_RAM_BASE = 0xc8000 -CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0 +CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_DCACHE_RAM_SIZE = 0x8000 -CONFIG_DIMM_SUPPORT = 0x108 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x6 -CONFIG_HT_CHAIN_UNITID_BASE = 0x1 +CONFIG_HT_CHAIN_UNITID_BASE = 0xa -CONFIG_HW_MEM_HOLE_SIZEK = 0x0 +CONFIG_HW_MEM_HOLE_SIZEK = 0x100000 -CONFIG_IRQ_SLOT_COUNT = 0xc +CONFIG_IRQ_SLOT_COUNT = 0xb -CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0 +CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAX_CPUS = 0x2 +CONFIG_MAX_CPUS = 0x4 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x0 +CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x2 -CONFIG_SERIAL_CPU_INIT = 0x1 +CONFIG_SERIAL_CPU_INIT = 0x0 +CONFIG_TINY_BOOTBLOCK = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WAIT_BEFORE_CPUS_INIT = 0x0 +CONFIG_WAIT_BEFORE_CPUS_INIT = 0x1 [57/116] iwill/dk8x ok. Processing mainboard/iwill/dk8x (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_APIC_ID_OFFSET = 0x0 +CONFIG_APIC_ID_OFFSET = 0x8 -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DCACHE_RAM_BASE = 0xcf000 +CONFIG_DCACHE_RAM_BASE = 0xc8000 -CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0 +CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_DCACHE_RAM_SIZE = 0x8000 -CONFIG_DIMM_SUPPORT = 0x108 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x6 -CONFIG_HT_CHAIN_UNITID_BASE = 0x1 +CONFIG_HT_CHAIN_UNITID_BASE = 0xa -CONFIG_HW_MEM_HOLE_SIZEK = 0x0 +CONFIG_HW_MEM_HOLE_SIZEK = 0x100000 -CONFIG_IRQ_SLOT_COUNT = 0x9 +CONFIG_IRQ_SLOT_COUNT = 0xb -CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0 +CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAX_CPUS = 0x2 +CONFIG_MAX_CPUS = 0x4 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x0 +CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x2 -CONFIG_SERIAL_CPU_INIT = 0x1 +CONFIG_SERIAL_CPU_INIT = 0x0 +CONFIG_TINY_BOOTBLOCK = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WAIT_BEFORE_CPUS_INIT = 0x0 +CONFIG_WAIT_BEFORE_CPUS_INIT = 0x1 [58/116] jetway/j7f24 ok. Processing mainboard/jetway/j7f24 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-4993/targets/jetway/j7f24/Config-abuild.lb ok Creating builddir...ok +CONFIG_CN700_VIDEO_MB_128MB = 0x0 +CONFIG_CN700_VIDEO_MB_16MB = 0x0 +CONFIG_CN700_VIDEO_MB_32MB = 0x1 +CONFIG_CN700_VIDEO_MB_64MB = 0x0 +CONFIG_CN700_VIDEO_MB_8MB = 0x0 +CONFIG_CN700_VIDEO_MB_OFF = 0x0 +CONFIG_CPU_VIA_C7 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x7 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_EPIA_VT8237R_INIT = 0x0 +CONFIG_FALLBACK_SIZE = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 -CONFIG_HAVE_OPTION_TABLE = 0x0 +CONFIG_HAVE_OPTION_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_TINY_BOOTBLOCK = 0x0 -CONFIG_UDELAY_TSC = 0x1 +CONFIG_UDELAY_TSC = 0x0 [59/116] kontron/986lcd-m ok. Processing mainboard/kontron/986lcd-m (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-4993/targets/kontron/986lcd-m/Config-abuild.lb ok Creating builddir...ok +CONFIG_CPU_INTEL_CORE = 0x1 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x5 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_ACPI_SLIC = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_MAX_CPUS = 0x4 +CONFIG_MAX_CPUS = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 +CONFIG_TINY_BOOTBLOCK = 0x0 [60/116] kontron/kt690 ok. Processing mainboard/kontron/kt690 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-4993/targets/kontron/kt690/Config-abuild.lb ok Creating builddir...ok +CONFIG_HAVE_ACPI_TABLES = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_ROM_SIZE = 0x100000 +CONFIG_ROM_SIZE = 0x80000 +CONFIG_TINY_BOOTBLOCK = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [61/116] lippert/frontrunner ok. Processing mainboard/lippert/frontrunner (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_GX2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_HAVE_HIGH_TABLES = 0x0 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 +CONFIG_TINY_BOOTBLOCK = 0x0 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WRITE_HIGH_TABLES = 0x1 +CONFIG_WRITE_HIGH_TABLES = 0x0 [62/116] lippert/roadrunner-lx ok. Processing mainboard/lippert/roadrunner-lx (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_LX = 0x1 -CONFIG_DEBUG = 0x1 +CONFIG_DEBUG = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 +CONFIG_TINY_BOOTBLOCK = 0x0 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [63/116] lippert/spacerunner-lx ok. Processing mainboard/lippert/spacerunner-lx (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_LX = 0x1 -CONFIG_DEBUG = 0x1 +CONFIG_DEBUG = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 +CONFIG_TINY_BOOTBLOCK = 0x0 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [64/116] mitac/6513wu ok. Processing mainboard/mitac/6513wu (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x7 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 +CONFIG_I810_VIDEO_MB_1MB = 0x1 +CONFIG_I810_VIDEO_MB_512KB = 0x0 +CONFIG_I810_VIDEO_MB_OFF = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 +CONFIG_MMX = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 +CONFIG_TINY_BOOTBLOCK = 0x0 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [65/116] msi/ms6119 ok. Processing mainboard/msi/ms6119 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_INTEL_SLOT_2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x0 +CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1462 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 +CONFIG_TINY_BOOTBLOCK = 0x0 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [66/116] msi/ms6147 ok. Processing mainboard/msi/ms6147 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_INTEL_SLOT_2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x0 +CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1462 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 +CONFIG_TINY_BOOTBLOCK = 0x0 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [67/116] msi/ms6156 ok. Processing mainboard/msi/ms6156 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_INTEL_SLOT_2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x0 +CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1462 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 +CONFIG_TINY_BOOTBLOCK = 0x0 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [68/116] msi/ms6178 ok. Processing mainboard/msi/ms6178 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 +CONFIG_I810_VIDEO_MB_1MB = 0x1 +CONFIG_I810_VIDEO_MB_512KB = 0x0 +CONFIG_I810_VIDEO_MB_OFF = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x0 +CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1462 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 +CONFIG_MMX = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 +CONFIG_TINY_BOOTBLOCK = 0x0 -CONFIG_UDELAY_IO = 0x0 +CONFIG_UDELAY_IO = 0x1 -CONFIG_UDELAY_TSC = 0x1 +CONFIG_UDELAY_TSC = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [69/116] msi/ms7135 ok. Processing mainboard/msi/ms7135 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-4993/targets/msi/ms7135/Config-abuild.lb ok Creating builddir...ok -CONFIG_APIC_ID_OFFSET = 0x0 +CONFIG_APIC_ID_OFFSET = 0x10 -CONFIG_DCACHE_RAM_BASE = 0xc8000 +CONFIG_DCACHE_RAM_BASE = 0xcf000 -CONFIG_DCACHE_RAM_SIZE = 0x8000 +CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DIMM_SUPPORT = 0x108 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_MEM_TRAIN_SEQ = 0x2 +CONFIG_MEM_TRAIN_SEQ = 0x0 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 +CONFIG_TINY_BOOTBLOCK = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [70/116] msi/ms7260 ok. Processing mainboard/msi/ms7260 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-4993/targets/msi/ms7260/Config-abuild.lb ok Creating builddir...ok -CONFIG_APIC_ID_OFFSET = 0x10 +CONFIG_APIC_ID_OFFSET = 0x16 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 -CONFIG_HAVE_FALLBACK_BOOT = 0x1 +CONFIG_HAVE_FALLBACK_BOOT = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x0 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_MEM_TRAIN_SEQ = 0x2 +CONFIG_MEM_TRAIN_SEQ = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0 +CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x1 -CONFIG_SERIAL_CPU_INIT = 0x1 +CONFIG_SERIAL_CPU_INIT = 0x0 +CONFIG_TINY_BOOTBLOCK = 0x0 -CONFIG_USE_FALLBACK_IMAGE = 0x1 +CONFIG_USE_FALLBACK_IMAGE = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [71/116] msi/ms9185 ok. Processing mainboard/msi/ms9185 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-4993/targets/msi/ms9185/Config-abuild.lb ok Creating builddir...ok -CONFIG_APIC_ID_OFFSET = 0x8 +CONFIG_APIC_ID_OFFSET = 0x10 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x1 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x0 -CONFIG_HT_CHAIN_UNITID_BASE = 0x6 +CONFIG_HT_CHAIN_UNITID_BASE = 0x0 -CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1022 +CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1462 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x1 +CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0 -CONFIG_SERIAL_CPU_INIT = 0x0 +CONFIG_SERIAL_CPU_INIT = 0x1 +CONFIG_TINY_BOOTBLOCK = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [72/116] msi/ms9282 ok. Processing mainboard/msi/ms9282 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-4993/targets/msi/ms9282/Config-abuild.lb ok Creating builddir...ok -CONFIG_APIC_ID_OFFSET = 0x10 +CONFIG_APIC_ID_OFFSET = 0x16 -CONFIG_ENABLE_APIC_EXT_ID = 0x1 +CONFIG_ENABLE_APIC_EXT_ID = 0x0 -CONFIG_HAVE_FALLBACK_BOOT = 0x1 +CONFIG_HAVE_FALLBACK_BOOT = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x0 -CONFIG_HW_MEM_HOLE_SIZEK = 0x0 +CONFIG_HW_MEM_HOLE_SIZEK = 0x100000 -CONFIG_MAX_CPUS = 0x4 +CONFIG_MAX_CPUS = 0x2 -CONFIG_MAX_PHYSICAL_CPUS = 0x2 +CONFIG_MAX_PHYSICAL_CPUS = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x1 +CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x2 -CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0 +CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x1 -CONFIG_SERIAL_CPU_INIT = 0x1 +CONFIG_SERIAL_CPU_INIT = 0x0 +CONFIG_TINY_BOOTBLOCK = 0x0 -CONFIG_USE_FALLBACK_IMAGE = 0x1 +CONFIG_USE_FALLBACK_IMAGE = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [73/116] nec/powermate2000 ok. Processing mainboard/nec/powermate2000 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 +CONFIG_I810_VIDEO_MB_1MB = 0x1 +CONFIG_I810_VIDEO_MB_512KB = 0x0 +CONFIG_I810_VIDEO_MB_OFF = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 +CONFIG_MMX = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 +CONFIG_TINY_BOOTBLOCK = 0x0 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [74/116] newisys/khepri ok. Processing mainboard/newisys/khepri (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_APIC_ID_OFFSET = 0x0 +CONFIG_APIC_ID_OFFSET = 0x10 -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0 +CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000 -CONFIG_DIMM_SUPPORT = 0x108 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x0 -CONFIG_HT_CHAIN_UNITID_BASE = 0x1 +CONFIG_HT_CHAIN_UNITID_BASE = 0x0 -CONFIG_IRQ_SLOT_COUNT = 0x9 +CONFIG_IRQ_SLOT_COUNT = 0xb -CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0 +CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x0 +CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x2 -CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x1 +CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0 +CONFIG_TINY_BOOTBLOCK = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [75/116] nvidia/l1_2pvv ok. Processing mainboard/nvidia/l1_2pvv (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-4993/targets/nvidia/l1_2pvv/Config-abuild.lb ok Creating builddir...ok -CONFIG_APIC_ID_OFFSET = 0x10 +CONFIG_APIC_ID_OFFSET = 0x16 -CONFIG_HAVE_FALLBACK_BOOT = 0x1 +CONFIG_HAVE_FALLBACK_BOOT = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x0 -CONFIG_MAX_CPUS = 0x4 +CONFIG_MAX_CPUS = 0x2 -CONFIG_MAX_PHYSICAL_CPUS = 0x2 +CONFIG_MAX_PHYSICAL_CPUS = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0 +CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x1 -CONFIG_SERIAL_CPU_INIT = 0x1 +CONFIG_SERIAL_CPU_INIT = 0x0 +CONFIG_TINY_BOOTBLOCK = 0x0 -CONFIG_USE_FALLBACK_IMAGE = 0x1 +CONFIG_USE_FALLBACK_IMAGE = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WAIT_BEFORE_CPUS_INIT = 0x1 +CONFIG_WAIT_BEFORE_CPUS_INIT = 0x0 [76/116] olpc/btest ok. Processing mainboard/olpc/btest (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_GX2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_HAVE_HIGH_TABLES = 0x0 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 +CONFIG_TINY_BOOTBLOCK = 0x0 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WRITE_HIGH_TABLES = 0x1 +CONFIG_WRITE_HIGH_TABLES = 0x0 [77/116] olpc/rev_a ok. Processing mainboard/olpc/rev_a (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_GX2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_HAVE_HIGH_TABLES = 0x0 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 +CONFIG_TINY_BOOTBLOCK = 0x0 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WRITE_HIGH_TABLES = 0x1 +CONFIG_WRITE_HIGH_TABLES = 0x0 [78/116] pcengines/alix1c ok. Processing mainboard/pcengines/alix1c (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_LX = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 +CONFIG_TINY_BOOTBLOCK = 0x0 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [79/116] rca/rm4100 ok. Processing mainboard/rca/rm4100 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-4993/targets/rca/rm4100/Config-abuild.lb ok Creating builddir...ok -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HARD_RESET = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 +CONFIG_I830_VIDEO_MB_1MB = 0x0 +CONFIG_I830_VIDEO_MB_512KB = 0x0 +CONFIG_I830_VIDEO_MB_8MB = 0x1 +CONFIG_I830_VIDEO_MB_OFF = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 +CONFIG_MMX = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 +CONFIG_TINY_BOOTBLOCK = 0x0 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [80/116] soyo/sy-6ba-plus-iii ok. Processing mainboard/soyo/sy-6ba-plus-iii (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_INTEL_SLOT_2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 +CONFIG_TINY_BOOTBLOCK = 0x0 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [81/116] sunw/ultra40 ok. Processing mainboard/sunw/ultra40 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0 +CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000 -CONFIG_DIMM_SUPPORT = 0x108 -CONFIG_ENABLE_APIC_EXT_ID = 0x1 +CONFIG_ENABLE_APIC_EXT_ID = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x0 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 +CONFIG_TINY_BOOTBLOCK = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [82/116] supermicro/h8dme ok. Processing mainboard/supermicro/h8dme (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-4993/targets/supermicro/h8dme/Config-abuild.lb ok Creating builddir...ok -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 -CONFIG_HAVE_LOW_TABLES = 0x0 +CONFIG_HAVE_LOW_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x0 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_SERIAL_CPU_INIT = 0x0 +CONFIG_SERIAL_CPU_INIT = 0x1 +CONFIG_TINY_BOOTBLOCK = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WAIT_BEFORE_CPUS_INIT = 0x1 +CONFIG_WAIT_BEFORE_CPUS_INIT = 0x0 [83/116] supermicro/h8dmr ok. Processing mainboard/supermicro/h8dmr (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-4993/targets/supermicro/h8dmr/Config-abuild.lb ok Creating builddir...ok +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x0 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_ROM_SIZE = 0x100000 +CONFIG_ROM_SIZE = 0x80000 -CONFIG_SERIAL_CPU_INIT = 0x0 +CONFIG_SERIAL_CPU_INIT = 0x1 +CONFIG_TINY_BOOTBLOCK = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WAIT_BEFORE_CPUS_INIT = 0x1 +CONFIG_WAIT_BEFORE_CPUS_INIT = 0x0 [84/116] supermicro/h8dmr_fam10 fail. [85/116] supermicro/x6dai_g ok. Processing mainboard/supermicro/x6dai_g (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_HAVE_HARD_RESET = 0x1 +CONFIG_HAVE_HARD_RESET = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 -CONFIG_HAVE_MOVNTI = 0x1 +CONFIG_HAVE_MOVNTI = 0x0 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_IOAPIC = 0x1 +CONFIG_IOAPIC = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_MMX = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 +CONFIG_SSE = 0x1 +CONFIG_TINY_BOOTBLOCK = 0x0 -CONFIG_UDELAY_TSC = 0x1 +CONFIG_UDELAY_TSC = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [86/116] supermicro/x6dhe_g ok. Processing mainboard/supermicro/x6dhe_g (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_HAVE_HARD_RESET = 0x1 +CONFIG_HAVE_HARD_RESET = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 -CONFIG_HAVE_MOVNTI = 0x1 +CONFIG_HAVE_MOVNTI = 0x0 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_IOAPIC = 0x1 +CONFIG_IOAPIC = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_MMX = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 +CONFIG_SSE = 0x1 +CONFIG_TINY_BOOTBLOCK = 0x0 -CONFIG_UDELAY_TSC = 0x1 +CONFIG_UDELAY_TSC = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [87/116] supermicro/x6dhe_g2 ok. Processing mainboard/supermicro/x6dhe_g2 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_HAVE_HARD_RESET = 0x1 +CONFIG_HAVE_HARD_RESET = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 -CONFIG_HAVE_MOVNTI = 0x1 +CONFIG_HAVE_MOVNTI = 0x0 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_IOAPIC = 0x1 +CONFIG_IOAPIC = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_MMX = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 +CONFIG_SSE = 0x1 +CONFIG_TINY_BOOTBLOCK = 0x0 -CONFIG_UDELAY_TSC = 0x1 +CONFIG_UDELAY_TSC = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [88/116] supermicro/x6dhr_ig ok. Processing mainboard/supermicro/x6dhr_ig (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_HAVE_HARD_RESET = 0x1 +CONFIG_HAVE_HARD_RESET = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 -CONFIG_HAVE_MOVNTI = 0x1 +CONFIG_HAVE_MOVNTI = 0x0 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_IOAPIC = 0x1 +CONFIG_IOAPIC = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_MMX = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 +CONFIG_SSE = 0x1 +CONFIG_TINY_BOOTBLOCK = 0x0 -CONFIG_UDELAY_TSC = 0x1 +CONFIG_UDELAY_TSC = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [89/116] supermicro/x6dhr_ig2 ok. Processing mainboard/supermicro/x6dhr_ig2 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_HAVE_HARD_RESET = 0x1 +CONFIG_HAVE_HARD_RESET = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 -CONFIG_HAVE_MOVNTI = 0x1 +CONFIG_HAVE_MOVNTI = 0x0 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_IOAPIC = 0x1 +CONFIG_IOAPIC = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_MMX = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 +CONFIG_SSE = 0x1 +CONFIG_TINY_BOOTBLOCK = 0x0 -CONFIG_UDELAY_TSC = 0x1 +CONFIG_UDELAY_TSC = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [90/116] technexion/tim5690 ok. Processing mainboard/technexion/tim5690 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-4993/targets/technexion/tim5690/Config-abuild.lb ok Creating builddir...ok +CONFIG_HAVE_ACPI_TABLES = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_TINY_BOOTBLOCK = 0x0 [91/116] technexion/tim8690 ok. Processing mainboard/technexion/tim8690 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-4993/targets/technexion/tim8690/Config-abuild.lb ok Creating builddir...ok -CONFIG_APIC_ID_OFFSET = 0x0 +CONFIG_APIC_ID_OFFSET = 0x8 -CONFIG_GFXUMA = 0x1 +CONFIG_GFXUMA = 0x0 +CONFIG_HAVE_ACPI_TABLES = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 -CONFIG_HAVE_MAINBOARD_RESOURCES = 0x1 +CONFIG_HAVE_MAINBOARD_RESOURCES = 0x0 +CONFIG_HAVE_MP_TABLE = 0x1 -CONFIG_HAVE_OPTION_TABLE = 0x0 +CONFIG_HAVE_OPTION_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x1 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x6 -CONFIG_HT_CHAIN_UNITID_BASE = 0x0 +CONFIG_HT_CHAIN_UNITID_BASE = 0xa -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x1 +CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x2 +CONFIG_TINY_BOOTBLOCK = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WAIT_BEFORE_CPUS_INIT = 0x0 +CONFIG_WAIT_BEFORE_CPUS_INIT = 0x1 [92/116] technologic/ts5300 ok. Processing mainboard/technologic/ts5300 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-4993/targets/technologic/ts5300/Config-abuild.lb ok Creating builddir...ok +CONFIG_CPU_AMD_SC520 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x0 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_ROM_SIZE = 0x20000 +CONFIG_ROM_SIZE = 0x40000 +CONFIG_TINY_BOOTBLOCK = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 -CONFIG_TTYS0_BASE = 0x2f8 +CONFIG_TTYS0_BASE = 0x3f8 +CONFIG_UDELAY_LAPIC = 0x0 +CONFIG_UDELAY_TSC = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [93/116] televideo/tc7020 ok. Processing mainboard/televideo/tc7020 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_GX1 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x6 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x0 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x6 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 +CONFIG_TINY_BOOTBLOCK = 0x0 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WRITE_HIGH_TABLES = 0x1 +CONFIG_WRITE_HIGH_TABLES = 0x0 [94/116] thomson/ip1000 ok. Processing mainboard/thomson/ip1000 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-4993/targets/thomson/ip1000/Config-abuild.lb ok Creating builddir...ok -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HARD_RESET = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 +CONFIG_I830_VIDEO_MB_1MB = 0x0 +CONFIG_I830_VIDEO_MB_512KB = 0x0 +CONFIG_I830_VIDEO_MB_8MB = 0x1 +CONFIG_I830_VIDEO_MB_OFF = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 +CONFIG_MMX = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 +CONFIG_TINY_BOOTBLOCK = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [95/116] tyan/s1846 ok. Processing mainboard/tyan/s1846 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_INTEL_SLOT_2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 +CONFIG_TINY_BOOTBLOCK = 0x0 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [96/116] tyan/s2735 ok. Processing mainboard/tyan/s2735 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_HAVE_HARD_RESET = 0x1 +CONFIG_HAVE_HARD_RESET = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 -CONFIG_HAVE_MOVNTI = 0x1 +CONFIG_HAVE_MOVNTI = 0x0 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_IOAPIC = 0x1 +CONFIG_IOAPIC = 0x0 +CONFIG_MMX = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_SERIAL_CPU_INIT = 0x0 +CONFIG_SERIAL_CPU_INIT = 0x1 +CONFIG_SSE = 0x1 +CONFIG_TINY_BOOTBLOCK = 0x0 -CONFIG_USE_PRINTK_IN_CAR = 0x1 +CONFIG_USE_PRINTK_IN_CAR = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [97/116] tyan/s2850 ok. Processing mainboard/tyan/s2850 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DCACHE_RAM_BASE = 0xcf000 +CONFIG_DCACHE_RAM_BASE = 0xc8000 -CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0 +CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_DCACHE_RAM_SIZE = 0x8000 -CONFIG_DIMM_SUPPORT = 0x108 -CONFIG_HAVE_HARD_RESET = 0x1 +CONFIG_HAVE_HARD_RESET = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_IOAPIC = 0x1 +CONFIG_IOAPIC = 0x0 -CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0 +CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 +CONFIG_TINY_BOOTBLOCK = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [98/116] tyan/s2875 ok. Processing mainboard/tyan/s2875 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DCACHE_RAM_BASE = 0xcf000 +CONFIG_DCACHE_RAM_BASE = 0xc8000 -CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0 +CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_DCACHE_RAM_SIZE = 0x8000 -CONFIG_DIMM_SUPPORT = 0x108 -CONFIG_HAVE_HARD_RESET = 0x1 +CONFIG_HAVE_HARD_RESET = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0 +CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 +CONFIG_TINY_BOOTBLOCK = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [99/116] tyan/s2880 ok. Processing mainboard/tyan/s2880 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_APIC_ID_OFFSET = 0x0 +CONFIG_APIC_ID_OFFSET = 0x10 -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DCACHE_RAM_BASE = 0xcf000 +CONFIG_DCACHE_RAM_BASE = 0xc8000 -CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0 +CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_DCACHE_RAM_SIZE = 0x8000 -CONFIG_DIMM_SUPPORT = 0x108 -CONFIG_HAVE_HARD_RESET = 0x1 +CONFIG_HAVE_HARD_RESET = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x6 -CONFIG_HT_CHAIN_UNITID_BASE = 0x1 +CONFIG_HT_CHAIN_UNITID_BASE = 0xa -CONFIG_IOAPIC = 0x1 +CONFIG_IOAPIC = 0x0 -CONFIG_IRQ_SLOT_COUNT = 0xd +CONFIG_IRQ_SLOT_COUNT = 0x9 -CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0 +CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAX_CPUS = 0x2 +CONFIG_MAX_CPUS = 0x4 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x0 +CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x2 -CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x1 +CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0 +CONFIG_TINY_BOOTBLOCK = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [100/116] tyan/s2881 ok. Processing mainboard/tyan/s2881 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_APIC_ID_OFFSET = 0x0 +CONFIG_APIC_ID_OFFSET = 0x10 -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DCACHE_RAM_BASE = 0xcf000 +CONFIG_DCACHE_RAM_BASE = 0xc8000 -CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0 +CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_DCACHE_RAM_SIZE = 0x8000 -CONFIG_DIMM_SUPPORT = 0x108 -CONFIG_HAVE_HARD_RESET = 0x1 +CONFIG_HAVE_HARD_RESET = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_IOAPIC = 0x1 +CONFIG_IOAPIC = 0x0 -CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0 +CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x0 +CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x2 -CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x1 +CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0 +CONFIG_TINY_BOOTBLOCK = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [101/116] tyan/s2882 ok. Processing mainboard/tyan/s2882 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_APIC_ID_OFFSET = 0x0 +CONFIG_APIC_ID_OFFSET = 0x10 -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DCACHE_RAM_BASE = 0xcf000 +CONFIG_DCACHE_RAM_BASE = 0xc8000 -CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0 +CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_DCACHE_RAM_SIZE = 0x8000 -CONFIG_DIMM_SUPPORT = 0x108 -CONFIG_HAVE_HARD_RESET = 0x1 +CONFIG_HAVE_HARD_RESET = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x6 -CONFIG_HT_CHAIN_UNITID_BASE = 0x1 +CONFIG_HT_CHAIN_UNITID_BASE = 0xa -CONFIG_IOAPIC = 0x1 +CONFIG_IOAPIC = 0x0 -CONFIG_IRQ_SLOT_COUNT = 0xf +CONFIG_IRQ_SLOT_COUNT = 0x9 -CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0 +CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x0 +CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x2 -CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x1 +CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0 +CONFIG_TINY_BOOTBLOCK = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [102/116] tyan/s2885 ok. Processing mainboard/tyan/s2885 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DCACHE_RAM_BASE = 0xcf000 +CONFIG_DCACHE_RAM_BASE = 0xc8000 -CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0 +CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_DCACHE_RAM_SIZE = 0x8000 -CONFIG_DIMM_SUPPORT = 0x108 -CONFIG_ENABLE_APIC_EXT_ID = 0x1 +CONFIG_ENABLE_APIC_EXT_ID = 0x0 -CONFIG_HAVE_HARD_RESET = 0x1 +CONFIG_HAVE_HARD_RESET = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_IOAPIC = 0x1 +CONFIG_IOAPIC = 0x0 -CONFIG_IRQ_SLOT_COUNT = 0xb +CONFIG_IRQ_SLOT_COUNT = 0x9 -CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0 +CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x1 +CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0 +CONFIG_TINY_BOOTBLOCK = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [103/116] tyan/s2891 ok. Processing mainboard/tyan/s2891 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-4993/targets/tyan/s2891/Config-abuild.lb ok Creating builddir...ok -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DCACHE_RAM_BASE = 0xcf000 +CONFIG_DCACHE_RAM_BASE = 0xc8000 -CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0 +CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_DCACHE_RAM_SIZE = 0x8000 -CONFIG_DIMM_SUPPORT = 0x108 +CONFIG_HAVE_ACPI_TABLES = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0 +CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_ROM_SIZE = 0x80000 +CONFIG_ROM_SIZE = 0x100000 -CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x1 +CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0 +CONFIG_TINY_BOOTBLOCK = 0x0 [104/116] tyan/s2892 ok. Processing mainboard/tyan/s2892 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-4993/targets/tyan/s2892/Config-abuild.lb ok Creating builddir...ok -CONFIG_APIC_ID_OFFSET = 0x0 +CONFIG_APIC_ID_OFFSET = 0x10 -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DCACHE_RAM_BASE = 0xcf000 +CONFIG_DCACHE_RAM_BASE = 0xc8000 -CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0 +CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_DCACHE_RAM_SIZE = 0x8000 -CONFIG_DIMM_SUPPORT = 0x108 +CONFIG_HAVE_ACPI_TABLES = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0 +CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 +CONFIG_TINY_BOOTBLOCK = 0x0 [105/116] tyan/s2895 ok. Processing mainboard/tyan/s2895 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-4993/targets/tyan/s2895/Config-abuild.lb ok Creating builddir...ok -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DCACHE_RAM_BASE = 0xcf000 +CONFIG_DCACHE_RAM_BASE = 0xc8000 -CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0 +CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_DCACHE_RAM_SIZE = 0x8000 -CONFIG_DIMM_SUPPORT = 0x108 +CONFIG_HAVE_ACPI_TABLES = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_SERIAL_CPU_INIT = 0x0 +CONFIG_SERIAL_CPU_INIT = 0x1 +CONFIG_TINY_BOOTBLOCK = 0x0 [106/116] tyan/s2912 ok. Processing mainboard/tyan/s2912 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-4993/targets/tyan/s2912/Config-abuild.lb ok Creating builddir...ok -CONFIG_ACPI_SSDTX_NUM = 0x3 +CONFIG_ACPI_SSDTX_NUM = 0x0 -CONFIG_APIC_ID_OFFSET = 0x10 +CONFIG_APIC_ID_OFFSET = 0x16 -CONFIG_HAVE_FALLBACK_BOOT = 0x1 +CONFIG_HAVE_FALLBACK_BOOT = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x0 -CONFIG_MAX_CPUS = 0x4 +CONFIG_MAX_CPUS = 0x2 -CONFIG_MAX_PHYSICAL_CPUS = 0x2 +CONFIG_MAX_PHYSICAL_CPUS = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0 +CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x1 -CONFIG_SERIAL_CPU_INIT = 0x1 +CONFIG_SERIAL_CPU_INIT = 0x0 +CONFIG_TINY_BOOTBLOCK = 0x0 -CONFIG_USE_FALLBACK_IMAGE = 0x1 +CONFIG_USE_FALLBACK_IMAGE = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WAIT_BEFORE_CPUS_INIT = 0x1 +CONFIG_WAIT_BEFORE_CPUS_INIT = 0x0 [107/116] tyan/s2912_fam10 fail. [108/116] tyan/s4880 ok. Processing mainboard/tyan/s4880 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0 +CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000 -CONFIG_DIMM_SUPPORT = 0x108 -CONFIG_ENABLE_APIC_EXT_ID = 0x1 +CONFIG_ENABLE_APIC_EXT_ID = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x0 -CONFIG_HT_CHAIN_UNITID_BASE = 0x1 +CONFIG_HT_CHAIN_UNITID_BASE = 0x0 -CONFIG_IRQ_SLOT_COUNT = 0x16 +CONFIG_IRQ_SLOT_COUNT = 0xb -CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0 +CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1 -CONFIG_MAX_CPUS = 0x8 +CONFIG_MAX_CPUS = 0x4 -CONFIG_MAX_PHYSICAL_CPUS = 0x4 +CONFIG_MAX_PHYSICAL_CPUS = 0x2 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x0 +CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x2 -CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x1 +CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0 +CONFIG_TINY_BOOTBLOCK = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [109/116] tyan/s4882 ok. Processing mainboard/tyan/s4882 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0 +CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000 -CONFIG_DIMM_SUPPORT = 0x108 -CONFIG_ENABLE_APIC_EXT_ID = 0x1 +CONFIG_ENABLE_APIC_EXT_ID = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x0 -CONFIG_HT_CHAIN_UNITID_BASE = 0x1 +CONFIG_HT_CHAIN_UNITID_BASE = 0x0 -CONFIG_IRQ_SLOT_COUNT = 0x16 +CONFIG_IRQ_SLOT_COUNT = 0xb -CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0 +CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1 -CONFIG_MAX_CPUS = 0x8 +CONFIG_MAX_CPUS = 0x4 -CONFIG_MAX_PHYSICAL_CPUS = 0x4 +CONFIG_MAX_PHYSICAL_CPUS = 0x2 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x2000 +CONFIG_RAMBASE = 0x100000 -CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x0 +CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x2 -CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x1 +CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0 +CONFIG_TINY_BOOTBLOCK = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [110/116] via/epia-cn ok. Processing mainboard/via/epia-cn (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-4993/targets/via/epia-cn/Config-abuild.lb ok Creating builddir...ok +CONFIG_CN700_VIDEO_MB_128MB = 0x0 +CONFIG_CN700_VIDEO_MB_16MB = 0x0 +CONFIG_CN700_VIDEO_MB_32MB = 0x1 +CONFIG_CN700_VIDEO_MB_64MB = 0x0 +CONFIG_CN700_VIDEO_MB_8MB = 0x0 +CONFIG_CN700_VIDEO_MB_OFF = 0x0 +CONFIG_CPU_VIA_C7 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x7 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_EPIA_VT8237R_INIT = 0x0 +CONFIG_FALLBACK_SIZE = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_TINY_BOOTBLOCK = 0x0 -CONFIG_UDELAY_TSC = 0x1 +CONFIG_UDELAY_TSC = 0x0 [111/116] via/epia-m ok. Processing mainboard/via/epia-m (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-4993/targets/via/epia-m/Config-abuild.lb ok Creating builddir...ok +CONFIG_CPU_VIA_C3 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_FALLBACK_SIZE = 0x0 +CONFIG_HAVE_ACPI_TABLES = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_TINY_BOOTBLOCK = 0x0 -CONFIG_UDELAY_TSC = 0x1 +CONFIG_UDELAY_TSC = 0x0 [112/116] via/epia-m700 ok. Processing mainboard/via/epia-m700 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-4993/targets/via/epia-m700/Config-abuild.lb ok Creating builddir...ok +CONFIG_CPU_VIA_C7 = 0x1 -CONFIG_DCACHE_RAM_SIZE = 0x2000 +CONFIG_DCACHE_RAM_SIZE = 0x8000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_FALLBACK_SIZE = 0x0 +CONFIG_HAVE_ACPI_TABLES = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x0 -CONFIG_HEAP_SIZE = 0x5000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_IOAPIC = 0x1 +CONFIG_IOAPIC = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x0 +CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1019 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 +CONFIG_TINY_BOOTBLOCK = 0x0 -CONFIG_UDELAY_TSC = 0x1 +CONFIG_UDELAY_TSC = 0x0 -CONFIG_USE_DCACHE_RAM = 0x1 +CONFIG_USE_DCACHE_RAM = 0x0 [113/116] via/epia-n ok. Processing mainboard/via/epia-n (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-4993/targets/via/epia-n/Config-abuild.lb ok Creating builddir...ok +CONFIG_CN400_VIDEO_MB_128MB = 0x0 +CONFIG_CN400_VIDEO_MB_16MB = 0x0 +CONFIG_CN400_VIDEO_MB_32MB = 0x1 +CONFIG_CN400_VIDEO_MB_64MB = 0x0 +CONFIG_CN400_VIDEO_MB_8MB = 0x0 +CONFIG_CN400_VIDEO_MB_OFF = 0x0 +CONFIG_CPU_VIA_C3 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x7 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_FALLBACK_SIZE = 0x0 +CONFIG_HAVE_ACPI_TABLES = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x0 -CONFIG_HAVE_MAINBOARD_RESOURCES = 0x1 +CONFIG_HAVE_MAINBOARD_RESOURCES = 0x0 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_IOAPIC = 0x1 +CONFIG_IOAPIC = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_SMP = 0x1 +CONFIG_SMP = 0x0 +CONFIG_TINY_BOOTBLOCK = 0x0 -CONFIG_UDELAY_TSC = 0x1 +CONFIG_UDELAY_TSC = 0x0 -CONFIG_WRITE_HIGH_TABLES = 0x1 +CONFIG_WRITE_HIGH_TABLES = 0x0 [114/116] via/epia ok. Processing mainboard/via/epia (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_VIA_C3 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x7 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_FALLBACK_SIZE = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 -CONFIG_HAVE_INIT_TIMER = 0x0 +CONFIG_HAVE_INIT_TIMER = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 +CONFIG_TINY_BOOTBLOCK = 0x0 -CONFIG_UDELAY_IO = 0x1 +CONFIG_UDELAY_IO = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [115/116] via/pc2500e ok. Processing mainboard/via/pc2500e (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-4993/targets/via/pc2500e/Config-abuild.lb ok Creating builddir...ok +CONFIG_CN700_VIDEO_MB_128MB = 0x0 +CONFIG_CN700_VIDEO_MB_16MB = 0x0 +CONFIG_CN700_VIDEO_MB_32MB = 0x1 +CONFIG_CN700_VIDEO_MB_64MB = 0x0 +CONFIG_CN700_VIDEO_MB_8MB = 0x0 +CONFIG_CN700_VIDEO_MB_OFF = 0x0 +CONFIG_CPU_VIA_C7 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_EPIA_VT8237R_INIT = 0x0 +CONFIG_FALLBACK_SIZE = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 +CONFIG_TINY_BOOTBLOCK = 0x0 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_USE_OPTION_TABLE = 0x1 +CONFIG_USE_OPTION_TABLE = 0x0 [116/116] via/vt8454c ok. Processing mainboard/via/vt8454c (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-4993/targets/via/vt8454c/Config-abuild.lb ok Creating builddir...ok +CONFIG_CPU_VIA_C7 = 0x1 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x5 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_ACPI_TABLES = 0x1 -CONFIG_HAVE_HARD_RESET = 0x1 +CONFIG_HAVE_HARD_RESET = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x0 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_IOAPIC = 0x1 +CONFIG_IOAPIC = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x0 +CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1019 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x5 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_ROM_SIZE = 0x80000 +CONFIG_ROM_SIZE = 0x100000 -CONFIG_SMP = 0x1 +CONFIG_SMP = 0x0 +CONFIG_TINY_BOOTBLOCK = 0x0 -CONFIG_UDELAY_TSC = 0x1 +CONFIG_UDELAY_TSC = 0x0 -CONFIG_USE_DCACHE_RAM = 0x1 +CONFIG_USE_DCACHE_RAM = 0x0 -CONFIG_WRITE_HIGH_TABLES = 0x1 +CONFIG_WRITE_HIGH_TABLES = 0x0

1 0

[commit] r4993 - in trunk/src/superio: fintek/f71805f intel/i3100 ite/it8661f ite/it8671f ite/it8673f ite/it8705f ite/it8712f ite/it8716f ite/it8718f nsc/pc8374 nsc/pc87309 nsc/pc87351 nsc/pc87360 nsc/pc87366 nsc/pc87417 nsc/pc87427 nsc/pc97307 nsc/pc97317 smsc/fdc37m60x smsc/lpc47b272 smsc/lpc47b397 smsc/lpc47m10x smsc/lpc47m15x smsc/lpc47n217 smsc/smscsuperio via/vt1211 winbond/w83627dhg winbond/w83627ehg winbond/w83627hf winbond/w83627thf winbond/w83627thg winbond/w83627uhg winbond/w83697hf wi
by svn＠coreboot.org 28 Dec '09

28 Dec '09

Author: zbao Date: 2009-12-28 10:59:44 +0100 (Mon, 28 Dec 2009) New Revision: 4993 Modified: trunk/src/superio/fintek/f71805f/Config.lb trunk/src/superio/fintek/f71805f/Makefile.inc trunk/src/superio/fintek/f71805f/f71805f.h trunk/src/superio/fintek/f71805f/superio.c trunk/src/superio/intel/i3100/Config.lb trunk/src/superio/intel/i3100/Makefile.inc trunk/src/superio/intel/i3100/superio.c trunk/src/superio/ite/it8661f/Config.lb trunk/src/superio/ite/it8661f/Makefile.inc trunk/src/superio/ite/it8661f/chip.h trunk/src/superio/ite/it8661f/it8661f.h trunk/src/superio/ite/it8661f/it8661f_early_serial.c trunk/src/superio/ite/it8661f/superio.c trunk/src/superio/ite/it8671f/Config.lb trunk/src/superio/ite/it8671f/Makefile.inc trunk/src/superio/ite/it8671f/chip.h trunk/src/superio/ite/it8671f/it8671f.h trunk/src/superio/ite/it8671f/it8671f_early_serial.c trunk/src/superio/ite/it8671f/superio.c trunk/src/superio/ite/it8673f/Config.lb trunk/src/superio/ite/it8673f/Makefile.inc trunk/src/superio/ite/it8673f/chip.h trunk/src/superio/ite/it8673f/it8673f.h trunk/src/superio/ite/it8673f/it8673f_early_serial.c trunk/src/superio/ite/it8673f/superio.c trunk/src/superio/ite/it8705f/Config.lb trunk/src/superio/ite/it8705f/Makefile.inc trunk/src/superio/ite/it8705f/chip.h trunk/src/superio/ite/it8705f/it8705f.h trunk/src/superio/ite/it8705f/it8705f_early_serial.c trunk/src/superio/ite/it8705f/superio.c trunk/src/superio/ite/it8712f/Config.lb trunk/src/superio/ite/it8712f/Makefile.inc trunk/src/superio/ite/it8712f/chip.h trunk/src/superio/ite/it8712f/it8712f.h trunk/src/superio/ite/it8712f/it8712f_early_serial.c trunk/src/superio/ite/it8712f/superio.c trunk/src/superio/ite/it8716f/Config.lb trunk/src/superio/ite/it8716f/Makefile.inc trunk/src/superio/ite/it8716f/chip.h trunk/src/superio/ite/it8716f/it8716f.h trunk/src/superio/ite/it8716f/it8716f_early_init.c trunk/src/superio/ite/it8716f/it8716f_early_serial.c trunk/src/superio/ite/it8718f/Config.lb trunk/src/superio/ite/it8718f/Makefile.inc trunk/src/superio/ite/it8718f/chip.h trunk/src/superio/ite/it8718f/it8718f_early_serial.c trunk/src/superio/ite/it8718f/superio.c trunk/src/superio/nsc/pc8374/Config.lb trunk/src/superio/nsc/pc8374/Makefile.inc trunk/src/superio/nsc/pc8374/chip.h trunk/src/superio/nsc/pc8374/pc8374.h trunk/src/superio/nsc/pc8374/pc8374_early_init.c trunk/src/superio/nsc/pc8374/superio.c trunk/src/superio/nsc/pc87309/Config.lb trunk/src/superio/nsc/pc87309/Makefile.inc trunk/src/superio/nsc/pc87309/superio.c trunk/src/superio/nsc/pc87351/Config.lb trunk/src/superio/nsc/pc87351/Makefile.inc trunk/src/superio/nsc/pc87351/chip.h trunk/src/superio/nsc/pc87351/pc87351.h trunk/src/superio/nsc/pc87351/pc87351_early_serial.c trunk/src/superio/nsc/pc87351/superio.c trunk/src/superio/nsc/pc87360/Config.lb trunk/src/superio/nsc/pc87360/Makefile.inc trunk/src/superio/nsc/pc87360/chip.h trunk/src/superio/nsc/pc87360/pc87360.h trunk/src/superio/nsc/pc87360/pc87360_early_serial.c trunk/src/superio/nsc/pc87360/superio.c trunk/src/superio/nsc/pc87366/Config.lb trunk/src/superio/nsc/pc87366/Makefile.inc trunk/src/superio/nsc/pc87366/chip.h trunk/src/superio/nsc/pc87366/pc87366.h trunk/src/superio/nsc/pc87366/pc87366_early_serial.c trunk/src/superio/nsc/pc87366/superio.c trunk/src/superio/nsc/pc87417/Config.lb trunk/src/superio/nsc/pc87417/Makefile.inc trunk/src/superio/nsc/pc87417/chip.h trunk/src/superio/nsc/pc87417/pc87417.h trunk/src/superio/nsc/pc87417/pc87417_early_init.c trunk/src/superio/nsc/pc87417/pc87417_early_serial.c trunk/src/superio/nsc/pc87417/superio.c trunk/src/superio/nsc/pc87427/Config.lb trunk/src/superio/nsc/pc87427/Makefile.inc trunk/src/superio/nsc/pc87427/chip.h trunk/src/superio/nsc/pc87427/pc87427.h trunk/src/superio/nsc/pc87427/pc87427_early_init.c trunk/src/superio/nsc/pc87427/superio.c trunk/src/superio/nsc/pc97307/Config.lb trunk/src/superio/nsc/pc97307/Makefile.inc trunk/src/superio/nsc/pc97307/chip.h trunk/src/superio/nsc/pc97307/pc97307.h trunk/src/superio/nsc/pc97307/superio.c trunk/src/superio/nsc/pc97317/Config.lb trunk/src/superio/nsc/pc97317/Makefile.inc trunk/src/superio/nsc/pc97317/chip.h trunk/src/superio/nsc/pc97317/pc97317.h trunk/src/superio/nsc/pc97317/pc97317_early_serial.c trunk/src/superio/nsc/pc97317/superio.c trunk/src/superio/smsc/fdc37m60x/Config.lb trunk/src/superio/smsc/fdc37m60x/Makefile.inc trunk/src/superio/smsc/fdc37m60x/chip.h trunk/src/superio/smsc/fdc37m60x/fdc37m60x.h trunk/src/superio/smsc/fdc37m60x/fdc37m60x_early_serial.c trunk/src/superio/smsc/fdc37m60x/superio.c trunk/src/superio/smsc/lpc47b272/Config.lb trunk/src/superio/smsc/lpc47b272/Makefile.inc trunk/src/superio/smsc/lpc47b272/lpc47b272.h trunk/src/superio/smsc/lpc47b272/lpc47b272_early_serial.c trunk/src/superio/smsc/lpc47b272/superio.c trunk/src/superio/smsc/lpc47b397/Config.lb trunk/src/superio/smsc/lpc47b397/Makefile.inc trunk/src/superio/smsc/lpc47b397/chip.h trunk/src/superio/smsc/lpc47b397/lpc47b397.h trunk/src/superio/smsc/lpc47b397/lpc47b397_early_gpio.c trunk/src/superio/smsc/lpc47b397/lpc47b397_early_serial.c trunk/src/superio/smsc/lpc47b397/superio.c trunk/src/superio/smsc/lpc47m10x/Config.lb trunk/src/superio/smsc/lpc47m10x/Makefile.inc trunk/src/superio/smsc/lpc47m10x/chip.h trunk/src/superio/smsc/lpc47m10x/lpc47m10x.h trunk/src/superio/smsc/lpc47m10x/lpc47m10x_early_serial.c trunk/src/superio/smsc/lpc47m10x/superio.c trunk/src/superio/smsc/lpc47m15x/Makefile.inc trunk/src/superio/smsc/lpc47m15x/lpc47m15x_early_serial.c trunk/src/superio/smsc/lpc47m15x/superio.c trunk/src/superio/smsc/lpc47n217/Config.lb trunk/src/superio/smsc/lpc47n217/Makefile.inc trunk/src/superio/smsc/lpc47n217/lpc47n217.h trunk/src/superio/smsc/lpc47n217/lpc47n217_early_serial.c trunk/src/superio/smsc/lpc47n217/superio.c trunk/src/superio/smsc/smscsuperio/Config.lb trunk/src/superio/smsc/smscsuperio/Makefile.inc trunk/src/superio/smsc/smscsuperio/superio.c trunk/src/superio/via/vt1211/Config.lb trunk/src/superio/via/vt1211/Makefile.inc trunk/src/superio/via/vt1211/chip.h trunk/src/superio/via/vt1211/vt1211.c trunk/src/superio/via/vt1211/vt1211.h trunk/src/superio/winbond/w83627dhg/Config.lb trunk/src/superio/winbond/w83627dhg/Makefile.inc trunk/src/superio/winbond/w83627dhg/superio.c trunk/src/superio/winbond/w83627ehg/Config.lb trunk/src/superio/winbond/w83627ehg/Makefile.inc trunk/src/superio/winbond/w83627ehg/superio.c trunk/src/superio/winbond/w83627ehg/w83627ehg.h trunk/src/superio/winbond/w83627ehg/w83627ehg_early_init.c trunk/src/superio/winbond/w83627ehg/w83627ehg_early_serial.c trunk/src/superio/winbond/w83627hf/Config.lb trunk/src/superio/winbond/w83627hf/Makefile.inc trunk/src/superio/winbond/w83627hf/chip.h trunk/src/superio/winbond/w83627hf/superio.c trunk/src/superio/winbond/w83627hf/w83627hf.h trunk/src/superio/winbond/w83627hf/w83627hf_early_init.c trunk/src/superio/winbond/w83627hf/w83627hf_early_serial.c trunk/src/superio/winbond/w83627thf/Config.lb trunk/src/superio/winbond/w83627thf/Makefile.inc trunk/src/superio/winbond/w83627thf/chip.h trunk/src/superio/winbond/w83627thf/superio.c trunk/src/superio/winbond/w83627thf/w83627thf.h trunk/src/superio/winbond/w83627thf/w83627thf_early_serial.c trunk/src/superio/winbond/w83627thg/Config.lb trunk/src/superio/winbond/w83627thg/Makefile.inc trunk/src/superio/winbond/w83627thg/chip.h trunk/src/superio/winbond/w83627thg/superio.c trunk/src/superio/winbond/w83627thg/w83627thg.h trunk/src/superio/winbond/w83627thg/w83627thg_early_serial.c trunk/src/superio/winbond/w83627uhg/superio.c trunk/src/superio/winbond/w83697hf/w83697hf_early_serial.c trunk/src/superio/winbond/w83977f/Config.lb trunk/src/superio/winbond/w83977f/Makefile.inc trunk/src/superio/winbond/w83977f/superio.c trunk/src/superio/winbond/w83977tf/Config.lb trunk/src/superio/winbond/w83977tf/Makefile.inc trunk/src/superio/winbond/w83977tf/chip.h trunk/src/superio/winbond/w83977tf/superio.c trunk/src/superio/winbond/w83977tf/w83977tf.h trunk/src/superio/winbond/w83977tf/w83977tf_early_serial.c Log: trival. All the changes is about comment and spaces. In superio folder. 1. Delete trailing white spaces. 2. Change the // comment to /* */. 3. Add some copyright header. 4. reindent. 5. delete multi blank lines. I tried my best to find them. If anything left, please fix it or tell me. Signed-off-by: Zheng Bao <zheng.bao(a)amd.com> Acked-by: Zheng Bao <zheng.bao(a)amd.com> Modified: trunk/src/superio/fintek/f71805f/Config.lb =================================================================== --- trunk/src/superio/fintek/f71805f/Config.lb 2009-12-23 22:16:18 UTC (rev 4992) +++ trunk/src/superio/fintek/f71805f/Config.lb 2009-12-28 09:59:44 UTC (rev 4993) @@ -20,4 +20,3 @@ config chip.h object superio.o - Modified: trunk/src/superio/fintek/f71805f/Makefile.inc =================================================================== --- trunk/src/superio/fintek/f71805f/Makefile.inc 2009-12-23 22:16:18 UTC (rev 4992) +++ trunk/src/superio/fintek/f71805f/Makefile.inc 2009-12-28 09:59:44 UTC (rev 4993) @@ -20,4 +20,3 @@ #config chip.h obj-$(CONFIG_SUPERIO_FINTEK_F71805F) += superio.o - Modified: trunk/src/superio/fintek/f71805f/f71805f.h =================================================================== --- trunk/src/superio/fintek/f71805f/f71805f.h 2009-12-23 22:16:18 UTC (rev 4992) +++ trunk/src/superio/fintek/f71805f/f71805f.h 2009-12-28 09:59:44 UTC (rev 4993) @@ -24,7 +24,7 @@ * - URL: http://www.fintek.com.tw/eng/products.asp?BID=1&SID=17 * - PDF: http://www.fintek.com.tw/files/productfiles/F71805F_V025.pdf * - Revision: V0.25P - */ + */ /* Logical Device Numbers (LDN). */ #define F71805F_FDC 0x00 /* Floppy */ Modified: trunk/src/superio/fintek/f71805f/superio.c =================================================================== --- trunk/src/superio/fintek/f71805f/superio.c 2009-12-23 22:16:18 UTC (rev 4992) +++ trunk/src/superio/fintek/f71805f/superio.c 2009-12-28 09:59:44 UTC (rev 4993) @@ -29,12 +29,12 @@ #include "chip.h" #include "f71805f.h" -static void pnp_enter_conf_state(device_t dev) +static void pnp_enter_conf_state(device_t dev) { outb(0x87, dev->path.pnp.port); } -static void pnp_exit_conf_state(device_t dev) +static void pnp_exit_conf_state(device_t dev) { outb(0xaa, dev->path.pnp.port); } @@ -46,7 +46,7 @@ if (!dev->enabled) return; - + switch(dev->path.pnp.device) { /* TODO: Might potentially need code for HWM or FDC etc. */ case F71805F_SP1: @@ -110,4 +110,3 @@ CHIP_NAME("Fintek F71805F Super I/O") .enable_dev = enable_dev }; - Modified: trunk/src/superio/intel/i3100/Config.lb =================================================================== --- trunk/src/superio/intel/i3100/Config.lb 2009-12-23 22:16:18 UTC (rev 4992) +++ trunk/src/superio/intel/i3100/Config.lb 2009-12-28 09:59:44 UTC (rev 4993) @@ -20,4 +20,3 @@ config chip.h object superio.o - Modified: trunk/src/superio/intel/i3100/Makefile.inc =================================================================== --- trunk/src/superio/intel/i3100/Makefile.inc 2009-12-23 22:16:18 UTC (rev 4992) +++ trunk/src/superio/intel/i3100/Makefile.inc 2009-12-28 09:59:44 UTC (rev 4993) @@ -20,4 +20,3 @@ #config chip.h obj-$(CONFIG_SUPERIO_INTEL_I3100) += superio.o - Modified: trunk/src/superio/intel/i3100/superio.c =================================================================== --- trunk/src/superio/intel/i3100/superio.c 2009-12-23 22:16:18 UTC (rev 4992) +++ trunk/src/superio/intel/i3100/superio.c 2009-12-28 09:59:44 UTC (rev 4993) @@ -105,4 +105,3 @@ CHIP_NAME("Intel 3100 Super I/O") .enable_dev = enable_dev, }; - Modified: trunk/src/superio/ite/it8661f/Config.lb =================================================================== --- trunk/src/superio/ite/it8661f/Config.lb 2009-12-23 22:16:18 UTC (rev 4992) +++ trunk/src/superio/ite/it8661f/Config.lb 2009-12-28 09:59:44 UTC (rev 4993) @@ -20,4 +20,3 @@ config chip.h object superio.o - Modified: trunk/src/superio/ite/it8661f/Makefile.inc =================================================================== --- trunk/src/superio/ite/it8661f/Makefile.inc 2009-12-23 22:16:18 UTC (rev 4992) +++ trunk/src/superio/ite/it8661f/Makefile.inc 2009-12-28 09:59:44 UTC (rev 4993) @@ -20,4 +20,3 @@ #config chip.h obj-$(CONFIG_SUPERIO_ITE_IT8661F) += superio.o - Modified: trunk/src/superio/ite/it8661f/chip.h =================================================================== --- trunk/src/superio/ite/it8661f/chip.h 2009-12-23 22:16:18 UTC (rev 4992) +++ trunk/src/superio/ite/it8661f/chip.h 2009-12-28 09:59:44 UTC (rev 4993) @@ -33,4 +33,3 @@ }; #endif /* _SUPERIO_ITE_IT8661F */ - Modified: trunk/src/superio/ite/it8661f/it8661f.h =================================================================== --- trunk/src/superio/ite/it8661f/it8661f.h 2009-12-23 22:16:18 UTC (rev 4992) +++ trunk/src/superio/ite/it8661f/it8661f.h 2009-12-28 09:59:44 UTC (rev 4993) @@ -29,4 +29,3 @@ #define IT8661F_PP 0x03 /* Parallel port */ #define IT8661F_IR 0x04 /* IR */ #define IT8661F_GPIO 0x05 /* GPIO & Alternate Function Configuration */ - Modified: trunk/src/superio/ite/it8661f/it8661f_early_serial.c =================================================================== --- trunk/src/superio/ite/it8661f/it8661f_early_serial.c 2009-12-23 22:16:18 UTC (rev 4992) +++ trunk/src/superio/ite/it8661f/it8661f_early_serial.c 2009-12-28 09:59:44 UTC (rev 4993) @@ -91,4 +91,3 @@ /* (3) Exit the configuration state (MB PnP mode). */ it8661f_sio_write(0x00, IT8661F_CONFIG_REG_CC, 0x02); } - Modified: trunk/src/superio/ite/it8661f/superio.c =================================================================== --- trunk/src/superio/ite/it8661f/superio.c 2009-12-23 22:16:18 UTC (rev 4992) +++ trunk/src/superio/ite/it8661f/superio.c 2009-12-28 09:59:44 UTC (rev 4993) @@ -66,8 +66,8 @@ /* TODO: FDC, PP, IR, GPIO. */ static struct pnp_info pnp_dev_info[] = { - { &ops, IT8661F_SP1, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, }, - { &ops, IT8661F_SP2, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0 | PNP_DRQ1, { 0x7f8, 0 }, }, + { &ops, IT8661F_SP1, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, }, + { &ops, IT8661F_SP2, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0 | PNP_DRQ1, { 0x7f8, 0 }, }, }; static void enable_dev(struct device *dev) @@ -80,4 +80,3 @@ CHIP_NAME("ITE IT8661F Super I/O") .enable_dev = enable_dev, }; - Modified: trunk/src/superio/ite/it8671f/Config.lb =================================================================== --- trunk/src/superio/ite/it8671f/Config.lb 2009-12-23 22:16:18 UTC (rev 4992) +++ trunk/src/superio/ite/it8671f/Config.lb 2009-12-28 09:59:44 UTC (rev 4993) @@ -20,4 +20,3 @@ config chip.h object superio.o - Modified: trunk/src/superio/ite/it8671f/Makefile.inc =================================================================== --- trunk/src/superio/ite/it8671f/Makefile.inc 2009-12-23 22:16:18 UTC (rev 4992) +++ trunk/src/superio/ite/it8671f/Makefile.inc 2009-12-28 09:59:44 UTC (rev 4993) @@ -20,4 +20,3 @@ #config chip.h obj-$(CONFIG_SUPERIO_ITE_IT8671F) += superio.o - Modified: trunk/src/superio/ite/it8671f/chip.h =================================================================== --- trunk/src/superio/ite/it8671f/chip.h 2009-12-23 22:16:18 UTC (rev 4992) +++ trunk/src/superio/ite/it8671f/chip.h 2009-12-28 09:59:44 UTC (rev 4993) @@ -33,4 +33,3 @@ }; #endif /* _SUPERIO_ITE_IT8671F */ - Modified: trunk/src/superio/ite/it8671f/it8671f.h =================================================================== --- trunk/src/superio/ite/it8671f/it8671f.h 2009-12-23 22:16:18 UTC (rev 4992) +++ trunk/src/superio/ite/it8671f/it8671f.h 2009-12-28 09:59:44 UTC (rev 4993) @@ -27,4 +27,3 @@ #define IT8671F_PP 0x03 /* Parallel port */ #define IT8671F_KBCK 0x05 /* Keyboard */ #define IT8671F_KBCM 0x06 /* Mouse */ - Modified: trunk/src/superio/ite/it8671f/it8671f_early_serial.c =================================================================== --- trunk/src/superio/ite/it8671f/it8671f_early_serial.c 2009-12-23 22:16:18 UTC (rev 4992) +++ trunk/src/superio/ite/it8671f/it8671f_early_serial.c 2009-12-28 09:59:44 UTC (rev 4993) @@ -91,4 +91,3 @@ /* (3) Exit the configuration state (MB PnP mode). */ it8671f_sio_write(0x00, IT8671F_CONFIG_REG_CC, 0x02); } - Modified: trunk/src/superio/ite/it8671f/superio.c =================================================================== --- trunk/src/superio/ite/it8671f/superio.c 2009-12-23 22:16:18 UTC (rev 4992) +++ trunk/src/superio/ite/it8671f/superio.c 2009-12-28 09:59:44 UTC (rev 4993) @@ -70,9 +70,9 @@ /* TODO: FDC, PP, KBCM. */ static struct pnp_info pnp_dev_info[] = { - { &ops, IT8671F_SP1, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, }, - { &ops, IT8671F_SP2, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0 | PNP_DRQ1, { 0x7f8, 0 }, }, - { &ops, IT8671F_KBCK, PNP_IO0 | PNP_IO1 | PNP_IRQ0, { 0x7f8, 0 }, { 0x7f8, 0x4}, }, + { &ops, IT8671F_SP1, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, }, + { &ops, IT8671F_SP2, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0 | PNP_DRQ1, { 0x7f8, 0 }, }, + { &ops, IT8671F_KBCK, PNP_IO0 | PNP_IO1 | PNP_IRQ0, { 0x7f8, 0 }, { 0x7f8, 0x4}, }, }; static void enable_dev(struct device *dev) @@ -85,4 +85,3 @@ CHIP_NAME("ITE IT8671F Super I/O") .enable_dev = enable_dev, }; - Modified: trunk/src/superio/ite/it8673f/Config.lb =================================================================== --- trunk/src/superio/ite/it8673f/Config.lb 2009-12-23 22:16:18 UTC (rev 4992) +++ trunk/src/superio/ite/it8673f/Config.lb 2009-12-28 09:59:44 UTC (rev 4993) @@ -20,4 +20,3 @@ config chip.h object superio.o - Modified: trunk/src/superio/ite/it8673f/Makefile.inc =================================================================== --- trunk/src/superio/ite/it8673f/Makefile.inc 2009-12-23 22:16:18 UTC (rev 4992) +++ trunk/src/superio/ite/it8673f/Makefile.inc 2009-12-28 09:59:44 UTC (rev 4993) @@ -20,4 +20,3 @@ #config chip.h obj-$(CONFIG_SUPERIO_ITE_IT8673F) += superio.o - Modified: trunk/src/superio/ite/it8673f/chip.h =================================================================== --- trunk/src/superio/ite/it8673f/chip.h 2009-12-23 22:16:18 UTC (rev 4992) +++ trunk/src/superio/ite/it8673f/chip.h 2009-12-28 09:59:44 UTC (rev 4993) @@ -33,4 +33,3 @@ }; #endif /* _SUPERIO_ITE_IT8673F */ - Modified: trunk/src/superio/ite/it8673f/it8673f.h =================================================================== --- trunk/src/superio/ite/it8673f/it8673f.h 2009-12-23 22:16:18 UTC (rev 4992) +++ trunk/src/superio/ite/it8673f/it8673f.h 2009-12-28 09:59:44 UTC (rev 4993) @@ -28,4 +28,3 @@ #define IT8673F_FAN 0x04 /* Fan controller */ #define IT8673F_KBCK 0x05 /* Keyboard */ #define IT8673F_KBCM 0x06 /* Mouse */ - Modified: trunk/src/superio/ite/it8673f/it8673f_early_serial.c =================================================================== --- trunk/src/superio/ite/it8673f/it8673f_early_serial.c 2009-12-23 22:16:18 UTC (rev 4992) +++ trunk/src/superio/ite/it8673f/it8673f_early_serial.c 2009-12-28 09:59:44 UTC (rev 4993) @@ -89,4 +89,3 @@ /* (3) Exit the configuration state (MB PnP mode). */ it8673f_sio_write(0x00, IT8673F_CONFIG_REG_CC, 0x02); } - Modified: trunk/src/superio/ite/it8673f/superio.c =================================================================== --- trunk/src/superio/ite/it8673f/superio.c 2009-12-23 22:16:18 UTC (rev 4992) +++ trunk/src/superio/ite/it8673f/superio.c 2009-12-28 09:59:44 UTC (rev 4993) @@ -87,4 +87,3 @@ CHIP_NAME("ITE IT8673F Super I/O") .enable_dev = enable_dev, }; - Modified: trunk/src/superio/ite/it8705f/Config.lb =================================================================== --- trunk/src/superio/ite/it8705f/Config.lb 2009-12-23 22:16:18 UTC (rev 4992) +++ trunk/src/superio/ite/it8705f/Config.lb 2009-12-28 09:59:44 UTC (rev 4993) @@ -20,4 +20,3 @@ config chip.h object superio.o - Modified: trunk/src/superio/ite/it8705f/Makefile.inc =================================================================== --- trunk/src/superio/ite/it8705f/Makefile.inc 2009-12-23 22:16:18 UTC (rev 4992) +++ trunk/src/superio/ite/it8705f/Makefile.inc 2009-12-28 09:59:44 UTC (rev 4993) @@ -20,4 +20,3 @@ #config chip.h obj-$(CONFIG_SUPERIO_ITE_IT8705F) += superio.o - Modified: trunk/src/superio/ite/it8705f/chip.h =================================================================== --- trunk/src/superio/ite/it8705f/chip.h 2009-12-23 22:16:18 UTC (rev 4992) +++ trunk/src/superio/ite/it8705f/chip.h 2009-12-28 09:59:44 UTC (rev 4993) @@ -33,4 +33,3 @@ }; #endif /* _SUPERIO_ITE_IT8705F */ - Modified: trunk/src/superio/ite/it8705f/it8705f.h =================================================================== --- trunk/src/superio/ite/it8705f/it8705f.h 2009-12-23 22:16:18 UTC (rev 4992) +++ trunk/src/superio/ite/it8705f/it8705f.h 2009-12-28 09:59:44 UTC (rev 4993) @@ -33,4 +33,3 @@ #define IT8705F_GAME 0x06 /* GAME port */ #define IT8705F_IR 0x07 /* Consumer IR */ #define IT8705F_MIDI 0x08 /* MIDI port */ - Modified: trunk/src/superio/ite/it8705f/it8705f_early_serial.c =================================================================== --- trunk/src/superio/ite/it8705f/it8705f_early_serial.c 2009-12-23 22:16:18 UTC (rev 4992) +++ trunk/src/superio/ite/it8705f/it8705f_early_serial.c 2009-12-28 09:59:44 UTC (rev 4993) @@ -63,8 +63,8 @@ /* (2) Modify the data of configuration registers. */ /* Select the chip to configure (if there's more than one). - Set bit 7 to select JP3=1, clear bit 7 to select JP3=0. - If this register is not written, both chips are configured. */ + Set bit 7 to select JP3=1, clear bit 7 to select JP3=0. + If this register is not written, both chips are configured. */ /* it8705f_sio_write(0x00, IT8705F_CONFIG_REG_CONFIGSEL, 0x00); */ /* Enable serial port(s). */ @@ -80,4 +80,3 @@ /* (3) Exit the configuration state (MB PnP mode). */ it8705f_sio_write(0x00, IT8705F_CONFIG_REG_CC, 0x02); } - Modified: trunk/src/superio/ite/it8705f/superio.c =================================================================== --- trunk/src/superio/ite/it8705f/superio.c 2009-12-23 22:16:18 UTC (rev 4992) +++ trunk/src/superio/ite/it8705f/superio.c 2009-12-28 09:59:44 UTC (rev 4993) @@ -74,8 +74,8 @@ /* TODO: FDC, PP, EC, GPIO, GAME, IR, MIDI. */ static struct pnp_info pnp_dev_info[] = { - { &ops, IT8705F_SP1, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, }, - { &ops, IT8705F_SP2, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0 | PNP_DRQ1, { 0x7f8, 0 }, }, + { &ops, IT8705F_SP1, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, }, + { &ops, IT8705F_SP2, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0 | PNP_DRQ1, { 0x7f8, 0 }, }, }; static void enable_dev(struct device *dev) @@ -88,4 +88,3 @@ CHIP_NAME("ITE IT8705F Super I/O") .enable_dev = enable_dev, }; - Modified: trunk/src/superio/ite/it8712f/Config.lb =================================================================== --- trunk/src/superio/ite/it8712f/Config.lb 2009-12-23 22:16:18 UTC (rev 4992) +++ trunk/src/superio/ite/it8712f/Config.lb 2009-12-28 09:59:44 UTC (rev 4993) @@ -20,4 +20,3 @@ config chip.h object superio.o - Modified: trunk/src/superio/ite/it8712f/Makefile.inc =================================================================== --- trunk/src/superio/ite/it8712f/Makefile.inc 2009-12-23 22:16:18 UTC (rev 4992) +++ trunk/src/superio/ite/it8712f/Makefile.inc 2009-12-28 09:59:44 UTC (rev 4993) @@ -20,4 +20,3 @@ #config chip.h obj-$(CONFIG_SUPERIO_ITE_IT8712F) += superio.o - Modified: trunk/src/superio/ite/it8712f/chip.h =================================================================== --- trunk/src/superio/ite/it8712f/chip.h 2009-12-23 22:16:18 UTC (rev 4992) +++ trunk/src/superio/ite/it8712f/chip.h 2009-12-28 09:59:44 UTC (rev 4993) @@ -33,4 +33,3 @@ }; #endif /* _SUPERIO_ITE_IT8712F */ - Modified: trunk/src/superio/ite/it8712f/it8712f.h =================================================================== --- trunk/src/superio/ite/it8712f/it8712f.h 2009-12-23 22:16:18 UTC (rev 4992) +++ trunk/src/superio/ite/it8712f/it8712f.h 2009-12-28 09:59:44 UTC (rev 4993) @@ -32,4 +32,3 @@ #define IT8712F_MIDI 0x08 /* MIDI port */ #define IT8712F_GAME 0x09 /* GAME port */ #define IT8712F_IR 0x0a /* Consumer IR */ - Modified: trunk/src/superio/ite/it8712f/it8712f_early_serial.c =================================================================== --- trunk/src/superio/ite/it8712f/it8712f_early_serial.c 2009-12-23 22:16:18 UTC (rev 4992) +++ trunk/src/superio/ite/it8712f/it8712f_early_serial.c 2009-12-28 09:59:44 UTC (rev 4993) @@ -47,7 +47,6 @@ outb(value, SIO_DATA); } - static void it8712f_enter_conf(void) { /* Enter the configuration state (MB PnP mode). */ @@ -67,7 +66,6 @@ it8712f_sio_write(0x00, IT8712F_CONFIG_REG_CC, 0x02); } - static void it8712f_24mhz_clkin(void) { it8712f_enter_conf(); @@ -76,10 +74,10 @@ it8712f_sio_write(0x00, IT8712F_CONFIG_REG_CLOCKSEL, 0x1); it8712f_exit_conf(); - } -static void it8712f_enable_3vsbsw(void) { +static void it8712f_enable_3vsbsw(void) +{ /* We need to set enable 3VSBSW#, this was documented only in IT8712F_V0.9.2! LDN 7, reg 0x2a - needed for S3, or memory power will be cut off. @@ -93,7 +91,6 @@ it8712f_exit_conf(); } - static void it8712f_kill_watchdog(void) { it8712f_enter_conf(); @@ -114,8 +111,8 @@ /* (2) Modify the data of configuration registers. */ /* Select the chip to configure (if there's more than one). - Set bit 7 to select JP3=1, clear bit 7 to select JP3=0. - If this register is not written, both chips are configured. */ + Set bit 7 to select JP3=1, clear bit 7 to select JP3=0. + If this register is not written, both chips are configured. */ /* it8712f_sio_write(0x00, IT8712F_CONFIG_REG_CONFIGSEL, 0x00); */ /* Enable serial port(s). */ Modified: trunk/src/superio/ite/it8712f/superio.c =================================================================== --- trunk/src/superio/ite/it8712f/superio.c 2009-12-23 22:16:18 UTC (rev 4992) +++ trunk/src/superio/ite/it8712f/superio.c 2009-12-28 09:59:44 UTC (rev 4993) @@ -145,4 +145,3 @@ CHIP_NAME("ITE IT8712F Super I/O") .enable_dev = enable_dev, }; - Modified: trunk/src/superio/ite/it8716f/Config.lb =================================================================== --- trunk/src/superio/ite/it8716f/Config.lb 2009-12-23 22:16:18 UTC (rev 4992) +++ trunk/src/superio/ite/it8716f/Config.lb 2009-12-28 09:59:44 UTC (rev 4993) @@ -20,4 +20,3 @@ config chip.h object superio.o - Modified: trunk/src/superio/ite/it8716f/Makefile.inc =================================================================== --- trunk/src/superio/ite/it8716f/Makefile.inc 2009-12-23 22:16:18 UTC (rev 4992) +++ trunk/src/superio/ite/it8716f/Makefile.inc 2009-12-28 09:59:44 UTC (rev 4993) @@ -20,4 +20,3 @@ #config chip.h obj-$(CONFIG_SUPERIO_ITE_IT8716F) += superio.o - Modified: trunk/src/superio/ite/it8716f/chip.h =================================================================== --- trunk/src/superio/ite/it8716f/chip.h 2009-12-23 22:16:18 UTC (rev 4992) +++ trunk/src/superio/ite/it8716f/chip.h 2009-12-28 09:59:44 UTC (rev 4993) @@ -33,4 +33,3 @@ }; #endif /* _SUPERIO_ITE_IT8716F */ - Modified: trunk/src/superio/ite/it8716f/it8716f.h =================================================================== --- trunk/src/superio/ite/it8716f/it8716f.h 2009-12-23 22:16:18 UTC (rev 4992) +++ trunk/src/superio/ite/it8716f/it8716f.h 2009-12-28 09:59:44 UTC (rev 4993) @@ -32,4 +32,3 @@ #define IT8716F_MIDI 0x08 /* MIDI port */ #define IT8716F_GAME 0x09 /* GAME port */ #define IT8716F_IR 0x0a /* Consumer IR */ - Modified: trunk/src/superio/ite/it8716f/it8716f_early_init.c =================================================================== --- trunk/src/superio/ite/it8716f/it8716f_early_init.c 2009-12-23 22:16:18 UTC (rev 4992) +++ trunk/src/superio/ite/it8716f/it8716f_early_init.c 2009-12-28 09:59:44 UTC (rev 4993) @@ -35,4 +35,3 @@ pnp_set_iobase(dev, PNP_IDX_IO0, iobase); pnp_set_enable(dev, 1); } - Modified: trunk/src/superio/ite/it8716f/it8716f_early_serial.c =================================================================== --- trunk/src/superio/ite/it8716f/it8716f_early_serial.c 2009-12-23 22:16:18 UTC (rev 4992) +++ trunk/src/superio/ite/it8716f/it8716f_early_serial.c 2009-12-28 09:59:44 UTC (rev 4993) @@ -41,7 +41,7 @@ /* Perform MB PnP setup to put the SIO chip at 0x2e. */ /* Base address 0x2e: 0x87 0x01 0x55 0x55. */ /* Base address 0x4e: 0x87 0x01 0x55 0xaa. */ -static inline void pnp_enter_ext_func_mode(device_t dev) +static inline void pnp_enter_ext_func_mode(device_t dev) { unsigned port = dev >> 8; outb(0x87, port); @@ -68,4 +68,3 @@ pnp_set_enable(dev, 1); pnp_exit_ext_func_mode(dev); } - Modified: trunk/src/superio/ite/it8718f/Config.lb =================================================================== --- trunk/src/superio/ite/it8718f/Config.lb 2009-12-23 22:16:18 UTC (rev 4992) +++ trunk/src/superio/ite/it8718f/Config.lb 2009-12-28 09:59:44 UTC (rev 4993) @@ -20,4 +20,3 @@ config chip.h object superio.o - Modified: trunk/src/superio/ite/it8718f/Makefile.inc =================================================================== --- trunk/src/superio/ite/it8718f/Makefile.inc 2009-12-23 22:16:18 UTC (rev 4992) +++ trunk/src/superio/ite/it8718f/Makefile.inc 2009-12-28 09:59:44 UTC (rev 4993) @@ -20,4 +20,3 @@ #config chip.h obj-$(CONFIG_SUPERIO_ITE_IT8718F) += superio.o - Modified: trunk/src/superio/ite/it8718f/chip.h =================================================================== --- trunk/src/superio/ite/it8718f/chip.h 2009-12-23 22:16:18 UTC (rev 4992) +++ trunk/src/superio/ite/it8718f/chip.h 2009-12-28 09:59:44 UTC (rev 4993) @@ -33,4 +33,3 @@ }; #endif /* _SUPERIO_ITE_IT8718F */ - Modified: trunk/src/superio/ite/it8718f/it8718f_early_serial.c =================================================================== --- trunk/src/superio/ite/it8718f/it8718f_early_serial.c 2009-12-23 22:16:18 UTC (rev 4992) +++ trunk/src/superio/ite/it8718f/it8718f_early_serial.c 2009-12-28 09:59:44 UTC (rev 4993) @@ -83,8 +83,8 @@ /* (2) Modify the data of configuration registers. */ /* Select the chip to configure (if there's more than one). - Set bit 7 to select JP3=1, clear bit 7 to select JP3=0. - If this register is not written, both chips are configured. */ + Set bit 7 to select JP3=1, clear bit 7 to select JP3=0. + If this register is not written, both chips are configured. */ /* it8718f_sio_write(0x00, IT8718F_CONFIG_REG_CONFIGSEL, 0x00); */ /* Enable serial port(s). */ @@ -97,4 +97,3 @@ /* (3) Exit the configuration state (MB PnP mode). */ it8718f_exit_conf(); } - Modified: trunk/src/superio/ite/it8718f/superio.c =================================================================== --- trunk/src/superio/ite/it8718f/superio.c 2009-12-23 22:16:18 UTC (rev 4992) +++ trunk/src/superio/ite/it8718f/superio.c 2009-12-28 09:59:44 UTC (rev 4993) @@ -74,9 +74,9 @@ /* TODO: FDC, PP, EC, KBCM, IR. */ static struct pnp_info pnp_dev_info[] = { - { &ops, IT8718F_SP1, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, }, - { &ops, IT8718F_SP2, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0 | PNP_DRQ1, { 0x7f8, 0 }, }, - { &ops, IT8718F_KBCK, PNP_IO0 | PNP_IO1 | PNP_IRQ0, { 0x7f8, 0 }, { 0x7f8, 0x4}, }, + { &ops, IT8718F_SP1, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, }, + { &ops, IT8718F_SP2, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0 | PNP_DRQ1, { 0x7f8, 0 }, }, + { &ops, IT8718F_KBCK, PNP_IO0 | PNP_IO1 | PNP_IRQ0, { 0x7f8, 0 }, { 0x7f8, 0x4}, }, }; static void enable_dev(struct device *dev) @@ -89,4 +89,3 @@ CHIP_NAME("ITE IT8718F Super I/O") .enable_dev = enable_dev, }; - Modified: trunk/src/superio/nsc/pc8374/Config.lb =================================================================== --- trunk/src/superio/nsc/pc8374/Config.lb 2009-12-23 22:16:18 UTC (rev 4992) +++ trunk/src/superio/nsc/pc8374/Config.lb 2009-12-28 09:59:44 UTC (rev 4993) @@ -1,2 +1,23 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2000 AG Electronics Ltd. +## Copyright (C) 2003-2004 Linux Networx +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + config chip.h object superio.o Modified: trunk/src/superio/nsc/pc8374/Makefile.inc =================================================================== --- trunk/src/superio/nsc/pc8374/Makefile.inc 2009-12-23 22:16:18 UTC (rev 4992) +++ trunk/src/superio/nsc/pc8374/Makefile.inc 2009-12-28 09:59:44 UTC (rev 4993) @@ -1,2 +1,23 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2000 AG Electronics Ltd. +## Copyright (C) 2003-2004 Linux Networx +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + #config chip.h obj-$(CONFIG_SUPERIO_NSC_PC8374) += superio.o Modified: trunk/src/superio/nsc/pc8374/chip.h =================================================================== --- trunk/src/superio/nsc/pc8374/chip.h 2009-12-23 22:16:18 UTC (rev 4992) +++ trunk/src/superio/nsc/pc8374/chip.h 2009-12-28 09:59:44 UTC (rev 4993) @@ -1,3 +1,24 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2000 AG Electronics Ltd. + * Copyright (C) 2003-2004 Linux Networx + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + struct chip_operations; extern struct chip_operations superio_nsc_pc8374_ops; Modified: trunk/src/superio/nsc/pc8374/pc8374.h =================================================================== --- trunk/src/superio/nsc/pc8374/pc8374.h 2009-12-23 22:16:18 UTC (rev 4992) +++ trunk/src/superio/nsc/pc8374/pc8374.h 2009-12-28 09:59:44 UTC (rev 4993) @@ -1,3 +1,24 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2000 AG Electronics Ltd. + * Copyright (C) 2003-2004 Linux Networx + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + #define PC8374_FDC 0x00 /* Floppy */ #define PC8374_PP 0x01 /* Parallel port */ #define PC8374_SP2 0x02 /* Com2 */ Modified: trunk/src/superio/nsc/pc8374/pc8374_early_init.c =================================================================== --- trunk/src/superio/nsc/pc8374/pc8374_early_init.c 2009-12-23 22:16:18 UTC (rev 4992) +++ trunk/src/superio/nsc/pc8374/pc8374_early_init.c 2009-12-28 09:59:44 UTC (rev 4993) @@ -1,3 +1,24 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2000 AG Electronics Ltd. + * Copyright (C) 2003-2004 Linux Networx + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + #include <arch/romcc_io.h> #include "pc8374.h" @@ -22,8 +43,6 @@ val |= *init; outb(val, iobase+1); } - - } static void pc8374_enable_dev(device_t dev, unsigned iobase) @@ -34,4 +53,3 @@ pnp_set_iobase(dev, PNP_IDX_IO0, iobase); pnp_set_enable(dev, 1); } - Modified: trunk/src/superio/nsc/pc8374/superio.c =================================================================== --- trunk/src/superio/nsc/pc8374/superio.c 2009-12-23 22:16:18 UTC (rev 4992) +++ trunk/src/superio/nsc/pc8374/superio.c 2009-12-28 09:59:44 UTC (rev 4993) @@ -1,6 +1,23 @@ -/* Copyright 2000 AG Electronics Ltd. */ -/* Copyright 2003-2004 Linux Networx */ -/* This code is distributed without warranty under the GPL v2 (see COPYING) */ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2000 AG Electronics Ltd. + * Copyright (C) 2003-2004 Linux Networx + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ #include <arch/io.h> #include <device/device.h> @@ -26,7 +43,7 @@ } conf = dev->chip_info; switch(dev->path.pnp.device) { - case PC8374_SP1: + case PC8374_SP1: res0 = find_resource(dev, PNP_IDX_IO0); init_uart8250(res0->base, &conf->com1); break; @@ -51,17 +68,16 @@ }; static struct pnp_info pnp_dev_info[] = { - { &ops, PC8374_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07fa, 0}, }, - { &ops, PC8374_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x04f8, 0}, }, - { &ops, PC8374_SP2, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0 | PNP_DRQ1, { 0x7f8, 0 }, }, - { &ops, PC8374_SP1, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, }, - { &ops, PC8374_SWC, PNP_IO0 | PNP_IRQ0, { 0xfff0, 0 }, }, - { &ops, PC8374_KBCM, PNP_IRQ0 }, - { &ops, PC8374_KBCK, PNP_IO0 | PNP_IO1 | PNP_IRQ0, { 0x7f8, 0 }, { 0x7f8, 0x4}, }, - { &ops, PC8374_GPIO, PNP_IO0 | PNP_IRQ0, { 0xfff8, 0 } }, + { &ops, PC8374_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07fa, 0}, }, + { &ops, PC8374_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x04f8, 0}, }, + { &ops, PC8374_SP2, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0 | PNP_DRQ1, { 0x7f8, 0 }, }, + { &ops, PC8374_SP1, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, }, + { &ops, PC8374_SWC, PNP_IO0 | PNP_IRQ0, { 0xfff0, 0 }, }, + { &ops, PC8374_KBCM, PNP_IRQ0 }, + { &ops, PC8374_KBCK, PNP_IO0 | PNP_IO1 | PNP_IRQ0, { 0x7f8, 0 }, { 0x7f8, 0x4}, }, + { &ops, PC8374_GPIO, PNP_IO0 | PNP_IRQ0, { 0xfff8, 0 } }, }; - static void enable_dev(struct device *dev) { pnp_enable_devices(dev, &ops, Modified: trunk/src/superio/nsc/pc87309/Config.lb =================================================================== --- trunk/src/superio/nsc/pc87309/Config.lb 2009-12-23 22:16:18 UTC (rev 4992) +++ trunk/src/superio/nsc/pc87309/Config.lb 2009-12-28 09:59:44 UTC (rev 4993) @@ -1,23 +1,22 @@ -## +## ## This file is part of the coreboot project. -## +## ## Copyright (C) 2007 Uwe Hermann <uwe(a)hermann-uwe.de> -## +## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by ## the Free Software Foundation; either version 2 of the License, or ## (at your option) any later version. -## +## ## This program is distributed in the hope that it will be useful, ## but WITHOUT ANY WARRANTY; without even the implied warranty of ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ## GNU General Public License for more details. -## +## ## You should have received a copy of the GNU General Public License ## along with this program; if not, write to the Free Software ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -## +## config chip.h object superio.o - Modified: trunk/src/superio/nsc/pc87309/Makefile.inc =================================================================== --- trunk/src/superio/nsc/pc87309/Makefile.inc 2009-12-23 22:16:18 UTC (rev 4992) +++ trunk/src/superio/nsc/pc87309/Makefile.inc 2009-12-28 09:59:44 UTC (rev 4993) @@ -1,23 +1,22 @@ -## +## ## This file is part of the coreboot project. -## +## ## Copyright (C) 2007 Uwe Hermann <uwe(a)hermann-uwe.de> -## +## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by ## the Free Software Foundation; either version 2 of the License, or ## (at your option) any later version. -## +## ## This program is distributed in the hope that it will be useful, ## but WITHOUT ANY WARRANTY; without even the implied warranty of ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ## GNU General Public License for more details. -## +## ## You should have received a copy of the GNU General Public License ## along with this program; if not, write to the Free Software ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -## +## #config chip.h obj-$(CONFIG_SUPERIO_NSC_PC87309) += superio.o - Modified: trunk/src/superio/nsc/pc87309/superio.c =================================================================== --- trunk/src/superio/nsc/pc87309/superio.c 2009-12-23 22:16:18 UTC (rev 4992) +++ trunk/src/superio/nsc/pc87309/superio.c 2009-12-28 09:59:44 UTC (rev 4993) @@ -66,7 +66,7 @@ {&ops, PC87309_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x04f8, 0},}, {&ops, PC87309_SP2, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0 | PNP_DRQ1, {0x7f8, 0},}, {&ops, PC87309_SP1, PNP_IO0 | PNP_IRQ0, {0x7f8, 0},}, - // TODO: PM. + /* TODO: PM. */ {&ops, PC87309_KBCM, PNP_IRQ0}, {&ops, PC87309_KBCK, PNP_IO0 | PNP_IO1 | PNP_IRQ0, {0x7f8, 0}, {0x7f8, 0x4},}, }; Modified: trunk/src/superio/nsc/pc87351/Config.lb =================================================================== --- trunk/src/superio/nsc/pc87351/Config.lb 2009-12-23 22:16:18 UTC (rev 4992) +++ trunk/src/superio/nsc/pc87351/Config.lb 2009-12-28 09:59:44 UTC (rev 4993) @@ -1,2 +1,23 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2000 AG Electronics Ltd. +## Copyright (C) 2003-2004 Linux Networx +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + config chip.h object superio.o Modified: trunk/src/superio/nsc/pc87351/Makefile.inc =================================================================== --- trunk/src/superio/nsc/pc87351/Makefile.inc 2009-12-23 22:16:18 UTC (rev 4992) +++ trunk/src/superio/nsc/pc87351/Makefile.inc 2009-12-28 09:59:44 UTC (rev 4993) @@ -1,2 +1,23 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2000 AG Electronics Ltd. +## Copyright (C) 2003-2004 Linux Networx +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + #config chip.h obj-$(CONFIG_SUPERIO_NSC_PC87351) += superio.o Modified: trunk/src/superio/nsc/pc87351/chip.h =================================================================== --- trunk/src/superio/nsc/pc87351/chip.h 2009-12-23 22:16:18 UTC (rev 4992) +++ trunk/src/superio/nsc/pc87351/chip.h 2009-12-28 09:59:44 UTC (rev 4993) @@ -1,3 +1,24 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2000 AG Electronics Ltd. + * Copyright (C) 2003-2004 Linux Networx + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + struct chip_operations; extern struct chip_operations superio_nsc_pc87351_ops; Modified: trunk/src/superio/nsc/pc87351/pc87351.h =================================================================== --- trunk/src/superio/nsc/pc87351/pc87351.h 2009-12-23 22:16:18 UTC (rev 4992) +++ trunk/src/superio/nsc/pc87351/pc87351.h 2009-12-28 09:59:44 UTC (rev 4993) @@ -1,3 +1,24 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2000 AG Electronics Ltd. + * Copyright (C) 2003-2004 Linux Networx + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + #define PC87351_FDC 0x00 /* Floppy */ #define PC87351_PP 0x01 /* Parallel port */ #define PC87351_SP2 0x02 /* Com2 */ Modified: trunk/src/superio/nsc/pc87351/pc87351_early_serial.c =================================================================== --- trunk/src/superio/nsc/pc87351/pc87351_early_serial.c 2009-12-23 22:16:18 UTC (rev 4992) +++ trunk/src/superio/nsc/pc87351/pc87351_early_serial.c 2009-12-28 09:59:44 UTC (rev 4993) @@ -1,3 +1,24 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2000 AG Electronics Ltd. + * Copyright (C) 2003-2004 Linux Networx + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + #include <arch/romcc_io.h> #include "pc87351.h" Modified: trunk/src/superio/nsc/pc87351/superio.c =================================================================== --- trunk/src/superio/nsc/pc87351/superio.c 2009-12-23 22:16:18 UTC (rev 4992) +++ trunk/src/superio/nsc/pc87351/superio.c 2009-12-28 09:59:44 UTC (rev 4993) @@ -1,12 +1,29 @@ -/* Copyright 2000 AG Electronics Ltd. */ -/* Copyright 2003-2004 Linux Networx */ -/* This code is distributed without warranty under the GPL v2 (see COPYING) */ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2000 AG Electronics Ltd. + * Copyright (C) 2003-2004 Linux Networx + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ -/* - * Richard A Smith +/* + * Richard A Smith * I derived this code from the pc87360 device and removed the stuff the 87351 * dosen't do. -*/ + */ #include <arch/io.h> #include <device/device.h> @@ -32,7 +49,7 @@ } conf = dev->chip_info; switch(dev->path.pnp.device) { - case PC87351_SP1: + case PC87351_SP1: res0 = find_resource(dev, PNP_IDX_IO0); init_uart8250(res0->base, &conf->com1); break; @@ -57,18 +74,17 @@ }; static struct pnp_info pnp_dev_info[] = { - { &ops, PC87351_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07fa, 0}, }, - { &ops, PC87351_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x04f8, 0}, }, - { &ops, PC87351_SP2, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0 | PNP_DRQ1, { 0x7f8, 0 }, }, - { &ops, PC87351_SP1, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, }, - { &ops, PC87351_SWC, PNP_IO0 | PNP_IRQ0, { 0xfff0, 0 }, }, - { &ops, PC87351_KBCM, PNP_IRQ0 }, - { &ops, PC87351_KBCK, PNP_IO0 | PNP_IO1 | PNP_IRQ0, { 0x7f8, 0 }, { 0x7f8, 0x4}, }, - { &ops, PC87351_GPIO, PNP_IO0 | PNP_IRQ0, { 0xfff8, 0 } }, - { &ops, PC87351_FSD, PNP_IO0 | PNP_IRQ0, { 0xfff8, 0 } }, + { &ops, PC87351_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07fa, 0}, }, + { &ops, PC87351_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x04f8, 0}, }, + { &ops, PC87351_SP2, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0 | PNP_DRQ1, { 0x7f8, 0 }, }, + { &ops, PC87351_SP1, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, }, + { &ops, PC87351_SWC, PNP_IO0 | PNP_IRQ0, { 0xfff0, 0 }, }, + { &ops, PC87351_KBCM, PNP_IRQ0 }, + { &ops, PC87351_KBCK, PNP_IO0 | PNP_IO1 | PNP_IRQ0, { 0x7f8, 0 }, { 0x7f8, 0x4}, }, + { &ops, PC87351_GPIO, PNP_IO0 | PNP_IRQ0, { 0xfff8, 0 } }, + { &ops, PC87351_FSD, PNP_IO0 | PNP_IRQ0, { 0xfff8, 0 } }, }; - static void enable_dev(struct device *dev) { pnp_enable_devices(dev, &pnp_ops, Modified: trunk/src/superio/nsc/pc87360/Config.lb =================================================================== --- trunk/src/superio/nsc/pc87360/Config.lb 2009-12-23 22:16:18 UTC (rev 4992) +++ trunk/src/superio/nsc/pc87360/Config.lb 2009-12-28 09:59:44 UTC (rev 4993) @@ -1,2 +1,23 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2000 AG Electronics Ltd. +## Copyright (C) 2003-2004 Linux Networx +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + config chip.h object superio.o Modified: trunk/src/superio/nsc/pc87360/Makefile.inc =================================================================== --- trunk/src/superio/nsc/pc87360/Makefile.inc 2009-12-23 22:16:18 UTC (rev 4992) +++ trunk/src/superio/nsc/pc87360/Makefile.inc 2009-12-28 09:59:44 UTC (rev 4993) @@ -1,2 +1,23 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2000 AG Electronics Ltd. +## Copyright (C) 2003-2004 Linux Networx +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + #config chip.h obj-$(CONFIG_SUPERIO_NSC_PC87360) += superio.o Modified: trunk/src/superio/nsc/pc87360/chip.h =================================================================== --- trunk/src/superio/nsc/pc87360/chip.h 2009-12-23 22:16:18 UTC (rev 4992) +++ trunk/src/superio/nsc/pc87360/chip.h 2009-12-28 09:59:44 UTC (rev 4993) @@ -1,3 +1,24 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2000 AG Electronics Ltd. + * Copyright (C) 2003-2004 Linux Networx + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + struct chip_operations; extern struct chip_operations superio_nsc_pc87360_ops; Modified: trunk/src/superio/nsc/pc87360/pc87360.h =================================================================== --- trunk/src/superio/nsc/pc87360/pc87360.h 2009-12-23 22:16:18 UTC (rev 4992) +++ trunk/src/superio/nsc/pc87360/pc87360.h 2009-12-28 09:59:44 UTC (rev 4993) @@ -1,3 +1,24 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2000 AG Electronics Ltd. + * Copyright (C) 2003-2004 Linux Networx + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + #define PC87360_FDC 0x00 /* Floppy */ #define PC87360_PP 0x01 /* Parallel port */ #define PC87360_SP2 0x02 /* Com2 */ Modified: trunk/src/superio/nsc/pc87360/pc87360_early_serial.c =================================================================== --- trunk/src/superio/nsc/pc87360/pc87360_early_serial.c 2009-12-23 22:16:18 UTC (rev 4992) +++ trunk/src/superio/nsc/pc87360/pc87360_early_serial.c 2009-12-28 09:59:44 UTC (rev 4993) @@ -1,7 +1,27 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2000 AG Electronics Ltd. + * Copyright (C) 2003-2004 Linux Networx + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + #include <arch/romcc_io.h> #include "pc87360.h" - static void pc87360_enable_serial(device_t dev, unsigned iobase) { pnp_set_logical_device(dev); Modified: trunk/src/superio/nsc/pc87360/superio.c =================================================================== --- trunk/src/superio/nsc/pc87360/superio.c 2009-12-23 22:16:18 UTC (rev 4992) +++ trunk/src/superio/nsc/pc87360/superio.c 2009-12-28 09:59:44 UTC (rev 4993) @@ -1,6 +1,23 @@ -/* Copyright 2000 AG Electronics Ltd. */ -/* Copyright 2003-2004 Linux Networx */ -/* This code is distributed without warranty under the GPL v2 (see COPYING) */ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2000 AG Electronics Ltd. + * Copyright (C) 2003-2004 Linux Networx + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ #include <arch/io.h> #include <device/device.h> @@ -26,7 +43,7 @@ } conf = dev->chip_info; switch(dev->path.pnp.device) { - case PC87360_SP1: + case PC87360_SP1: res0 = find_resource(dev, PNP_IDX_IO0); init_uart8250(res0->base, &conf->com1); break; @@ -51,20 +68,19 @@ }; static struct pnp_info pnp_dev_info[] = { - { &ops, PC87360_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07fa, 0}, }, - { &ops, PC87360_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x04f8, 0}, }, - { &ops, PC87360_SP2, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0 | PNP_DRQ1, { 0x7f8, 0 }, }, - { &ops, PC87360_SP1, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, }, - { &ops, PC87360_SWC, PNP_IO0 | PNP_IRQ0, { 0xfff0, 0 }, }, - { &ops, PC87360_KBCM, PNP_IRQ0 }, - { &ops, PC87360_KBCK, PNP_IO0 | PNP_IO1 | PNP_IRQ0, { 0x7f8, 0 }, { 0x7f8, 0x4}, }, - { &ops, PC87360_GPIO, PNP_IO0 | PNP_IRQ0, { 0xfff8, 0 } }, - { &ops, PC87360_ACB, PNP_IO0 | PNP_IRQ0, { 0xfff8, 0 } }, - { &ops, PC87360_FSCM, PNP_IO0 | PNP_IRQ0, { 0xfff8, 0 } }, - { &ops, PC87360_WDT, PNP_IO0 | PNP_IRQ0, { 0xfffc, 0 } }, + { &ops, PC87360_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07fa, 0}, }, + { &ops, PC87360_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x04f8, 0}, }, + { &ops, PC87360_SP2, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0 | PNP_DRQ1, { 0x7f8, 0 }, }, + { &ops, PC87360_SP1, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, }, + { &ops, PC87360_SWC, PNP_IO0 | PNP_IRQ0, { 0xfff0, 0 }, }, + { &ops, PC87360_KBCM, PNP_IRQ0 }, + { &ops, PC87360_KBCK, PNP_IO0 | PNP_IO1 | PNP_IRQ0, { 0x7f8, 0 }, { 0x7f8, 0x4}, }, + { &ops, PC87360_GPIO, PNP_IO0 | PNP_IRQ0, { 0xfff8, 0 } }, + { &ops, PC87360_ACB, PNP_IO0 | PNP_IRQ0, { 0xfff8, 0 } }, + { &ops, PC87360_FSCM, PNP_IO0 | PNP_IRQ0, { 0xfff8, 0 } }, + { &ops, PC87360_WDT, PNP_IO0 | PNP_IRQ0, { 0xfffc, 0 } }, }; - static void enable_dev(struct device *dev) { pnp_enable_devices(dev, &ops, Modified: trunk/src/superio/nsc/pc87366/Config.lb =================================================================== --- trunk/src/superio/nsc/pc87366/Config.lb 2009-12-23 22:16:18 UTC (rev 4992) +++ trunk/src/superio/nsc/pc87366/Config.lb 2009-12-28 09:59:44 UTC (rev 4993) @@ -1,2 +1,23 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2000 AG Electronics Ltd. +## Copyright (C) 2003-2004 Linux Networx +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + config chip.h object superio.o Modified: trunk/src/superio/nsc/pc87366/Makefile.inc =================================================================== --- trunk/src/superio/nsc/pc87366/Makefile.inc 2009-12-23 22:16:18 UTC (rev 4992) +++ trunk/src/superio/nsc/pc87366/Makefile.inc 2009-12-28 09:59:44 UTC (rev 4993) @@ -1,2 +1,23 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2000 AG Electronics Ltd. +## Copyright (C) 2003-2004 Linux Networx +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + #config chip.h obj-$(CONFIG_SUPERIO_NSC_PC87366) += superio.o Modified: trunk/src/superio/nsc/pc87366/chip.h =================================================================== --- trunk/src/superio/nsc/pc87366/chip.h 2009-12-23 22:16:18 UTC (rev 4992) +++ trunk/src/superio/nsc/pc87366/chip.h 2009-12-28 09:59:44 UTC (rev 4993) @@ -1,3 +1,24 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2000 AG Electronics Ltd. + * Copyright (C) 2003-2004 Linux Networx + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + extern struct chip_operations superio_nsc_pc87366_ops; #include <pc80/keyboard.h> Modified: trunk/src/superio/nsc/pc87366/pc87366.h =================================================================== --- trunk/src/superio/nsc/pc87366/pc87366.h 2009-12-23 22:16:18 UTC (rev 4992) +++ trunk/src/superio/nsc/pc87366/pc87366.h 2009-12-28 09:59:44 UTC (rev 4993) @@ -1,3 +1,24 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2000 AG Electronics Ltd. + * Copyright (C) 2003-2004 Linux Networx + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + #define PC87366_FDC 0x00 /* Floppy */ #define PC87366_PP 0x01 /* Parallel port */ #define PC87366_SP2 0x02 /* Com2 */ @@ -13,4 +34,3 @@ #define PC87366_MIDI 0x0C #define PC87366_VLM 0x0D #define PC87366_TMS 0x0E - Modified: trunk/src/superio/nsc/pc87366/pc87366_early_serial.c =================================================================== --- trunk/src/superio/nsc/pc87366/pc87366_early_serial.c 2009-12-23 22:16:18 UTC (rev 4992) +++ trunk/src/superio/nsc/pc87366/pc87366_early_serial.c 2009-12-28 09:59:44 UTC (rev 4993) @@ -1,7 +1,27 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2000 AG Electronics Ltd. + * Copyright (C) 2003-2004 Linux Networx + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + #include <arch/romcc_io.h> #include "pc87366.h" - static void pc87366_enable_serial(device_t dev, unsigned iobase) { pnp_set_logical_device(dev); Modified: trunk/src/superio/nsc/pc87366/superio.c =================================================================== --- trunk/src/superio/nsc/pc87366/superio.c 2009-12-23 22:16:18 UTC (rev 4992) +++ trunk/src/superio/nsc/pc87366/superio.c 2009-12-28 09:59:44 UTC (rev 4993) @@ -1,6 +1,23 @@ -/* Copyright 2000 AG Electronics Ltd. */ -/* Copyright 2003-2004 Linux Networx */ -/* This code is distributed without warranty under the GPL v2 (see COPYING) */ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2000 AG Electronics Ltd. + * Copyright (C) 2003-2004 Linux Networx + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ #include <arch/io.h> #include <device/device.h> @@ -26,7 +43,7 @@ } conf = dev->chip_info; switch(dev->path.pnp.device) { - case PC87366_SP1: + case PC87366_SP1: res0 = find_resource(dev, PNP_IDX_IO0); init_uart8250(res0->base, &conf->com1); break; @@ -51,23 +68,22 @@ }; static struct pnp_info pnp_dev_info[] = { - { &ops, PC87366_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07fa, 0}, }, - { &ops, PC87366_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x04f8, 0}, }, - { &ops, PC87366_SP2, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0 | PNP_DRQ1, { 0x7f8, 0 }, }, - { &ops, PC87366_SP1, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, }, - { &ops, PC87366_SWC, PNP_IO0 | PNP_IRQ0, { 0xfff0, 0 }, }, - { &ops, PC87366_KBCM, PNP_IRQ0 }, - { &ops, PC87366_KBCK, PNP_IO0 | PNP_IO1 | PNP_IRQ0, { 0x7f8, 0 }, { 0x7f8, 0x4}, }, - { &ops, PC87366_GPIO, PNP_IO0 | PNP_IRQ0, { 0xfff8, 0 } }, - { &ops, PC87366_ACB, PNP_IO0 | PNP_IRQ0, { 0xfff8, 0 } }, - { &ops, PC87366_FSCM, PNP_IO0 | PNP_IRQ0, { 0xfff8, 0 } }, - { &ops, PC87366_WDT, PNP_IO0 | PNP_IRQ0, { 0xfffc, 0 } }, + { &ops, PC87366_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07fa, 0}, }, + { &ops, PC87366_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x04f8, 0}, }, + { &ops, PC87366_SP2, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0 | PNP_DRQ1, { 0x7f8, 0 }, }, + { &ops, PC87366_SP1, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, }, + { &ops, PC87366_SWC, PNP_IO0 | PNP_IRQ0, { 0xfff0, 0 }, }, + { &ops, PC87366_KBCM, PNP_IRQ0 }, + { &ops, PC87366_KBCK, PNP_IO0 | PNP_IO1 | PNP_IRQ0, { 0x7f8, 0 }, { 0x7f8, 0x4}, }, + { &ops, PC87366_GPIO, PNP_IO0 | PNP_IRQ0, { 0xfff8, 0 } }, + { &ops, PC87366_ACB, PNP_IO0 | PNP_IRQ0, { 0xfff8, 0 } }, + { &ops, PC87366_FSCM, PNP_IO0 | PNP_IRQ0, { 0xfff8, 0 } }, + { &ops, PC87366_WDT, PNP_IO0 | PNP_IRQ0, { 0xfffc, 0 } }, }; - static void enable_dev(struct device *dev) { - pnp_enable_devices(dev, &pnp_ops, + pnp_enable_devices(dev, &pnp_ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info); } Modified: trunk/src/superio/nsc/pc87417/Config.lb =================================================================== --- trunk/src/superio/nsc/pc87417/Config.lb 2009-12-23 22:16:18 UTC (rev 4992) +++ trunk/src/superio/nsc/pc87417/Config.lb 2009-12-28 09:59:44 UTC (rev 4993) @@ -1,2 +1,24 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2000 AG Electronics Ltd. +## Copyright (C) 2003-2004 Linux Networx +## Copyright (C) 2004 Tyan by yhlu +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + config chip.h object superio.o Modified: trunk/src/superio/nsc/pc87417/Makefile.inc =================================================================== --- trunk/src/superio/nsc/pc87417/Makefile.inc 2009-12-23 22:16:18 UTC (rev 4992) +++ trunk/src/superio/nsc/pc87417/Makefile.inc 2009-12-28 09:59:44 UTC (rev 4993) @@ -1,2 +1,24 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2000 AG Electronics Ltd. +## Copyright (C) 2003-2004 Linux Networx +## Copyright (C) 2004 Tyan by yhlu +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + #config chip.h obj-$(CONFIG_SUPERIO_NSC_PC87417) += superio.o Modified: trunk/src/superio/nsc/pc87417/chip.h =================================================================== --- trunk/src/superio/nsc/pc87417/chip.h 2009-12-23 22:16:18 UTC (rev 4992) +++ trunk/src/superio/nsc/pc87417/chip.h 2009-12-28 09:59:44 UTC (rev 4993) @@ -1,3 +1,25 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2000 AG Electronics Ltd. + * Copyright (C) 2003-2004 Linux Networx + * Copyright (C) 2004 Tyan by yhlu + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + extern struct chip_operations superio_nsc_pc87417_ops; #include <pc80/keyboard.h> Modified: trunk/src/superio/nsc/pc87417/pc87417.h =================================================================== --- trunk/src/superio/nsc/pc87417/pc87417.h 2009-12-23 22:16:18 UTC (rev 4992) +++ trunk/src/superio/nsc/pc87417/pc87417.h 2009-12-28 09:59:44 UTC (rev 4993) @@ -1,3 +1,25 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2000 AG Electronics Ltd. + * Copyright (C) 2003-2004 Linux Networx + * Copyright (C) 2004 Tyan by yhlu + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + #define PC87417_FDC 0x00 /* Floppy */ #define PC87417_PP 0x01 /* Parallel Port */ #define PC87417_SP2 0x02 /* Com2 */ @@ -11,7 +33,7 @@ #define PC87417_GPIO_DEV PNP_DEV(0x2e, PC87417_GPIO) /* This is to get around a romcc bug */ -//#define PC87417_XBUS_DEV PNP_DEV(0x2e, PC87417_XBUS) +/* #define PC87417_XBUS_DEV PNP_DEV(0x2e, PC87417_XBUS) */ #define PC87417_XBUS_DEV PNP_DEV(0x2e, 0x0f) #define PC87417_GPSEL 0xf0 @@ -88,5 +110,3 @@ #define PC87417_HAP1 0x14 #define PC87417_XSCNF 0x15 #define PC87417_XWBCNF 0x16 - - Modified: trunk/src/superio/nsc/pc87417/pc87417_early_init.c =================================================================== --- trunk/src/superio/nsc/pc87417/pc87417_early_init.c 2009-12-23 22:16:18 UTC (rev 4992) +++ trunk/src/superio/nsc/pc87417/pc87417_early_init.c 2009-12-28 09:59:44 UTC (rev 4993) @@ -1,3 +1,25 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2000 AG Electronics Ltd. + * Copyright (C) 2003-2004 Linux Networx + * Copyright (C) 2004 Tyan by yhlu + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + #include <arch/romcc_io.h> #include "pc87417.h" @@ -6,6 +28,7 @@ pnp_set_logical_device(dev); pnp_set_enable(dev, 0); } + static void pc87417_enable_dev(device_t dev, unsigned iobase) { pnp_set_logical_device(dev); @@ -13,6 +36,7 @@ pnp_set_iobase(dev, PNP_IDX_IO0, iobase); pnp_set_enable(dev, 1); } + static void xbus_cfg(device_t dev) { uint8_t i, data; @@ -27,5 +51,5 @@ for (i=0; i<= 0xf; i++) { outb((i<<4), xbus_index + PC87417_HAP0); } - return; -} + return; +} Modified: trunk/src/superio/nsc/pc87417/pc87417_early_serial.c =================================================================== --- trunk/src/superio/nsc/pc87417/pc87417_early_serial.c 2009-12-23 22:16:18 UTC (rev 4992) +++ trunk/src/superio/nsc/pc87417/pc87417_early_serial.c 2009-12-28 09:59:44 UTC (rev 4993) @@ -1,7 +1,28 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2000 AG Electronics Ltd. + * Copyright (C) 2003-2004 Linux Networx + * Copyright (C) 2004 Tyan by yhlu + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + #include <arch/romcc_io.h> #include "pc87417.h" - static void pc87417_enable_serial(device_t dev, unsigned iobase) { pnp_set_logical_device(dev); @@ -9,8 +30,9 @@ pnp_set_iobase(dev, PNP_IDX_IO0, iobase); pnp_set_enable(dev, 1); } + static void pc87417_enable_dev(device_t dev) { - pnp_set_logical_device(dev); - pnp_set_enable(dev, 1); + pnp_set_logical_device(dev); + pnp_set_enable(dev, 1); } Modified: trunk/src/superio/nsc/pc87417/superio.c =================================================================== --- trunk/src/superio/nsc/pc87417/superio.c 2009-12-23 22:16:18 UTC (rev 4992) +++ trunk/src/superio/nsc/pc87417/superio.c 2009-12-28 09:59:44 UTC (rev 4993) @@ -1,8 +1,24 @@ -/* Copyright 2000 AG Electronics Ltd. */ -/* Copyright 2003-2004 Linux Networx */ -/* Copyright 2005 Tyan */ -/* By yhlu */ -/* This code is distributed without warranty under the GPL v2 (see COPYING) */ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2000 AG Electronics Ltd. + * Copyright (C) 2003-2004 Linux Networx + * Copyright (C) 2004 Tyan by yhlu + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ #include <arch/io.h> #include <device/device.h> @@ -28,7 +44,7 @@ } conf = dev->chip_info; switch(dev->path.pnp.device) { - case PC87417_SP1: + case PC87417_SP1: res0 = find_resource(dev, PNP_IDX_IO0); init_uart8250(res0->base, &conf->com1); break; @@ -53,19 +69,18 @@ }; static struct pnp_info pnp_dev_info[] = { - { &ops, PC87417_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07fa, 0}, }, - { &ops, PC87417_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x04f8, 0}, }, - { &ops, PC87417_SP2, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0 | PNP_DRQ1, { 0x7f8, 0 }, }, - { &ops, PC87417_SP1, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, }, - { &ops, PC87417_SWC, PNP_IO0 | PNP_IRQ0, { 0xfff0, 0 }, }, - { &ops, PC87417_KBCM, PNP_IRQ0 }, - { &ops, PC87417_KBCK, PNP_IO0 | PNP_IO1 | PNP_IRQ0, { 0x7f8, 0 }, { 0x7f8, 0x4}, }, - { &ops, PC87417_GPIO, PNP_IO0 | PNP_IRQ0, { 0xfff8, 0 } }, - { &ops, PC87417_XBUS, PNP_IO0 | PNP_IRQ0, { 0xffe0, 0 } }, - { &ops, PC87417_RTC, PNP_IO0 | PNP_IO1, { 0xfffe, 0 }, {0xfffe, 0x4} }, + { &ops, PC87417_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07fa, 0}, }, + { &ops, PC87417_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x04f8, 0}, }, + { &ops, PC87417_SP2, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0 | PNP_DRQ1, { 0x7f8, 0 }, }, + { &ops, PC87417_SP1, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, }, + { &ops, PC87417_SWC, PNP_IO0 | PNP_IRQ0, { 0xfff0, 0 }, }, + { &ops, PC87417_KBCM, PNP_IRQ0 }, + { &ops, PC87417_KBCK, PNP_IO0 | PNP_IO1 | PNP_IRQ0, { 0x7f8, 0 }, { 0x7f8, 0x4}, }, + { &ops, PC87417_GPIO, PNP_IO0 | PNP_IRQ0, { 0xfff8, 0 } }, + { &ops, PC87417_XBUS, PNP_IO0 | PNP_IRQ0, { 0xffe0, 0 } }, + { &ops, PC87417_RTC, PNP_IO0 | PNP_IO1, { 0xfffe, 0 }, {0xfffe, 0x4} }, }; - static void enable_dev(struct device *dev) { pnp_enable_devices(dev, &pnp_ops, Modified: trunk/src/superio/nsc/pc87427/Config.lb =================================================================== --- trunk/src/superio/nsc/pc87427/Config.lb 2009-12-23 22:16:18 UTC (rev 4992) +++ trunk/src/superio/nsc/pc87427/Config.lb 2009-12-28 09:59:44 UTC (rev 4993) @@ -1,2 +1,23 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2000 AG Electronics Ltd. +## Copyright (C) 2003-2004 Linux Networx +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + config chip.h object superio.o Modified: trunk/src/superio/nsc/pc87427/Makefile.inc =================================================================== --- trunk/src/superio/nsc/pc87427/Makefile.inc 2009-12-23 22:16:18 UTC (rev 4992) +++ trunk/src/superio/nsc/pc87427/Makefile.inc 2009-12-28 09:59:44 UTC (rev 4993) @@ -1,2 +1,23 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2000 AG Electronics Ltd. +## Copyright (C) 2003-2004 Linux Networx +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + #config chip.h obj-$(CONFIG_SUPERIO_NSC_PC87427) += superio.o Modified: trunk/src/superio/nsc/pc87427/chip.h =================================================================== --- trunk/src/superio/nsc/pc87427/chip.h 2009-12-23 22:16:18 UTC (rev 4992) +++ trunk/src/superio/nsc/pc87427/chip.h 2009-12-28 09:59:44 UTC (rev 4993) @@ -1,3 +1,24 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2000 AG Electronics Ltd. + * Copyright (C) 2003-2004 Linux Networx + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + extern struct chip_operations superio_nsc_pc87427_ops; #include <pc80/keyboard.h> Modified: trunk/src/superio/nsc/pc87427/pc87427.h =================================================================== --- trunk/src/superio/nsc/pc87427/pc87427.h 2009-12-23 22:16:18 UTC (rev 4992) +++ trunk/src/superio/nsc/pc87427/pc87427.h 2009-12-28 09:59:44 UTC (rev 4993) @@ -13,7 +13,7 @@ #define PC87427_GPIO_DEV PNP_DEV(0x2e, PC87427_GPIO) /* This is to get around a romcc bug */ -//#define PC87427_XBUS_DEV PNP_DEV(0x2e, PC87427_XBUS) +/* #define PC87427_XBUS_DEV PNP_DEV(0x2e, PC87427_XBUS) */ #define PC87427_XBUS_DEV PNP_DEV(0x2e, 0x0f) #define PC87427_GPSEL 0xf0 Modified: trunk/src/superio/nsc/pc87427/pc87427_early_init.c =================================================================== --- trunk/src/superio/nsc/pc87427/pc87427_early_init.c 2009-12-23 22:16:18 UTC (rev 4992) +++ trunk/src/superio/nsc/pc87427/pc87427_early_init.c 2009-12-28 09:59:44 UTC (rev 4993) @@ -1,3 +1,24 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2000 AG Electronics Ltd. + * Copyright (C) 2003-2004 Linux Networx + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + #include <arch/romcc_io.h> #include "pc87427.h" @@ -27,5 +48,5 @@ for (i=0; i<= 0xf; i++) { outb((i<<4), xbus_index + PC87427_HAP0); } - return; -} + return; +} Modified: trunk/src/superio/nsc/pc87427/superio.c =================================================================== --- trunk/src/superio/nsc/pc87427/superio.c 2009-12-23 22:16:18 UTC (rev 4992) +++ trunk/src/superio/nsc/pc87427/superio.c 2009-12-28 09:59:44 UTC (rev 4993) @@ -1,6 +1,23 @@ -/* Copyright 2000 AG Electronics Ltd. */ -/* Copyright 2003-2004 Linux Networx */ -/* This code is distributed without warranty under the GPL v2 (see COPYING) */ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2000 AG Electronics Ltd. + * Copyright (C) 2003-2004 Linux Networx + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ #include <arch/io.h> #include <device/device.h> @@ -12,7 +29,6 @@ #include "chip.h" #include "pc87427.h" - static void init(device_t dev) { struct superio_nsc_pc87427_config *conf; @@ -25,7 +41,7 @@ } conf = dev->chip_info; switch(dev->path.pnp.device) { - case PC87427_SP1: + case PC87427_SP1: res0 = find_resource(dev, PNP_IDX_IO0); init_uart8250(res0->base, &conf->com1); break; @@ -50,26 +66,25 @@ }; static struct pnp_info pnp_dev_info[] = { - { &ops, PC87427_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07fa, 0}, }, - { &ops, PC87427_SP2, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, }, - { &ops, PC87427_SP1, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, }, - { &ops, PC87427_SWC, PNP_IO0 | PNP_IO1 | PNP_IO2 | PNP_IO3 | PNP_IRQ0, - { 0xfff0, 0 }, { 0xfffc, 0 }, { 0xfffc, 0 }, { 0xfff8, 0 } }, - { &ops, PC87427_KBCM, PNP_IRQ0 }, - { &ops, PC87427_KBCK, PNP_IO0 | PNP_IO1 | PNP_IRQ0, { 0x7f8, 0 }, { 0x7f8, 0x4}, }, - { &ops, PC87427_GPIO, PNP_IO0 | PNP_IRQ0, { 0xffe0, 0 } }, - { &ops, PC87427_WDT, PNP_IO0 | PNP_IRQ0, { 0xfff0, 0 } }, - { &ops, PC87427_FMC, PNP_IO0 | PNP_IRQ0, { 0xffe0, 0 } }, - { &ops, PC87427_XBUS, PNP_IO0 | PNP_IRQ0, { 0xffe0, 0 } }, - { &ops, PC87427_RTC, PNP_IO0 | PNP_IO1 | PNP_IRQ0, { 0xfffe, 0 }, { 0xfffe, 0 } }, - { &ops, PC87427_MHC, PNP_IO0 | PNP_IO1 | PNP_IRQ0, { 0xffe0, 0 }, { 0xffe0, 0 } }, + { &ops, PC87427_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07fa, 0}, }, + { &ops, PC87427_SP2, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, }, + { &ops, PC87427_SP1, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, }, + { &ops, PC87427_SWC, PNP_IO0 | PNP_IO1 | PNP_IO2 | PNP_IO3 | PNP_IRQ0, + { 0xfff0, 0 }, { 0xfffc, 0 }, { 0xfffc, 0 }, { 0xfff8, 0 } }, + { &ops, PC87427_KBCM, PNP_IRQ0 }, + { &ops, PC87427_KBCK, PNP_IO0 | PNP_IO1 | PNP_IRQ0, { 0x7f8, 0 }, { 0x7f8, 0x4}, }, + { &ops, PC87427_GPIO, PNP_IO0 | PNP_IRQ0, { 0xffe0, 0 } }, + { &ops, PC87427_WDT, PNP_IO0 | PNP_IRQ0, { 0xfff0, 0 } }, + { &ops, PC87427_FMC, PNP_IO0 | PNP_IRQ0, { 0xffe0, 0 } }, + { &ops, PC87427_XBUS, PNP_IO0 | PNP_IRQ0, { 0xffe0, 0 } }, + { &ops, PC87427_RTC, PNP_IO0 | PNP_IO1 | PNP_IRQ0, { 0xfffe, 0 }, { 0xfffe, 0 } }, + { &ops, PC87427_MHC, PNP_IO0 | PNP_IO1 | PNP_IRQ0, { 0xffe0, 0 }, { 0xffe0, 0 } }, }; - static void enable_dev(struct device *dev) { pnp_enable_devices(dev, &ops, - ARRAY_SIZE(pnp_dev_info), pnp_dev_info); + ARRAY_SIZE(pnp_dev_info), pnp_dev_info); } struct chip_operations superio_nsc_pc87427_ops = { Modified: trunk/src/superio/nsc/pc97307/Config.lb =================================================================== --- trunk/src/superio/nsc/pc97307/Config.lb 2009-12-23 22:16:18 UTC (rev 4992) +++ trunk/src/superio/nsc/pc97307/Config.lb 2009-12-28 09:59:44 UTC (rev 4993) @@ -1,2 +1,22 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2000 AG Electronics Ltd. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + config chip.h object superio.c Modified: trunk/src/superio/nsc/pc97307/Makefile.inc =================================================================== --- trunk/src/superio/nsc/pc97307/Makefile.inc 2009-12-23 22:16:18 UTC (rev 4992) +++ trunk/src/superio/nsc/pc97307/Makefile.inc 2009-12-28 09:59:44 UTC (rev 4993) @@ -1,2 +1,22 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2000 AG Electronics Ltd. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + #config chip.h obj-$(CONFIG_SUPERIO_NSC_PC97307) += superio.o Modified: trunk/src/superio/nsc/pc97307/chip.h =================================================================== --- trunk/src/superio/nsc/pc97307/chip.h 2009-12-23 22:16:18 UTC (rev 4992) +++ trunk/src/superio/nsc/pc97307/chip.h 2009-12-28 09:59:44 UTC (rev 4993) @@ -1,3 +1,23 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2000 AG Electronics Ltd. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + #ifndef _SUPERIO_NSC_PC97307 #define _SUPERIO_NSC_PC97307 Modified: trunk/src/superio/nsc/pc97307/pc97307.h =================================================================== --- trunk/src/superio/nsc/pc97307/pc97307.h 2009-12-23 22:16:18 UTC (rev 4992) +++ trunk/src/superio/nsc/pc97307/pc97307.h 2009-12-28 09:59:44 UTC (rev 4993) @@ -1,3 +1,23 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2000 AG Electronics Ltd. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + #define PC97307_KBCK 0x00 /* Keyboard */ #define PC97307_KBCM 0x01 /* Mouse */ #define PC97307_RTC 0x02 /* Real-Time Clock */ Modified: trunk/src/superio/nsc/pc97307/superio.c =================================================================== --- trunk/src/superio/nsc/pc97307/superio.c 2009-12-23 22:16:18 UTC (rev 4992) +++ trunk/src/superio/nsc/pc97307/superio.c 2009-12-28 09:59:44 UTC (rev 4993) @@ -1,5 +1,22 @@ -/* Copyright 2000 AG Electronics Ltd. */ -/* This code is distributed without warranty under the GPL v2 (see COPYING) */ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2000 AG Electronics Ltd. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ #include <arch/io.h> #include <console/console.h> @@ -66,15 +83,15 @@ }; static struct pnp_info pnp_dev_info[] = { - { &ops, PC97307_KBCK, PNP_IO0 | PNP_IO1 | PNP_IRQ0, { 0xffb, 0 }, { 0xffb, 0x4}, }, - { &ops, PC97307_KBCM, PNP_IRQ0 }, - { &ops, PC97307_RTC, PNP_IO0 | PNP_IRQ0, { 0xfffe, 0}, }, - { &ops, PC97307_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0xfffa, 0}, }, - { &ops, PC97307_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x03fc, 0}, }, - { &ops, PC97307_SP2, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0 | PNP_DRQ1, { 0xfff8, 0 }, }, - { &ops, PC97307_SP1, PNP_IO0 | PNP_IRQ0, { 0xfff8, 0 }, }, - { &ops, PC97307_GPIO, PNP_IO0, { 0xfff8, 0 } }, - { &ops, PC97307_PM, PNP_IO0, { 0xfffe, 0 } }, + { &ops, PC97307_KBCK, PNP_IO0 | PNP_IO1 | PNP_IRQ0, { 0xffb, 0 }, { 0xffb, 0x4}, }, + { &ops, PC97307_KBCM, PNP_IRQ0 }, + { &ops, PC97307_RTC, PNP_IO0 | PNP_IRQ0, { 0xfffe, 0}, }, + { &ops, PC97307_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0xfffa, 0}, }, + { &ops, PC97307_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x03fc, 0}, }, + { &ops, PC97307_SP2, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0 | PNP_DRQ1, { 0xfff8, 0 }, }, + { &ops, PC97307_SP1, PNP_IO0 | PNP_IRQ0, { 0xfff8, 0 }, }, + { &ops, PC97307_GPIO, PNP_IO0, { 0xfff8, 0 } }, + { &ops, PC97307_PM, PNP_IO0, { 0xfffe, 0 } }, }; static void enable_dev(struct device *dev) Modified: trunk/src/superio/nsc/pc97317/Config.lb =================================================================== --- trunk/src/superio/nsc/pc97317/Config.lb 2009-12-23 22:16:18 UTC (rev 4992) +++ trunk/src/superio/nsc/pc97317/Config.lb 2009-12-28 09:59:44 UTC (rev 4993) @@ -1,2 +1,22 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2000 AG Electronics Ltd. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + config chip.h object superio.c Modified: trunk/src/superio/nsc/pc97317/Makefile.inc =================================================================== --- trunk/src/superio/nsc/pc97317/Makefile.inc 2009-12-23 22:16:18 UTC (rev 4992) +++ trunk/src/superio/nsc/pc97317/Makefile.inc 2009-12-28 09:59:44 UTC (rev 4993) @@ -1,2 +1,22 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2000 AG Electronics Ltd. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + #config chip.h obj-$(CONFIG_SUPERIO_NSC_PC97317) += superio.o Modified: trunk/src/superio/nsc/pc97317/chip.h =================================================================== --- trunk/src/superio/nsc/pc97317/chip.h 2009-12-23 22:16:18 UTC (rev 4992) +++ trunk/src/superio/nsc/pc97317/chip.h 2009-12-28 09:59:44 UTC (rev 4993) @@ -1,3 +1,23 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2000 AG Electronics Ltd. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + #ifndef _SUPERIO_NSC_PC97317 #define _SUPERIO_NSC_PC97317 @@ -17,4 +37,5 @@ struct uart8250 com1, com2; struct pc_keyboard keyboard; }; + #endif /* _SUPERIO_NSC_PC97317 */ Modified: trunk/src/superio/nsc/pc97317/pc97317.h =================================================================== --- trunk/src/superio/nsc/pc97317/pc97317.h 2009-12-23 22:16:18 UTC (rev 4992) +++ trunk/src/superio/nsc/pc97317/pc97317.h 2009-12-28 09:59:44 UTC (rev 4993) @@ -1,3 +1,23 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2000 AG Electronics Ltd. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + #define PC97317_KBCK 0x00 /* Keyboard */ #define PC97317_KBCM 0x01 /* Mouse */ #define PC97317_RTC 0x02 /* Real-Time Clock */ @@ -7,4 +27,3 @@ #define PC97317_SP1 0x06 /* Com1 */ #define PC97317_GPIO 0x07 #define PC97317_PM 0x08 /* Power Management */ - Modified: trunk/src/superio/nsc/pc97317/pc97317_early_serial.c =================================================================== --- trunk/src/superio/nsc/pc97317/pc97317_early_serial.c 2009-12-23 22:16:18 UTC (rev 4992) +++ trunk/src/superio/nsc/pc97317/pc97317_early_serial.c 2009-12-28 09:59:44 UTC (rev 4993) @@ -1,3 +1,23 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2000 AG Electronics Ltd. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + #include <arch/romcc_io.h> #include "pc97317.h" @@ -19,7 +39,7 @@ outb(0x03, PM_BASE); outb(inb(PM_BASE + 1) | 0x07, PM_BASE + 1); - + /* Wait for the clock to stabilise */ while(!inb(PM_BASE + 1 & 0x80)) ; Modified: trunk/src/superio/nsc/pc97317/superio.c =================================================================== --- trunk/src/superio/nsc/pc97317/superio.c 2009-12-23 22:16:18 UTC (rev 4992) +++ trunk/src/superio/nsc/pc97317/superio.c 2009-12-28 09:59:44 UTC (rev 4993) @@ -1,5 +1,22 @@ -/* Copyright 2000 AG Electronics Ltd. */ -/* This code is distributed without warranty under the GPL v2 (see COPYING) */ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2000 AG Electronics Ltd. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ #include <arch/io.h> #include <console/console.h> @@ -68,15 +85,15 @@ }; static struct pnp_info pnp_dev_info[] = { - { &ops, PC97317_KBCK, PNP_IO0 | PNP_IO1 | PNP_IRQ0, { 0xffb, 0 }, { 0xffb, 0x4}, }, - { &ops, PC97317_KBCM, PNP_IRQ0 }, - { &ops, PC97317_RTC, PNP_IO0 | PNP_IRQ0, { 0xfffe, 0}, }, - { &ops, PC97317_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0xfffa, 0}, }, - { &ops, PC97317_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x03fc, 0}, }, - { &ops, PC97317_SP2, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0 | PNP_DRQ1, { 0xfff8, 0 }, }, - { &ops, PC97317_SP1, PNP_IO0 | PNP_IRQ0, { 0xfff8, 0 }, }, - { &ops, PC97317_GPIO, PNP_IO0, { 0xfff8, 0 } }, - { &ops, PC97317_PM, PNP_IO0, { 0xfffe, 0 } }, + { &ops, PC97317_KBCK, PNP_IO0 | PNP_IO1 | PNP_IRQ0, { 0xffb, 0 }, { 0xffb, 0x4}, }, + { &ops, PC97317_KBCM, PNP_IRQ0 }, + { &ops, PC97317_RTC, PNP_IO0 | PNP_IRQ0, { 0xfffe, 0}, }, + { &ops, PC97317_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0xfffa, 0}, }, + { &ops, PC97317_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x03fc, 0}, }, + { &ops, PC97317_SP2, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0 | PNP_DRQ1, { 0xfff8, 0 }, }, + { &ops, PC97317_SP1, PNP_IO0 | PNP_IRQ0, { 0xfff8, 0 }, }, + { &ops, PC97317_GPIO, PNP_IO0, { 0xfff8, 0 } }, + { &ops, PC97317_PM, PNP_IO0, { 0xfffe, 0 } }, }; static void enable_dev(struct device *dev) Modified: trunk/src/superio/smsc/fdc37m60x/Config.lb =================================================================== --- trunk/src/superio/smsc/fdc37m60x/Config.lb 2009-12-23 22:16:18 UTC (rev 4992) +++ trunk/src/superio/smsc/fdc37m60x/Config.lb 2009-12-28 09:59:44 UTC (rev 4993) @@ -20,4 +20,3 @@ config chip.h object superio.o - Modified: trunk/src/superio/smsc/fdc37m60x/Makefile.inc =================================================================== --- trunk/src/superio/smsc/fdc37m60x/Makefile.inc 2009-12-23 22:16:18 UTC (rev 4992) +++ trunk/src/superio/smsc/fdc37m60x/Makefile.inc 2009-12-28 09:59:44 UTC (rev 4993) @@ -20,4 +20,3 @@ #config chip.h obj-$(CONFIG_SUPERIO_SMSC_FDC37M60X) += superio.o - Modified: trunk/src/superio/smsc/fdc37m60x/chip.h =================================================================== --- trunk/src/superio/smsc/fdc37m60x/chip.h 2009-12-23 22:16:18 UTC (rev 4992) +++ trunk/src/superio/smsc/fdc37m60x/chip.h 2009-12-28 09:59:44 UTC (rev 4993) @@ -33,4 +33,3 @@ }; #endif /* _SUPERIO_SMSC_FDC37M60X */ - Modified: trunk/src/superio/smsc/fdc37m60x/fdc37m60x.h =================================================================== --- trunk/src/superio/smsc/fdc37m60x/fdc37m60x.h 2009-12-23 22:16:18 UTC (rev 4992) +++ trunk/src/superio/smsc/fdc37m60x/fdc37m60x.h 2009-12-28 09:59:44 UTC (rev 4993) @@ -36,4 +36,3 @@ #define FDC37M60X_SP2 0x05 /* Com2 */ #define FDC37M60X_KBCK 0x07 /* Keyboard */ #define FDC37M60X_AUX 0x08 /* Auxiliary I/O */ - Modified: trunk/src/superio/smsc/fdc37m60x/fdc37m60x_early_serial.c =================================================================== --- trunk/src/superio/smsc/fdc37m60x/fdc37m60x_early_serial.c 2009-12-23 22:16:18 UTC (rev 4992) +++ trunk/src/superio/smsc/fdc37m60x/fdc37m60x_early_serial.c 2009-12-28 09:59:44 UTC (rev 4993) @@ -75,4 +75,3 @@ /* (3) Exit the configuration state. */ outb(0xaa, FDC37M60X_CONFIGURATION_PORT); } - Modified: trunk/src/superio/smsc/fdc37m60x/superio.c =================================================================== --- trunk/src/superio/smsc/fdc37m60x/superio.c 2009-12-23 22:16:18 UTC (rev 4992) +++ trunk/src/superio/smsc/fdc37m60x/superio.c 2009-12-28 09:59:44 UTC (rev 4993) @@ -70,9 +70,9 @@ /* TODO: FDC, PP, AUX. */ static struct pnp_info pnp_dev_info[] = { - { &ops, FDC37M60X_SP1, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, }, - { &ops, FDC37M60X_SP2, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0 | PNP_DRQ1, { 0x7f8, 0 }, }, - { &ops, FDC37M60X_KBCK, PNP_IO0 | PNP_IO1 | PNP_IRQ0, { 0x7f8, 0 }, { 0x7f8, 0x4}, }, + { &ops, FDC37M60X_SP1, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, }, + { &ops, FDC37M60X_SP2, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0 | PNP_DRQ1, { 0x7f8, 0 }, }, + { &ops, FDC37M60X_KBCK, PNP_IO0 | PNP_IO1 | PNP_IRQ0, { 0x7f8, 0 }, { 0x7f8, 0x4}, }, }; static void enable_dev(struct device *dev) @@ -85,4 +85,3 @@ CHIP_NAME("SMSC FDC37M60X Super I/O") .enable_dev = enable_dev, }; - Modified: trunk/src/superio/smsc/lpc47b272/Config.lb =================================================================== --- trunk/src/superio/smsc/lpc47b272/Config.lb 2009-12-23 22:16:18 UTC (rev 4992) +++ trunk/src/superio/smsc/lpc47b272/Config.lb 2009-12-28 09:59:44 UTC (rev 4993) @@ -20,4 +20,3 @@ config chip.h object superio.o - Modified: trunk/src/superio/smsc/lpc47b272/Makefile.inc =================================================================== --- trunk/src/superio/smsc/lpc47b272/Makefile.inc 2009-12-23 22:16:18 UTC (rev 4992) +++ trunk/src/superio/smsc/lpc47b272/Makefile.inc 2009-12-28 09:59:44 UTC (rev 4993) @@ -20,4 +20,3 @@ #config chip.h obj-$(CONFIG_SUPERIO_SMSC_LPC47B272) += superio.o - Modified: trunk/src/superio/smsc/lpc47b272/lpc47b272.h =================================================================== --- trunk/src/superio/smsc/lpc47b272/lpc47b272.h 2009-12-23 22:16:18 UTC (rev 4992) +++ trunk/src/superio/smsc/lpc47b272/lpc47b272.h 2009-12-28 09:59:44 UTC (rev 4993) @@ -26,4 +26,3 @@ #define LPC47B272_RT 10 /* Runtime reg*/ #define LPC47B272_MAX_CONFIG_REGISTER 0x5F - Modified: trunk/src/superio/smsc/lpc47b272/lpc47b272_early_serial.c =================================================================== --- trunk/src/superio/smsc/lpc47b272/lpc47b272_early_serial.c 2009-12-23 22:16:18 UTC (rev 4992) +++ trunk/src/superio/smsc/lpc47b272/lpc47b272_early_serial.c 2009-12-28 09:59:44 UTC (rev 4993) @@ -23,37 +23,39 @@ #include <arch/romcc_io.h> #include "lpc47b272.h" -//---------------------------------------------------------------------------------- -// Function: pnp_enter_conf_state -// Parameters: dev - high 8 bits = Super I/O port -// Return Value: None -// Description: Enable access to the LPC47B272's configuration registers. -// -static inline void pnp_enter_conf_state(device_t dev) { +/* + * Function: pnp_enter_conf_state + * Parameters: dev - high 8 bits = Super I/O port + * Return Value: None + * Description: Enable access to the LPC47B272's configuration registers. + */ +static inline void pnp_enter_conf_state(device_t dev) +{ unsigned port = dev>>8; - outb(0x55, port); + outb(0x55, port); } -//---------------------------------------------------------------------------------- -// Function: pnp_exit_conf_state -// Parameters: dev - high 8 bits = Super I/O port -// Return Value: None -// Description: Disable access to the LPC47B272's configuration registers. -// -static void pnp_exit_conf_state(device_t dev) { +/* + * Function: pnp_exit_conf_state + * Parameters: dev - high 8 bits = Super I/O port + * Return Value: None + * Description: Disable access to the LPC47B272's configuration registers. + */ +static void pnp_exit_conf_state(device_t dev) +{ unsigned port = dev>>8; - outb(0xaa, port); + outb(0xaa, port); } -//---------------------------------------------------------------------------------- -// Function: lpc47b272_enable_serial -// Parameters: dev - high 8 bits = Super I/O port, -// low 8 bits = logical device number (per lpc47b272.h) -// iobase - processor I/O port address to assign to this serial device -// Return Value: bool -// Description: Configure the base I/O port of the specified serial device -// and enable the serial device. -// +/* + * Function: lpc47b272_enable_serial + * Parameters: dev - high 8 bits = Super I/O port, + * low 8 bits = logical device number (per lpc47b272.h) + * iobase - processor I/O port address to assign to this serial device + * Return Value: bool + * Description: Configure the base I/O port of the specified serial device + * and enable the serial device. + */ static void lpc47b272_enable_serial(device_t dev, unsigned iobase) { pnp_enter_conf_state(dev); Modified: trunk/src/superio/smsc/lpc47b272/superio.c =================================================================== --- trunk/src/superio/smsc/lpc47b272/superio.c 2009-12-23 22:16:18 UTC (rev 4992) +++ trunk/src/superio/smsc/lpc47b272/superio.c 2009-12-28 09:59:44 UTC (rev 4993) @@ -3,7 +3,7 @@ * * Copyright (C) 2000 AG Electronics Ltd. * Copyright (C) 2003-2004 Linux Networx - * Copyright (C) 2004 Tyan + * Copyright (C) 2004 Tyan * Copyright (C) 2005 Digital Design Corporation * * This program is free software; you can redistribute it and/or modify @@ -36,7 +36,7 @@ #include "chip.h" #include "lpc47b272.h" -// Forward declarations +/* Forward declarations */ static void enable_dev(device_t dev); static void lpc47b272_pnp_set_resources(device_t dev); static void lpc47b272_pnp_enable_resources(device_t dev); @@ -47,7 +47,6 @@ static void pnp_exit_conf_state(device_t dev); static void dump_pnp_device(device_t dev); - struct chip_operations superio_smsc_lpc47b272_ops = { CHIP_NAME("SMSC LPC47B272 Super I/O") .enable_dev = enable_dev @@ -62,56 +61,56 @@ }; static struct pnp_info pnp_dev_info[] = { - { &ops, LPC47B272_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07f8, 0}, }, - { &ops, LPC47B272_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07f8, 0}, }, - { &ops, LPC47B272_SP1, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, }, - { &ops, LPC47B272_SP2, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, }, - { &ops, LPC47B272_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1, { 0x7ff, 0 }, { 0x7ff, 0x4}, }, - { &ops, LPC47B272_RT, PNP_IO0, { 0x780, 0 }, }, + { &ops, LPC47B272_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07f8, 0}, }, + { &ops, LPC47B272_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07f8, 0}, }, + { &ops, LPC47B272_SP1, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, }, + { &ops, LPC47B272_SP2, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, }, + { &ops, LPC47B272_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1, { 0x7ff, 0 }, { 0x7ff, 0x4}, }, + { &ops, LPC47B272_RT, PNP_IO0, { 0x780, 0 }, }, }; /**********************************************************************************/ -/* PUBLIC INTERFACE */ +/* PUBLIC INTERFACE */ /**********************************************************************************/ -//---------------------------------------------------------------------------------- -// Function: enable_dev -// Parameters: dev - pointer to structure describing a Super I/O device -// Return Value: None -// Description: Create device structures and allocate resources to devices -// specified in the pnp_dev_info array (above). -// +/* + * Function: enable_dev + * Parameters: dev - pointer to structure describing a Super I/O device + * Return Value: None + * Description: Create device structures and allocate resources to devices + * specified in the pnp_dev_info array (above). + */ static void enable_dev(device_t dev) { - pnp_enable_devices(dev, &pnp_ops, - ARRAY_SIZE(pnp_dev_info), - pnp_dev_info); + pnp_enable_devices(dev, &pnp_ops, + ARRAY_SIZE(pnp_dev_info), + pnp_dev_info); } -//---------------------------------------------------------------------------------- -// Function: lpc47b272_pnp_set_resources -// Parameters: dev - pointer to structure describing a Super I/O device -// Return Value: None -// Description: Configure the specified Super I/O device with the resources -// (I/O space, etc.) that have been allocated for it. -// +/* + * Function: lpc47b272_pnp_set_resources + * Parameters: dev - pointer to structure describing a Super I/O device + * Return Value: None + * Description: Configure the specified Super I/O device with the resources + * (I/O space, etc.) that have been allocated for it. + */ static void lpc47b272_pnp_set_resources(device_t dev) { - pnp_enter_conf_state(dev); + pnp_enter_conf_state(dev); pnp_set_resources(dev); - pnp_exit_conf_state(dev); -} + pnp_exit_conf_state(dev); +} static void lpc47b272_pnp_enable_resources(device_t dev) -{ +{ pnp_enter_conf_state(dev); - pnp_enable_resources(dev); - pnp_exit_conf_state(dev); + pnp_enable_resources(dev); + pnp_exit_conf_state(dev); } static void lpc47b272_pnp_enable(device_t dev) { - pnp_enter_conf_state(dev); + pnp_enter_conf_state(dev); pnp_set_logical_device(dev); if(dev->enabled) { @@ -120,17 +119,17 @@ else { pnp_set_enable(dev, 0); } - pnp_exit_conf_state(dev); + pnp_exit_conf_state(dev); } -//---------------------------------------------------------------------------------- -// Function: lpc47b272_init -// Parameters: dev - pointer to structure describing a Super I/O device -// Return Value: None -// Description: Initialize the specified Super I/O device. -// Devices other than COM ports and the keyboard controller are -// ignored. For COM ports, we configure the baud rate. -// +/* + * Function: lpc47b272_init + * Parameters: dev - pointer to structure describing a Super I/O device + * Return Value: None + * Description: Initialize the specified Super I/O device. + * Devices other than COM ports and the keyboard controller are + * ignored. For COM ports, we configure the baud rate. + */ static void lpc47b272_init(device_t dev) { struct superio_smsc_lpc47b272_config *conf = dev->chip_info; @@ -138,18 +137,18 @@ if (!dev->enabled) return; - + switch(dev->path.pnp.device) { - case LPC47B272_SP1: + case LPC47B272_SP1: res0 = find_resource(dev, PNP_IDX_IO0); init_uart8250(res0->base, &conf->com1); break; - + case LPC47B272_SP2: res0 = find_resource(dev, PNP_IDX_IO0); init_uart8250(res0->base, &conf->com2); break; - + case LPC47B272_KBC: res0 = find_resource(dev, PNP_IDX_IO0); res1 = find_resource(dev, PNP_IDX_IO1); @@ -159,65 +158,65 @@ } /**********************************************************************************/ -/* PRIVATE FUNCTIONS */ +/* PRIVATE FUNCTIONS */ /**********************************************************************************/ -//---------------------------------------------------------------------------------- -// Function: pnp_enter_conf_state -// Parameters: dev - pointer to structure describing a Super I/O device -// Return Value: None -// Description: Enable access to the LPC47B272's configuration registers. -// -static void pnp_enter_conf_state(device_t dev) +/* + * Function: pnp_enter_conf_state + * Parameters: dev - pointer to structure describing a Super I/O device + * Return Value: None + * Description: Enable access to the LPC47B272's configuration registers. + */ +static void pnp_enter_conf_state(device_t dev) { outb(0x55, dev->path.pnp.port); } -//---------------------------------------------------------------------------------- -// Function: pnp_exit_conf_state -// Parameters: dev - pointer to structure describing a Super I/O device -// Return Value: None -// Description: Disable access to the LPC47B272's configuration registers. -// -static void pnp_exit_conf_state(device_t dev) +/* + * Function: pnp_exit_conf_state + * Parameters: dev - pointer to structure describing a Super I/O device + * Return Value: None + * Description: Disable access to the LPC47B272's configuration registers. + */ +static void pnp_exit_conf_state(device_t dev) { - outb(0xaa, dev->path.pnp.port); + outb(0xaa, dev->path.pnp.port); } #if 0 -//---------------------------------------------------------------------------------- -// Function: dump_pnp_device -// Parameters: dev - pointer to structure describing a Super I/O device -// Return Value: None -// Description: Print the values of all of the LPC47B272's configuration registers. -// NOTE: The LPC47B272 must be in configuration mode when this -// function is called. -// +/* + * Function: dump_pnp_device + * Parameters: dev - pointer to structure describing a Super I/O device + * Return Value: None + * Description: Print the values of all of the LPC47B272's configuration registers. + * NOTE: The LPC47B272 must be in configuration mode when this + * function is called. + */ static void dump_pnp_device(device_t dev) { - int register_index; - print_debug("\r\n"); + int register_index; + print_debug("\r\n"); - for(register_index = 0; register_index <= LPC47B272_MAX_CONFIG_REGISTER; register_index++) { - uint8_t register_value; + for(register_index = 0; register_index <= LPC47B272_MAX_CONFIG_REGISTER; register_index++) { + uint8_t register_value; - if ((register_index & 0x0f) == 0) { - print_debug_hex8(register_index); - print_debug_char(':'); - } + if ((register_index & 0x0f) == 0) { + print_debug_hex8(register_index); + print_debug_char(':'); + } - // Skip over 'register' that would cause exit from configuration mode - if (register_index == 0xaa) + /* Skip over 'register' that would cause exit from configuration mode */ + if (register_index == 0xaa) register_value = 0xaa; else - register_value = pnp_read_config(dev, register_index); + register_value = pnp_read_config(dev, register_index); - print_debug_char(' '); - print_debug_hex8(register_value); - if ((register_index & 0x0f) == 0x0f) { - print_debug("\r\n"); - } - } + print_debug_char(' '); + print_debug_hex8(register_value); + if ((register_index & 0x0f) == 0x0f) { + print_debug("\r\n"); + } + } print_debug("\r\n"); } Modified: trunk/src/superio/smsc/lpc47b397/Config.lb =================================================================== --- trunk/src/superio/smsc/lpc47b397/Config.lb 2009-12-23 22:16:18 UTC (rev 4992) +++ trunk/src/superio/smsc/lpc47b397/Config.lb 2009-12-28 09:59:44 UTC (rev 4993) @@ -1,2 +1,24 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2000 AG Electronics Ltd. +## Copyright (C) 2003-2004 Linux Networx +## Copyright (C) 2004 Tyan +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + config chip.h object superio.o Modified: trunk/src/superio/smsc/lpc47b397/Makefile.inc =================================================================== --- trunk/src/superio/smsc/lpc47b397/Makefile.inc 2009-12-23 22:16:18 UTC (rev 4992) +++ trunk/src/superio/smsc/lpc47b397/Makefile.inc 2009-12-28 09:59:44 UTC (rev 4993) @@ -1,2 +1,24 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2000 AG Electronics Ltd. +## Copyright (C) 2003-2004 Linux Networx +## Copyright (C) 2004 Tyan +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + #config chip.h obj-$(CONFIG_SUPERIO_SMSC_LPC47B397) += superio.o Modified: trunk/src/superio/smsc/lpc47b397/chip.h =================================================================== --- trunk/src/superio/smsc/lpc47b397/chip.h 2009-12-23 22:16:18 UTC (rev 4992) +++ trunk/src/superio/smsc/lpc47b397/chip.h 2009-12-28 09:59:44 UTC (rev 4993) @@ -1,3 +1,25 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2000 AG Electronics Ltd. + * Copyright (C) 2003-2004 Linux Networx + * Copyright (C) 2004 Tyan + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + struct chip_operations; extern struct chip_operations superio_smsc_lpc47b397_ops; Modified: trunk/src/superio/smsc/lpc47b397/lpc47b397.h =================================================================== --- trunk/src/superio/smsc/lpc47b397/lpc47b397.h 2009-12-23 22:16:18 UTC (rev 4992) +++ trunk/src/superio/smsc/lpc47b397/lpc47b397.h 2009-12-28 09:59:44 UTC (rev 4993) @@ -1,3 +1,25 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2000 AG Electronics Ltd. + * Copyright (C) 2003-2004 Linux Networx + * Copyright (C) 2004 Tyan + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + #define LPC47B397_FDC 0 /* Floppy */ #define LPC47B397_PP 3 /* Parallel Port */ #define LPC47B397_SP1 4 /* Com1 */ Modified: trunk/src/superio/smsc/lpc47b397/lpc47b397_early_gpio.c =================================================================== --- trunk/src/superio/smsc/lpc47b397/lpc47b397_early_gpio.c 2009-12-23 22:16:18 UTC (rev 4992) +++ trunk/src/superio/smsc/lpc47b397/lpc47b397_early_gpio.c 2009-12-28 09:59:44 UTC (rev 4993) @@ -1,3 +1,25 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2000 AG Electronics Ltd. + * Copyright (C) 2003-2004 Linux Networx + * Copyright (C) 2004 Tyan + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + static void lpc47b397_gpio_offset_out(unsigned iobase, unsigned offset, unsigned value) { outb(value,iobase+offset); @@ -8,7 +30,7 @@ return inb(iobase+offset); } -//for GP60-GP64, GP66-GP85 +/* for GP60-GP64, GP66-GP85 */ #define LPC47B397_GPIO_CNTL_INDEX 0x70 #define LPC47B397_GPIO_CNTL_DATA 0x71 @@ -23,4 +45,3 @@ outb(index,iobase+LPC47B397_GPIO_CNTL_INDEX); return inb(iobase+LPC47B397_GPIO_CNTL_DATA); } - Modified: trunk/src/superio/smsc/lpc47b397/lpc47b397_early_serial.c =================================================================== --- trunk/src/superio/smsc/lpc47b397/lpc47b397_early_serial.c 2009-12-23 22:16:18 UTC (rev 4992) +++ trunk/src/superio/smsc/lpc47b397/lpc47b397_early_serial.c 2009-12-28 09:59:44 UTC (rev 4993) @@ -1,12 +1,36 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2000 AG Electronics Ltd. + * Copyright (C) 2003-2004 Linux Networx + * Copyright (C) 2004 Tyan + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + #include <arch/romcc_io.h> #include "lpc47b397.h" -static inline void pnp_enter_conf_state(device_t dev) { +static inline void pnp_enter_conf_state(device_t dev) +{ unsigned port = dev>>8; outb(0x55, port); } -static void pnp_exit_conf_state(device_t dev) { +static void pnp_exit_conf_state(device_t dev) +{ unsigned port = dev>>8; outb(0xaa, port); } Modified: trunk/src/superio/smsc/lpc47b397/superio.c =================================================================== --- trunk/src/superio/smsc/lpc47b397/superio.c 2009-12-23 22:16:18 UTC (rev 4992) +++ trunk/src/superio/smsc/lpc47b397/superio.c 2009-12-28 09:59:44 UTC (rev 4993) @@ -1,10 +1,25 @@ -/* Copyright 2000 AG Electronics Ltd. */ -/* Copyright 2003-2004 Linux Networx */ -/* Copyright 2004 Tyan +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2000 AG Electronics Ltd. + * Copyright (C) 2003-2004 Linux Networx + * Copyright (C) 2004 Tyan + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -/* This code is distributed without warranty under the GPL v2 (see COPYING) */ - #include <arch/io.h> #include <device/device.h> #include <device/pnp.h> @@ -18,11 +33,12 @@ #include "chip.h" #include "lpc47b397.h" - -static void pnp_enter_conf_state(device_t dev) { +static void pnp_enter_conf_state(device_t dev) +{ outb(0x55, dev->path.pnp.port); } -static void pnp_exit_conf_state(device_t dev) { +static void pnp_exit_conf_state(device_t dev) +{ outb(0xaa, dev->path.pnp.port); } @@ -38,7 +54,8 @@ return inb(port_base + 1); } -static void enable_hwm_smbus(device_t dev) { +static void enable_hwm_smbus(device_t dev) +{ /* enable SensorBus register access */ uint8_t reg, value; reg = 0xf0; @@ -47,7 +64,6 @@ pnp_write_config(dev, reg, value); } - static void lpc47b397_init(device_t dev) { struct superio_smsc_lpc47b397_config *conf; @@ -71,29 +87,21 @@ init_pc_keyboard(res0->base, res1->base, &conf->keyboard); break; } - } static void lpc47b397_pnp_set_resources(device_t dev) { - pnp_enter_conf_state(dev); - pnp_set_resources(dev); - #if 0 dump_pnp_device(dev); #endif - pnp_exit_conf_state(dev); - } static void lpc47b397_pnp_enable_resources(device_t dev) { - pnp_enter_conf_state(dev); - pnp_enable_resources(dev); switch(dev->path.pnp.device) { @@ -103,20 +111,15 @@ enable_hwm_smbus(dev); break; } - #if 0 dump_pnp_device(dev); #endif - pnp_exit_conf_state(dev); - } static void lpc47b397_pnp_enable(device_t dev) { - pnp_enter_conf_state(dev); - pnp_set_logical_device(dev); if(dev->enabled) { @@ -125,9 +128,7 @@ else { pnp_set_enable(dev, 0); } - pnp_exit_conf_state(dev); - } static struct device_operations ops = { @@ -138,7 +139,6 @@ .init = lpc47b397_init, }; - #define HWM_INDEX 0 #define HWM_DATA 1 #define SB_INDEX 0x0b @@ -157,9 +157,9 @@ res = find_resource(get_pbus_smbus(dev)->dev, PNP_IDX_IO0); - pnp_write_index(res->base+HWM_INDEX, 0, device); // why 0? + pnp_write_index(res->base+HWM_INDEX, 0, device); /* why 0? */ - result = pnp_read_index(res->base+SB_INDEX, address); // we only read it one byte one time + result = pnp_read_index(res->base+SB_INDEX, address); /* we only read it one byte one time */ return result; } @@ -172,16 +172,16 @@ device = dev->path.i2c.device; res = find_resource(get_pbus_smbus(dev)->dev, PNP_IDX_IO0); - pnp_write_index(res->base+HWM_INDEX, 0, device); // why 0? + pnp_write_index(res->base+HWM_INDEX, 0, device); /* why 0? */ - pnp_write_index(res->base+SB_INDEX, address, val); // we only write it one byte one time + pnp_write_index(res->base+SB_INDEX, address, val); /* we only write it one byte one time */ return 0; } static struct smbus_bus_operations lops_smbus_bus = { -// .recv_byte = lsmbus_recv_byte, -// .send_byte = lsmbus_send_byte, + /* .recv_byte = lsmbus_recv_byte, */ + /* .send_byte = lsmbus_send_byte, */ .read_byte = lsmbus_read_byte, .write_byte = lsmbus_write_byte, }; @@ -215,4 +215,3 @@ CHIP_NAME("SMSC LPC47B397 Super I/O") .enable_dev = enable_dev, }; - Modified: trunk/src/superio/smsc/lpc47m10x/Config.lb =================================================================== --- trunk/src/superio/smsc/lpc47m10x/Config.lb 2009-12-23 22:16:18 UTC (rev 4992) +++ trunk/src/superio/smsc/lpc47m10x/Config.lb 2009-12-28 09:59:44 UTC (rev 4993) @@ -1,2 +1,26 @@ +## +## superio.c: RAM driver for SMSC LPC47M10X2 Super I/O chip +## +## Copyright 2000 AG Electronics Ltd. +## Copyright 2003-2004 Linux Networx +## Copyright 2004 Tyan +## Copyright (C) 2005 Digital Design Corporation +## Copyright (C) Ron Minnich, LANL +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + config chip.h object superio.o Modified: trunk/src/superio/smsc/lpc47m10x/Makefile.inc =================================================================== --- trunk/src/superio/smsc/lpc47m10x/Makefile.inc 2009-12-23 22:16:18 UTC (rev 4992) +++ trunk/src/superio/smsc/lpc47m10x/Makefile.inc 2009-12-28 09:59:44 UTC (rev 4993) @@ -1,2 +1,26 @@ +## +## superio.c: RAM driver for SMSC LPC47M10X2 Super I/O chip +## +## Copyright 2000 AG Electronics Ltd. +## Copyright 2003-2004 Linux Networx +## Copyright 2004 Tyan +## Copyright (C) 2005 Digital Design Corporation +## Copyright (C) Ron Minnich, LANL +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + #config chip.h obj-$(CONFIG_SUPERIO_SMSC_LPC47M10X) += superio.o Modified: trunk/src/superio/smsc/lpc47m10x/chip.h =================================================================== --- trunk/src/superio/smsc/lpc47m10x/chip.h 2009-12-23 22:16:18 UTC (rev 4992) +++ trunk/src/superio/smsc/lpc47m10x/chip.h 2009-12-28 09:59:44 UTC (rev 4993) @@ -1,3 +1,27 @@ +/* + * superio.c: RAM driver for SMSC LPC47M10X2 Super I/O chip + * + * Copyright 2000 AG Electronics Ltd. + * Copyright 2003-2004 Linux Networx + * Copyright 2004 Tyan + * Copyright (C) 2005 Digital Design Corporation + * Copyright (C) Ron Minnich, LANL + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + struct chip_operations; extern struct chip_operations superio_smsc_lpc47m10x_ops; Modified: trunk/src/superio/smsc/lpc47m10x/lpc47m10x.h =================================================================== --- trunk/src/superio/smsc/lpc47m10x/lpc47m10x.h 2009-12-23 22:16:18 UTC (rev 4992) +++ trunk/src/superio/smsc/lpc47m10x/lpc47m10x.h 2009-12-28 09:59:44 UTC (rev 4993) @@ -1,3 +1,27 @@ +/* + * superio.c: RAM driver for SMSC LPC47M10X2 Super I/O chip + * + * Copyright 2000 AG Electronics Ltd. + * Copyright 2003-2004 Linux Networx + * Copyright 2004 Tyan + * Copyright (C) 2005 Digital Design Corporation + * Copyright (C) Ron Minnich, LANL + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + #define LPC47M10X2_FDC 0 /* Floppy */ #define LPC47M10X2_PP 3 /* Parallel Port */ #define LPC47M10X2_SP1 4 /* Com1 */ Modified: trunk/src/superio/smsc/lpc47m10x/lpc47m10x_early_serial.c =================================================================== --- trunk/src/superio/smsc/lpc47m10x/lpc47m10x_early_serial.c 2009-12-23 22:16:18 UTC (rev 4992) +++ trunk/src/superio/smsc/lpc47m10x/lpc47m10x_early_serial.c 2009-12-28 09:59:44 UTC (rev 4993) @@ -22,37 +22,39 @@ #include <arch/romcc_io.h> #include "lpc47m10x.h" -//---------------------------------------------------------------------------------- -// Function: pnp_enter_conf_state -// Parameters: dev - high 8 bits = Super I/O port -// Return Value: None -// Description: Enable access to the LPC47M10X2's configuration registers. -// -static inline void pnp_enter_conf_state(device_t dev) { +/* + * Function: pnp_enter_conf_state + * Parameters: dev - high 8 bits = Super I/O port + * Return Value: None + * Description: Enable access to the LPC47M10X2's configuration registers. + */ +static inline void pnp_enter_conf_state(device_t dev) +{ unsigned port = dev>>8; - outb(0x55, port); + outb(0x55, port); } -//---------------------------------------------------------------------------------- -// Function: pnp_exit_conf_state -// Parameters: dev - high 8 bits = Super I/O port -// Return Value: None -// Description: Disable access to the LPC47M10X2's configuration registers. -// -static void pnp_exit_conf_state(device_t dev) { +/* + * Function: pnp_exit_conf_state + * Parameters: dev - high 8 bits = Super I/O port + * Return Value: None + * Description: Disable access to the LPC47M10X2's configuration registers. + */ +static void pnp_exit_conf_state(device_t dev) +{ unsigned port = dev>>8; - outb(0xaa, port); + outb(0xaa, port); } -//---------------------------------------------------------------------------------- -// Function: lpc47b272_enable_serial -// Parameters: dev - high 8 bits = Super I/O port, -// low 8 bits = logical device number (per lpc47b272.h) -// iobase - processor I/O port address to assign to this serial device -// Return Value: bool -// Description: Configure the base I/O port of the specified serial device -// and enable the serial device. -// +/* + * Function: lpc47b272_enable_serial + * Parameters: dev - high 8 bits = Super I/O port, + * low 8 bits = logical device number (per lpc47b272.h) + * iobase - processor I/O port address to assign to this serial device + * Return Value: bool + * Description: Configure the base I/O port of the specified serial device + * and enable the serial device. + */ static void lpc47b272_enable_serial(device_t dev, unsigned iobase) { pnp_enter_conf_state(dev); Modified: trunk/src/superio/smsc/lpc47m10x/superio.c =================================================================== --- trunk/src/superio/smsc/lpc47m10x/superio.c 2009-12-23 22:16:18 UTC (rev 4992) +++ trunk/src/superio/smsc/lpc47m10x/superio.c 2009-12-28 09:59:44 UTC (rev 4993) @@ -3,7 +3,7 @@ * * Copyright 2000 AG Electronics Ltd. * Copyright 2003-2004 Linux Networx - * Copyright 2004 Tyan + * Copyright 2004 Tyan * Copyright (C) 2005 Digital Design Corporation * Copyright (C) Ron Minnich, LANL * @@ -35,7 +35,7 @@ #include "chip.h" #include "lpc47m10x.h" -// Forward declarations +/* Forward declarations */ static void enable_dev(device_t dev); static void lpc47m10x_pnp_set_resources(device_t dev); static void lpc47m10x_pnp_enable_resources(device_t dev); @@ -46,7 +46,6 @@ static void pnp_exit_conf_state(device_t dev); static void dump_pnp_device(device_t dev); - struct chip_operations superio_smsc_lpc47m10x_ops = { CHIP_NAME("SMSC LPC47M10x Super I/O") .enable_dev = enable_dev @@ -61,55 +60,55 @@ }; static struct pnp_info pnp_dev_info[] = { - { &ops, LPC47M10X2_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07f8, 0}, }, - { &ops, LPC47M10X2_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07f8, 0}, }, - { &ops, LPC47M10X2_SP1, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, }, - { &ops, LPC47M10X2_SP2, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, }, - { &ops, LPC47M10X2_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1, { 0x7ff, 0 }, { 0x7ff, 0x4}, }, + { &ops, LPC47M10X2_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07f8, 0}, }, + { &ops, LPC47M10X2_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07f8, 0}, }, + { &ops, LPC47M10X2_SP1, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, }, + { &ops, LPC47M10X2_SP2, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, }, + { &ops, LPC47M10X2_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1, { 0x7ff, 0 }, { 0x7ff, 0x4}, }, }; /**********************************************************************************/ -/* PUBLIC INTERFACE */ +/* PUBLIC INTERFACE */ /**********************************************************************************/ -//---------------------------------------------------------------------------------- -// Function: enable_dev -// Parameters: dev - pointer to structure describing a Super I/O device -// Return Value: None -// Description: Create device structures and allocate resources to devices -// specified in the pnp_dev_info array (above). -// +/* + * Function: enable_dev + * Parameters: dev - pointer to structure describing a Super I/O device + * Return Value: None + * Description: Create device structures and allocate resources to devices + * specified in the pnp_dev_info array (above). + */ static void enable_dev(device_t dev) { - pnp_enable_devices(dev, &pnp_ops, - ARRAY_SIZE(pnp_dev_info), - pnp_dev_info); + pnp_enable_devices(dev, &pnp_ops, + ARRAY_SIZE(pnp_dev_info), + pnp_dev_info); } -//---------------------------------------------------------------------------------- -// Function: lpc47m10x_pnp_set_resources -// Parameters: dev - pointer to structure describing a Super I/O device -// Return Value: None -// Description: Configure the specified Super I/O device with the resources -// (I/O space, etc.) that have been allocated for it. -// +/* + * Function: lpc47m10x_pnp_set_resources + * Parameters: dev - pointer to structure describing a Super I/O device + * Return Value: None + * Description: Configure the specified Super I/O device with the resources + * (I/O space, etc.) that have been allocated for it. + */ static void lpc47m10x_pnp_set_resources(device_t dev) { - pnp_enter_conf_state(dev); + pnp_enter_conf_state(dev); pnp_set_resources(dev); - pnp_exit_conf_state(dev); -} + pnp_exit_conf_state(dev); +} static void lpc47m10x_pnp_enable_resources(device_t dev) -{ +{ pnp_enter_conf_state(dev); - pnp_enable_resources(dev); - pnp_exit_conf_state(dev); + pnp_enable_resources(dev); + pnp_exit_conf_state(dev); } static void lpc47m10x_pnp_enable(device_t dev) { - pnp_enter_conf_state(dev); + pnp_enter_conf_state(dev); pnp_set_logical_device(dev); if(dev->enabled) { @@ -118,17 +117,17 @@ else { pnp_set_enable(dev, 0); } - pnp_exit_conf_state(dev); + pnp_exit_conf_state(dev); } -//---------------------------------------------------------------------------------- -// Function: lpc47m10x_init -// Parameters: dev - pointer to structure describing a Super I/O device -// Return Value: None -// Description: Initialize the specified Super I/O device. -// Devices other than COM ports and the keyboard controller are -// ignored. For COM ports, we configure the baud rate. -// +/* + * Function: lpc47m10x_init + * Parameters: dev - pointer to structure describing a Super I/O device + * Return Value: None + * Description: Initialize the specified Super I/O device. + * Devices other than COM ports and the keyboard controller are + * ignored. For COM ports, we configure the baud rate. + */ static void lpc47m10x_init(device_t dev) { struct superio_smsc_lpc47m10x_config *conf = dev->chip_info; @@ -136,18 +135,18 @@ if (!dev->enabled) return; - + switch(dev->path.pnp.device) { - case LPC47M10X2_SP1: + case LPC47M10X2_SP1: res0 = find_resource(dev, PNP_IDX_IO0); init_uart8250(res0->base, &conf->com1); break; - + case LPC47M10X2_SP2: res0 = find_resource(dev, PNP_IDX_IO0); init_uart8250(res0->base, &conf->com2); break; - + case LPC47M10X2_KBC: res0 = find_resource(dev, PNP_IDX_IO0); res1 = find_resource(dev, PNP_IDX_IO1); @@ -157,65 +156,65 @@ } /**********************************************************************************/ -/* PRIVATE FUNCTIONS */ +/* PRIVATE FUNCTIONS */ /**********************************************************************************/ -//---------------------------------------------------------------------------------- -// Function: pnp_enter_conf_state -// Parameters: dev - pointer to structure describing a Super I/O device -// Return Value: None -// Description: Enable access to the LPC47M10X2's configuration registers. -// -static void pnp_enter_conf_state(device_t dev) +/* + * Function: pnp_enter_conf_state + * Parameters: dev - pointer to structure describing a Super I/O device + * Return Value: None + * Description: Enable access to the LPC47M10X2's configuration registers. + */ +static void pnp_enter_conf_state(device_t dev) { outb(0x55, dev->path.pnp.port); } -//---------------------------------------------------------------------------------- -// Function: pnp_exit_conf_state -// Parameters: dev - pointer to structure describing a Super I/O device -// Return Value: None -// Description: Disable access to the LPC47M10X2's configuration registers. -// -static void pnp_exit_conf_state(device_t dev) +/* + * Function: pnp_exit_conf_state + * Parameters: dev - pointer to structure describing a Super I/O device + * Return Value: None + * Description: Disable access to the LPC47M10X2's configuration registers. + */ +static void pnp_exit_conf_state(device_t dev) { - outb(0xaa, dev->path.pnp.port); + outb(0xaa, dev->path.pnp.port); } #if 0 -//---------------------------------------------------------------------------------- -// Function: dump_pnp_device -// Parameters: dev - pointer to structure describing a Super I/O device -// Return Value: None -// Description: Print the values of all of the LPC47M10X2's configuration registers. -// NOTE: The LPC47M10X2 must be in configuration mode when this -// function is called. -// +/* + * Function: dump_pnp_device + * Parameters: dev - pointer to structure describing a Super I/O device + * Return Value: None + * Description: Print the values of all of the LPC47M10X2's configuration registers. + * NOTE: The LPC47M10X2 must be in configuration mode when this + * function is called. + */ static void dump_pnp_device(device_t dev) { - int register_index; - print_debug("\r\n"); + int register_index; + print_debug("\r\n"); - for(register_index = 0; register_index <= LPC47M10X2_MAX_CONFIG_REGISTER; register_index++) { - uint8_t register_value; + for(register_index = 0; register_index <= LPC47M10X2_MAX_CONFIG_REGISTER; register_index++) { + uint8_t register_value; - if ((register_index & 0x0f) == 0) { - print_debug_hex8(register_index); - print_debug_char(':'); - } + if ((register_index & 0x0f) == 0) { + print_debug_hex8(register_index); + print_debug_char(':'); + } - // Skip over 'register' that would cause exit from configuration mode - if (register_index == 0xaa) + /* Skip over 'register' that would cause exit from configuration mode */ + if (register_index == 0xaa) register_value = 0xaa; else - register_value = pnp_read_config(dev, register_index); + register_value = pnp_read_config(dev, register_index); - print_debug_char(' '); - print_debug_hex8(register_value); - if ((register_index & 0x0f) == 0x0f) { - print_debug("\r\n"); - } - } + print_debug_char(' '); + print_debug_hex8(register_value); + if ((register_index & 0x0f) == 0x0f) { + print_debug("\r\n"); + } + } print_debug("\r\n"); } Modified: trunk/src/superio/smsc/lpc47m15x/Makefile.inc =================================================================== --- trunk/src/superio/smsc/lpc47m15x/Makefile.inc 2009-12-23 22:16:18 UTC (rev 4992) +++ trunk/src/superio/smsc/lpc47m15x/Makefile.inc 2009-12-28 09:59:44 UTC (rev 4993) @@ -1,2 +1,21 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2009 coresystems GmbH +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + #config chip.h obj-$(CONFIG_SUPERIO_SMSC_LPC47M15X) += superio.o Modified: trunk/src/superio/smsc/lpc47m15x/lpc47m15x_early_serial.c =================================================================== --- trunk/src/superio/smsc/lpc47m15x/lpc47m15x_early_serial.c 2009-12-23 22:16:18 UTC (rev 4992) +++ trunk/src/superio/smsc/lpc47m15x/lpc47m15x_early_serial.c 2009-12-28 09:59:44 UTC (rev 4993) @@ -28,7 +28,8 @@ outb(0x55, port); } -static void pnp_exit_conf_state(device_t dev) { +static void pnp_exit_conf_state(device_t dev) +{ unsigned port = dev>>8; outb(0xaa, port); } Modified: trunk/src/superio/smsc/lpc47m15x/superio.c =================================================================== --- trunk/src/superio/smsc/lpc47m15x/superio.c 2009-12-23 22:16:18 UTC (rev 4992) +++ trunk/src/superio/smsc/lpc47m15x/superio.c 2009-12-28 09:59:44 UTC (rev 4993) @@ -32,7 +32,7 @@ #include "chip.h" #include "lpc47m15x.h" -// Forward declarations +/* Forward declarations */ static void enable_dev(device_t dev); static void lpc47m15x_pnp_set_resources(device_t dev); static void lpc47m15x_pnp_enable_resources(device_t dev); @@ -43,7 +43,6 @@ static void pnp_exit_conf_state(device_t dev); static void dump_pnp_device(device_t dev); - struct chip_operations superio_smsc_lpc47m15x_ops = { CHIP_NAME("SMSC LPC47M15x/192/997 Super I/O") .enable_dev = enable_dev @@ -58,11 +57,11 @@ }; static struct pnp_info pnp_dev_info[] = { - { &ops, LPC47M15X_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07f8, 0}, }, - { &ops, LPC47M15X_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07f8, 0}, }, - { &ops, LPC47M15X_SP1, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, }, - { &ops, LPC47M15X_SP2, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, }, - { &ops, LPC47M15X_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1, { 0x7ff, 0 }, { 0x7ff, 0x4}, }, + { &ops, LPC47M15X_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07f8, 0}, }, + { &ops, LPC47M15X_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07f8, 0}, }, + { &ops, LPC47M15X_SP1, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, }, + { &ops, LPC47M15X_SP2, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, }, + { &ops, LPC47M15X_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1, { 0x7ff, 0 }, { 0x7ff, 0x4}, }, }; static void enable_dev(device_t dev) @@ -72,13 +71,13 @@ static void lpc47m15x_pnp_set_resources(device_t dev) { - pnp_enter_conf_state(dev); + pnp_enter_conf_state(dev); pnp_set_resources(dev); - pnp_exit_conf_state(dev); -} + pnp_exit_conf_state(dev); +} static void lpc47m15x_pnp_enable_resources(device_t dev) -{ +{ pnp_enter_conf_state(dev); pnp_enable_resources(dev); pnp_exit_conf_state(dev); @@ -86,7 +85,7 @@ static void lpc47m15x_pnp_enable(device_t dev) { - pnp_enter_conf_state(dev); + pnp_enter_conf_state(dev); pnp_set_logical_device(dev); if(dev->enabled) { @@ -95,7 +94,7 @@ else { pnp_set_enable(dev, 0); } - pnp_exit_conf_state(dev); + pnp_exit_conf_state(dev); } static void lpc47m15x_init(device_t dev) @@ -105,18 +104,18 @@ if (!dev->enabled) return; - + switch(dev->path.pnp.device) { - case LPC47M15X_SP1: + case LPC47M15X_SP1: res0 = find_resource(dev, PNP_IDX_IO0); init_uart8250(res0->base, &conf->com1); break; - + case LPC47M15X_SP2: res0 = find_resource(dev, PNP_IDX_IO0); init_uart8250(res0->base, &conf->com2); break; - + case LPC47M15X_KBC: res0 = find_resource(dev, PNP_IDX_IO0); res1 = find_resource(dev, PNP_IDX_IO1); @@ -125,13 +124,12 @@ } } -static void pnp_enter_conf_state(device_t dev) +static void pnp_enter_conf_state(device_t dev) { outb(0x55, dev->path.pnp.port); } -static void pnp_exit_conf_state(device_t dev) +static void pnp_exit_conf_state(device_t dev) { - outb(0xaa, dev->path.pnp.port); + outb(0xaa, dev->path.pnp.port); } - Modified: trunk/src/superio/smsc/lpc47n217/Config.lb =================================================================== --- trunk/src/superio/smsc/lpc47n217/Config.lb 2009-12-23 22:16:18 UTC (rev 4992) +++ trunk/src/superio/smsc/lpc47n217/Config.lb 2009-12-28 09:59:44 UTC (rev 4993) @@ -1,22 +1,22 @@ -## +## ## This file is part of the coreboot project. -## +## ## Copyright (C) 2005 Digital Design Corporation -## +## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by ## the Free Software Foundation; either version 2 of the License, or ## (at your option) any later version. -## +## ## This program is distributed in the hope that it will be useful, ## but WITHOUT ANY WARRANTY; without even the implied warranty of ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ## GNU General Public License for more details. -## +## ## You should have received a copy of the GNU General Public License ## along with this program; if not, write to the Free Software ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -## +## config chip.h object superio.o Modified: trunk/src/superio/smsc/lpc47n217/Makefile.inc =================================================================== --- trunk/src/superio/smsc/lpc47n217/Makefile.inc 2009-12-23 22:16:18 UTC (rev 4992) +++ trunk/src/superio/smsc/lpc47n217/Makefile.inc 2009-12-28 09:59:44 UTC (rev 4993) @@ -1,22 +1,22 @@ -## +## ## This file is part of the coreboot project. -## +## ## Copyright (C) 2005 Digital Design Corporation -## +## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by ## the Free Software Foundation; either version 2 of the License, or ## (at your option) any later version. -## +## ## This program is distributed in the hope that it will be useful, ## but WITHOUT ANY WARRANTY; without even the implied warranty of ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ## GNU General Public License for more details. -## +## ## You should have received a copy of the GNU General Public License ## along with this program; if not, write to the Free Software ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -## +## #config chip.h obj-$(CONFIG_SUPERIO_SMSC_LPC47N217) += superio.o Modified: trunk/src/superio/smsc/lpc47n217/lpc47n217.h =================================================================== --- trunk/src/superio/smsc/lpc47n217/lpc47n217.h 2009-12-23 22:16:18 UTC (rev 4992) +++ trunk/src/superio/smsc/lpc47n217/lpc47n217.h 2009-12-28 09:59:44 UTC (rev 4993) @@ -18,8 +18,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -// These are arbitrary, but must match declarations in the mainboard config file. -// Values chosen to match SMSC 47B37x. +/* These are arbitrary, but must match declarations in the mainboard config file. + * Values chosen to match SMSC 47B37x. + */ #define LPC47N217_PP 3 /* Parallel Port */ #define LPC47N217_SP1 4 /* Com1 */ Modified: trunk/src/superio/smsc/lpc47n217/lpc47n217_early_serial.c =================================================================== --- trunk/src/superio/smsc/lpc47n217/lpc47n217_early_serial.c 2009-12-23 22:16:18 UTC (rev 4992) +++ trunk/src/superio/smsc/lpc47n217/lpc47n217_early_serial.c 2009-12-28 09:59:44 UTC (rev 4993) @@ -24,123 +24,126 @@ #include <assert.h> #include "lpc47n217.h" -//---------------------------------------------------------------------------------- -// Function: pnp_enter_conf_state -// Parameters: dev - high 8 bits = Super I/O port -// Return Value: None -// Description: Enable access to the LPC47N217's configuration registers. -// -static inline void pnp_enter_conf_state(device_t dev) { +/* + * Function: pnp_enter_conf_state + * Parameters: dev - high 8 bits = Super I/O port + * Return Value: None + * Description: Enable access to the LPC47N217's configuration registers. + */ +static inline void pnp_enter_conf_state(device_t dev) +{ unsigned port = dev>>8; - outb(0x55, port); + outb(0x55, port); } -//---------------------------------------------------------------------------------- -// Function: pnp_exit_conf_state -// Parameters: dev - high 8 bits = Super I/O port -// Return Value: None -// Description: Disable access to the LPC47N217's configuration registers. -// -static void pnp_exit_conf_state(device_t dev) { +/* + * Function: pnp_exit_conf_state + * Parameters: dev - high 8 bits = Super I/O port + * Return Value: None + * Description: Disable access to the LPC47N217's configuration registers. + */ +static void pnp_exit_conf_state(device_t dev) +{ unsigned port = dev>>8; - outb(0xaa, port); + outb(0xaa, port); } -//---------------------------------------------------------------------------------- -// Function: lpc47n217_pnp_set_iobase -// Parameters: dev - high 8 bits = Super I/O port, -// low 8 bits = logical device number (per lpc47n217.h) -// iobase - base I/O port for the logical device -// Return Value: None -// Description: Program the base I/O port for the specified logical device. -// +/* + * Function: lpc47n217_pnp_set_iobase + * Parameters: dev - high 8 bits = Super I/O port, + * low 8 bits = logical device number (per lpc47n217.h) + * iobase - base I/O port for the logical device + * Return Value:None + * Description: Program the base I/O port for the specified logical device. + * + */ void lpc47n217_pnp_set_iobase(device_t dev, unsigned iobase) { - // LPC47N217 requires base ports to be a multiple of 4 + /* LPC47N217 requires base ports to be a multiple of 4 */ ASSERT(!(iobase & 0x3)); switch(dev & 0xFF) { - case LPC47N217_PP: + case LPC47N217_PP: pnp_write_config(dev, 0x23, (iobase >> 2) & 0xff); break; - - case LPC47N217_SP1: + + case LPC47N217_SP1: pnp_write_config(dev, 0x24, (iobase >> 2) & 0xff); break; - + case LPC47N217_SP2: pnp_write_config(dev, 0x25, (iobase >> 2) & 0xff); break; - + default: break; } } -//---------------------------------------------------------------------------------- -// Function: lpc47n217_pnp_set_enable -// Parameters: dev - high 8 bits = Super I/O port, -// low 8 bits = logical device number (per lpc47n217.h) -// enable - 0 to disable, anythig else to enable -// Return Value: None -// Description: Enable or disable the specified logical device. -// Technically, a full disable requires setting the device's base -// I/O port below 0x100. We don't do that here, because we don't -// have access to a data structure that specifies what the 'real' -// base port is (when asked to enable the device). Also the function -// is used only to disable the device while its true base port is -// programmed (see lpc47n217_enable_serial() below). -// +/* + * Function: lpc47n217_pnp_set_enable + * Parameters: dev - high 8 bits = Super I/O port, + * low 8 bits = logical device number (per lpc47n217.h) + * enable - 0 to disable, anythig else to enable + * Return Value:None + * Description: Enable or disable the specified logical device. + * Technically, a full disable requires setting the device's base + * I/O port below 0x100. We don't do that here, because we don't + * have access to a data structure that specifies what the 'real' + * base port is (when asked to enable the device). Also the function + * is used only to disable the device while its true base port is + * programmed (see lpc47n217_enable_serial() below). + */ void lpc47n217_pnp_set_enable(device_t dev, int enable) { uint8_t power_register = 0; uint8_t power_mask = 0; uint8_t current_power; uint8_t new_power; - + switch(dev & 0xFF) { - case LPC47N217_PP: + case LPC47N217_PP: power_register = 0x01; power_mask = 0x04; break; - - case LPC47N217_SP1: + + case LPC47N217_SP1: power_register = 0x02; power_mask = 0x08; break; - + case LPC47N217_SP2: power_register = 0x02; power_mask = 0x80; break; - + default: return; } current_power = pnp_read_config(dev, power_register); - new_power = current_power & ~power_mask; // disable by default + new_power = current_power & ~power_mask; /* disable by default */ if (enable) - new_power |= power_mask; // Enable + new_power |= power_mask; /* Enable */ pnp_write_config(dev, power_register, new_power); } -//---------------------------------------------------------------------------------- -// Function: lpc47n217_enable_serial -// Parameters: dev - high 8 bits = Super I/O port, -// low 8 bits = logical device number (per lpc47n217.h) -// iobase - processor I/O port address to assign to this serial device -// Return Value: bool -// Description: Configure the base I/O port of the specified serial device -// and enable the serial device. -// +/* + * Function: lpc47n217_enable_serial + * Parameters: dev - high 8 bits = Super I/O port, + * low 8 bits = logical device number (per lpc47n217.h) + * iobase - processor I/O port address to assign to this serial device + * Return Value:bool + * Description: Configure the base I/O port of the specified serial device + * and enable the serial device. + */ static void lpc47n217_enable_serial(device_t dev, unsigned iobase) { - // NOTE: Cannot use pnp_set_XXX() here because they assume chip - // support for logical devices, which the LPC47N217 doesn't have - + /* NOTE: Cannot use pnp_set_XXX() here because they assume chip + * support for logical devices, which the LPC47N217 doesn't have*/ + pnp_enter_conf_state(dev); lpc47n217_pnp_set_enable(dev, 0); lpc47n217_pnp_set_iobase(dev, iobase); Modified: trunk/src/superio/smsc/lpc47n217/superio.c =================================================================== --- trunk/src/superio/smsc/lpc47n217/superio.c 2009-12-23 22:16:18 UTC (rev 4992) +++ trunk/src/superio/smsc/lpc47n217/superio.c 2009-12-28 09:59:44 UTC (rev 4993) @@ -3,7 +3,7 @@ * * Copyright (C) 2000 AG Electronics Ltd. * Copyright (C) 2003-2004 Linux Networx - * Copyright (C) 2004 Tyan + * Copyright (C) 2004 Tyan * Copyright (C) 2005 Digital Design Corporation * * This program is free software; you can redistribute it and/or modify @@ -37,7 +37,7 @@ #include "chip.h" #include "lpc47n217.h" -// Forward declarations +/* Forward declarations */ static void enable_dev(device_t dev); static void lpc47n217_pnp_set_resources(device_t dev); static void lpc47n217_pnp_enable_resources(device_t dev); @@ -53,7 +53,6 @@ static void pnp_enter_conf_state(device_t dev); static void pnp_exit_conf_state(device_t dev); - struct chip_operations superio_smsc_lpc47n217_ops = { CHIP_NAME("SMSC LPC47N217 Super I/O") .enable_dev = enable_dev, @@ -68,69 +67,72 @@ }; static struct pnp_info pnp_dev_info[] = { - { &ops, LPC47N217_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07f8, 0}, }, - { &ops, LPC47N217_SP1, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, }, - { &ops, LPC47N217_SP2, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, } + { &ops, LPC47N217_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07f8, 0}, }, + { &ops, LPC47N217_SP1, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, }, + { &ops, LPC47N217_SP2, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, } }; /**********************************************************************************/ -/* PUBLIC INTERFACE */ +/* PUBLIC INTERFACE */ /**********************************************************************************/ -//---------------------------------------------------------------------------------- -// Function: enable_dev -// Parameters: dev - pointer to structure describing a Super I/O device -// Return Value: None -// Description: Create device structures and allocate resources to devices -// specified in the pnp_dev_info array (above). -// +/* + * Function: enable_dev + * Parameters: dev - pointer to structure describing a Super I/O device + * Return Value: None + * Description: Create device structures and allocate resources to devices + * specified in the pnp_dev_info array (above). + */ static void enable_dev(device_t dev) { - pnp_enable_devices(dev, &pnp_ops, - ARRAY_SIZE(pnp_dev_info), - pnp_dev_info); + pnp_enable_devices(dev, &pnp_ops, + ARRAY_SIZE(pnp_dev_info), + pnp_dev_info); } -//---------------------------------------------------------------------------------- -// Function: lpc47n217_pnp_set_resources -// Parameters: dev - pointer to structure describing a Super I/O device -// Return Value: None -// Description: Configure the specified Super I/O device with the resources -// (I/O space, etc.) that have been allocate for it. -// +/* + * Function: lpc47n217_pnp_set_resources + * Parameters: dev - pointer to structure describing a Super I/O device + * Return Value: None + * Description: Configure the specified Super I/O device with the resources + * (I/O space, etc.) that have been allocate for it. + */ static void lpc47n217_pnp_set_resources(device_t dev) { int i; - - pnp_enter_conf_state(dev); - // NOTE: Cannot use pnp_set_resources() here because it assumes chip - // support for logical devices, which the LPC47N217 doesn't have + pnp_enter_conf_state(dev); + + /* NOTE: Cannot use pnp_set_resources() here because it assumes chip + * support for logical devices, which the LPC47N217 doesn't have + */ for(i = 0; i < dev->resources; i++) lpc47n217_pnp_set_resource(dev, &dev->resource[i]); -// dump_pnp_device(dev); - - pnp_exit_conf_state(dev); -} + /* dump_pnp_device(dev); */ + pnp_exit_conf_state(dev); +} + static void lpc47n217_pnp_enable_resources(device_t dev) -{ - pnp_enter_conf_state(dev); +{ + pnp_enter_conf_state(dev); - // NOTE: Cannot use pnp_enable_resources() here because it assumes chip - // support for logical devices, which the LPC47N217 doesn't have - lpc47n217_pnp_set_enable(dev, 1); + /* NOTE: Cannot use pnp_enable_resources() here because it assumes chip + * support for logical devices, which the LPC47N217 doesn't have + */ + lpc47n217_pnp_set_enable(dev, 1); - pnp_exit_conf_state(dev); + pnp_exit_conf_state(dev); } static void lpc47n217_pnp_enable(device_t dev) { - pnp_enter_conf_state(dev); + pnp_enter_conf_state(dev); - // NOTE: Cannot use pnp_set_enable() here because it assumes chip - // support for logical devices, which the LPC47N217 doesn't have + /* NOTE: Cannot use pnp_set_enable() here because it assumes chip + * support for logical devices, which the LPC47N217 doesn't have + */ if(dev->enabled) { lpc47n217_pnp_set_enable(dev, 1); @@ -139,17 +141,17 @@ lpc47n217_pnp_set_enable(dev, 0); } - pnp_exit_conf_state(dev); + pnp_exit_conf_state(dev); } -//---------------------------------------------------------------------------------- -// Function: lpc47n217_init -// Parameters: dev - pointer to structure describing a Super I/O device -// Return Value: None -// Description: Initialize the specified Super I/O device. -// Devices other than COM ports are ignored. -// For COM ports, we configure the baud rate. -// +/* + * Function: lpc47n217_init + * Parameters: dev - pointer to structure describing a Super I/O device + * Return Value: None + * Description: Initialize the specified Super I/O device. + * Devices other than COM ports are ignored. + * For COM ports, we configure the baud rate. + */ static void lpc47n217_init(device_t dev) { struct superio_smsc_lpc47n217_config* conf = dev->chip_info; @@ -159,7 +161,7 @@ return; switch(dev->path.pnp.device) { - case LPC47N217_SP1: + case LPC47N217_SP1: res0 = find_resource(dev, PNP_IDX_IO0); init_uart8250(res0->base, &conf->com1); break; @@ -171,9 +173,8 @@ } } - /**********************************************************************************/ -/* PRIVATE FUNCTIONS */ +/* PRIVATE FUNCTIONS */ /**********************************************************************************/ static void lpc47n217_pnp_set_resource(device_t dev, struct resource *resource) @@ -185,8 +186,9 @@ } /* Now store the resource */ - // NOTE: Cannot use pnp_set_XXX() here because they assume chip - // support for logical devices, which the LPC47N217 doesn't have + /* NOTE: Cannot use pnp_set_XXX() here because they assume chip + * support for logical devices, which the LPC47N217 doesn't have + */ if (resource->flags & IORESOURCE_IO) { lpc47n217_pnp_set_iobase(dev, resource->base); @@ -210,20 +212,20 @@ static void lpc47n217_pnp_set_iobase(device_t dev, unsigned iobase) { ASSERT(!(iobase & 0x3)); - + switch(dev->path.pnp.device) { - case LPC47N217_PP: + case LPC47N217_PP: pnp_write_config(dev, 0x23, (iobase >> 2) & 0xff); break; - - case LPC47N217_SP1: + + case LPC47N217_SP1: pnp_write_config(dev, 0x24, (iobase >> 2) & 0xff); break; - + case LPC47N217_SP2: pnp_write_config(dev, 0x25, (iobase >> 2) & 0xff); break; - + default: BUG(); break; @@ -238,7 +240,7 @@ uint8_t current_config = pnp_read_config(dev, PP_DMA_SELECTION_REGISTER); uint8_t new_config; - ASSERT(!(drq & ~PP_DMA_MASK)); // DRQ out of range?? + ASSERT(!(drq & ~PP_DMA_MASK)); /* DRQ out of range?? */ new_config = (current_config & ~PP_DMA_MASK) | drq; pnp_write_config(dev, PP_DMA_SELECTION_REGISTER, new_config); } else { @@ -252,31 +254,31 @@ uint8_t irq_config_mask = 0; uint8_t current_config; uint8_t new_config; - + switch(dev->path.pnp.device) { - case LPC47N217_PP: + case LPC47N217_PP: irq_config_register = 0x27; irq_config_mask = 0x0F; break; - - case LPC47N217_SP1: + + case LPC47N217_SP1: irq_config_register = 0x28; irq_config_mask = 0xF0; irq <<= 4; break; - + case LPC47N217_SP2: irq_config_register = 0x28; irq_config_mask = 0x0F; break; - + default: BUG(); return; } - ASSERT(!(irq & ~irq_config_mask)); // IRQ out of range?? - + ASSERT(!(irq & ~irq_config_mask)); /* IRQ out of range?? */ + current_config = pnp_read_config(dev, irq_config_register); new_config = (current_config & ~irq_config_mask) | irq; pnp_write_config(dev, irq_config_register, new_config); @@ -288,100 +290,99 @@ uint8_t power_mask = 0; uint8_t current_power; uint8_t new_power; - + switch(dev->path.pnp.device) { - case LPC47N217_PP: + case LPC47N217_PP: power_register = 0x01; power_mask = 0x04; break; - - case LPC47N217_SP1: + + case LPC47N217_SP1: power_register = 0x02; power_mask = 0x08; break; - + case LPC47N217_SP2: power_register = 0x02; power_mask = 0x80; break; - + default: BUG(); return; } current_power = pnp_read_config(dev, power_register); - new_power = current_power & ~power_mask; // disable by default + new_power = current_power & ~power_mask; /* disable by default */ if (enable) { struct resource* ioport_resource = find_resource(dev, PNP_IDX_IO0); lpc47n217_pnp_set_iobase(dev, ioport_resource->base); - - new_power |= power_mask; // Enable - - } else { + + new_power |= power_mask; /* Enable */ + + } else { lpc47n217_pnp_set_iobase(dev, 0); } pnp_write_config(dev, power_register, new_power); } - -//---------------------------------------------------------------------------------- -// Function: pnp_enter_conf_state -// Parameters: dev - pointer to structure describing a Super I/O device -// Return Value: None -// Description: Enable access to the LPC47N217's configuration registers. -// -static void pnp_enter_conf_state(device_t dev) +/* + * Function: pnp_enter_conf_state + * Parameters: dev - pointer to structure describing a Super I/O device + * Return Value: None + * Description: Enable access to the LPC47N217's configuration registers. + */ +static void pnp_enter_conf_state(device_t dev) { outb(0x55, dev->path.pnp.port); } -//---------------------------------------------------------------------------------- -// Function: pnp_exit_conf_state -// Parameters: dev - pointer to structure describing a Super I/O device -// Return Value: None -// Description: Disable access to the LPC47N217's configuration registers. -// -static void pnp_exit_conf_state(device_t dev) +/* + * Function: pnp_exit_conf_state + * Parameters: dev - pointer to structure describing a Super I/O device + * Return Value: None + * Description: Disable access to the LPC47N217's configuration registers. + */ +static void pnp_exit_conf_state(device_t dev) { - outb(0xaa, dev->path.pnp.port); + outb(0xaa, dev->path.pnp.port); } #if 0 -//---------------------------------------------------------------------------------- -// Function: dump_pnp_device -// Parameters: dev - pointer to structure describing a Super I/O device -// Return Value: None -// Description: Print the values of all of the LPC47N217's configuration registers. -// NOTE: The LPC47N217 must be in configuration mode when this -// function is called. -// +/* + * Function: dump_pnp_device + * Parameters: dev - pointer to structure describing a Super I/O device + * Return Value: None + * Description: Print the values of all of the LPC47N217's configuration registers. + * NOTE: The LPC47N217 must be in configuration mode when this + * function is called. + */ static void dump_pnp_device(device_t dev) { - int register_index; - print_debug("\r\n"); + int register_index; + print_debug("\r\n"); - for(register_index = 0; register_index <= LPC47N217_MAX_CONFIG_REGISTER; register_index++) { - uint8_t register_value; + for(register_index = 0; register_index <= LPC47N217_MAX_CONFIG_REGISTER; register_index++) { + uint8_t register_value; - if ((register_index & 0x0f) == 0) { - print_debug_hex8(register_index); - print_debug_char(':'); - } + if ((register_index & 0x0f) == 0) { + print_debug_hex8(register_index); + print_debug_char(':'); + } - // Skip over 'register' that would cause exit from configuration mode - if (register_index == 0xaa) + /* Skip over 'register' that would cause exit from configuration mode */ + if (register_index == 0xaa) register_value = 0xaa; else - register_value = pnp_read_config(dev, register_index); + register_value = pnp_read_config(dev, register_index); - print_debug_char(' '); - print_debug_hex8(register_value); - if ((register_index & 0x0f) == 0x0f) { - print_debug("\r\n"); - } - } + print_debug_char(' '); + print_debug_hex8(register_value); + if ((register_index & 0x0f) == 0x0f) { + print_debug("\r\n"); + } + } print_debug("\r\n"); } Modified: trunk/src/superio/smsc/smscsuperio/Config.lb =================================================================== --- trunk/src/superio/smsc/smscsuperio/Config.lb 2009-12-23 22:16:18 UTC (rev 4992) +++ trunk/src/superio/smsc/smscsuperio/Config.lb 2009-12-28 09:59:44 UTC (rev 4993) @@ -20,4 +20,3 @@ config chip.h object superio.o - Modified: trunk/src/superio/smsc/smscsuperio/Makefile.inc =================================================================== --- trunk/src/superio/smsc/smscsuperio/Makefile.inc 2009-12-23 22:16:18 UTC (rev 4992) +++ trunk/src/superio/smsc/smscsuperio/Makefile.inc 2009-12-28 09:59:44 UTC (rev 4993) @@ -20,4 +20,3 @@ #config chip.h obj-$(CONFIG_SUPERIO_SMSC_SMSCSUPERIO) += superio.o - Modified: trunk/src/superio/smsc/smscsuperio/superio.c =================================================================== --- trunk/src/superio/smsc/smscsuperio/superio.c 2009-12-23 22:16:18 UTC (rev 4992) +++ trunk/src/superio/smsc/smscsuperio/superio.c 2009-12-28 09:59:44 UTC (rev 4993) @@ -120,7 +120,7 @@ uint8_t superio_id; int devs[MAX_LOGICAL_DEVICES]; } logical_device_table[] = { - // Chip FDC PP SP1 SP2 RTC KBC AUX XBUS HWM GAME PME MPU RT ACPI SMB + /* Chip FDC PP SP1 SP2 RTC KBC AUX XBUS HWM GAME PME MPU RT ACPI SMB */ {LPC47M172,{0, 3, 4, 2, -1, 7, -1, -1, -1, -1, -1, -1, 10, -1, -1}}, {FDC37B80X,{0, 3, 4, 5, -1, 7, 8, -1, -1, -1, -1, -1, -1, -1, -1}}, {FDC37B78X,{0, 3, 4, 5, 6, 7, 8, -1, -1, -1, -1, -1, -1, 10, -1}}, Modified: trunk/src/superio/via/vt1211/Config.lb =================================================================== --- trunk/src/superio/via/vt1211/Config.lb 2009-12-23 22:16:18 UTC (rev 4992) +++ trunk/src/superio/via/vt1211/Config.lb 2009-12-28 09:59:44 UTC (rev 4993) @@ -1,2 +1,23 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2004 Nick Barker <nick.barker9(a)btinternet.com> +## +## This program is free software; you can redistribute it and/or +## modify it under the terms of the GNU General Public License as +## published by the Free Software Foundation; either version 2 of +## the License, or (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, +## MA 02110-1301 USA +## + config chip.h object vt1211.o Modified: trunk/src/superio/via/vt1211/Makefile.inc =================================================================== --- trunk/src/superio/via/vt1211/Makefile.inc 2009-12-23 22:16:18 UTC (rev 4992) +++ trunk/src/superio/via/vt1211/Makefile.inc 2009-12-28 09:59:44 UTC (rev 4993) @@ -1,2 +1,23 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2004 Nick Barker <nick.barker9(a)btinternet.com> +## +## This program is free software; you can redistribute it and/or +## modify it under the terms of the GNU General Public License as +## published by the Free Software Foundation; either version 2 of +## the License, or (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, +## MA 02110-1301 USA +## + #config chip.h obj-$(CONFIG_SUPERIO_VIA_VT1211) += vt1211.o Modified: trunk/src/superio/via/vt1211/chip.h =================================================================== --- trunk/src/superio/via/vt1211/chip.h 2009-12-23 22:16:18 UTC (rev 4992) +++ trunk/src/superio/via/vt1211/chip.h 2009-12-28 09:59:44 UTC (rev 4993) @@ -1,3 +1,24 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2004 Nick Barker <nick.barker9(a)btinternet.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + #ifndef _SUPERIO_VIA_VT1211 #define _SUPERIO_VIA_VT1211 Modified: trunk/src/superio/via/vt1211/vt1211.c =================================================================== --- trunk/src/superio/via/vt1211/vt1211.c 2009-12-23 22:16:18 UTC (rev 4992) +++ trunk/src/superio/via/vt1211/vt1211.c 2009-12-28 09:59:44 UTC (rev 4993) @@ -1,6 +1,7 @@ /* - * (C) Copyright 2004 Nick Barker <nick.barker9(a)btinternet.com> + * This file is part of the coreboot project. * + * Copyright (C) 2004 Nick Barker <nick.barker9(a)btinternet.com> * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as @@ -20,7 +21,6 @@ /* vt1211 routines and defines*/ - #include <arch/io.h> #include <console/console.h> #include <device/device.h> @@ -31,37 +31,36 @@ #include "vt1211.h" #include "chip.h" - static unsigned char vt1211hwmonitorinits[]={ - 0x10,0x3, 0x11,0x10, 0x12,0xd, 0x13,0x7f, - 0x14,0x21, 0x15,0x81, 0x16,0xbd, 0x17,0x8a, - 0x18,0x0, 0x19,0x0, 0x1a,0x0, 0x1b,0x0, - 0x1d,0xff, 0x1e,0x0, 0x1f,0x73, 0x20,0x67, - 0x21,0xc1, 0x22,0xca, 0x23,0x74, 0x24,0xc2, - 0x25,0xc7, 0x26,0xc9, 0x27,0x7f, 0x29,0x0, - 0x2a,0x0, 0x2b,0xff, 0x2c,0x0, 0x2d,0xff, - 0x2e,0x0, 0x2f,0xff, 0x30,0x0, 0x31,0xff, - 0x32,0x0, 0x33,0xff, 0x34,0x0, 0x39,0xff, - 0x3a,0x0, 0x3b,0xff, 0x3c,0xff, 0x3d,0xff, - 0x3e,0x0, 0x3f,0xb0, 0x43,0xff, 0x44,0xff, - 0x46,0xff, 0x47,0x50, 0x4a,0x3, 0x4b,0xc0, - 0x4c,0x0, 0x4d,0x0, 0x4e,0xf, 0x5d,0x77, - 0x5c,0x0, 0x5f,0x33, 0x40,0x1}; + 0x10,0x3, 0x11,0x10, 0x12,0xd, 0x13,0x7f, + 0x14,0x21, 0x15,0x81, 0x16,0xbd, 0x17,0x8a, + 0x18,0x0, 0x19,0x0, 0x1a,0x0, 0x1b,0x0, + 0x1d,0xff, 0x1e,0x0, 0x1f,0x73, 0x20,0x67, + 0x21,0xc1, 0x22,0xca, 0x23,0x74, 0x24,0xc2, + 0x25,0xc7, 0x26,0xc9, 0x27,0x7f, 0x29,0x0, + 0x2a,0x0, 0x2b,0xff, 0x2c,0x0, 0x2d,0xff, + 0x2e,0x0, 0x2f,0xff, 0x30,0x0, 0x31,0xff, + 0x32,0x0, 0x33,0xff, 0x34,0x0, 0x39,0xff, + 0x3a,0x0, 0x3b,0xff, 0x3c,0xff, 0x3d,0xff, + 0x3e,0x0, 0x3f,0xb0, 0x43,0xff, 0x44,0xff, + 0x46,0xff, 0x47,0x50, 0x4a,0x3, 0x4b,0xc0, + 0x4c,0x0, 0x4d,0x0, 0x4e,0xf, 0x5d,0x77, + 0x5c,0x0, 0x5f,0x33, 0x40,0x1 +}; -static void pnp_enter_ext_func_mode(device_t dev) +static void pnp_enter_ext_func_mode(device_t dev) { outb(0x87, dev->path.pnp.port); outb(0x87, dev->path.pnp.port); } -static void pnp_exit_ext_func_mode(device_t dev) +static void pnp_exit_ext_func_mode(device_t dev) { outb(0xaa, dev->path.pnp.port); } static void vt1211_set_iobase(device_t dev, unsigned index, unsigned iobase) { - switch (dev->path.pnp.device) { case VT1211_FDC: case VT1211_PP: @@ -75,14 +74,13 @@ pnp_write_config(dev, index + 1, iobase & 0xff); break; } - } static void init_hwm(unsigned long base) { int i; - // initialize vt1211 hardware monitor registers, which are at 0xECXX + /* initialize vt1211 hardware monitor registers, which are at 0xECXX */ for(i = 0; i < sizeof(vt1211hwmonitorinits); i += 2) { outb(vt1211hwmonitorinits[i + 1], base + vt1211hwmonitorinits[i]); @@ -117,8 +115,6 @@ default: printk_info("vt1211 asked to initialise unknown device!\n"); } - - } void vt1211_pnp_enable_resources(device_t dev) @@ -139,7 +135,7 @@ for( i = 0 ; i < dev->resources; i++){ resource = &dev->resource[i]; resource->flags |= IORESOURCE_STORED; - report_resource_stored(dev, resource, ""); + report_resource_stored(dev, resource, ""); } return; } @@ -176,7 +172,7 @@ } resource->flags |= IORESOURCE_STORED; - report_resource_stored(dev, resource, ""); + report_resource_stored(dev, resource, ""); } pnp_exit_ext_func_mode(dev); Modified: trunk/src/superio/via/vt1211/vt1211.h =================================================================== --- trunk/src/superio/via/vt1211/vt1211.h 2009-12-23 22:16:18 UTC (rev 4992) +++ trunk/src/superio/via/vt1211/vt1211.h 2009-12-28 09:59:44 UTC (rev 4993) @@ -1,6 +1,7 @@ /* - * (C) Copyright 2004 Nick Barker <nick.barker9(a)btinternet.com> + * This file is part of the coreboot project. * + * Copyright (C) 2004 Nick Barker <nick.barker9(a)btinternet.com> * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as Modified: trunk/src/superio/winbond/w83627dhg/Config.lb =================================================================== --- trunk/src/superio/winbond/w83627dhg/Config.lb 2009-12-23 22:16:18 UTC (rev 4992) +++ trunk/src/superio/winbond/w83627dhg/Config.lb 2009-12-28 09:59:44 UTC (rev 4993) @@ -20,4 +20,3 @@ config chip.h object superio.o - Modified: trunk/src/superio/winbond/w83627dhg/Makefile.inc =================================================================== --- trunk/src/superio/winbond/w83627dhg/Makefile.inc 2009-12-23 22:16:18 UTC (rev 4992) +++ trunk/src/superio/winbond/w83627dhg/Makefile.inc 2009-12-28 09:59:44 UTC (rev 4993) @@ -20,4 +20,3 @@ #config chip.h obj-$(CONFIG_SUPERIO_WINBOND_W83627DHG) += superio.o - Modified: trunk/src/superio/winbond/w83627dhg/superio.c =================================================================== --- trunk/src/superio/winbond/w83627dhg/superio.c 2009-12-23 22:16:18 UTC (rev 4992) +++ trunk/src/superio/winbond/w83627dhg/superio.c 2009-12-28 09:59:44 UTC (rev 4993) @@ -103,8 +103,8 @@ { &ops, W83627DHG_SP1, PNP_IO0 | PNP_IRQ0, { 0xff8, 0 }, }, { &ops, W83627DHG_SP2, PNP_IO0 | PNP_IRQ0, { 0xff8, 0 }, }, { &ops, W83627DHG_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1, { 0xfff, 0 }, { 0xfff, 0x4}, }, - // the next line makes coreboot hang in pnp_enable_devices() - // { &ops, W83627DHG_SPI, PNP_IO1, { 0xff8, 0 }, }, + /* the next line makes coreboot hang in pnp_enable_devices() */ + /* { &ops, W83627DHG_SPI, PNP_IO1, { 0xff8, 0 }, }, */ { &ops, W83627DHG_GPIO6, }, { &ops, W83627DHG_WDTO_PLED, }, { &ops, W83627DHG_GPIO2345, }, Modified: trunk/src/superio/winbond/w83627ehg/Config.lb =================================================================== --- trunk/src/superio/winbond/w83627ehg/Config.lb 2009-12-23 22:16:18 UTC (rev 4992) +++ trunk/src/superio/winbond/w83627ehg/Config.lb 2009-12-28 09:59:44 UTC (rev 4993) @@ -1,24 +1,23 @@ -## +## ## This file is part of the coreboot project. -## +## ## Copyright (C) 2007 AMD ## Written by Yinghai Lu <yinghai.lu(a)amd.com> for AMD. -## +## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by ## the Free Software Foundation; either version 2 of the License, or ## (at your option) any later version. -## +## ## This program is distributed in the hope that it will be useful, ## but WITHOUT ANY WARRANTY; without even the implied warranty of ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ## GNU General Public License for more details. -## +## ## You should have received a copy of the GNU General Public License ## along with this program; if not, write to the Free Software ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -## +## config chip.h object superio.o - Modified: trunk/src/superio/winbond/w83627ehg/Makefile.inc =================================================================== --- trunk/src/superio/winbond/w83627ehg/Makefile.inc 2009-12-23 22:16:18 UTC (rev 4992) +++ trunk/src/superio/winbond/w83627ehg/Makefile.inc 2009-12-28 09:59:44 UTC (rev 4993) @@ -1,24 +1,23 @@ -## +## ## This file is part of the coreboot project. -## +## ## Copyright (C) 2007 AMD ## Written by Yinghai Lu <yinghai.lu(a)amd.com> for AMD. -## +## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by ## the Free Software Foundation; either version 2 of the License, or ## (at your option) any later version. -## +## ## This program is distributed in the hope that it will be useful, ## but WITHOUT ANY WARRANTY; without even the implied warranty of ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ## GNU General Public License for more details. -## +## ## You should have received a copy of the GNU General Public License ## along with this program; if not, write to the Free Software ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -## +## #config chip.h obj-$(CONFIG_SUPERIO_WINBOND_W83627EHG) += superio.o - Modified: trunk/src/superio/winbond/w83627ehg/superio.c =================================================================== --- trunk/src/superio/winbond/w83627ehg/superio.c 2009-12-23 22:16:18 UTC (rev 4992) +++ trunk/src/superio/winbond/w83627ehg/superio.c 2009-12-28 09:59:44 UTC (rev 4993) @@ -3,7 +3,7 @@ * * Copyright (C) 2000 AG Electronics Ltd. * Copyright (C) 2003-2004 Linux Networx - * Copyright (C) 2004 Tyan + * Copyright (C) 2004 Tyan * Copyright (C) 2007 AMD * Written by Yinghai Lu <yinghai.lu(a)amd.com> for AMD. * @@ -57,7 +57,8 @@ return inb(port_base + 1); } -static void enable_hwm_smbus(device_t dev) { +static void enable_hwm_smbus(device_t dev) +{ /* Set the pin 91,92 as I2C bus. */ uint8_t reg, value; reg = 0x2a; @@ -99,7 +100,7 @@ value = pnp_read_index(base, reg); value &= 0xff & (~(hwm_reg_values[i + 1])); value |= 0xff & hwm_reg_values[i + 2]; - // printk_debug("base = 0x%04x, reg = 0x%02x, value = 0x%02x\r\n", base, reg,value); + /* printk_debug("base = 0x%04x, reg = 0x%02x, value = 0x%02x\r\n", base, reg,value); */ pnp_write_index(base, reg, value); } } @@ -182,7 +183,7 @@ { &ops, W83627EHG_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07f8, 0}, }, { &ops, W83627EHG_SP1, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, }, { &ops, W83627EHG_SP2, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, }, - // No 4 { 0,}, + /* No 4 { 0,}, */ { &ops, W83627EHG_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1, { 0x7ff, 0 }, { 0x7ff, 0x4}, }, { &ops, W83627EHG_SFI, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, }, { &ops, W83627EHG_WDTO_PLED, }, @@ -208,4 +209,3 @@ CHIP_NAME("Winbond W83627EHG Super I/O") .enable_dev = enable_dev, }; - Modified: trunk/src/superio/winbond/w83627ehg/w83627ehg.h =================================================================== --- trunk/src/superio/winbond/w83627ehg/w83627ehg.h 2009-12-23 22:16:18 UTC (rev 4992) +++ trunk/src/superio/winbond/w83627ehg/w83627ehg.h 2009-12-28 09:59:44 UTC (rev 4993) @@ -31,8 +31,8 @@ #define W83627EHG_HWM 11 /* Hardware Monitor */ /* virtual devices sharing the enables are encoded as follows: - VLDN = baseLDN[7:0] | [10:8] bitpos of enable in 0x30 of baseLDN -*/ + * VLDN = baseLDN[7:0] | [10:8] bitpos of enable in 0x30 of baseLDN + */ #define W83627EHG_SFI ((1 << 8) | 6) /* Flash has bit1 as enable */ #define W83627EHG_GPIO1 W83627EHG_GPIO_GAME_MIDI /* GPIO1 is at LDN 7, bit 0 */ Modified: trunk/src/superio/winbond/w83627ehg/w83627ehg_early_init.c =================================================================== --- trunk/src/superio/winbond/w83627ehg/w83627ehg_early_init.c 2009-12-23 22:16:18 UTC (rev 4992) +++ trunk/src/superio/winbond/w83627ehg/w83627ehg_early_init.c 2009-12-28 09:59:44 UTC (rev 4993) @@ -35,4 +35,3 @@ pnp_set_iobase(dev, PNP_IDX_IO0, iobase); pnp_set_enable(dev, 1); } - Modified: trunk/src/superio/winbond/w83627ehg/w83627ehg_early_serial.c =================================================================== --- trunk/src/superio/winbond/w83627ehg/w83627ehg_early_serial.c 2009-12-23 22:16:18 UTC (rev 4992) +++ trunk/src/superio/winbond/w83627ehg/w83627ehg_early_serial.c 2009-12-28 09:59:44 UTC (rev 4993) @@ -44,4 +44,3 @@ pnp_set_enable(dev, 1); pnp_exit_ext_func_mode(dev); } - Modified: trunk/src/superio/winbond/w83627hf/Config.lb =================================================================== --- trunk/src/superio/winbond/w83627hf/Config.lb 2009-12-23 22:16:18 UTC (rev 4992) +++ trunk/src/superio/winbond/w83627hf/Config.lb 2009-12-28 09:59:44 UTC (rev 4993) @@ -1,2 +1,24 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2000 AG Electronics Ltd. +## Copyright (C) 2003-2004 Linux Networx +## Copyright (C) 2004 Tyan By LYH change from PC87360 +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + config chip.h object superio.o Modified: trunk/src/superio/winbond/w83627hf/Makefile.inc =================================================================== --- trunk/src/superio/winbond/w83627hf/Makefile.inc 2009-12-23 22:16:18 UTC (rev 4992) +++ trunk/src/superio/winbond/w83627hf/Makefile.inc 2009-12-28 09:59:44 UTC (rev 4993) @@ -1,2 +1,24 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2000 AG Electronics Ltd. +## Copyright (C) 2003-2004 Linux Networx +## Copyright (C) 2004 Tyan By LYH change from PC87360 +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + #config chip.h obj-$(CONFIG_SUPERIO_WINBOND_W83627HF) += superio.o Modified: trunk/src/superio/winbond/w83627hf/chip.h =================================================================== --- trunk/src/superio/winbond/w83627hf/chip.h 2009-12-23 22:16:18 UTC (rev 4992) +++ trunk/src/superio/winbond/w83627hf/chip.h 2009-12-28 09:59:44 UTC (rev 4993) @@ -1,3 +1,25 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2000 AG Electronics Ltd. + * Copyright (C) 2003-2004 Linux Networx + * Copyright (C) 2004 Tyan By LYH change from PC87360 + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + #include <pc80/keyboard.h> #include <uart8250.h> Modified: trunk/src/superio/winbond/w83627hf/superio.c =================================================================== --- trunk/src/superio/winbond/w83627hf/superio.c 2009-12-23 22:16:18 UTC (rev 4992) +++ trunk/src/superio/winbond/w83627hf/superio.c 2009-12-28 09:59:44 UTC (rev 4993) @@ -1,8 +1,24 @@ -/* Copyright 2000 AG Electronics Ltd. */ -/* Copyright 2003-2004 Linux Networx */ -/* Copyright 2004 Tyan - By LYH change from PC87360 */ -/* This code is distributed without warranty under the GPL v2 (see COPYING) */ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2000 AG Electronics Ltd. + * Copyright (C) 2003-2004 Linux Networx + * Copyright (C) 2004 Tyan By LYH change from PC87360 + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ #include <arch/io.h> #include <device/device.h> @@ -17,12 +33,12 @@ #include "chip.h" #include "w83627hf.h" - static void pnp_enter_ext_func_mode(device_t dev) { outb(0x87, dev->path.pnp.port); outb(0x87, dev->path.pnp.port); } + static void pnp_exit_ext_func_mode(device_t dev) { outb(0xaa, dev->path.pnp.port); @@ -40,7 +56,8 @@ return inb(port_base + 1); } -static void enable_hwm_smbus(device_t dev) { +static void enable_hwm_smbus(device_t dev) +{ /* set the pin 91,92 as I2C bus */ uint8_t reg, value; reg = 0x2b; @@ -72,7 +89,7 @@ int i; unsigned hwm_reg_values[] = { -/* reg mask data */ + /* reg mask data */ 0x40, 0xff, 0x81, /* start HWM */ 0x48, 0xaa, 0x2a, /* set SMBus base to 0x54>>1 */ 0x4a, 0x21, 0x21, /* set T2 SMBus base to 0x92>>1 and T3 SMBus base to 0x94>>1 */ @@ -84,9 +101,9 @@ }; - for(i = 0; i< ARRAY_SIZE(hwm_reg_values); i+=3 ) { - reg = hwm_reg_values[i]; - value = pnp_read_index(base, reg); + for(i = 0; i< ARRAY_SIZE(hwm_reg_values); i+=3 ) { + reg = hwm_reg_values[i]; + value = pnp_read_index(base, reg); value &= 0xff & hwm_reg_values[i+1]; value |= 0xff & hwm_reg_values[i+2]; #if 0 @@ -134,7 +151,6 @@ pnp_enter_ext_func_mode(dev); pnp_set_resources(dev); pnp_exit_ext_func_mode(dev); - } static void w83627hf_pnp_enable_resources(device_t dev) @@ -148,12 +164,10 @@ break; } pnp_exit_ext_func_mode(dev); - } static void w83627hf_pnp_enable(device_t dev) { - if (!dev->enabled) { pnp_enter_ext_func_mode(dev); @@ -177,7 +191,7 @@ { &ops, W83627HF_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07f8, 0}, }, { &ops, W83627HF_SP1, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, }, { &ops, W83627HF_SP2, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, }, - // No 4 { 0,}, + /* No 4 { 0,}, */ { &ops, W83627HF_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1, { 0x7ff, 0 }, { 0x7ff, 0x4}, }, { &ops, W83627HF_CIR, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, }, { &ops, W83627HF_GAME_MIDI_GPIO1, PNP_IO0 | PNP_IO1 | PNP_IRQ0, { 0x7ff, 0 }, {0x7fe, 0x4}, }, Modified: trunk/src/superio/winbond/w83627hf/w83627hf.h =================================================================== --- trunk/src/superio/winbond/w83627hf/w83627hf.h 2009-12-23 22:16:18 UTC (rev 4992) +++ trunk/src/superio/winbond/w83627hf/w83627hf.h 2009-12-28 09:59:44 UTC (rev 4993) @@ -1,3 +1,25 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2000 AG Electronics Ltd. + * Copyright (C) 2003-2004 Linux Networx + * Copyright (C) 2004 Tyan By LYH change from PC87360 + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + #define W83627HF_FDC 0 /* Floppy */ #define W83627HF_PP 1 /* Parallel Port */ #define W83627HF_SP1 2 /* Com1 */ @@ -10,8 +32,8 @@ #define W83627HF_ACPI 10 #define W83627HF_HWM 11 /* Hardware Monitor */ -//#define W83627HF_GPIO_DEV PNP_DEV(0x2e, W83627HF_GPIO) -//#define W83627HF_XBUS_DEV PNP_DEV(0x2e, W83627HF_XBUS) +/* #define W83627HF_GPIO_DEV PNP_DEV(0x2e, W83627HF_GPIO) */ +/* #define W83627HF_XBUS_DEV PNP_DEV(0x2e, W83627HF_XBUS) */ #define W83627HF_GPSEL 0xf0 #define W83627HF_GPCFG1 0xf1 @@ -87,5 +109,3 @@ #define W83627HF_HAP1 0x14 #define W83627HF_XSCNF 0x15 #define W83627HF_XWBCNF 0x16 - - Modified: trunk/src/superio/winbond/w83627hf/w83627hf_early_init.c =================================================================== --- trunk/src/superio/winbond/w83627hf/w83627hf_early_init.c 2009-12-23 22:16:18 UTC (rev 4992) +++ trunk/src/superio/winbond/w83627hf/w83627hf_early_init.c 2009-12-28 09:59:44 UTC (rev 4993) @@ -1,3 +1,25 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2000 AG Electronics Ltd. + * Copyright 2003-2004 Linux Networx + * Copyright 2004 Tyan By LYH change from PC87360 + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + #include <arch/romcc_io.h> #include "w83627hf.h" @@ -6,6 +28,7 @@ pnp_set_logical_device(dev); pnp_set_enable(dev, 0); } + static void w83627hf_enable_dev(device_t dev, unsigned iobase) { pnp_set_logical_device(dev); Modified: trunk/src/superio/winbond/w83627hf/w83627hf_early_serial.c =================================================================== --- trunk/src/superio/winbond/w83627hf/w83627hf_early_serial.c 2009-12-23 22:16:18 UTC (rev 4992) +++ trunk/src/superio/winbond/w83627hf/w83627hf_early_serial.c 2009-12-28 09:59:44 UTC (rev 4993) @@ -1,3 +1,25 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2000 AG Electronics Ltd. + * Copyright (C) 2003-2004 Linux Networx + * Copyright (C) 2004 Tyan By LYH change from PC87360 + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + #include <arch/romcc_io.h> #include "w83627hf.h" Modified: trunk/src/superio/winbond/w83627thf/Config.lb =================================================================== --- trunk/src/superio/winbond/w83627thf/Config.lb 2009-12-23 22:16:18 UTC (rev 4992) +++ trunk/src/superio/winbond/w83627thf/Config.lb 2009-12-28 09:59:44 UTC (rev 4993) @@ -1,2 +1,24 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2000 AG Electronics Ltd. +## Copyright (C) 2003-2004 Linux Networx +## Copyright (C) 2004 Tyan By LYH change from PC87360 +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + config chip.h object superio.o Modified: trunk/src/superio/winbond/w83627thf/Makefile.inc =================================================================== --- trunk/src/superio/winbond/w83627thf/Makefile.inc 2009-12-23 22:16:18 UTC (rev 4992) +++ trunk/src/superio/winbond/w83627thf/Makefile.inc 2009-12-28 09:59:44 UTC (rev 4993) @@ -1,2 +1,24 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2000 AG Electronics Ltd. +## Copyright (C) 2003-2004 Linux Networx +## Copyright (C) 2004 Tyan By LYH change from PC87360 +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + #config chip.h obj-$(CONFIG_SUPERIO_WINBOND_W83627THF) += superio.o Modified: trunk/src/superio/winbond/w83627thf/chip.h =================================================================== --- trunk/src/superio/winbond/w83627thf/chip.h 2009-12-23 22:16:18 UTC (rev 4992) +++ trunk/src/superio/winbond/w83627thf/chip.h 2009-12-28 09:59:44 UTC (rev 4993) @@ -1,3 +1,25 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2000 AG Electronics Ltd. + * Copyright (C) 2003-2004 Linux Networx + * Copyright (C) 2004 Tyan By LYH change from PC87360 + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + #include <pc80/keyboard.h> #include <uart8250.h> Modified: trunk/src/superio/winbond/w83627thf/superio.c =================================================================== --- trunk/src/superio/winbond/w83627thf/superio.c 2009-12-23 22:16:18 UTC (rev 4992) +++ trunk/src/superio/winbond/w83627thf/superio.c 2009-12-28 09:59:44 UTC (rev 4993) @@ -1,8 +1,24 @@ -/* Copyright 2000 AG Electronics Ltd. */ -/* Copyright 2003-2004 Linux Networx */ -/* Copyright 2004 Tyan - By LYH change from PC87360 */ -/* This code is distributed without warranty under the GPL v2 (see COPYING) */ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2000 AG Electronics Ltd. + * Copyright (C) 2003-2004 Linux Networx + * Copyright (C) 2004 Tyan By LYH change from PC87360 + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ #include <arch/io.h> #include <device/device.h> @@ -16,14 +32,15 @@ #include "chip.h" #include "w83627thf.h" -static void w83627thf_enter_ext_func_mode(device_t dev) +static void w83627thf_enter_ext_func_mode(device_t dev) { - outb(0x87, dev->path.pnp.port); - outb(0x87, dev->path.pnp.port); + outb(0x87, dev->path.pnp.port); + outb(0x87, dev->path.pnp.port); } -static void w83627thf_exit_ext_func_mode(device_t dev) + +static void w83627thf_exit_ext_func_mode(device_t dev) { - outb(0xaa, dev->path.pnp.port); + outb(0xaa, dev->path.pnp.port); } static void w83627thf_init(device_t dev) @@ -38,7 +55,7 @@ } conf = dev->chip_info; switch(dev->path.pnp.device) { - case W83627THF_SP1: + case W83627THF_SP1: res0 = find_resource(dev, PNP_IDX_IO0); init_uart8250(res0->base, &conf->com1); break; @@ -70,12 +87,11 @@ static void w83627thf_enable(device_t dev) { - w83627thf_enter_ext_func_mode(dev); + w83627thf_enter_ext_func_mode(dev); pnp_enable(dev); - w83627thf_exit_ext_func_mode(dev); + w83627thf_exit_ext_func_mode(dev); } - static struct device_operations ops = { .read_resources = pnp_read_resources, .set_resources = w83627thf_set_resources, @@ -85,18 +101,18 @@ }; static struct pnp_info pnp_dev_info[] = { - { &ops, W83627THF_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07f8, 0}, }, - { &ops, W83627THF_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07f8, 0}, }, - { &ops, W83627THF_SP1, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, }, - { &ops, W83627THF_SP2, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, }, - // No 4 { 0,}, - { &ops, W83627THF_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1, { 0x7ff, 0 }, { 0x7ff, 0x4}, }, - { &ops, W83627THF_CIR, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, }, - { &ops, W83627THF_GAME_MIDI_GPIO1, PNP_IO0 | PNP_IO1 | PNP_IRQ0, { 0x7ff, 0 }, {0x7fe, 4} }, - // { W83627THF_GPIO2,}, - // { W83627THF_GPIO3,}, - { &ops, W83627THF_ACPI, PNP_IRQ0, }, - { &ops, W83627THF_HWM, PNP_IO0 | PNP_IRQ0, { 0xff8, 0 } }, + { &ops, W83627THF_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07f8, 0}, }, + { &ops, W83627THF_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07f8, 0}, }, + { &ops, W83627THF_SP1, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, }, + { &ops, W83627THF_SP2, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, }, + /* No 4 { 0,}, */ + { &ops, W83627THF_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1, { 0x7ff, 0 }, { 0x7ff, 0x4}, }, + { &ops, W83627THF_CIR, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, }, + { &ops, W83627THF_GAME_MIDI_GPIO1, PNP_IO0 | PNP_IO1 | PNP_IRQ0, { 0x7ff, 0 }, {0x7fe, 4} }, + /* { W83627THF_GPIO2,}, */ + /* { W83627THF_GPIO3,}, */ + { &ops, W83627THF_ACPI, PNP_IRQ0, }, + { &ops, W83627THF_HWM, PNP_IO0 | PNP_IRQ0, { 0xff8, 0 } }, }; static void enable_dev(device_t dev) Modified: trunk/src/superio/winbond/w83627thf/w83627thf.h =================================================================== --- trunk/src/superio/winbond/w83627thf/w83627thf.h 2009-12-23 22:16:18 UTC (rev 4992) +++ trunk/src/superio/winbond/w83627thf/w83627thf.h 2009-12-28 09:59:44 UTC (rev 4993) @@ -1,3 +1,25 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2000 AG Electronics Ltd. + * Copyright (C) 2003-2004 Linux Networx + * Copyright (C) 2004 Tyan By LYH change from PC87360 + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + #define W83627THF_FDC 0 /* Floppy */ #define W83627THF_PP 1 /* Parallel Port */ #define W83627THF_SP1 2 /* Com1 */ Modified: trunk/src/superio/winbond/w83627thf/w83627thf_early_serial.c =================================================================== --- trunk/src/superio/winbond/w83627thf/w83627thf_early_serial.c 2009-12-23 22:16:18 UTC (rev 4992) +++ trunk/src/superio/winbond/w83627thf/w83627thf_early_serial.c 2009-12-28 09:59:44 UTC (rev 4993) @@ -1,3 +1,25 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2000 AG Electronics Ltd. + * Copyright (C) 2003-2004 Linux Networx + * Copyright (C) 2004 Tyan By LYH change from PC87360 + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + #include <arch/romcc_io.h> #include "w83627thf.h" Modified: trunk/src/superio/winbond/w83627thg/Config.lb =================================================================== --- trunk/src/superio/winbond/w83627thg/Config.lb 2009-12-23 22:16:18 UTC (rev 4992) +++ trunk/src/superio/winbond/w83627thg/Config.lb 2009-12-28 09:59:44 UTC (rev 4993) @@ -1,2 +1,24 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2000 AG Electronics Ltd. +## Copyright (C) 2003-2004 Linux Networx +## Copyright (C) 2004 Tyan By LYH change from PC87360 +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + config chip.h object superio.o Modified: trunk/src/superio/winbond/w83627thg/Makefile.inc =================================================================== --- trunk/src/superio/winbond/w83627thg/Makefile.inc 2009-12-23 22:16:18 UTC (rev 4992) +++ trunk/src/superio/winbond/w83627thg/Makefile.inc 2009-12-28 09:59:44 UTC (rev 4993) @@ -1,2 +1,24 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2000 AG Electronics Ltd. +## Copyright (C) 2003-2004 Linux Networx +## Copyright (C) 2004 Tyan By LYH change from PC87360 +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + #config chip.h obj-$(CONFIG_SUPERIO_WINBOND_W83627THG) += superio.o Modified: trunk/src/superio/winbond/w83627thg/chip.h =================================================================== --- trunk/src/superio/winbond/w83627thg/chip.h 2009-12-23 22:16:18 UTC (rev 4992) +++ trunk/src/superio/winbond/w83627thg/chip.h 2009-12-28 09:59:44 UTC (rev 4993) @@ -1,3 +1,25 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2000 AG Electronics Ltd. + * Copyright (C) 2003-2004 Linux Networx + * Copyright (C) 2004 Tyan By LYH change from PC87360 + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + #include <pc80/keyboard.h> #include <uart8250.h> Modified: trunk/src/superio/winbond/w83627thg/superio.c =================================================================== --- trunk/src/superio/winbond/w83627thg/superio.c 2009-12-23 22:16:18 UTC (rev 4992) +++ trunk/src/superio/winbond/w83627thg/superio.c 2009-12-28 09:59:44 UTC (rev 4993) @@ -1,8 +1,24 @@ -/* Copyright 2000 AG Electronics Ltd. */ -/* Copyright 2003-2004 Linux Networx */ -/* Copyright 2004 Tyan - By LYH change from PC87360 */ -/* This code is distributed without warranty under the GPL v2 (see COPYING) */ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2000 AG Electronics Ltd. + * Copyright (C) 2003-2004 Linux Networx + * Copyright (C) 2004 Tyan By LYH change from PC87360 + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ #include <arch/io.h> #include <device/device.h> @@ -15,14 +31,14 @@ #include "chip.h" #include "w83627thg.h" -static void w83627thg_enter_ext_func_mode(device_t dev) +static void w83627thg_enter_ext_func_mode(device_t dev) { - outb(0x87, dev->path.pnp.port); - outb(0x87, dev->path.pnp.port); + outb(0x87, dev->path.pnp.port); + outb(0x87, dev->path.pnp.port); } -static void w83627thg_exit_ext_func_mode(device_t dev) +static void w83627thg_exit_ext_func_mode(device_t dev) { - outb(0xaa, dev->path.pnp.port); + outb(0xaa, dev->path.pnp.port); } static void w83627thg_init(device_t dev) @@ -37,7 +53,7 @@ } conf = dev->chip_info; switch(dev->path.pnp.device) { - case W83627THG_SP1: + case W83627THG_SP1: res0 = find_resource(dev, PNP_IDX_IO0); init_uart8250(res0->base, &conf->com1); break; @@ -69,12 +85,11 @@ static void w83627thg_enable(device_t dev) { - w83627thg_enter_ext_func_mode(dev); + w83627thg_enter_ext_func_mode(dev); pnp_enable(dev); - w83627thg_exit_ext_func_mode(dev); + w83627thg_exit_ext_func_mode(dev); } - static struct device_operations ops = { .read_resources = pnp_read_resources, .set_resources = w83627thg_set_resources, @@ -84,17 +99,17 @@ }; static struct pnp_info pnp_dev_info[] = { - { &ops, W83627THG_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07f8, 0}, }, - { &ops, W83627THG_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07f8, 0}, }, - { &ops, W83627THG_SP1, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, }, - { &ops, W83627THG_SP2, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, }, - // No 4 { 0,}, - { &ops, W83627THG_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1, { 0x7ff, 0 }, { 0x7ff, 0x4}, }, - { &ops, W83627THG_GAME_MIDI_GPIO1, PNP_IO0 | PNP_IO1 | PNP_IRQ0, { 0x7ff, 0 }, {0x7fe, 4} }, - { &ops, W83627THG_GPIO2,}, - { &ops, W83627THG_GPIO3,}, - { &ops, W83627THG_ACPI, PNP_IRQ0, }, - { &ops, W83627THG_HWM, PNP_IO0 | PNP_IRQ0, { 0xff8, 0 } }, + { &ops, W83627THG_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07f8, 0}, }, + { &ops, W83627THG_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07f8, 0}, }, + { &ops, W83627THG_SP1, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, }, + { &ops, W83627THG_SP2, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, }, + /* No 4 { 0,}, */ + { &ops, W83627THG_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1, { 0x7ff, 0 }, { 0x7ff, 0x4}, }, + { &ops, W83627THG_GAME_MIDI_GPIO1, PNP_IO0 | PNP_IO1 | PNP_IRQ0, { 0x7ff, 0 }, {0x7fe, 4} }, + { &ops, W83627THG_GPIO2,}, + { &ops, W83627THG_GPIO3,}, + { &ops, W83627THG_ACPI, PNP_IRQ0, }, + { &ops, W83627THG_HWM, PNP_IO0 | PNP_IRQ0, { 0xff8, 0 } }, }; static void enable_dev(device_t dev) Modified: trunk/src/superio/winbond/w83627thg/w83627thg.h =================================================================== --- trunk/src/superio/winbond/w83627thg/w83627thg.h 2009-12-23 22:16:18 UTC (rev 4992) +++ trunk/src/superio/winbond/w83627thg/w83627thg.h 2009-12-28 09:59:44 UTC (rev 4993) @@ -1,3 +1,25 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2000 AG Electronics Ltd. + * Copyright (C) 2003-2004 Linux Networx + * Copyright (C) 2004 Tyan By LYH change from PC87360 + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + #define W83627THG_FDC 0 /* Floppy */ #define W83627THG_PP 1 /* Parallel Port */ #define W83627THG_SP1 2 /* Com1 */ Modified: trunk/src/superio/winbond/w83627thg/w83627thg_early_serial.c =================================================================== --- trunk/src/superio/winbond/w83627thg/w83627thg_early_serial.c 2009-12-23 22:16:18 UTC (rev 4992) +++ trunk/src/superio/winbond/w83627thg/w83627thg_early_serial.c 2009-12-28 09:59:44 UTC (rev 4993) @@ -1,3 +1,25 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2000 AG Electronics Ltd. + * Copyright (C) 2003-2004 Linux Networx + * Copyright (C) 2004 Tyan By LYH change from PC87360 + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + #include <arch/romcc_io.h> #include "w83627thg.h" Modified: trunk/src/superio/winbond/w83627uhg/superio.c =================================================================== --- trunk/src/superio/winbond/w83627uhg/superio.c 2009-12-23 22:16:18 UTC (rev 4992) +++ trunk/src/superio/winbond/w83627uhg/superio.c 2009-12-28 09:59:44 UTC (rev 4993) @@ -80,7 +80,7 @@ conf = dev->chip_info; switch(dev->path.pnp.device) { - case W83627UHG_SP1: + case W83627UHG_SP1: res0 = find_resource(dev, PNP_IDX_IO0); /* set_uart_clock_source(dev, 0); */ init_uart8250(res0->base, &conf->com1); Modified: trunk/src/superio/winbond/w83697hf/w83697hf_early_serial.c =================================================================== --- trunk/src/superio/winbond/w83697hf/w83697hf_early_serial.c 2009-12-23 22:16:18 UTC (rev 4992) +++ trunk/src/superio/winbond/w83697hf/w83697hf_early_serial.c 2009-12-28 09:59:44 UTC (rev 4993) @@ -29,7 +29,7 @@ outb(0x87, port); } -static void pnp_exit_ext_func_mode(device_t dev) +static void pnp_exit_ext_func_mode(device_t dev) { u16 port = dev >> 8; outb(0xaa, port); Modified: trunk/src/superio/winbond/w83977f/Config.lb =================================================================== --- trunk/src/superio/winbond/w83977f/Config.lb 2009-12-23 22:16:18 UTC (rev 4992) +++ trunk/src/superio/winbond/w83977f/Config.lb 2009-12-28 09:59:44 UTC (rev 4993) @@ -1,22 +1,22 @@ -## +## ## This file is part of the coreboot project. -## +## ## Copyright (C) 2007 Nikolay Petukhov <nikolay.petukhov(a)gmail.com> -## +## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by ## the Free Software Foundation; either version 2 of the License, or ## (at your option) any later version. -## +## ## This program is distributed in the hope that it will be useful, ## but WITHOUT ANY WARRANTY; without even the implied warranty of ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ## GNU General Public License for more details. -## +## ## You should have received a copy of the GNU General Public License ## along with this program; if not, write to the Free Software ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -## +## config chip.h object superio.o Modified: trunk/src/superio/winbond/w83977f/Makefile.inc =================================================================== --- trunk/src/superio/winbond/w83977f/Makefile.inc 2009-12-23 22:16:18 UTC (rev 4992) +++ trunk/src/superio/winbond/w83977f/Makefile.inc 2009-12-28 09:59:44 UTC (rev 4993) @@ -1,22 +1,22 @@ -## +## ## This file is part of the coreboot project. -## +## ## Copyright (C) 2007 Nikolay Petukhov <nikolay.petukhov(a)gmail.com> -## +## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by ## the Free Software Foundation; either version 2 of the License, or ## (at your option) any later version. -## +## ## This program is distributed in the hope that it will be useful, ## but WITHOUT ANY WARRANTY; without even the implied warranty of ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ## GNU General Public License for more details. -## +## ## You should have received a copy of the GNU General Public License ## along with this program; if not, write to the Free Software ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -## +## #config chip.h obj-$(CONFIG_SUPERIO_WINBOND_W83977F) += superio.o Modified: trunk/src/superio/winbond/w83977f/superio.c =================================================================== --- trunk/src/superio/winbond/w83977f/superio.c 2009-12-23 22:16:18 UTC (rev 4992) +++ trunk/src/superio/winbond/w83977f/superio.c 2009-12-28 09:59:44 UTC (rev 4993) @@ -30,12 +30,12 @@ #include "chip.h" #include "w83977f.h" -static void w83977f_enter_ext_func_mode(device_t dev) +static void w83977f_enter_ext_func_mode(device_t dev) { outb(0x87, dev->path.pnp.port); outb(0x87, dev->path.pnp.port); } -static void w83977f_exit_ext_func_mode(device_t dev) +static void w83977f_exit_ext_func_mode(device_t dev) { outb(0xaa, dev->path.pnp.port); } Modified: trunk/src/superio/winbond/w83977tf/Config.lb =================================================================== --- trunk/src/superio/winbond/w83977tf/Config.lb 2009-12-23 22:16:18 UTC (rev 4992) +++ trunk/src/superio/winbond/w83977tf/Config.lb 2009-12-28 09:59:44 UTC (rev 4993) @@ -1,2 +1,24 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2000 AG Electronics Ltd. +## Copyright (C) 2003-2004 Linux Networx +## Copyright (C) 2004 Tyan By LYH change from PC87360 +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + config chip.h object superio.o Modified: trunk/src/superio/winbond/w83977tf/Makefile.inc =================================================================== --- trunk/src/superio/winbond/w83977tf/Makefile.inc 2009-12-23 22:16:18 UTC (rev 4992) +++ trunk/src/superio/winbond/w83977tf/Makefile.inc 2009-12-28 09:59:44 UTC (rev 4993) @@ -1,2 +1,24 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2000 AG Electronics Ltd. +## Copyright (C) 2003-2004 Linux Networx +## Copyright (C) 2004 Tyan By LYH change from PC87360 +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + #config chip.h obj-$(CONFIG_SUPERIO_WINBOND_W83977TF) += superio.o Modified: trunk/src/superio/winbond/w83977tf/chip.h =================================================================== --- trunk/src/superio/winbond/w83977tf/chip.h 2009-12-23 22:16:18 UTC (rev 4992) +++ trunk/src/superio/winbond/w83977tf/chip.h 2009-12-28 09:59:44 UTC (rev 4993) @@ -1,3 +1,25 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2000 AG Electronics Ltd. + * Copyright (C) 2003-2004 Linux Networx + * Copyright (C) 2004 Tyan By LYH change from PC87360 + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + #include <pc80/keyboard.h> #include <uart8250.h> Modified: trunk/src/superio/winbond/w83977tf/superio.c =================================================================== --- trunk/src/superio/winbond/w83977tf/superio.c 2009-12-23 22:16:18 UTC (rev 4992) +++ trunk/src/superio/winbond/w83977tf/superio.c 2009-12-28 09:59:44 UTC (rev 4993) @@ -1,11 +1,27 @@ -/* Copyright 2000 AG Electronics Ltd. */ -/* Copyright 2003-2004 Linux Networx */ -/* Copyright 2004 Tyan - By LYH change from PC87360 */ -/* This code is distributed without warranty under the GPL v2 (see COPYING) */ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2000 AG Electronics Ltd. + * Copyright (C) 2003-2004 Linux Networx + * Copyright (C) 2004 Tyan By LYH change from PC87360 + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ -/* 2006-4-24 - * Adapted for the w83977 by rsmith <smithbone(a)gmail.com> +/* 2006-4-24 + * Adapted for the w83977 by rsmith <smithbone(a)gmail.com> * This is mostly just a search and replace on the part type * TODO: Actually see if all the sub functionis exist and are * setup correctly. @@ -23,14 +39,14 @@ #include "chip.h" #include "w83977tf.h" -static void w83977tf_enter_ext_func_mode(device_t dev) +static void w83977tf_enter_ext_func_mode(device_t dev) { - outb(0x87, dev->path.pnp.port); - outb(0x87, dev->path.pnp.port); + outb(0x87, dev->path.pnp.port); + outb(0x87, dev->path.pnp.port); } -static void w83977tf_exit_ext_func_mode(device_t dev) +static void w83977tf_exit_ext_func_mode(device_t dev) { - outb(0xaa, dev->path.pnp.port); + outb(0xaa, dev->path.pnp.port); } static void w83977tf_init(device_t dev) @@ -45,7 +61,7 @@ } conf = dev->chip_info; switch(dev->path.pnp.device) { - case W83977TF_SP1: + case W83977TF_SP1: res0 = find_resource(dev, PNP_IDX_IO0); init_uart8250(res0->base, &conf->com1); break; @@ -77,12 +93,11 @@ static void w83977tf_enable(device_t dev) { - w83977tf_enter_ext_func_mode(dev); + w83977tf_enter_ext_func_mode(dev); pnp_enable(dev); - w83977tf_exit_ext_func_mode(dev); + w83977tf_exit_ext_func_mode(dev); } - static struct device_operations ops = { .read_resources = pnp_read_resources, .set_resources = w83977tf_set_resources, @@ -92,15 +107,15 @@ }; static struct pnp_info pnp_dev_info[] = { - { &ops, W83977TF_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07f8, 0}, }, - { &ops, W83977TF_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07f8, 0}, }, - { &ops, W83977TF_SP1, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, }, - { &ops, W83977TF_SP2, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, }, - // No 4 { 0,}, - { &ops, W83977TF_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1, { 0x7ff, 0 }, { 0x7ff, 0x4}, }, - { &ops, W83977TF_CIR, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, }, - { &ops, W83977TF_GAME_MIDI_GPIO1, PNP_IO0 | PNP_IO1 | PNP_IRQ0, { 0x7ff, 0 }, {0x7fe, 4} }, - { &ops, W83977TF_ACPI, PNP_IRQ0, }, + { &ops, W83977TF_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07f8, 0}, }, + { &ops, W83977TF_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07f8, 0}, }, + { &ops, W83977TF_SP1, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, }, + { &ops, W83977TF_SP2, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, }, + /* No 4 { 0,}, */ + { &ops, W83977TF_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1, { 0x7ff, 0 }, { 0x7ff, 0x4}, }, + { &ops, W83977TF_CIR, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, }, + { &ops, W83977TF_GAME_MIDI_GPIO1, PNP_IO0 | PNP_IO1 | PNP_IRQ0, { 0x7ff, 0 }, {0x7fe, 4} }, + { &ops, W83977TF_ACPI, PNP_IRQ0, }, }; static void enable_dev(device_t dev) Modified: trunk/src/superio/winbond/w83977tf/w83977tf.h =================================================================== --- trunk/src/superio/winbond/w83977tf/w83977tf.h 2009-12-23 22:16:18 UTC (rev 4992) +++ trunk/src/superio/winbond/w83977tf/w83977tf.h 2009-12-28 09:59:44 UTC (rev 4993) @@ -1,3 +1,25 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2000 AG Electronics Ltd. + * Copyright (C) 2003-2004 Linux Networx + * Copyright (C) 2004 Tyan By LYH change from PC87360 + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + #define W83977TF_FDC 0 /* Floppy */ #define W83977TF_PP 1 /* Parallel Port */ #define W83977TF_SP1 2 /* Com1 */ @@ -8,4 +30,3 @@ #define W83977TF_GPIO2 8 #define W83977TF_GPIO3 9 #define W83977TF_ACPI 10 - Modified: trunk/src/superio/winbond/w83977tf/w83977tf_early_serial.c =================================================================== --- trunk/src/superio/winbond/w83977tf/w83977tf_early_serial.c 2009-12-23 22:16:18 UTC (rev 4992) +++ trunk/src/superio/winbond/w83977tf/w83977tf_early_serial.c 2009-12-28 09:59:44 UTC (rev 4993) @@ -1,3 +1,25 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2000 AG Electronics Ltd. + * Copyright (C) 2003-2004 Linux Networx + * Copyright (C) 2004 Tyan By LYH change from PC87360 + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + #include <arch/romcc_io.h> #include "w83977tf.h"

1 0

M2v-mx_se asus : s3 sleeping broken since rev4625 ruik
by congedete＠voila.fr 28 Dec '09

28 Dec '09

Hello, I did some testing on my Asus M2v-mx_se and I discover that s3 sleeping state in broken since revision 4625 from Rudolf Marek for the motherboard. It enters in s3 sleeping state, the LED is blinking, but during the wakeup it simply reboots instead of jumping to the boot segment. Does anyone encounter the same problem ? I don't know if it's an ACPI problem or the coreboot v3 features added that causes the trouble. Hope someone could help or upgrade coreboot for M2v-mx_se. Thanks in advance. ____________________________________________________ Tables en fête, recettes parfaites, sorties en goguette tout est sur http://evenementiel.voila.fr/Noel

2 3

Tr: Re: M2v-mx_se asus : s3 sleeping broken since rev4625 ruik
by congedete＠voila.fr 27 Dec '09

27 Dec '09

> Message du 27/12/09 à 23h18 > De : congedete(a)voila.fr > A : "Rudolf Marek" <r.marek(a)assembler.cz> > Copie à : > Objet : Re: [coreboot] M2v-mx_se asus : s3 sleeping broken since rev4625 ruik > > Sorry Rudolf, > > rev 4625 is working, but as you tell it is broken after Stephan made changes. > It's to be up to date with those changes. > > Thank you to give your precious time. > Regards. > > > > Message du 27/12/09 à 23h10 > > De : "Rudolf Marek" <r.marek(a)assembler.cz> > > A : congedete(a)voila.fr > > Copie à : coreboot(a)coreboot.org > > Objet : Re: [coreboot] M2v-mx_se asus : s3 sleeping broken since rev4625 ruik > > > > Hi, > > > > Yeah I know. I think it is broken since Stephan changes to wakeup core and the > > memory manager for the "blocks" stuff. There is one patch for consolidating the > > integrated UMA stuff - this patch needs to be adjusted plus there must be some > > patches for the zero copy logic. I had no time for this. I can try to fix it > > tomorrow if I find some semi finished patch. But mine time is limited so it is > > difficult. > > > > You mentioned the patch 4625 broke it. Can you try 4624 and/or 4627? I suspect > > this change is unrelated. > > > > Rudolf > > > > congedete(a)voila.fr napsal(a): > > > Hello, > > > > > > I did some testing on my Asus M2v-mx_se and I discover that s3 sleeping state in broken since revision 4625 from Rudolf Marek for the motherboard. > > > It enters in s3 sleeping state, the LED is blinking, but during the wakeup it simply reboots instead of jumping to the boot segment. > > > > > > Does anyone encounter the same problem ? > > > I don't know if it's an ACPI problem or the coreboot v3 features added that causes the trouble. > > > > > > Hope someone could help or upgrade coreboot for M2v-mx_se. > > > > > > Thanks in advance. > > > > > > ____________________________________________________ > > > > > > Tables en fête, recettes parfaites, sorties en goguette tout est sur http://evenementiel.voila.fr/Noel > > > > > > > > > > > > > > > > -- > > coreboot mailing list: coreboot(a)coreboot.org > > http://www.coreboot.org/mailman/listinfo/coreboot > > ____________________________________________________ > > Tables en fête, recettes parfaites, sorties en goguette tout est sur http://evenementiel.voila.fr/Noel > ____________________________________________________ Tables en fête, recettes parfaites, sorties en goguette tout est sur http://evenementiel.voila.fr/Noel

1 0

Coreboot BSD-style Open Source licence (was: Re: Coreboot or UEFI, who will be the winner.)
by Guillaume FORTAINE 27 Dec '09

27 Dec '09

Misters, Let me introduce myself : Guillaume FORTAINE, Engineer in Computer Science. I am currently working on a Virtualization Firmware and I would greatly appreciate to go further into the ideas mentioned in the coreboot GSOC project AVATT [1]. I am definitely aware about the UEFI Forum and especially the Hypervista's effort to implement an UEFI Hypervisor [2]. From my analysis, Hypervista is of particular interest as business case for an SMB trying to innovate around UEFI. Their effort has been a failure and I am not surprised, because three years ago (in 2006), I was the first to post on the edk2 website to kindly ask some hardware support from the UEFI Forum [3]. To quote the reply from an Intel engineer [4]: "The Edk2 project on www.TianoCore.org does not have silicon enabling code but it does implement UEFI conformant interfaces. It currently builds under Windows, Linux, and Mac OS X. So this code may be helpful to you." The first point is to show you that I followed the UEFI's effort since the beginning and that as a small organization, we tried to contribute to something new. And I didn't receive any support. What is the point of a Platform Initialization software that doesn't provide any hardware ? At least an Intel Customer Reference Board with an initial UEFI port would have been an invaluable help to provide further innovation. Two years later, the situation was the same for Hypervista. To quote [2] : "During our recent search for a UEFI compliant PC motherboard, even Intel®, AMI®, and Phoenix® had difficulty identifying PC motherboards that support UEFI 2.x in June 2008." That's why I have chosen coreboot as my hardware initialization firmware. However, to date, there was no case of large scale adoption of coreboot and Intel gave the main reason. To quote [5]: "And with the GPL issues around intellectual property, hardware vendors and OEM’s will be unlikely to adopt LinuxBIOS going forward." We can see that the main concern for Hardware Vendors to deploy coreboot is not because it is open source, but, because it is under a GPL License. I believe that it could be valuable to find a compromise for letting the big players use coreboot technology. And my conclusion is that a switch to a BSD-style Open Source licence could be a smart move, thus letting Hardware Vendors (CPU, Chipset, OEMs, IHVs) protect innovation. To prove the business case for a BSD-Licensed coreboot, I contacted two prominent hardware vendors from the UEFI Forum. To quote : a) "If you are able to make a clean break with the GPL-based Coreboot for your project to be BSD licensed, there may be elements that we may be interested, or maybe it could be of interest to a special platform. We don't need to open source firmware in that scenario and we can use any of the code for whatever reasons we want to. " b) > "And with the GPL issues around intellectual property, hardware vendors and OEM’s will be unlikely to adopt LinuxBIOS > going forward." [5] I think that's nonsense. VIA, AMD et al are quite happily contributing to coreboot. Not as much as we might like, perhaps, but they are doing more than X. That's why despite all the work that X engineers are putting into fast-boot work for Moblin, we still see people out there saying "If you want it to boot fast, use AMD or VIA hardware". There is absolutely no reason why a platform firmware couldn't be GPL licensed. There's no real need for people to hide how the memory controller is initialised. It's just baseless paranoia. If there is _anything_ that actually _needs_ to be kept secret, then it'll be crypto (and DRM) stuff -- and if that stuff actually _does_ need to be kept secret then it's a clear indication that the hardware is fundamentally broken anyway. > We can see that the main concern for Hardware Vendors to deploy coreboot is not because it is open source, but, because it> is under a GPL License. > > That's why we believe that to switch to a BSD-style Open Source licence could be a smart move, thus letting Hardware > Vendors (CPU, Chipset, OEMs, IHVs) protect innovation. This is still a good move anyway, I think. People are too entrenched in the idea that the world will end if they actually tell people how to initialise the hardware, which is insane. We'll never cure that brain damage all in one go and get to a fully open implementation; I think it _has_ to be done piecemeal, which a BSD solution allows. We can start off with some binary-only parts, and then pin the nay-sayers down on one at a time, and make them tell us _precisely_ what form the apocalypse will take if we publish the source code to each one. > Our question is fairly simple. Would X consider any interest to coreboot AVATT under a BSD License ? I cannot speak for X on such matters. But there are certainly individuals who would _like_ the company X to be interested, because we believe it's the right approach. My question is fairly simple : Would people from the coreboot project agree to release the source code under a BSD-style Open Source licence instead of the GPL ? I look forward to your answer, Best Regards, Guillaume FORTAINE [1] http://www.coreboot.org/AVATT[2] http://x86asm.net/articles/uefi-hypervisors-winning-the-race-to-bare-metal/… https://edk2.tianocore.org/ds/viewMessage.do?dsForumId=139&dsMessageId=1375… https://edk2.tianocore.org/ds/viewMessage.do?dsForumId=139&dsMessageId=1380… http://www.uefi.org/learning_center/A_Tale_of_Two_Standards.pdf _________________________________________________________________ Windows Live Hotmail: Your friends can get your Facebook updates, right from Hotmail®. http://www.microsoft.com/middleeast/windows/windowslive/see-it-in-action/so…

5 4

Asrock 939A785GMH - bit of report
by Rudolf Marek 26 Dec '09

26 Dec '09

Hello, I did some hacking. I have the CAR stage booting, I hacked the RS690 code and early SB600 code to work on SB700/RS780. However I'm stuck with ht - reset. I'm not able to set the new HT settings - the documentation disagrees with reality. The docs are bad also for 690. 8.4.2 Changing to High-Speed HyperTransport 1 Mode suggests to write new freq NBCFG x d0 [11:8]. This reg is RO. I tried to do the same as 690 code but the reg seems to be RO too. So I'm stuck. It would really help if AMD could release the code. I released the SerialICE patch for this board and I also mapped the GPIO settings. Thanks, Rudolf

1 0

← Newer
1
2
3
4
5
6
7
8
9
...
17
Older →

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

2012

2011

2010

2009

2008

2007

2006

2005

2004

2003

2002

coreboot December 2009