coreboot December 2009

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169 discussions

build service results for r4990
by coreboot information 23 Dec '09

23 Dec '09

Dear coreboot readers! This is the automatic build system of coreboot. The developer "mjones" checked in revision 4990 to the coreboot repository. This caused the following changes: Change Log: Add mainboard x86emu interrupt function support. Add tim5690 VGA BIOS functions: int15 getting LCD panel ID. Signed-off-by: Libra Li <libra.li(a)technexion.com> Acked-by: Marc Jones <marcj303(a)gmail.com> Build Log: Compilation of technexion:tim5690 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4990&device=tim5690&vendor… If something broke during this checkin please be a pain in mjones's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

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[PATCH]tinybootblock
by Patrick Georgi 23 Dec '09

23 Dec '09

Hi, attached patch implements my tinybootblock concept (formerly known as newfailover) in Kconfig. It's designed to be non-instrusive, so boards will continue to build as usual unless they're changed to use the feature. As a proof of concept (which I used for development), emulation/qemu-x86 is changed to tinybootblock, but other boards will require more changes, so it not a complete example on how to convert a board. Objectives of tinybootblock (when fully implemented): - Fix Fam10 boards on Kconfig, which require >64kb for raminit. That should help with replacing newconfig with kconfig completely. newconfig requires the failover mechanism on those boards to work around this limit, and this solves it similarily by splitting the code in a top-64k block and "the rest". - Use CBFS The newconfig failover mechanism uses the pre-CBFS image layout (cat(1)ing files together and relying on magic offsets to determine entry points). CBFS provides a clean solution for that. - Provide a framework to build image selection logic In newconfig, most boards have their own code to select the image. The goal in this layout is to have generic decision routines to take care of that, and encourage their use. - Push as much as possible out of the bootblock The failover mechanism so far did CAR in the bootblock and raminit in the later stage. With tinybootblock, CAR is supposed to end up outside the bootblock. "Safe updates", once we provide them, will be able to update CAR support for new CPU types, too. Code flow in tinybootblock: - 16bit reset vector (0xfffffff0) - jump to 32bit mode - Do whatever is necessary to have the entire ROM around (C code, compiled with romcc) - Look up fallback/romstage in CBFS (this can be extended with selection logic if desired) ("selection logic" is C, compiled with romcc, lookup is assembly) - Fetch the entry point which is stored in the romstage's header - Jump to the entry point. fallback/romstage is linked for the address where it finally resides in the image, so it's execute in place. - fallback/romstage is the original bootblock code (except for ROM enable): Setup CAR if available, do raminit, call coreboot_ram Current issues: - No support for rom enable sequences yet. QEmu doesn't need them, but they're what I do next. - The bootblock isn't exactly tiny, it's 64kb. Most of it is empty (on qemu, it's ~400 used bytes including id section and reset vector, ~350 byte for all code). To be done after rom enable works. - There might be better places to push files to (both in the sources and in the build tree) - There's some problem with the various section types in ELF which I worked around in cbfstool: If the section starts earlier than the desired load address, strip the bytes before the load address. This is no problem in automatic operation but can have lead to mistakes in manual operation. Future developments: - At some point we might want to have various variants of the bootblock: Unconditionally loading a given romstage (what we have now), selecting between fallback/normal by CMOS (as in newconfig), enabling a rescue flash routine on GPIO, etc. As mentioned, ROM enable support is still missing. Once this is done, tinybootblock should be useful for a broader audience (eg. to port boards), but I wanted to get the current state out now, as it finally works. Signed-off-by: Patrick Georgi <patrick.georgi(a)coresystems.de>

4 5

[PATCH] The function int15 working on the Technexion's tim5690.
by Libra Li 23 Dec '09

23 Dec '09

Hi, The VGA BIOS is through int15 getting LCD panel ID. Then the VBIOS call int15's "Get LCD panel ID". The panel ID is selection by switch. This function is reference "AMD RS690 ASIC Family BIOS Developer's Guide". Thanks. Signed-off-by: Libra Li <libra.li(a)technexion.com>

2 4

[commit] r4990 - in trunk: src/arch/i386/include/arch src/mainboard/technexion/tim5690 util/x86emu
by svn＠coreboot.org 23 Dec '09

23 Dec '09

Author: mjones Date: 2009-12-23 20:16:47 +0100 (Wed, 23 Dec 2009) New Revision: 4990 Added: trunk/src/arch/i386/include/arch/interrupt.h trunk/src/mainboard/technexion/tim5690/vgabios.c trunk/src/mainboard/technexion/tim5690/vgabios.h Modified: trunk/src/mainboard/technexion/tim5690/Makefile.inc trunk/src/mainboard/technexion/tim5690/cache_as_ram_auto.c trunk/src/mainboard/technexion/tim5690/mainboard.c trunk/util/x86emu/x86.c Log: Add mainboard x86emu interrupt function support. Add tim5690 VGA BIOS functions: int15 getting LCD panel ID. Signed-off-by: Libra Li <libra.li(a)technexion.com> Acked-by: Marc Jones <marcj303(a)gmail.com> Added: trunk/src/arch/i386/include/arch/interrupt.h =================================================================== --- trunk/src/arch/i386/include/arch/interrupt.h (rev 0) +++ trunk/src/arch/i386/include/arch/interrupt.h 2009-12-23 19:16:47 UTC (rev 4990) @@ -0,0 +1,25 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2009 coresystems GmbH + * Copyright (C) 2009 Libra Li <libra.li(a)technexion.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include "registers.h" + +/* setup interrupt handlers for mainboard */ +extern void mainboard_interrupt_handlers(int intXX, void *intXX_func); Modified: trunk/src/mainboard/technexion/tim5690/Makefile.inc =================================================================== --- trunk/src/mainboard/technexion/tim5690/Makefile.inc 2009-12-23 12:52:56 UTC (rev 4989) +++ trunk/src/mainboard/technexion/tim5690/Makefile.inc 2009-12-23 19:16:47 UTC (rev 4990) @@ -33,6 +33,7 @@ obj-y += tn_post_code.o obj-y += speaker.o +obj-y += vgabios.o # This is part of the conversion to init-obj and away from included code. Modified: trunk/src/mainboard/technexion/tim5690/cache_as_ram_auto.c =================================================================== --- trunk/src/mainboard/technexion/tim5690/cache_as_ram_auto.c 2009-12-23 12:52:56 UTC (rev 4989) +++ trunk/src/mainboard/technexion/tim5690/cache_as_ram_auto.c 2009-12-23 19:16:47 UTC (rev 4990) @@ -145,20 +145,6 @@ } #endif /* CONFIG_USE_FALLBACK_IMAGE == 1 */ -/* Early mainboard specific GPIO setup. */ -static void mb_gpio_init(void) -{ - /* Init Super I/O GPIOs. Done early. */ - it8712f_enter_conf(); - outb(IT8712F_CONFIG_REG_LDN, SIO_INDEX); - outb(IT8712F_GPIO, SIO_DATA); - outb(0x62, SIO_INDEX); // set Simple I/O Base Address 0x200 - outb(0x02, SIO_DATA); - outb(0x63, SIO_INDEX); - outb(0x00, SIO_DATA); - it8712f_exit_conf(); -} - void real_main(unsigned long bist, unsigned long cpu_init_detectedx); void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) @@ -191,7 +177,6 @@ /* it8712f_enable_serial does not use its 1st parameter. */ it8712f_enable_serial(0, CONFIG_TTYS0_BASE); - mb_gpio_init(); it8712f_kill_watchdog(); uart_init(); console_init(); Modified: trunk/src/mainboard/technexion/tim5690/mainboard.c =================================================================== --- trunk/src/mainboard/technexion/tim5690/mainboard.c 2009-12-23 12:52:56 UTC (rev 4989) +++ trunk/src/mainboard/technexion/tim5690/mainboard.c 2009-12-23 19:16:47 UTC (rev 4990) @@ -26,13 +26,56 @@ #include <cpu/amd/mtrr.h> #include <device/pci_def.h> #include <../southbridge/amd/sb600/sb600.h> +#include <../superio/ite/it8712f/it8712f.h> #include "chip.h" #include "tn_post_code.h" +#include "vgabios.h" #define ADT7461_ADDRESS 0x4C #define ARA_ADDRESS 0x0C /* Alert Response Address */ #define SMBUS_IO_BASE 0x1000 + +/* Video BIOS Function Extensions Specification + */ +//Callback Sub-Function 00h - Get LCD Panel ID +#define LCD_PANEL_ID_NO 0x00 /* No LCD */ +#define LCD_PANEL_ID_01 0x01 /* 1024x768, 24 bits, 1 channel */ +#define LCD_PANEL_ID_02 0x02 /* 1280x1024, 24 bits, 2 channels */ +#define LCD_PANEL_ID_03 0x03 /* 1440x900, 24 bits, 2 channels */ +#define LCD_PANEL_ID_04 0x04 /* 1680x1050, 24 bits, 2 channels */ +#define LCD_PANEL_ID_05 0x05 /* 1920x1200, 24 bits, 2 channels */ +#define LCD_PANEL_ID_06 0x06 /* 1920x1080, 24 bits, 2 channels */ +//Callback Sub-Function 05h – Select Boot-up TV Standard +#define TV_MODE_00 0x00 /* NTSC */ +#define TV_MODE_01 0x01 /* PAL */ +#define TV_MODE_02 0x02 /* PALM */ +#define TV_MODE_03 0x03 /* PAL60 */ +#define TV_MODE_04 0x04 /* NTSCJ */ +#define TV_MODE_05 0x05 /* PALCN */ +#define TV_MODE_06 0x06 /* PALN */ +#define TV_MODE_09 0x09 /* SCART-RGB */ +#define TV_MODE_NO 0xff /* No TV Support */ + + +/* The base address is 0x2e or 0x4e, depending on config bytes. */ +#define SIO_BASE 0x2e +#define SIO_INDEX SIO_BASE +#define SIO_DATA SIO_BASE+1 + +/* Global configuration registers. */ +#define IT8712F_CONFIG_REG_CC 0x02 /* Configure Control (write-only). */ +#define IT8712F_CONFIG_REG_LDN 0x07 /* Logical Device Number. */ +#define IT8712F_CONFIG_REG_CONFIGSEL 0x22 /* Configuration Select. */ +#define IT8712F_CONFIG_REG_CLOCKSEL 0x23 /* Clock Selection. */ +#define IT8712F_CONFIG_REG_SWSUSP 0x24 /* Software Suspend, Flash I/F. */ +#define IT8712F_CONFIG_REG_MFC 0x2a /* Multi-function control */ +#define IT8712F_CONFIG_REG_WATCHDOG 0x72 /* Watchdog control. */ + +#define IT8712F_CONFIGURATION_PORT 0x2e /* Write-only. */ +#define IT8712F_SIMPLE_IO_BASE 0x200 /* Simple I/O base address */ + + extern int do_smbus_read_byte(u32 smbus_io_base, u32 device, u32 address); extern int do_smbus_write_byte(u32 smbus_io_base, u32 device, u32 address, u8 val); @@ -54,6 +97,36 @@ uint64_t uma_memory_base, uma_memory_size; +/* The content of IT8712F_CONFIG_REG_LDN (index 0x07) must be set to the + LDN the register belongs to, before you can access the register. */ +static void it8712f_sio_write(uint8_t ldn, uint8_t index, uint8_t value) +{ + outb(IT8712F_CONFIG_REG_LDN, SIO_BASE); + outb(ldn, SIO_DATA); + outb(index, SIO_BASE); + outb(value, SIO_DATA); +} + +static void it8712f_enter_conf(void) +{ + /* Enter the configuration state (MB PnP mode). */ + + /* Perform MB PnP setup to put the SIO chip at 0x2e. */ + /* Base address 0x2e: 0x87 0x01 0x55 0x55. */ + /* Base address 0x4e: 0x87 0x01 0x55 0xaa. */ + outb(0x87, IT8712F_CONFIGURATION_PORT); + outb(0x01, IT8712F_CONFIGURATION_PORT); + outb(0x55, IT8712F_CONFIGURATION_PORT); + outb(0x55, IT8712F_CONFIGURATION_PORT); +} + +static void it8712f_exit_conf(void) +{ + /* Exit the configuration state (MB PnP mode). */ + it8712f_sio_write(0x00, IT8712F_CONFIG_REG_CC, 0x02); +} + + /* set thermal config */ static void set_thermal_config(void) @@ -117,6 +190,48 @@ */ } +/* Mainboard specific GPIO setup. */ +void mb_gpio_init(u16 *iobase) +{ + /* Init Super I/O GPIOs. */ + it8712f_enter_conf(); + outb(IT8712F_CONFIG_REG_LDN, SIO_INDEX); + outb(IT8712F_GPIO, SIO_DATA); + outb(0x62, SIO_INDEX); + outb((*iobase >> 8), SIO_DATA); + outb(0x63, SIO_INDEX); + outb((*iobase & 0xff), SIO_DATA); + it8712f_exit_conf(); +} + +/* The LCD's panel id seletion. */ +void lcd_panel_id(rs690_vbios_regs *vbios_regs, u8 num_id) +{ + switch (num_id) { + case 0x1: + vbios_regs->int15_regs.fun00_panel_id = LCD_PANEL_ID_01; + break; + case 0x2: + vbios_regs->int15_regs.fun00_panel_id = LCD_PANEL_ID_02; + break; + case 0x3: + vbios_regs->int15_regs.fun00_panel_id = LCD_PANEL_ID_03; + break; + case 0x4: + vbios_regs->int15_regs.fun00_panel_id = LCD_PANEL_ID_04; + break; + case 0x5: + vbios_regs->int15_regs.fun00_panel_id = LCD_PANEL_ID_05; + break; + case 0x6: + vbios_regs->int15_regs.fun00_panel_id = LCD_PANEL_ID_06; + break; + default: + vbios_regs->int15_regs.fun00_panel_id = LCD_PANEL_ID_NO; + break; + } +} + /************************************************* * enable the dedicated function in tim5690 board. * This function called early than rs690_enable. @@ -126,8 +241,21 @@ struct mainboard_config *mainboard = (struct mainboard_config *)dev->chip_info; + rs690_vbios_regs vbios_regs; + u16 gpio_base = IT8712F_SIMPLE_IO_BASE; + u8 port2; + printk_info("Mainboard tim5690 Enable. dev=0x%p\n", dev); + mb_gpio_init(&gpio_base); + + /* The LCD's panel id seletion by switch. */ + port2 = inb(gpio_base+1); + lcd_panel_id(&vbios_regs, ((~port2) & 0xf)); + /* No support TV */ + vbios_regs.int15_regs.fun05_tv_standard = TV_MODE_NO; + vgabios_init(&vbios_regs); + #if (CONFIG_GFXUMA == 1) msr_t msr, msr2; Added: trunk/src/mainboard/technexion/tim5690/vgabios.c =================================================================== --- trunk/src/mainboard/technexion/tim5690/vgabios.c (rev 0) +++ trunk/src/mainboard/technexion/tim5690/vgabios.c 2009-12-23 19:16:47 UTC (rev 4990) @@ -0,0 +1,77 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2009 coresystems GmbH + * Copyright (C) 2009 Libra Li <libra.li(a)technexion.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <stdint.h> +#include <stdlib.h> +#include <console/console.h> +#include <arch/interrupt.h> +#include "vgabios.h" + + +int tim5690_int15_handler(struct eregs *regs); + +static rs690_vbios_regs vbios_regs_local; + +/* Initialization interrupt function */ +static void vbios_fun_init(rs690_vbios_regs *vbios_regs) +{ + vbios_regs_local.int15_regs.fun00_panel_id = vbios_regs->int15_regs.fun00_panel_id; + vbios_regs_local.int15_regs.fun05_tv_standard = vbios_regs->int15_regs.fun05_tv_standard; +} +/* BIOS int15 function */ +int tim5690_int15_handler(struct eregs *regs) +{ + int res = -1; + + printk(BIOS_DEBUG, "tim5690_int15_handler\n"); + + switch (regs->eax & 0xffff) { + case AMD_RS690_INT15: + switch (regs->ebx & 0xff) { + case 0x00: + regs->eax &= ~(0xff); + regs->ebx = (regs->ebx & ~(0xff)) | vbios_regs_local.int15_regs.fun00_panel_id; + res = 0; + break; + case 0x05: + regs->eax &= ~(0xff); + regs->ebx = (regs->ebx & ~(0xff)) | vbios_regs_local.int15_regs.fun05_tv_standard; + res = 0; + break; + } + break; + default: + printk(BIOS_DEBUG, "Unknown INT15 function %04x!\n", + regs->eax & 0xffff); + break; + } + + return res; +} + +/* Initialization VBIOS function */ +void vgabios_init(rs690_vbios_regs *vbios_regs) +{ + printk(BIOS_DEBUG, "vgabios_init\n"); + + mainboard_interrupt_handlers(0x15, &tim5690_int15_handler); + vbios_fun_init(vbios_regs); +} Added: trunk/src/mainboard/technexion/tim5690/vgabios.h =================================================================== --- trunk/src/mainboard/technexion/tim5690/vgabios.h (rev 0) +++ trunk/src/mainboard/technexion/tim5690/vgabios.h 2009-12-23 19:16:47 UTC (rev 4990) @@ -0,0 +1,37 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2009 coresystems GmbH + * Copyright (C) 2009 Libra Li <libra.li(a)technexion.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* AMD Chipset */ +#define AMD_RS690_INT15 0x4E08 + +typedef struct __rs690_int15_regs__ +{ + u8 fun00_panel_id; // Callback Sub-Function 00h - Get LCD Panel ID + u8 fun05_tv_standard; // Callback Sub-Function 05h - Select Boot-up TV Standard +}rs690_int15_regs; + +typedef struct __rs690_vbios_regs__ +{ + rs690_int15_regs int15_regs; +}rs690_vbios_regs; + +/* Initialization VBIOS function */ +extern void vgabios_init(rs690_vbios_regs *vbios_regs); Modified: trunk/util/x86emu/x86.c =================================================================== --- trunk/util/x86emu/x86.c 2009-12-23 12:52:56 UTC (rev 4989) +++ trunk/util/x86emu/x86.c 2009-12-23 19:16:47 UTC (rev 4990) @@ -29,6 +29,8 @@ #include <console.h> #endif +#include <arch/interrupt.h> + #define REALMODE_BASE ((void *)0x600) struct realmode_idt { @@ -64,6 +66,12 @@ return -1; } +/* setup interrupt handlers for mainboard */ +void mainboard_interrupt_handlers(int intXX, void *intXX_func) +{ + intXX_handler[intXX] = intXX_func; +} + int int12_handler(struct eregs *regs); int int15_handler(struct eregs *regs); int int1a_handler(struct eregs *regs); @@ -80,16 +88,32 @@ /* Mark all other intXX calls as unknown first */ for (i = 0x10; i < 0x100; i++) - intXX_handler[i] = &intXX_unknown_handler; - - /* Now set the default functions that are actually - * needed to initialize the option roms. This is very - * slick, as it allows us to implement mainboard specific - * interrupt handlers, such as the int15 - */ - intXX_handler[0x12] = &int12_handler; - intXX_handler[0x15] = &int15_handler; - intXX_handler[0x1a] = &int1a_handler; + { + /* If the mainboard_interrupt_handler isn't called first. + */ + if(!intXX_handler[i]) + { + /* Now set the default functions that are actually + * needed to initialize the option roms. This is very + * slick, as it allows us to implement mainboard specific + * interrupt handlers, such as the int15 + */ + switch (i) { + case 0x12: + intXX_handler[0x12] = &int12_handler; + break; + case 0x15: + intXX_handler[0x15] = &int15_handler; + break; + case 0x1a: + intXX_handler[0x1a] = &int1a_handler; + break; + default: + intXX_handler[i] = &intXX_unknown_handler; + break; + } + } + } } static void write_idt_stub(void *target, u8 intnum) @@ -127,7 +151,7 @@ { /* clear vga bios data area */ memset((void *)0x400, 0, 0x200); - + /* Set up C interrupt handlers */ setup_interrupt_handlers();

1 0

KBuild Report [r4989]
by coresystems autobuild service 23 Dec '09

23 Dec '09

[1/116] a-trend/atc-6220 ok. Processing mainboard/a-trend/atc-6220 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_INTEL_SLOT_2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 +CONFIG_TINY_BOOTBLOCK = 0x0 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [2/116] a-trend/atc-6240 ok. Processing mainboard/a-trend/atc-6240 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_INTEL_SLOT_2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 +CONFIG_TINY_BOOTBLOCK = 0x0 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [3/116] abit/be6-ii_v2_0 ok. Processing mainboard/abit/be6-ii_v2_0 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_INTEL_SLOT_2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 +CONFIG_TINY_BOOTBLOCK = 0x0 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [4/116] advantech/pcm-5820 ok. Processing mainboard/advantech/pcm-5820 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_GX1 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x0 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 +CONFIG_TINY_BOOTBLOCK = 0x0 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WRITE_HIGH_TABLES = 0x1 +CONFIG_WRITE_HIGH_TABLES = 0x0 [5/116] amd/db800 ok. Processing mainboard/amd/db800 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_LX = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_IRQ_SLOT_COUNT = 0x4 +CONFIG_IRQ_SLOT_COUNT = 0x6 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 +CONFIG_TINY_BOOTBLOCK = 0x0 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [6/116] amd/dbm690t ok. Processing mainboard/amd/dbm690t (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-4989/targets/amd/dbm690t/Config-abuild.lb ok Creating builddir...ok -CONFIG_GFXUMA = 0x1 +CONFIG_GFXUMA = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_ROM_SIZE = 0x100000 +CONFIG_ROM_SIZE = 0x80000 +CONFIG_TINY_BOOTBLOCK = 0x0 [7/116] amd/norwich ok. Processing mainboard/amd/norwich (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_LX = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 +CONFIG_TINY_BOOTBLOCK = 0x0 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [8/116] amd/pistachio ok. Processing mainboard/amd/pistachio (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-4989/targets/amd/pistachio/Config-abuild.lb ok Creating builddir...ok -CONFIG_APIC_ID_OFFSET = 0x0 +CONFIG_APIC_ID_OFFSET = 0x8 -CONFIG_GFXUMA = 0x1 +CONFIG_GFXUMA = 0x0 +CONFIG_HAVE_ACPI_TABLES = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 -CONFIG_HAVE_MAINBOARD_RESOURCES = 0x1 +CONFIG_HAVE_MAINBOARD_RESOURCES = 0x0 +CONFIG_HAVE_MP_TABLE = 0x1 -CONFIG_HAVE_OPTION_TABLE = 0x0 +CONFIG_HAVE_OPTION_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x1 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x6 -CONFIG_HT_CHAIN_UNITID_BASE = 0x0 +CONFIG_HT_CHAIN_UNITID_BASE = 0xa -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_ROM_SIZE = 0x100000 +CONFIG_ROM_SIZE = 0x80000 -CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x1 +CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x2 +CONFIG_TINY_BOOTBLOCK = 0x0 -CONFIG_WAIT_BEFORE_CPUS_INIT = 0x0 +CONFIG_WAIT_BEFORE_CPUS_INIT = 0x1 [9/116] amd/rumba ok. Processing mainboard/amd/rumba (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_GX2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_HAVE_HIGH_TABLES = 0x0 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 +CONFIG_TINY_BOOTBLOCK = 0x0 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WRITE_HIGH_TABLES = 0x1 +CONFIG_WRITE_HIGH_TABLES = 0x0 [10/116] amd/serengeti_cheetah ok. Processing mainboard/amd/serengeti_cheetah (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-4989/targets/amd/serengeti_cheetah/Config-abuild.lb ok Creating builddir...ok -CONFIG_ACPI_SSDTX_NUM = 0x1 +CONFIG_ACPI_SSDTX_NUM = 0x0 +CONFIG_HAVE_ACPI_TABLES = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_TINY_BOOTBLOCK = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [11/116] amd/serengeti_cheetah_fam10 fail. [12/116] arima/hdama ok. Processing mainboard/arima/hdama (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-4989/targets/arima/hdama/Config-abuild.lb ok Creating builddir...ok -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DCACHE_RAM_BASE = 0xcf000 +CONFIG_DCACHE_RAM_BASE = 0xc8000 -CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0 +CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_DCACHE_RAM_SIZE = 0x8000 -CONFIG_DIMM_SUPPORT = 0x108 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0 +CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x0 +CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x1 +CONFIG_TINY_BOOTBLOCK = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [13/116] artecgroup/dbe61 ok. Processing mainboard/artecgroup/dbe61 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_LX = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 +CONFIG_TINY_BOOTBLOCK = 0x0 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [14/116] asi/mb_5blgp ok. Processing mainboard/asi/mb_5blgp (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_GX1 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x0 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 +CONFIG_TINY_BOOTBLOCK = 0x0 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WRITE_HIGH_TABLES = 0x1 +CONFIG_WRITE_HIGH_TABLES = 0x0 [15/116] asi/mb_5blmp ok. Processing mainboard/asi/mb_5blmp (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_GX1 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_GENERATE_MP_TABLE = 0x0 +CONFIG_GX1_VIDEO = 0x1 +CONFIG_GX1_VIDEOMODE = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x0 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 +CONFIG_SPLASH_GRAPHIC = 0x1 +CONFIG_TINY_BOOTBLOCK = 0x0 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WRITE_HIGH_TABLES = 0x1 +CONFIG_WRITE_HIGH_TABLES = 0x0 [16/116] asus/a8n_e ok. Processing mainboard/asus/a8n_e (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-4989/targets/asus/a8n_e/Config-abuild.lb ok Creating builddir...ok -CONFIG_APIC_ID_OFFSET = 0x0 +CONFIG_APIC_ID_OFFSET = 0x10 -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DCACHE_RAM_BASE = 0xc8000 +CONFIG_DCACHE_RAM_BASE = 0xcf000 -CONFIG_DCACHE_RAM_SIZE = 0x8000 +CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DIMM_SUPPORT = 0x108 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x0 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 +CONFIG_TINY_BOOTBLOCK = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [17/116] asus/a8v-e_se ok. Processing mainboard/asus/a8v-e_se (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DIMM_SUPPORT = 0x108 +CONFIG_EPIA_VT8237R_INIT = 0x0 +CONFIG_HAVE_ACPI_TABLES = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_IRQ_SLOT_COUNT = 0xd -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 +CONFIG_TINY_BOOTBLOCK = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [18/116] asus/m2v-mx_se ok. Processing mainboard/asus/m2v-mx_se (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-4989/targets/asus/m2v-mx_se/Config-abuild.lb ok Creating builddir...ok -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_EPIA_VT8237R_INIT = 0x0 -CONFIG_HAVE_ACPI_RESUME = 0x1 +CONFIG_HAVE_ACPI_RESUME = 0x0 +CONFIG_HAVE_ACPI_TABLES = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 -CONFIG_HAVE_LOW_TABLES = 0x0 +CONFIG_HAVE_LOW_TABLES = 0x1 -CONFIG_HAVE_MAINBOARD_RESOURCES = 0x1 +CONFIG_HAVE_MAINBOARD_RESOURCES = 0x0 -CONFIG_HW_MEM_HOLE_SIZEK = 0x0 +CONFIG_HW_MEM_HOLE_SIZEK = 0x100000 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x1f00000 +CONFIG_RAMBASE = 0x100000 -CONFIG_RAMTOP = 0x2000000 +CONFIG_RAMTOP = 0x200000 +CONFIG_TINY_BOOTBLOCK = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [19/116] asus/mew-am ok. Processing mainboard/asus/mew-am (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 +CONFIG_I810_VIDEO_MB_1MB = 0x1 +CONFIG_I810_VIDEO_MB_512KB = 0x0 +CONFIG_I810_VIDEO_MB_OFF = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 +CONFIG_MMX = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 +CONFIG_TINY_BOOTBLOCK = 0x0 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [20/116] asus/mew-vm ok. Processing mainboard/asus/mew-vm (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 -CONFIG_HAVE_OPTION_TABLE = 0x0 +CONFIG_HAVE_OPTION_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 +CONFIG_I810_VIDEO_MB_1MB = 0x1 +CONFIG_I810_VIDEO_MB_512KB = 0x0 +CONFIG_I810_VIDEO_MB_OFF = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 +CONFIG_MMX = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 +CONFIG_TINY_BOOTBLOCK = 0x0 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [21/116] asus/p2b-d ok. Processing mainboard/asus/p2b-d (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_INTEL_SLOT_2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 +CONFIG_TINY_BOOTBLOCK = 0x0 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [22/116] asus/p2b-ds ok. Processing mainboard/asus/p2b-ds (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_AGP_APERTURE_SIZE = 0x4000000 -CONFIG_APIC_ID_OFFSET = 0x0 +CONFIG_APIC_ID_OFFSET = 0x10 -CONFIG_CPU_ADDR_BITS = 0x24 +CONFIG_CPU_ADDR_BITS = 0x28 -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DCACHE_RAM_BASE = 0xc0000 +CONFIG_DCACHE_RAM_BASE = 0xcf000 -CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0 +CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 -CONFIG_DIMM_SUPPORT = 0x108 -CONFIG_HAVE_HARD_RESET = 0x0 +CONFIG_HAVE_HARD_RESET = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 -CONFIG_HAVE_MOVNTI = 0x0 +CONFIG_HAVE_MOVNTI = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 -CONFIG_HAVE_OPTION_TABLE = 0x0 +CONFIG_HAVE_OPTION_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x0 -CONFIG_HT_CHAIN_UNITID_BASE = 0x1 +CONFIG_HT_CHAIN_UNITID_BASE = 0x0 -CONFIG_HW_MEM_HOLE_SIZEK = 0x0 +CONFIG_HW_MEM_HOLE_SIZEK = 0x100000 -CONFIG_ID_SECTION_OFFSET = 0x10 +CONFIG_ID_SECTION_OFFSET = 0x80 -CONFIG_IRQ_SLOT_COUNT = 0x7 +CONFIG_IRQ_SLOT_COUNT = 0xd -CONFIG_LB_CKS_LOC = 0x7e +CONFIG_LB_CKS_LOC = 0x7b -CONFIG_LB_CKS_RANGE_END = 0x7d +CONFIG_LB_CKS_RANGE_END = 0x7a -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID = 0x0 +CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID = 0x815a -CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x0 +CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1043 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_MEM_TRAIN_SEQ = 0x0 +CONFIG_MEM_TRAIN_SEQ = 0x2 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_ROM_SIZE = 0x40000 +CONFIG_ROM_SIZE = 0x80000 -CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x0 +CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x2 -CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x1 +CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0 +CONFIG_TINY_BOOTBLOCK = 0x0 -CONFIG_UDELAY_TSC = 0x1 +CONFIG_UDELAY_TSC = 0x0 -CONFIG_USE_DCACHE_RAM = 0x0 +CONFIG_USE_DCACHE_RAM = 0x1 -CONFIG_USE_PRINTK_IN_CAR = 0x0 +CONFIG_USE_PRINTK_IN_CAR = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [23/116] asus/p2b-f ok. Processing mainboard/asus/p2b-f (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_INTEL_SLOT_2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 +CONFIG_TINY_BOOTBLOCK = 0x0 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [24/116] asus/p2b ok. Processing mainboard/asus/p2b (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_INTEL_SLOT_2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 +CONFIG_TINY_BOOTBLOCK = 0x0 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [25/116] asus/p3b-f ok. Processing mainboard/asus/p3b-f (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_INTEL_SLOT_2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 +CONFIG_TINY_BOOTBLOCK = 0x0 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [26/116] axus/tc320 ok. Processing mainboard/axus/tc320 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_GX1 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x6 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x0 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x6 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 +CONFIG_TINY_BOOTBLOCK = 0x0 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WRITE_HIGH_TABLES = 0x1 +CONFIG_WRITE_HIGH_TABLES = 0x0 [27/116] azza/pt-6ibd ok. Processing mainboard/azza/pt-6ibd (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_INTEL_SLOT_2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 +CONFIG_TINY_BOOTBLOCK = 0x0 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [28/116] bcom/winnet100 ok. Processing mainboard/bcom/winnet100 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_GX1 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x6 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x0 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x6 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 +CONFIG_TINY_BOOTBLOCK = 0x0 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WRITE_HIGH_TABLES = 0x1 +CONFIG_WRITE_HIGH_TABLES = 0x0 [29/116] bcom/winnetp680 ok. Processing mainboard/bcom/winnetp680 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-4989/targets/bcom/winnetp680/Config-abuild.lb ok Creating builddir...ok +CONFIG_CN700_VIDEO_MB_128MB = 0x0 +CONFIG_CN700_VIDEO_MB_16MB = 0x0 +CONFIG_CN700_VIDEO_MB_32MB = 0x1 +CONFIG_CN700_VIDEO_MB_64MB = 0x0 +CONFIG_CN700_VIDEO_MB_8MB = 0x0 +CONFIG_CN700_VIDEO_MB_OFF = 0x0 +CONFIG_CPU_VIA_C7 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x7 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_EPIA_VT8237R_INIT = 0x0 +CONFIG_FALLBACK_SIZE = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_TINY_BOOTBLOCK = 0x0 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 [30/116] biostar/m6tba ok. Processing mainboard/biostar/m6tba (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_INTEL_SLOT_2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 +CONFIG_TINY_BOOTBLOCK = 0x0 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [31/116] broadcom/blast ok. Processing mainboard/broadcom/blast (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_APIC_ID_OFFSET = 0x0 +CONFIG_APIC_ID_OFFSET = 0x10 -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DIMM_SUPPORT = 0x108 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x1 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x0 -CONFIG_HT_CHAIN_UNITID_BASE = 0x6 +CONFIG_HT_CHAIN_UNITID_BASE = 0x0 -CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0 +CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x1 +CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x2 -CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x1 +CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0 +CONFIG_TINY_BOOTBLOCK = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [32/116] compaq/deskpro_en_sff_p600 ok. Processing mainboard/compaq/deskpro_en_sff_p600 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_INTEL_SLOT_2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 +CONFIG_TINY_BOOTBLOCK = 0x0 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [33/116] dell/s1850 ok. Processing mainboard/dell/s1850 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_HAVE_HARD_RESET = 0x1 +CONFIG_HAVE_HARD_RESET = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 -CONFIG_HAVE_MOVNTI = 0x1 +CONFIG_HAVE_MOVNTI = 0x0 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_IOAPIC = 0x1 +CONFIG_IOAPIC = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAX_CPUS = 0x4 +CONFIG_MAX_CPUS = 0x2 -CONFIG_MAX_PHYSICAL_CPUS = 0x1 +CONFIG_MAX_PHYSICAL_CPUS = 0x2 +CONFIG_MMX = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 +CONFIG_SSE = 0x1 +CONFIG_TINY_BOOTBLOCK = 0x0 -CONFIG_TTYS0_BAUD = 0x4b00 +CONFIG_TTYS0_BAUD = 0x1c200 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [34/116] digitallogic/adl855pc ok. Processing mainboard/digitallogic/adl855pc (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HARD_RESET = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 +CONFIG_MMX = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_SMP = 0x0 +CONFIG_SMP = 0x1 +CONFIG_SSE = 0x1 +CONFIG_TINY_BOOTBLOCK = 0x0 -CONFIG_UDELAY_IO = 0x1 +CONFIG_UDELAY_IO = 0x0 -CONFIG_UDELAY_TSC = 0x0 +CONFIG_UDELAY_TSC = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [35/116] digitallogic/msm586seg ok. Processing mainboard/digitallogic/msm586seg (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-4989/targets/digitallogic/msm586seg/Config-abuild.lb ok Creating builddir...ok +CONFIG_CPU_AMD_SC520 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x0 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_ROM_SIZE = 0x80000 +CONFIG_ROM_SIZE = 0x40000 +CONFIG_TINY_BOOTBLOCK = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_UDELAY_LAPIC = 0x0 +CONFIG_UDELAY_TSC = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [36/116] digitallogic/msm800sev ok. Processing mainboard/digitallogic/msm800sev (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_LX = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_IRQ_SLOT_COUNT = 0x9 +CONFIG_IRQ_SLOT_COUNT = 0x7 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 +CONFIG_TINY_BOOTBLOCK = 0x0 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [37/116] eaglelion/5bcm ok. Processing mainboard/eaglelion/5bcm (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_GX1 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_GX1_VIDEO = 0x1 +CONFIG_GX1_VIDEOMODE = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x0 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 +CONFIG_SPLASH_GRAPHIC = 0x1 +CONFIG_TINY_BOOTBLOCK = 0x0 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WRITE_HIGH_TABLES = 0x1 +CONFIG_WRITE_HIGH_TABLES = 0x0 [38/116] emulation/qemu-x86 ok. Processing mainboard/emulation/qemu-x86 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-4989/targets/emulation/qemu-x86/Config-abuild.lb ok Creating builddir...ok +CONFIG_CPU_EMULATION_QEMU_X86 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0x8f000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_HAVE_HIGH_TABLES = 0x0 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 +CONFIG_TINY_BOOTBLOCK = 0x1 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_UDELAY_LAPIC = 0x0 +CONFIG_UDELAY_TSC = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WRITE_HIGH_TABLES = 0x1 +CONFIG_WRITE_HIGH_TABLES = 0x0 [39/116] gigabyte/ga-6bxc ok. Processing mainboard/gigabyte/ga-6bxc (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_INTEL_SLOT_2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_IRQ_SLOT_COUNT = 0x6 +CONFIG_IRQ_SLOT_COUNT = 0x5 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 +CONFIG_TINY_BOOTBLOCK = 0x0 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [40/116] gigabyte/ga_2761gxdk ok. Processing mainboard/gigabyte/ga_2761gxdk (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-4989/targets/gigabyte/ga_2761gxdk/Config-abuild.lb ok Creating builddir...ok -CONFIG_APIC_ID_OFFSET = 0x10 +CONFIG_APIC_ID_OFFSET = 0x16 -CONFIG_HAVE_FALLBACK_BOOT = 0x1 +CONFIG_HAVE_FALLBACK_BOOT = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x0 -CONFIG_MEM_TRAIN_SEQ = 0x2 +CONFIG_MEM_TRAIN_SEQ = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0 +CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x1 -CONFIG_SERIAL_CPU_INIT = 0x1 +CONFIG_SERIAL_CPU_INIT = 0x0 -CONFIG_SMP = 0x0 +CONFIG_SMP = 0x1 +CONFIG_TINY_BOOTBLOCK = 0x0 -CONFIG_USE_FALLBACK_IMAGE = 0x1 +CONFIG_USE_FALLBACK_IMAGE = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [41/116] gigabyte/m57sli ok. Processing mainboard/gigabyte/m57sli (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-4989/targets/gigabyte/m57sli/Config-abuild.lb ok Creating builddir...ok -CONFIG_APIC_ID_OFFSET = 0x10 +CONFIG_APIC_ID_OFFSET = 0x16 +CONFIG_HAVE_ACPI_TABLES = 0x1 -CONFIG_HAVE_FALLBACK_BOOT = 0x1 +CONFIG_HAVE_FALLBACK_BOOT = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x0 -CONFIG_MEM_TRAIN_SEQ = 0x2 +CONFIG_MEM_TRAIN_SEQ = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0 +CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x1 -CONFIG_SERIAL_CPU_INIT = 0x1 +CONFIG_SERIAL_CPU_INIT = 0x0 -CONFIG_SUPERIO_ITE_IT8716F_OVERRIDE_FANCTL = 0x1 +CONFIG_TINY_BOOTBLOCK = 0x0 -CONFIG_USE_FALLBACK_IMAGE = 0x1 +CONFIG_USE_FALLBACK_IMAGE = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [42/116] hp/dl145_g3 ok. Processing mainboard/hp/dl145_g3 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_APIC_ID_OFFSET = 0x8 +CONFIG_APIC_ID_OFFSET = 0x10 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x1 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x0 -CONFIG_HT_CHAIN_UNITID_BASE = 0x6 +CONFIG_HT_CHAIN_UNITID_BASE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x1 +CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0 -CONFIG_SERIAL_CPU_INIT = 0x0 +CONFIG_SERIAL_CPU_INIT = 0x1 +CONFIG_TINY_BOOTBLOCK = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [43/116] hp/e_vectra_p2706t ok. Processing mainboard/hp/e_vectra_p2706t (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 +CONFIG_I810_VIDEO_MB_1MB = 0x1 +CONFIG_I810_VIDEO_MB_512KB = 0x0 +CONFIG_I810_VIDEO_MB_OFF = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 +CONFIG_MMX = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 +CONFIG_TINY_BOOTBLOCK = 0x0 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 [44/116] ibm/e325 ok. Processing mainboard/ibm/e325 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_APIC_ID_OFFSET = 0x0 +CONFIG_APIC_ID_OFFSET = 0x8 -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DIMM_SUPPORT = 0x108 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x6 -CONFIG_HT_CHAIN_UNITID_BASE = 0x1 +CONFIG_HT_CHAIN_UNITID_BASE = 0xa -CONFIG_HW_MEM_HOLE_SIZEK = 0x0 +CONFIG_HW_MEM_HOLE_SIZEK = 0x100000 -CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0 +CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x0 +CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x2 -CONFIG_SERIAL_CPU_INIT = 0x1 +CONFIG_SERIAL_CPU_INIT = 0x0 -CONFIG_SMP = 0x1 +CONFIG_SMP = 0x0 +CONFIG_TINY_BOOTBLOCK = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WAIT_BEFORE_CPUS_INIT = 0x0 +CONFIG_WAIT_BEFORE_CPUS_INIT = 0x1 [45/116] ibm/e326 ok. Processing mainboard/ibm/e326 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-4989/targets/ibm/e326/Config-abuild.lb ok Creating builddir...ok -CONFIG_APIC_ID_OFFSET = 0x0 +CONFIG_APIC_ID_OFFSET = 0x8 -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DIMM_SUPPORT = 0x108 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x6 -CONFIG_HT_CHAIN_UNITID_BASE = 0x1 +CONFIG_HT_CHAIN_UNITID_BASE = 0xa -CONFIG_HW_MEM_HOLE_SIZEK = 0x0 +CONFIG_HW_MEM_HOLE_SIZEK = 0x100000 -CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0 +CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x0 +CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x2 -CONFIG_SERIAL_CPU_INIT = 0x1 +CONFIG_SERIAL_CPU_INIT = 0x0 +CONFIG_TINY_BOOTBLOCK = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WAIT_BEFORE_CPUS_INIT = 0x0 +CONFIG_WAIT_BEFORE_CPUS_INIT = 0x1 [46/116] iei/juki-511p ok. Processing mainboard/iei/juki-511p (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-4989/targets/iei/juki-511p/Config-abuild.lb ok Creating builddir...ok +CONFIG_CPU_AMD_GX1 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_GX1_VIDEO = 0x1 +CONFIG_GX1_VIDEOMODE = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x0 -CONFIG_HAVE_INIT_TIMER = 0x0 +CONFIG_HAVE_INIT_TIMER = 0x1 -CONFIG_HAVE_OPTION_TABLE = 0x0 +CONFIG_HAVE_OPTION_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 +CONFIG_SPLASH_GRAPHIC = 0x1 +CONFIG_TINY_BOOTBLOCK = 0x0 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_UDELAY_IO = 0x1 +CONFIG_UDELAY_IO = 0x0 -CONFIG_UDELAY_TSC = 0x0 +CONFIG_UDELAY_TSC = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WRITE_HIGH_TABLES = 0x1 +CONFIG_WRITE_HIGH_TABLES = 0x0 [47/116] iei/nova4899r ok. Processing mainboard/iei/nova4899r (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_GX1 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_GX1_VIDEO = 0x1 +CONFIG_GX1_VIDEOMODE = 0x0 -CONFIG_HAVE_FALLBACK_BOOT = 0x0 +CONFIG_HAVE_FALLBACK_BOOT = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x0 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 +CONFIG_SPLASH_GRAPHIC = 0x1 +CONFIG_TINY_BOOTBLOCK = 0x0 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WRITE_HIGH_TABLES = 0x1 +CONFIG_WRITE_HIGH_TABLES = 0x0 [48/116] iei/pcisa-lx-800-r10 ok. Processing mainboard/iei/pcisa-lx-800-r10 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_LX = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 -CONFIG_HAVE_INIT_TIMER = 0x0 +CONFIG_HAVE_INIT_TIMER = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 +CONFIG_TINY_BOOTBLOCK = 0x0 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_UDELAY_IO = 0x1 +CONFIG_UDELAY_IO = 0x0 -CONFIG_UDELAY_TSC = 0x0 +CONFIG_UDELAY_TSC = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [49/116] intel/d945gclf ok. Processing mainboard/intel/d945gclf (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-4989/targets/intel/d945gclf/Config-abuild.lb ok Creating builddir...ok +CONFIG_CPU_INTEL_CORE = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xffed8000 +CONFIG_DCACHE_RAM_BASE = 0xffdf8000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x5 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 -CONFIG_GENERATE_ACPI_TABLES = 0x1 +CONFIG_GENERATE_ACPI_TABLES = 0x0 -CONFIG_GFXUMA = 0x1 +CONFIG_GFXUMA = 0x0 -CONFIG_HAVE_ACPI_RESUME = 0x1 +CONFIG_HAVE_ACPI_RESUME = 0x0 -CONFIG_HAVE_HARD_RESET = 0x1 +CONFIG_HAVE_HARD_RESET = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 -CONFIG_HAVE_INIT_TIMER = 0x1 +CONFIG_HAVE_INIT_TIMER = 0x0 -CONFIG_HAVE_MAINBOARD_RESOURCES = 0x1 +CONFIG_HAVE_MAINBOARD_RESOURCES = 0x0 -CONFIG_HAVE_MOVNTI = 0x1 +CONFIG_HAVE_MOVNTI = 0x0 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HAVE_SMI_HANDLER = 0x1 +CONFIG_HAVE_SMI_HANDLER = 0x0 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_IOAPIC = 0x1 +CONFIG_IOAPIC = 0x0 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_MAX_CPUS = 0x4 +CONFIG_MAX_CPUS = 0x1 +CONFIG_MMX = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_ROM_SIZE = 0x80000 +CONFIG_ROM_SIZE = 0x100000 +CONFIG_SSE = 0x1 +CONFIG_TINY_BOOTBLOCK = 0x0 -CONFIG_USE_DCACHE_RAM = 0x1 +CONFIG_USE_DCACHE_RAM = 0x0 [50/116] intel/eagleheights ok. Processing mainboard/intel/eagleheights (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_INTEL_CORE2 = 0x1 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x7 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_ACPI_TABLES = 0x1 -CONFIG_HAVE_HARD_RESET = 0x1 +CONFIG_HAVE_HARD_RESET = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 -CONFIG_HAVE_MAINBOARD_RESOURCES = 0x1 +CONFIG_HAVE_MAINBOARD_RESOURCES = 0x0 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_IOAPIC = 0x1 +CONFIG_IOAPIC = 0x0 -CONFIG_IRQ_SLOT_COUNT = 0x9 +CONFIG_IRQ_SLOT_COUNT = 0x12 -CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x0 +CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x8086 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_MAX_CPUS = 0x4 +CONFIG_MAX_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 +CONFIG_TINY_BOOTBLOCK = 0x0 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_USE_DCACHE_RAM = 0x1 +CONFIG_USE_DCACHE_RAM = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [51/116] intel/jarrell ok. Processing mainboard/intel/jarrell (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_ATI_RAGE_XL = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_HAVE_HARD_RESET = 0x1 +CONFIG_HAVE_HARD_RESET = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 -CONFIG_HAVE_MOVNTI = 0x1 +CONFIG_HAVE_MOVNTI = 0x0 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_IOAPIC = 0x1 +CONFIG_IOAPIC = 0x0 -CONFIG_IRQ_SLOT_COUNT = 0x12 +CONFIG_IRQ_SLOT_COUNT = 0x9 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAX_REBOOT_CNT = 0x8 +CONFIG_MAX_REBOOT_CNT = 0x3 +CONFIG_MMX = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 +CONFIG_SSE = 0x1 +CONFIG_TINY_BOOTBLOCK = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [52/116] intel/mtarvon ok. Processing mainboard/intel/mtarvon (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x5 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 -CONFIG_HAVE_HARD_RESET = 0x1 +CONFIG_HAVE_HARD_RESET = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_IOAPIC = 0x1 +CONFIG_IOAPIC = 0x0 -CONFIG_LB_CKS_LOC = 0x7e +CONFIG_LB_CKS_LOC = 0x7b -CONFIG_LB_CKS_RANGE_END = 0x7d +CONFIG_LB_CKS_RANGE_END = 0x7a -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x5 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_MAX_CPUS = 0x4 +CONFIG_MAX_CPUS = 0x1 +CONFIG_MMX = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 +CONFIG_SSE = 0x1 +CONFIG_TINY_BOOTBLOCK = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [53/116] intel/truxton ok. Processing mainboard/intel/truxton (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_INTEL_EP80579 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x5 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 -CONFIG_HAVE_HARD_RESET = 0x1 +CONFIG_HAVE_HARD_RESET = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_IOAPIC = 0x1 +CONFIG_IOAPIC = 0x0 -CONFIG_LB_CKS_LOC = 0x7e +CONFIG_LB_CKS_LOC = 0x7b -CONFIG_LB_CKS_RANGE_END = 0x7d +CONFIG_LB_CKS_RANGE_END = 0x7a -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x5 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_MAX_CPUS = 0x4 +CONFIG_MAX_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_SMP = 0x1 +CONFIG_SMP = 0x0 +CONFIG_TINY_BOOTBLOCK = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [54/116] intel/xe7501devkit ok. Processing mainboard/intel/xe7501devkit (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEBUG = 0x1 +CONFIG_DEBUG = 0x0 +CONFIG_HAVE_ACPI_TABLES = 0x1 -CONFIG_HAVE_HARD_RESET = 0x1 +CONFIG_HAVE_HARD_RESET = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 -CONFIG_HAVE_MOVNTI = 0x1 +CONFIG_HAVE_MOVNTI = 0x0 +CONFIG_HAVE_MP_TABLE = 0x1 -CONFIG_HAVE_OPTION_TABLE = 0x0 +CONFIG_HAVE_OPTION_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_IOAPIC = 0x1 +CONFIG_IOAPIC = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_MMX = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 +CONFIG_SSE = 0x1 +CONFIG_TINY_BOOTBLOCK = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [55/116] iwill/dk8_htx ok. Processing mainboard/iwill/dk8_htx (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-4989/targets/iwill/dk8_htx/Config-abuild.lb ok Creating builddir...ok -CONFIG_ACPI_SSDTX_NUM = 0x3 +CONFIG_ACPI_SSDTX_NUM = 0x0 -CONFIG_APIC_ID_OFFSET = 0x10 +CONFIG_APIC_ID_OFFSET = 0x8 -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DCACHE_RAM_BASE = 0xc4000 +CONFIG_DCACHE_RAM_BASE = 0xc8000 -CONFIG_DCACHE_RAM_SIZE = 0xc000 +CONFIG_DCACHE_RAM_SIZE = 0x8000 -CONFIG_DIMM_SUPPORT = 0x108 +CONFIG_HAVE_ACPI_TABLES = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HW_MEM_HOLE_SIZEK = 0x80000 +CONFIG_HW_MEM_HOLE_SIZEK = 0x100000 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_TINY_BOOTBLOCK = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WAIT_BEFORE_CPUS_INIT = 0x0 +CONFIG_WAIT_BEFORE_CPUS_INIT = 0x1 [56/116] iwill/dk8s2 ok. Processing mainboard/iwill/dk8s2 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_APIC_ID_OFFSET = 0x0 +CONFIG_APIC_ID_OFFSET = 0x8 +CONFIG_ATI_RAGE_XL = 0x1 -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DCACHE_RAM_BASE = 0xcf000 +CONFIG_DCACHE_RAM_BASE = 0xc8000 -CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0 +CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_DCACHE_RAM_SIZE = 0x8000 -CONFIG_DIMM_SUPPORT = 0x108 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x6 -CONFIG_HT_CHAIN_UNITID_BASE = 0x1 +CONFIG_HT_CHAIN_UNITID_BASE = 0xa -CONFIG_HW_MEM_HOLE_SIZEK = 0x0 +CONFIG_HW_MEM_HOLE_SIZEK = 0x100000 -CONFIG_IRQ_SLOT_COUNT = 0xc +CONFIG_IRQ_SLOT_COUNT = 0xb -CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0 +CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAX_CPUS = 0x2 +CONFIG_MAX_CPUS = 0x4 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x0 +CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x2 -CONFIG_SERIAL_CPU_INIT = 0x1 +CONFIG_SERIAL_CPU_INIT = 0x0 +CONFIG_TINY_BOOTBLOCK = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WAIT_BEFORE_CPUS_INIT = 0x0 +CONFIG_WAIT_BEFORE_CPUS_INIT = 0x1 [57/116] iwill/dk8x ok. Processing mainboard/iwill/dk8x (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_APIC_ID_OFFSET = 0x0 +CONFIG_APIC_ID_OFFSET = 0x8 -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DCACHE_RAM_BASE = 0xcf000 +CONFIG_DCACHE_RAM_BASE = 0xc8000 -CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0 +CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_DCACHE_RAM_SIZE = 0x8000 -CONFIG_DIMM_SUPPORT = 0x108 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x6 -CONFIG_HT_CHAIN_UNITID_BASE = 0x1 +CONFIG_HT_CHAIN_UNITID_BASE = 0xa -CONFIG_HW_MEM_HOLE_SIZEK = 0x0 +CONFIG_HW_MEM_HOLE_SIZEK = 0x100000 -CONFIG_IRQ_SLOT_COUNT = 0x9 +CONFIG_IRQ_SLOT_COUNT = 0xb -CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0 +CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAX_CPUS = 0x2 +CONFIG_MAX_CPUS = 0x4 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x0 +CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x2 -CONFIG_SERIAL_CPU_INIT = 0x1 +CONFIG_SERIAL_CPU_INIT = 0x0 +CONFIG_TINY_BOOTBLOCK = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WAIT_BEFORE_CPUS_INIT = 0x0 +CONFIG_WAIT_BEFORE_CPUS_INIT = 0x1 [58/116] jetway/j7f24 ok. Processing mainboard/jetway/j7f24 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-4989/targets/jetway/j7f24/Config-abuild.lb ok Creating builddir...ok +CONFIG_CN700_VIDEO_MB_128MB = 0x0 +CONFIG_CN700_VIDEO_MB_16MB = 0x0 +CONFIG_CN700_VIDEO_MB_32MB = 0x1 +CONFIG_CN700_VIDEO_MB_64MB = 0x0 +CONFIG_CN700_VIDEO_MB_8MB = 0x0 +CONFIG_CN700_VIDEO_MB_OFF = 0x0 +CONFIG_CPU_VIA_C7 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x7 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_EPIA_VT8237R_INIT = 0x0 +CONFIG_FALLBACK_SIZE = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 -CONFIG_HAVE_OPTION_TABLE = 0x0 +CONFIG_HAVE_OPTION_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_TINY_BOOTBLOCK = 0x0 -CONFIG_UDELAY_TSC = 0x1 +CONFIG_UDELAY_TSC = 0x0 [59/116] kontron/986lcd-m ok. Processing mainboard/kontron/986lcd-m (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-4989/targets/kontron/986lcd-m/Config-abuild.lb ok Creating builddir...ok +CONFIG_CPU_INTEL_CORE = 0x1 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x5 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_ACPI_SLIC = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_MAX_CPUS = 0x4 +CONFIG_MAX_CPUS = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 +CONFIG_TINY_BOOTBLOCK = 0x0 [60/116] kontron/kt690 ok. Processing mainboard/kontron/kt690 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-4989/targets/kontron/kt690/Config-abuild.lb ok Creating builddir...ok +CONFIG_HAVE_ACPI_TABLES = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_ROM_SIZE = 0x100000 +CONFIG_ROM_SIZE = 0x80000 +CONFIG_TINY_BOOTBLOCK = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [61/116] lippert/frontrunner ok. Processing mainboard/lippert/frontrunner (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_GX2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_HAVE_HIGH_TABLES = 0x0 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 +CONFIG_TINY_BOOTBLOCK = 0x0 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WRITE_HIGH_TABLES = 0x1 +CONFIG_WRITE_HIGH_TABLES = 0x0 [62/116] lippert/roadrunner-lx ok. Processing mainboard/lippert/roadrunner-lx (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_LX = 0x1 -CONFIG_DEBUG = 0x1 +CONFIG_DEBUG = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 +CONFIG_TINY_BOOTBLOCK = 0x0 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [63/116] lippert/spacerunner-lx ok. Processing mainboard/lippert/spacerunner-lx (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_LX = 0x1 -CONFIG_DEBUG = 0x1 +CONFIG_DEBUG = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 +CONFIG_TINY_BOOTBLOCK = 0x0 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [64/116] mitac/6513wu ok. Processing mainboard/mitac/6513wu (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x7 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 +CONFIG_I810_VIDEO_MB_1MB = 0x1 +CONFIG_I810_VIDEO_MB_512KB = 0x0 +CONFIG_I810_VIDEO_MB_OFF = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 +CONFIG_MMX = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 +CONFIG_TINY_BOOTBLOCK = 0x0 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [65/116] msi/ms6119 ok. Processing mainboard/msi/ms6119 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_INTEL_SLOT_2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x0 +CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1462 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 +CONFIG_TINY_BOOTBLOCK = 0x0 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [66/116] msi/ms6147 ok. Processing mainboard/msi/ms6147 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_INTEL_SLOT_2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x0 +CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1462 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 +CONFIG_TINY_BOOTBLOCK = 0x0 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [67/116] msi/ms6156 ok. Processing mainboard/msi/ms6156 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_INTEL_SLOT_2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x0 +CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1462 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 +CONFIG_TINY_BOOTBLOCK = 0x0 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [68/116] msi/ms6178 ok. Processing mainboard/msi/ms6178 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 +CONFIG_I810_VIDEO_MB_1MB = 0x1 +CONFIG_I810_VIDEO_MB_512KB = 0x0 +CONFIG_I810_VIDEO_MB_OFF = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x0 +CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1462 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 +CONFIG_MMX = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 +CONFIG_TINY_BOOTBLOCK = 0x0 -CONFIG_UDELAY_IO = 0x0 +CONFIG_UDELAY_IO = 0x1 -CONFIG_UDELAY_TSC = 0x1 +CONFIG_UDELAY_TSC = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [69/116] msi/ms7135 ok. Processing mainboard/msi/ms7135 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-4989/targets/msi/ms7135/Config-abuild.lb ok Creating builddir...ok -CONFIG_APIC_ID_OFFSET = 0x0 +CONFIG_APIC_ID_OFFSET = 0x10 -CONFIG_DCACHE_RAM_BASE = 0xc8000 +CONFIG_DCACHE_RAM_BASE = 0xcf000 -CONFIG_DCACHE_RAM_SIZE = 0x8000 +CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DIMM_SUPPORT = 0x108 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_MEM_TRAIN_SEQ = 0x2 +CONFIG_MEM_TRAIN_SEQ = 0x0 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 +CONFIG_TINY_BOOTBLOCK = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [70/116] msi/ms7260 ok. Processing mainboard/msi/ms7260 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-4989/targets/msi/ms7260/Config-abuild.lb ok Creating builddir...ok -CONFIG_APIC_ID_OFFSET = 0x10 +CONFIG_APIC_ID_OFFSET = 0x16 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 -CONFIG_HAVE_FALLBACK_BOOT = 0x1 +CONFIG_HAVE_FALLBACK_BOOT = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x0 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_MEM_TRAIN_SEQ = 0x2 +CONFIG_MEM_TRAIN_SEQ = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0 +CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x1 -CONFIG_SERIAL_CPU_INIT = 0x1 +CONFIG_SERIAL_CPU_INIT = 0x0 +CONFIG_TINY_BOOTBLOCK = 0x0 -CONFIG_USE_FALLBACK_IMAGE = 0x1 +CONFIG_USE_FALLBACK_IMAGE = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [71/116] msi/ms9185 ok. Processing mainboard/msi/ms9185 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-4989/targets/msi/ms9185/Config-abuild.lb ok Creating builddir...ok -CONFIG_APIC_ID_OFFSET = 0x8 +CONFIG_APIC_ID_OFFSET = 0x10 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x1 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x0 -CONFIG_HT_CHAIN_UNITID_BASE = 0x6 +CONFIG_HT_CHAIN_UNITID_BASE = 0x0 -CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1022 +CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1462 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x1 +CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0 -CONFIG_SERIAL_CPU_INIT = 0x0 +CONFIG_SERIAL_CPU_INIT = 0x1 +CONFIG_TINY_BOOTBLOCK = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [72/116] msi/ms9282 ok. Processing mainboard/msi/ms9282 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-4989/targets/msi/ms9282/Config-abuild.lb ok Creating builddir...ok -CONFIG_APIC_ID_OFFSET = 0x10 +CONFIG_APIC_ID_OFFSET = 0x16 -CONFIG_ENABLE_APIC_EXT_ID = 0x1 +CONFIG_ENABLE_APIC_EXT_ID = 0x0 -CONFIG_HAVE_FALLBACK_BOOT = 0x1 +CONFIG_HAVE_FALLBACK_BOOT = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x0 -CONFIG_HW_MEM_HOLE_SIZEK = 0x0 +CONFIG_HW_MEM_HOLE_SIZEK = 0x100000 -CONFIG_MAX_CPUS = 0x4 +CONFIG_MAX_CPUS = 0x2 -CONFIG_MAX_PHYSICAL_CPUS = 0x2 +CONFIG_MAX_PHYSICAL_CPUS = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x1 +CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x2 -CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0 +CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x1 -CONFIG_SERIAL_CPU_INIT = 0x1 +CONFIG_SERIAL_CPU_INIT = 0x0 +CONFIG_TINY_BOOTBLOCK = 0x0 -CONFIG_USE_FALLBACK_IMAGE = 0x1 +CONFIG_USE_FALLBACK_IMAGE = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [73/116] nec/powermate2000 ok. Processing mainboard/nec/powermate2000 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 +CONFIG_I810_VIDEO_MB_1MB = 0x1 +CONFIG_I810_VIDEO_MB_512KB = 0x0 +CONFIG_I810_VIDEO_MB_OFF = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 +CONFIG_MMX = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 +CONFIG_TINY_BOOTBLOCK = 0x0 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [74/116] newisys/khepri ok. Processing mainboard/newisys/khepri (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_APIC_ID_OFFSET = 0x0 +CONFIG_APIC_ID_OFFSET = 0x10 -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0 +CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000 -CONFIG_DIMM_SUPPORT = 0x108 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x0 -CONFIG_HT_CHAIN_UNITID_BASE = 0x1 +CONFIG_HT_CHAIN_UNITID_BASE = 0x0 -CONFIG_IRQ_SLOT_COUNT = 0x9 +CONFIG_IRQ_SLOT_COUNT = 0xb -CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0 +CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x0 +CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x2 -CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x1 +CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0 +CONFIG_TINY_BOOTBLOCK = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [75/116] nvidia/l1_2pvv ok. Processing mainboard/nvidia/l1_2pvv (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-4989/targets/nvidia/l1_2pvv/Config-abuild.lb ok Creating builddir...ok -CONFIG_APIC_ID_OFFSET = 0x10 +CONFIG_APIC_ID_OFFSET = 0x16 -CONFIG_HAVE_FALLBACK_BOOT = 0x1 +CONFIG_HAVE_FALLBACK_BOOT = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x0 -CONFIG_MAX_CPUS = 0x4 +CONFIG_MAX_CPUS = 0x2 -CONFIG_MAX_PHYSICAL_CPUS = 0x2 +CONFIG_MAX_PHYSICAL_CPUS = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0 +CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x1 -CONFIG_SERIAL_CPU_INIT = 0x1 +CONFIG_SERIAL_CPU_INIT = 0x0 +CONFIG_TINY_BOOTBLOCK = 0x0 -CONFIG_USE_FALLBACK_IMAGE = 0x1 +CONFIG_USE_FALLBACK_IMAGE = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WAIT_BEFORE_CPUS_INIT = 0x1 +CONFIG_WAIT_BEFORE_CPUS_INIT = 0x0 [76/116] olpc/btest ok. Processing mainboard/olpc/btest (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_GX2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_HAVE_HIGH_TABLES = 0x0 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 +CONFIG_TINY_BOOTBLOCK = 0x0 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WRITE_HIGH_TABLES = 0x1 +CONFIG_WRITE_HIGH_TABLES = 0x0 [77/116] olpc/rev_a ok. Processing mainboard/olpc/rev_a (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_GX2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_HAVE_HIGH_TABLES = 0x0 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 +CONFIG_TINY_BOOTBLOCK = 0x0 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WRITE_HIGH_TABLES = 0x1 +CONFIG_WRITE_HIGH_TABLES = 0x0 [78/116] pcengines/alix1c ok. Processing mainboard/pcengines/alix1c (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_LX = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 +CONFIG_TINY_BOOTBLOCK = 0x0 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [79/116] rca/rm4100 ok. Processing mainboard/rca/rm4100 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-4989/targets/rca/rm4100/Config-abuild.lb ok Creating builddir...ok -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HARD_RESET = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 +CONFIG_I830_VIDEO_MB_1MB = 0x0 +CONFIG_I830_VIDEO_MB_512KB = 0x0 +CONFIG_I830_VIDEO_MB_8MB = 0x1 +CONFIG_I830_VIDEO_MB_OFF = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 +CONFIG_MMX = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 +CONFIG_TINY_BOOTBLOCK = 0x0 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [80/116] soyo/sy-6ba-plus-iii ok. Processing mainboard/soyo/sy-6ba-plus-iii (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_INTEL_SLOT_2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 +CONFIG_TINY_BOOTBLOCK = 0x0 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [81/116] sunw/ultra40 ok. Processing mainboard/sunw/ultra40 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0 +CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000 -CONFIG_DIMM_SUPPORT = 0x108 -CONFIG_ENABLE_APIC_EXT_ID = 0x1 +CONFIG_ENABLE_APIC_EXT_ID = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x0 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 +CONFIG_TINY_BOOTBLOCK = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [82/116] supermicro/h8dme ok. Processing mainboard/supermicro/h8dme (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-4989/targets/supermicro/h8dme/Config-abuild.lb ok Creating builddir...ok -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 -CONFIG_HAVE_LOW_TABLES = 0x0 +CONFIG_HAVE_LOW_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x0 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_SERIAL_CPU_INIT = 0x0 +CONFIG_SERIAL_CPU_INIT = 0x1 +CONFIG_TINY_BOOTBLOCK = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WAIT_BEFORE_CPUS_INIT = 0x1 +CONFIG_WAIT_BEFORE_CPUS_INIT = 0x0 [83/116] supermicro/h8dmr ok. Processing mainboard/supermicro/h8dmr (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-4989/targets/supermicro/h8dmr/Config-abuild.lb ok Creating builddir...ok +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x0 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_ROM_SIZE = 0x100000 +CONFIG_ROM_SIZE = 0x80000 -CONFIG_SERIAL_CPU_INIT = 0x0 +CONFIG_SERIAL_CPU_INIT = 0x1 +CONFIG_TINY_BOOTBLOCK = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WAIT_BEFORE_CPUS_INIT = 0x1 +CONFIG_WAIT_BEFORE_CPUS_INIT = 0x0 [84/116] supermicro/h8dmr_fam10 fail. [85/116] supermicro/x6dai_g ok. Processing mainboard/supermicro/x6dai_g (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_HAVE_HARD_RESET = 0x1 +CONFIG_HAVE_HARD_RESET = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 -CONFIG_HAVE_MOVNTI = 0x1 +CONFIG_HAVE_MOVNTI = 0x0 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_IOAPIC = 0x1 +CONFIG_IOAPIC = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_MMX = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 +CONFIG_SSE = 0x1 +CONFIG_TINY_BOOTBLOCK = 0x0 -CONFIG_UDELAY_TSC = 0x1 +CONFIG_UDELAY_TSC = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [86/116] supermicro/x6dhe_g ok. Processing mainboard/supermicro/x6dhe_g (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_HAVE_HARD_RESET = 0x1 +CONFIG_HAVE_HARD_RESET = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 -CONFIG_HAVE_MOVNTI = 0x1 +CONFIG_HAVE_MOVNTI = 0x0 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_IOAPIC = 0x1 +CONFIG_IOAPIC = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_MMX = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 +CONFIG_SSE = 0x1 +CONFIG_TINY_BOOTBLOCK = 0x0 -CONFIG_UDELAY_TSC = 0x1 +CONFIG_UDELAY_TSC = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [87/116] supermicro/x6dhe_g2 ok. Processing mainboard/supermicro/x6dhe_g2 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_HAVE_HARD_RESET = 0x1 +CONFIG_HAVE_HARD_RESET = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 -CONFIG_HAVE_MOVNTI = 0x1 +CONFIG_HAVE_MOVNTI = 0x0 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_IOAPIC = 0x1 +CONFIG_IOAPIC = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_MMX = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 +CONFIG_SSE = 0x1 +CONFIG_TINY_BOOTBLOCK = 0x0 -CONFIG_UDELAY_TSC = 0x1 +CONFIG_UDELAY_TSC = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [88/116] supermicro/x6dhr_ig ok. Processing mainboard/supermicro/x6dhr_ig (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_HAVE_HARD_RESET = 0x1 +CONFIG_HAVE_HARD_RESET = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 -CONFIG_HAVE_MOVNTI = 0x1 +CONFIG_HAVE_MOVNTI = 0x0 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_IOAPIC = 0x1 +CONFIG_IOAPIC = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_MMX = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 +CONFIG_SSE = 0x1 +CONFIG_TINY_BOOTBLOCK = 0x0 -CONFIG_UDELAY_TSC = 0x1 +CONFIG_UDELAY_TSC = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [89/116] supermicro/x6dhr_ig2 ok. Processing mainboard/supermicro/x6dhr_ig2 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_HAVE_HARD_RESET = 0x1 +CONFIG_HAVE_HARD_RESET = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 -CONFIG_HAVE_MOVNTI = 0x1 +CONFIG_HAVE_MOVNTI = 0x0 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_IOAPIC = 0x1 +CONFIG_IOAPIC = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_MMX = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 +CONFIG_SSE = 0x1 +CONFIG_TINY_BOOTBLOCK = 0x0 -CONFIG_UDELAY_TSC = 0x1 +CONFIG_UDELAY_TSC = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [90/116] technexion/tim5690 ok. Processing mainboard/technexion/tim5690 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-4989/targets/technexion/tim5690/Config-abuild.lb ok Creating builddir...ok +CONFIG_HAVE_ACPI_TABLES = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_TINY_BOOTBLOCK = 0x0 [91/116] technexion/tim8690 ok. Processing mainboard/technexion/tim8690 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-4989/targets/technexion/tim8690/Config-abuild.lb ok Creating builddir...ok -CONFIG_APIC_ID_OFFSET = 0x0 +CONFIG_APIC_ID_OFFSET = 0x8 -CONFIG_GFXUMA = 0x1 +CONFIG_GFXUMA = 0x0 +CONFIG_HAVE_ACPI_TABLES = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 -CONFIG_HAVE_MAINBOARD_RESOURCES = 0x1 +CONFIG_HAVE_MAINBOARD_RESOURCES = 0x0 +CONFIG_HAVE_MP_TABLE = 0x1 -CONFIG_HAVE_OPTION_TABLE = 0x0 +CONFIG_HAVE_OPTION_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x1 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x6 -CONFIG_HT_CHAIN_UNITID_BASE = 0x0 +CONFIG_HT_CHAIN_UNITID_BASE = 0xa -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x1 +CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x2 +CONFIG_TINY_BOOTBLOCK = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WAIT_BEFORE_CPUS_INIT = 0x0 +CONFIG_WAIT_BEFORE_CPUS_INIT = 0x1 [92/116] technologic/ts5300 ok. Processing mainboard/technologic/ts5300 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-4989/targets/technologic/ts5300/Config-abuild.lb ok Creating builddir...ok +CONFIG_CPU_AMD_SC520 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x0 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_ROM_SIZE = 0x20000 +CONFIG_ROM_SIZE = 0x40000 +CONFIG_TINY_BOOTBLOCK = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 -CONFIG_TTYS0_BASE = 0x2f8 +CONFIG_TTYS0_BASE = 0x3f8 +CONFIG_UDELAY_LAPIC = 0x0 +CONFIG_UDELAY_TSC = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [93/116] televideo/tc7020 ok. Processing mainboard/televideo/tc7020 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_GX1 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x6 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x0 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x6 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 +CONFIG_TINY_BOOTBLOCK = 0x0 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WRITE_HIGH_TABLES = 0x1 +CONFIG_WRITE_HIGH_TABLES = 0x0 [94/116] thomson/ip1000 ok. Processing mainboard/thomson/ip1000 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-4989/targets/thomson/ip1000/Config-abuild.lb ok Creating builddir...ok -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HARD_RESET = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 +CONFIG_I830_VIDEO_MB_1MB = 0x0 +CONFIG_I830_VIDEO_MB_512KB = 0x0 +CONFIG_I830_VIDEO_MB_8MB = 0x1 +CONFIG_I830_VIDEO_MB_OFF = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 +CONFIG_MMX = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 +CONFIG_TINY_BOOTBLOCK = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [95/116] tyan/s1846 ok. Processing mainboard/tyan/s1846 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_INTEL_SLOT_2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 +CONFIG_TINY_BOOTBLOCK = 0x0 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [96/116] tyan/s2735 ok. Processing mainboard/tyan/s2735 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_HAVE_HARD_RESET = 0x1 +CONFIG_HAVE_HARD_RESET = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 -CONFIG_HAVE_MOVNTI = 0x1 +CONFIG_HAVE_MOVNTI = 0x0 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_IOAPIC = 0x1 +CONFIG_IOAPIC = 0x0 +CONFIG_MMX = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_SERIAL_CPU_INIT = 0x0 +CONFIG_SERIAL_CPU_INIT = 0x1 +CONFIG_SSE = 0x1 +CONFIG_TINY_BOOTBLOCK = 0x0 -CONFIG_USE_PRINTK_IN_CAR = 0x1 +CONFIG_USE_PRINTK_IN_CAR = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [97/116] tyan/s2850 ok. Processing mainboard/tyan/s2850 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DCACHE_RAM_BASE = 0xcf000 +CONFIG_DCACHE_RAM_BASE = 0xc8000 -CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0 +CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_DCACHE_RAM_SIZE = 0x8000 -CONFIG_DIMM_SUPPORT = 0x108 -CONFIG_HAVE_HARD_RESET = 0x1 +CONFIG_HAVE_HARD_RESET = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_IOAPIC = 0x1 +CONFIG_IOAPIC = 0x0 -CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0 +CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 +CONFIG_TINY_BOOTBLOCK = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [98/116] tyan/s2875 ok. Processing mainboard/tyan/s2875 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DCACHE_RAM_BASE = 0xcf000 +CONFIG_DCACHE_RAM_BASE = 0xc8000 -CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0 +CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_DCACHE_RAM_SIZE = 0x8000 -CONFIG_DIMM_SUPPORT = 0x108 -CONFIG_HAVE_HARD_RESET = 0x1 +CONFIG_HAVE_HARD_RESET = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0 +CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 +CONFIG_TINY_BOOTBLOCK = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [99/116] tyan/s2880 ok. Processing mainboard/tyan/s2880 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_APIC_ID_OFFSET = 0x0 +CONFIG_APIC_ID_OFFSET = 0x10 -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DCACHE_RAM_BASE = 0xcf000 +CONFIG_DCACHE_RAM_BASE = 0xc8000 -CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0 +CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_DCACHE_RAM_SIZE = 0x8000 -CONFIG_DIMM_SUPPORT = 0x108 -CONFIG_HAVE_HARD_RESET = 0x1 +CONFIG_HAVE_HARD_RESET = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x6 -CONFIG_HT_CHAIN_UNITID_BASE = 0x1 +CONFIG_HT_CHAIN_UNITID_BASE = 0xa -CONFIG_IOAPIC = 0x1 +CONFIG_IOAPIC = 0x0 -CONFIG_IRQ_SLOT_COUNT = 0xd +CONFIG_IRQ_SLOT_COUNT = 0x9 -CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0 +CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAX_CPUS = 0x2 +CONFIG_MAX_CPUS = 0x4 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x0 +CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x2 -CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x1 +CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0 +CONFIG_TINY_BOOTBLOCK = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [100/116] tyan/s2881 ok. Processing mainboard/tyan/s2881 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_APIC_ID_OFFSET = 0x0 +CONFIG_APIC_ID_OFFSET = 0x10 -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DCACHE_RAM_BASE = 0xcf000 +CONFIG_DCACHE_RAM_BASE = 0xc8000 -CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0 +CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_DCACHE_RAM_SIZE = 0x8000 -CONFIG_DIMM_SUPPORT = 0x108 -CONFIG_HAVE_HARD_RESET = 0x1 +CONFIG_HAVE_HARD_RESET = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_IOAPIC = 0x1 +CONFIG_IOAPIC = 0x0 -CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0 +CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x0 +CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x2 -CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x1 +CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0 +CONFIG_TINY_BOOTBLOCK = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [101/116] tyan/s2882 ok. Processing mainboard/tyan/s2882 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_APIC_ID_OFFSET = 0x0 +CONFIG_APIC_ID_OFFSET = 0x10 -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DCACHE_RAM_BASE = 0xcf000 +CONFIG_DCACHE_RAM_BASE = 0xc8000 -CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0 +CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_DCACHE_RAM_SIZE = 0x8000 -CONFIG_DIMM_SUPPORT = 0x108 -CONFIG_HAVE_HARD_RESET = 0x1 +CONFIG_HAVE_HARD_RESET = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x6 -CONFIG_HT_CHAIN_UNITID_BASE = 0x1 +CONFIG_HT_CHAIN_UNITID_BASE = 0xa -CONFIG_IOAPIC = 0x1 +CONFIG_IOAPIC = 0x0 -CONFIG_IRQ_SLOT_COUNT = 0xf +CONFIG_IRQ_SLOT_COUNT = 0x9 -CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0 +CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x0 +CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x2 -CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x1 +CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0 +CONFIG_TINY_BOOTBLOCK = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [102/116] tyan/s2885 ok. Processing mainboard/tyan/s2885 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DCACHE_RAM_BASE = 0xcf000 +CONFIG_DCACHE_RAM_BASE = 0xc8000 -CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0 +CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_DCACHE_RAM_SIZE = 0x8000 -CONFIG_DIMM_SUPPORT = 0x108 -CONFIG_ENABLE_APIC_EXT_ID = 0x1 +CONFIG_ENABLE_APIC_EXT_ID = 0x0 -CONFIG_HAVE_HARD_RESET = 0x1 +CONFIG_HAVE_HARD_RESET = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_IOAPIC = 0x1 +CONFIG_IOAPIC = 0x0 -CONFIG_IRQ_SLOT_COUNT = 0xb +CONFIG_IRQ_SLOT_COUNT = 0x9 -CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0 +CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x1 +CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0 +CONFIG_TINY_BOOTBLOCK = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [103/116] tyan/s2891 ok. Processing mainboard/tyan/s2891 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-4989/targets/tyan/s2891/Config-abuild.lb ok Creating builddir...ok -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DCACHE_RAM_BASE = 0xcf000 +CONFIG_DCACHE_RAM_BASE = 0xc8000 -CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0 +CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_DCACHE_RAM_SIZE = 0x8000 -CONFIG_DIMM_SUPPORT = 0x108 +CONFIG_HAVE_ACPI_TABLES = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0 +CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_ROM_SIZE = 0x80000 +CONFIG_ROM_SIZE = 0x100000 -CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x1 +CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0 +CONFIG_TINY_BOOTBLOCK = 0x0 [104/116] tyan/s2892 ok. Processing mainboard/tyan/s2892 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-4989/targets/tyan/s2892/Config-abuild.lb ok Creating builddir...ok -CONFIG_APIC_ID_OFFSET = 0x0 +CONFIG_APIC_ID_OFFSET = 0x10 -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DCACHE_RAM_BASE = 0xcf000 +CONFIG_DCACHE_RAM_BASE = 0xc8000 -CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0 +CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_DCACHE_RAM_SIZE = 0x8000 -CONFIG_DIMM_SUPPORT = 0x108 +CONFIG_HAVE_ACPI_TABLES = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0 +CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 +CONFIG_TINY_BOOTBLOCK = 0x0 [105/116] tyan/s2895 ok. Processing mainboard/tyan/s2895 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-4989/targets/tyan/s2895/Config-abuild.lb ok Creating builddir...ok -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DCACHE_RAM_BASE = 0xcf000 +CONFIG_DCACHE_RAM_BASE = 0xc8000 -CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0 +CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_DCACHE_RAM_SIZE = 0x8000 -CONFIG_DIMM_SUPPORT = 0x108 +CONFIG_HAVE_ACPI_TABLES = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_SERIAL_CPU_INIT = 0x0 +CONFIG_SERIAL_CPU_INIT = 0x1 +CONFIG_TINY_BOOTBLOCK = 0x0 [106/116] tyan/s2912 ok. Processing mainboard/tyan/s2912 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-4989/targets/tyan/s2912/Config-abuild.lb ok Creating builddir...ok -CONFIG_ACPI_SSDTX_NUM = 0x3 +CONFIG_ACPI_SSDTX_NUM = 0x0 -CONFIG_APIC_ID_OFFSET = 0x10 +CONFIG_APIC_ID_OFFSET = 0x16 -CONFIG_HAVE_FALLBACK_BOOT = 0x1 +CONFIG_HAVE_FALLBACK_BOOT = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x0 -CONFIG_MAX_CPUS = 0x4 +CONFIG_MAX_CPUS = 0x2 -CONFIG_MAX_PHYSICAL_CPUS = 0x2 +CONFIG_MAX_PHYSICAL_CPUS = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0 +CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x1 -CONFIG_SERIAL_CPU_INIT = 0x1 +CONFIG_SERIAL_CPU_INIT = 0x0 +CONFIG_TINY_BOOTBLOCK = 0x0 -CONFIG_USE_FALLBACK_IMAGE = 0x1 +CONFIG_USE_FALLBACK_IMAGE = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WAIT_BEFORE_CPUS_INIT = 0x1 +CONFIG_WAIT_BEFORE_CPUS_INIT = 0x0 [107/116] tyan/s2912_fam10 fail. [108/116] tyan/s4880 ok. Processing mainboard/tyan/s4880 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0 +CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000 -CONFIG_DIMM_SUPPORT = 0x108 -CONFIG_ENABLE_APIC_EXT_ID = 0x1 +CONFIG_ENABLE_APIC_EXT_ID = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x0 -CONFIG_HT_CHAIN_UNITID_BASE = 0x1 +CONFIG_HT_CHAIN_UNITID_BASE = 0x0 -CONFIG_IRQ_SLOT_COUNT = 0x16 +CONFIG_IRQ_SLOT_COUNT = 0xb -CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0 +CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1 -CONFIG_MAX_CPUS = 0x8 +CONFIG_MAX_CPUS = 0x4 -CONFIG_MAX_PHYSICAL_CPUS = 0x4 +CONFIG_MAX_PHYSICAL_CPUS = 0x2 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x0 +CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x2 -CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x1 +CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0 +CONFIG_TINY_BOOTBLOCK = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [109/116] tyan/s4882 ok. Processing mainboard/tyan/s4882 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0 +CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000 -CONFIG_DIMM_SUPPORT = 0x108 -CONFIG_ENABLE_APIC_EXT_ID = 0x1 +CONFIG_ENABLE_APIC_EXT_ID = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x0 -CONFIG_HT_CHAIN_UNITID_BASE = 0x1 +CONFIG_HT_CHAIN_UNITID_BASE = 0x0 -CONFIG_IRQ_SLOT_COUNT = 0x16 +CONFIG_IRQ_SLOT_COUNT = 0xb -CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0 +CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1 -CONFIG_MAX_CPUS = 0x8 +CONFIG_MAX_CPUS = 0x4 -CONFIG_MAX_PHYSICAL_CPUS = 0x4 +CONFIG_MAX_PHYSICAL_CPUS = 0x2 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x2000 +CONFIG_RAMBASE = 0x100000 -CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x0 +CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x2 -CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x1 +CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0 +CONFIG_TINY_BOOTBLOCK = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [110/116] via/epia-cn ok. Processing mainboard/via/epia-cn (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-4989/targets/via/epia-cn/Config-abuild.lb ok Creating builddir...ok +CONFIG_CN700_VIDEO_MB_128MB = 0x0 +CONFIG_CN700_VIDEO_MB_16MB = 0x0 +CONFIG_CN700_VIDEO_MB_32MB = 0x1 +CONFIG_CN700_VIDEO_MB_64MB = 0x0 +CONFIG_CN700_VIDEO_MB_8MB = 0x0 +CONFIG_CN700_VIDEO_MB_OFF = 0x0 +CONFIG_CPU_VIA_C7 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x7 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_EPIA_VT8237R_INIT = 0x0 +CONFIG_FALLBACK_SIZE = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_TINY_BOOTBLOCK = 0x0 -CONFIG_UDELAY_TSC = 0x1 +CONFIG_UDELAY_TSC = 0x0 [111/116] via/epia-m ok. Processing mainboard/via/epia-m (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-4989/targets/via/epia-m/Config-abuild.lb ok Creating builddir...ok +CONFIG_CPU_VIA_C3 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_FALLBACK_SIZE = 0x0 +CONFIG_HAVE_ACPI_TABLES = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_TINY_BOOTBLOCK = 0x0 -CONFIG_UDELAY_TSC = 0x1 +CONFIG_UDELAY_TSC = 0x0 [112/116] via/epia-m700 ok. Processing mainboard/via/epia-m700 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-4989/targets/via/epia-m700/Config-abuild.lb ok Creating builddir...ok +CONFIG_CPU_VIA_C7 = 0x1 -CONFIG_DCACHE_RAM_SIZE = 0x2000 +CONFIG_DCACHE_RAM_SIZE = 0x8000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_FALLBACK_SIZE = 0x0 +CONFIG_HAVE_ACPI_TABLES = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x0 -CONFIG_HEAP_SIZE = 0x5000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_IOAPIC = 0x1 +CONFIG_IOAPIC = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x0 +CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1019 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 +CONFIG_TINY_BOOTBLOCK = 0x0 -CONFIG_UDELAY_TSC = 0x1 +CONFIG_UDELAY_TSC = 0x0 -CONFIG_USE_DCACHE_RAM = 0x1 +CONFIG_USE_DCACHE_RAM = 0x0 [113/116] via/epia-n ok. Processing mainboard/via/epia-n (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-4989/targets/via/epia-n/Config-abuild.lb ok Creating builddir...ok +CONFIG_CN400_VIDEO_MB_128MB = 0x0 +CONFIG_CN400_VIDEO_MB_16MB = 0x0 +CONFIG_CN400_VIDEO_MB_32MB = 0x1 +CONFIG_CN400_VIDEO_MB_64MB = 0x0 +CONFIG_CN400_VIDEO_MB_8MB = 0x0 +CONFIG_CN400_VIDEO_MB_OFF = 0x0 +CONFIG_CPU_VIA_C3 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x7 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_FALLBACK_SIZE = 0x0 +CONFIG_HAVE_ACPI_TABLES = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x0 -CONFIG_HAVE_MAINBOARD_RESOURCES = 0x1 +CONFIG_HAVE_MAINBOARD_RESOURCES = 0x0 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_IOAPIC = 0x1 +CONFIG_IOAPIC = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_SMP = 0x1 +CONFIG_SMP = 0x0 +CONFIG_TINY_BOOTBLOCK = 0x0 -CONFIG_UDELAY_TSC = 0x1 +CONFIG_UDELAY_TSC = 0x0 -CONFIG_WRITE_HIGH_TABLES = 0x1 +CONFIG_WRITE_HIGH_TABLES = 0x0 [114/116] via/epia ok. Processing mainboard/via/epia (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_VIA_C3 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x7 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_FALLBACK_SIZE = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 -CONFIG_HAVE_INIT_TIMER = 0x0 +CONFIG_HAVE_INIT_TIMER = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 +CONFIG_TINY_BOOTBLOCK = 0x0 -CONFIG_UDELAY_IO = 0x1 +CONFIG_UDELAY_IO = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [115/116] via/pc2500e ok. Processing mainboard/via/pc2500e (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-4989/targets/via/pc2500e/Config-abuild.lb ok Creating builddir...ok +CONFIG_CN700_VIDEO_MB_128MB = 0x0 +CONFIG_CN700_VIDEO_MB_16MB = 0x0 +CONFIG_CN700_VIDEO_MB_32MB = 0x1 +CONFIG_CN700_VIDEO_MB_64MB = 0x0 +CONFIG_CN700_VIDEO_MB_8MB = 0x0 +CONFIG_CN700_VIDEO_MB_OFF = 0x0 +CONFIG_CPU_VIA_C7 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_EPIA_VT8237R_INIT = 0x0 +CONFIG_FALLBACK_SIZE = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 +CONFIG_TINY_BOOTBLOCK = 0x0 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_USE_OPTION_TABLE = 0x1 +CONFIG_USE_OPTION_TABLE = 0x0 [116/116] via/vt8454c ok. Processing mainboard/via/vt8454c (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-4989/targets/via/vt8454c/Config-abuild.lb ok Creating builddir...ok +CONFIG_CPU_VIA_C7 = 0x1 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x5 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_ACPI_TABLES = 0x1 -CONFIG_HAVE_HARD_RESET = 0x1 +CONFIG_HAVE_HARD_RESET = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x0 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_IOAPIC = 0x1 +CONFIG_IOAPIC = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x0 +CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1019 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x5 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_ROM_SIZE = 0x80000 +CONFIG_ROM_SIZE = 0x100000 -CONFIG_SMP = 0x1 +CONFIG_SMP = 0x0 +CONFIG_TINY_BOOTBLOCK = 0x0 -CONFIG_UDELAY_TSC = 0x1 +CONFIG_UDELAY_TSC = 0x0 -CONFIG_USE_DCACHE_RAM = 0x1 +CONFIG_USE_DCACHE_RAM = 0x0 -CONFIG_WRITE_HIGH_TABLES = 0x1 +CONFIG_WRITE_HIGH_TABLES = 0x0

1 0

[commit] r4989 - in trunk: . src/arch/i386 src/arch/i386/init src/arch/i386/lib src/cpu/x86/32bit src/mainboard/emulation/qemu-x86 util/cbfstool
by svn＠coreboot.org 23 Dec '09

23 Dec '09

Author: oxygene Date: 2009-12-23 13:52:56 +0100 (Wed, 23 Dec 2009) New Revision: 4989 Added: trunk/src/arch/i386/Makefile.bigbootblock.inc trunk/src/arch/i386/Makefile.tinybootblock.inc trunk/src/arch/i386/init/bootblock.c trunk/src/arch/i386/init/bootblock_prologue.c trunk/src/arch/i386/lib/walkcbfs.S Modified: trunk/Makefile trunk/src/arch/i386/Kconfig trunk/src/arch/i386/Makefile.inc trunk/src/cpu/x86/32bit/entry32.lds trunk/src/mainboard/emulation/qemu-x86/Kconfig trunk/src/mainboard/emulation/qemu-x86/Makefile.inc trunk/util/cbfstool/cbfs-mkstage.c Log: Tiny Bootblock, step 1/n. Introduce the tiny bootblock infrastructure and use it on QEmu. Signed-off-by: Patrick Georgi <patrick.georgi(a)coresystems.de> Acked-by: Myles Watson <mylesgw(a)gmail.com> Acked-by: Ronald G. Minnich <rminnich(a)gmail.com> Modified: trunk/Makefile =================================================================== --- trunk/Makefile 2009-12-21 15:09:01 UTC (rev 4988) +++ trunk/Makefile 2009-12-23 12:52:56 UTC (rev 4989) @@ -293,6 +293,7 @@ clean: doxygen-clean rm -f $(allobjs) $(obj)/coreboot* + rm -rf $(obj)/bootblock* $(obj)/romstage* $(obj)/location.* rm -f $(obj)/option_table.* $(obj)/crt0_includes.h $(obj)/ldscript rm -f $(obj)/mainboard/$(MAINBOARDDIR)/static.c $(obj)/mainboard/$(MAINBOARDDIR)/config.py $(obj)/mainboard/$(MAINBOARDDIR)/static.dot rm -f $(obj)/mainboard/$(MAINBOARDDIR)/auto.inc $(obj)/mainboard/$(MAINBOARDDIR)/crt0.s $(obj)/mainboard/$(MAINBOARDDIR)/crt0.disasm Modified: trunk/src/arch/i386/Kconfig =================================================================== --- trunk/src/arch/i386/Kconfig 2009-12-21 15:09:01 UTC (rev 4988) +++ trunk/src/arch/i386/Kconfig 2009-12-23 12:52:56 UTC (rev 4989) @@ -40,3 +40,6 @@ int default 3 +config TINY_BOOTBLOCK + bool + default n Copied: trunk/src/arch/i386/Makefile.bigbootblock.inc (from rev 4988, trunk/src/arch/i386/Makefile.inc) =================================================================== --- trunk/src/arch/i386/Makefile.bigbootblock.inc (rev 0) +++ trunk/src/arch/i386/Makefile.bigbootblock.inc 2009-12-23 12:52:56 UTC (rev 4989) @@ -0,0 +1,35 @@ +ifdef POST_EVALUATION + +####################################################################### +# Build the final rom image + +$(obj)/coreboot.pre: $(obj)/coreboot.bootblock $(CBFSTOOL) + rm -f $@ + $(CBFSTOOL) $@ create $(CONFIG_COREBOOT_ROMSIZE_KB)K $(obj)/coreboot.bootblock + +####################################################################### +# Build the bootblock + +$(obj)/coreboot.bootblock: $(obj)/coreboot + @printf " OBJCOPY $(subst $(obj)/,,$(@))\n" + $(OBJCOPY) -O binary $< $@ + +$(obj)/ldscript.ld: $(ldscripts) $(obj)/ldoptions + printf 'INCLUDE "ldoptions"\n' > $@ + printf '$(foreach ldscript,$(ldscripts),INCLUDE "$(ldscript:$(obj)/%=%)"\n)' >> $@ + +$(obj)/crt0_includes.h: $(crt0s) + printf '$(foreach crt0,config.h $(crt0s),#include "$(crt0:$(obj)/%=%)"\n)' > $@ + +$(obj)/mainboard/$(MAINBOARDDIR)/crt0.o: $(obj)/mainboard/$(MAINBOARDDIR)/crt0.s + $(CC) -I$(obj) -Wa,-acdlns -c -o $@ $< > $(dir $(a))/crt0.disasm + +$(obj)/mainboard/$(MAINBOARDDIR)/crt0.s: $(src)/arch/i386/init/crt0.S.lb $(obj)/crt0_includes.h + $(CC) -x assembler-with-cpp -DASSEMBLY -E -I$(src)/include -I$(src)/arch/i386/include -I$(obj) -include $(obj)/config.h -I. -I$(src) $< > $@.new && mv $@.new $@ + +$(obj)/coreboot: $(initobjs) $(obj)/ldscript.ld + @printf " LINK $(subst $(obj)/,,$(@))\n" + $(CC) -nostdlib -nostartfiles -static -o $@ -L$(obj) -T $(obj)/ldscript.ld $(initobjs) + $(NM) -n $(obj)/coreboot | sort > $(obj)/coreboot.map + +endif Modified: trunk/src/arch/i386/Makefile.inc =================================================================== --- trunk/src/arch/i386/Makefile.inc 2009-12-21 15:09:01 UTC (rev 4988) +++ trunk/src/arch/i386/Makefile.inc 2009-12-23 12:52:56 UTC (rev 4989) @@ -11,10 +11,8 @@ ####################################################################### # Build the final rom image - -$(obj)/coreboot.rom: $(obj)/coreboot.bootblock $(obj)/coreboot_ram $(CBFSTOOL) - rm -f $@ - $(CBFSTOOL) $@ create $(CONFIG_COREBOOT_ROMSIZE_KB)K $(obj)/coreboot.bootblock +$(obj)/coreboot.rom: $(obj)/coreboot.pre $(obj)/coreboot_ram $(CBFSTOOL) + cp $(obj)/coreboot.pre $@ if [ -f fallback/coreboot_apc ]; \ then \ $(CBFSTOOL) $@ add-stage fallback/coreboot_apc fallback/coreboot_apc $(CBFS_COMPRESS_FLAG); \ @@ -33,36 +31,10 @@ @printf " CBFSPRINT $(subst $(obj)/,,$(@))\n\n" $(CBFSTOOL) $(obj)/coreboot.rom print - ####################################################################### -# Build the bootblock - -$(obj)/coreboot.bootblock: $(obj)/coreboot - @printf " OBJCOPY $(subst $(obj)/,,$(@))\n" - $(OBJCOPY) -O binary $< $@ - -$(obj)/ldscript.ld: $(ldscripts) $(obj)/ldoptions - printf 'INCLUDE "ldoptions"\n' > $@ - printf '$(foreach ldscript,$(ldscripts),INCLUDE "$(ldscript:$(obj)/%=%)"\n)' >> $@ - -$(obj)/crt0_includes.h: $(crt0s) - printf '$(foreach crt0,config.h $(crt0s),#include "$(crt0:$(obj)/%=%)"\n)' > $@ - -$(obj)/mainboard/$(MAINBOARDDIR)/crt0.o: $(obj)/mainboard/$(MAINBOARDDIR)/crt0.s - $(CC) -I$(obj) -Wa,-acdlns -c -o $@ $< > $(dir $(a))/crt0.disasm - -$(obj)/mainboard/$(MAINBOARDDIR)/crt0.s: $(src)/arch/i386/init/crt0.S.lb $(obj)/crt0_includes.h - $(CC) -x assembler-with-cpp -DASSEMBLY -E -I$(src)/include -I$(src)/arch/i386/include -I$(obj) -include $(obj)/config.h -I. -I$(src) $< > $@.new && mv $@.new $@ - -$(obj)/coreboot: $(initobjs) $(obj)/ldscript.ld - @printf " LINK $(subst $(obj)/,,$(@))\n" - $(CC) -nostdlib -nostartfiles -static -o $@ -L$(obj) -T $(obj)/ldscript.ld $(initobjs) - $(NM) -n $(obj)/coreboot | sort > $(obj)/coreboot.map - -####################################################################### # i386 specific tools -$(obj)/option_table.h $(obj)/option_table.c: $(obj)/build_opt_tbl $(top)/src/mainboard/$(MAINBOARDDIR)/cmos.layout +$(obj)/option_table.h $(obj)/option_table.c $(obj)/arch/i386/../../option_table.c: $(obj)/build_opt_tbl $(top)/src/mainboard/$(MAINBOARDDIR)/cmos.layout @printf " OPTION $(subst $(obj)/,,$(@))\n" $(obj)/build_opt_tbl --config $(top)/src/mainboard/$(MAINBOARDDIR)/cmos.layout --header $(obj)/option_table.h --option $(obj)/option_table.c @@ -91,3 +63,9 @@ # done endif + +ifeq ($(CONFIG_TINY_BOOTBLOCK),y) +include $(src)/arch/i386/Makefile.tinybootblock.inc +else +include $(src)/arch/i386/Makefile.bigbootblock.inc +endif Copied: trunk/src/arch/i386/Makefile.tinybootblock.inc (from rev 4988, trunk/src/arch/i386/Makefile.inc) =================================================================== --- trunk/src/arch/i386/Makefile.tinybootblock.inc (rev 0) +++ trunk/src/arch/i386/Makefile.tinybootblock.inc 2009-12-23 12:52:56 UTC (rev 4989) @@ -0,0 +1,87 @@ +ifdef POST_EVALUATION + +####################################################################### +# Build the final rom image + +$(obj)/coreboot.pre1: $(obj)/coreboot.bootblock $(CBFSTOOL) + rm -f $@ + $(CBFSTOOL) $@ create $(CONFIG_COREBOOT_ROMSIZE_KB)K $(obj)/coreboot.bootblock + +$(obj)/coreboot.pre: $(obj)/coreboot.romstage $(obj)/coreboot.pre1 $(CBFSTOOL) + rm -f $@ + cp $(obj)/coreboot.pre1 $@ + $(CBFSTOOL) $@ add-stage $(obj)/romstage.elf fallback/romstage x 0x$(shell cat $(obj)/location.txt) +#FIXME: location.txt might require an offset of header size + +####################################################################### +# Build the bootblock + +$(obj)/coreboot.bootblock: $(obj)/bootblock.elf + @printf " OBJCOPY $(subst $(obj)/,,$(@))\n" + $(OBJCOPY) -O binary $< $@ + +bootblock_lds := $(src)/arch/i386/init/ldscript_failover.lb +bootblock_lds += $(src)/cpu/x86/16bit/entry16.lds +bootblock_lds += $(src)/cpu/x86/16bit/reset16.lds +bootblock_lds += $(src)/arch/i386/lib/id.lds + +bootblock_inc := $(src)/arch/i386/init/bootblock_prologue.c +bootblock_inc += $(src)/cpu/x86/16bit/entry16.inc +bootblock_inc += $(src)/cpu/x86/16bit/reset16.inc +bootblock_inc += $(src)/cpu/x86/32bit/entry32.inc +bootblock_inc += $(src)/arch/i386/lib/id.inc +bootblock_inc += $(obj)/mainboard/$(MAINBOARDDIR)/bootblock.inc +bootblock_inc += $(src)/arch/i386/lib/walkcbfs.S + +$(obj)/bootblock/ldscript.ld: $(bootblock_ldscripts) $(obj)/ldoptions + mkdir -p $(obj)/bootblock + printf '$(foreach ldscript,ldoptions $(bootblock_lds),INCLUDE "$(ldscript)"\n)' > $@ + +$(obj)/bootblock/bootblock.c: $(bootblock_inc) + mkdir -p $(obj)/bootblock + printf '$(foreach crt0,config.h $(bootblock_inc),#include "$(crt0)"\n)' > $@ + +$(obj)/mainboard/$(MAINBOARDDIR)/bootblock.o: $(obj)/mainboard/$(MAINBOARDDIR)/bootblock.s + $(CC) -I$(obj) -Wa,-acdlns -c -o $@ $< > $(dir $(a))/crt0.disasm + +$(obj)/mainboard/$(MAINBOARDDIR)/bootblock.s: $(obj)/bootblock/bootblock.c + $(CC) -x assembler-with-cpp -DASSEMBLY -E -I$(src)/include -I$(src)/arch/i386/include -I$(obj) -I$(obj)/bootblock -include $(obj)/config.h -I. -I$(src) $< > $@.new && mv $@.new $@ + +$(obj)/mainboard/$(MAINBOARDDIR)/bootblock.inc: $(obj)/romcc $(src)/arch/i386/init/bootblock.c + $(obj)/romcc $(ROMCCFLAGS) $(INCLUDES) $(src)/arch/i386/init/bootblock.c -o $@ + +$(obj)/bootblock.elf: $(obj)/mainboard/$(MAINBOARDDIR)/bootblock.o $(obj)/bootblock/ldscript.ld + @printf " LINK $(subst $(obj)/,,$(@))\n" + $(CC) -nostdlib -nostartfiles -static -o $@ -L$(obj) -T $(obj)/bootblock/ldscript.ld $< + $(NM) -n $(obj)/bootblock.elf | sort > $(obj)/bootblock.map + +####################################################################### +# Build the romstage +$(obj)/coreboot.romstage: $(obj)/coreboot.pre1 $(initobjs) $(obj)/romstage/ldscript.ld + @printf " LINK $(subst $(obj)/,,$(@))\n" + printf "CONFIG_ROMBASE = 0x0;\n" > $(obj)/location.ld + $(CC) -nostdlib -nostartfiles -static -o $(obj)/romstage.elf -L$(obj) -T $(obj)/romstage/ldscript.ld $(initobjs) + $(OBJCOPY) -O binary $(obj)/romstage.elf $(obj)/romstage.bin + printf "CONFIG_ROMBASE = 0x" > $(obj)/location.ld + $(CBFSTOOL) $(obj)/coreboot.pre1 locate $(obj)/romstage.bin fallback/romstage $(CONFIG_XIP_ROM_SIZE) > $(obj)/location.txt + cat $(obj)/location.txt >> $(obj)/location.ld + printf ";\n" >> $(obj)/location.ld + $(CC) -nostdlib -nostartfiles -static -o $(obj)/romstage.elf -L$(obj) -T $(obj)/romstage/ldscript.ld $(initobjs) + $(NM) -n $(obj)/romstage.elf | sort > $(obj)/romstage.map + $(OBJCOPY) -O binary $(obj)/romstage.elf $@ + +$(obj)/romstage/ldscript.ld: $(ldscripts) $(obj)/ldoptions + mkdir -p $(obj)/romstage + printf '$(foreach ldscript,ldoptions location.ld $(ldscripts),INCLUDE "$(ldscript:$(obj)/%=%)"\n)' > $@ + +$(obj)/romstage/crt0_includes.h: $(crt0s) + mkdir -p $(obj)/romstage + printf '$(foreach crt0,config.h $(crt0s),#include "$(crt0:$(obj)/%=%)"\n)' > $@ + +$(obj)/mainboard/$(MAINBOARDDIR)/crt0.o: $(obj)/mainboard/$(MAINBOARDDIR)/crt0.s + $(CC) -I$(obj) -Wa,-acdlns -c -o $@ $< > $(dir $(a))/crt0.disasm + +$(obj)/mainboard/$(MAINBOARDDIR)/crt0.s: $(src)/arch/i386/init/crt0.S.lb $(obj)/romstage/crt0_includes.h + $(CC) -x assembler-with-cpp -DASSEMBLY -E -I$(src)/include -I$(src)/arch/i386/include -I$(obj) -I$(obj)/romstage -include $(obj)/config.h -I. -I$(src) $< > $@.new && mv $@.new $@ + +endif Added: trunk/src/arch/i386/init/bootblock.c =================================================================== --- trunk/src/arch/i386/init/bootblock.c (rev 0) +++ trunk/src/arch/i386/init/bootblock.c 2009-12-23 12:52:56 UTC (rev 4989) @@ -0,0 +1,24 @@ +static unsigned long findstage(char* target) +{ + unsigned long entry; + asm volatile ( + "mov $1f, %%esp\n\t" + "jmp walkcbfs\n\t" + "1:\n\t" : "=a" (entry) : "S" (target) : "ebx", "ecx", "edx", "edi", "ebp", "esp"); + return entry; +} + +static void call(unsigned long addr) +{ + asm volatile ("jmp %0\n\t" : : "r" (addr)); +} + +static void main(void) +{ + const char* target1 = "fallback/romstage"; + unsigned long entry; + entry = findstage(target1); + if (entry) call(entry); + asm volatile ("1:\n\thlt\n\tjmp 1b\n\t"); +} + Copied: trunk/src/arch/i386/init/bootblock_prologue.c (from rev 4988, trunk/src/arch/i386/init/crt0.S.lb) =================================================================== --- trunk/src/arch/i386/init/bootblock_prologue.c (rev 0) +++ trunk/src/arch/i386/init/bootblock_prologue.c 2009-12-23 12:52:56 UTC (rev 4989) @@ -0,0 +1,37 @@ +/* -*- asm -*- + * $ $ + * + */ + +/* + * Copyright (C) 1996-2002 Markus Franz Xaver Johannes Oberhumer + * + * This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * Originally this code was part of ucl the data compression library + * for upx the ``Ultimate Packer of eXecutables''. + * + * - Converted to gas assembly, and refitted to work with etherboot. + * Eric Biederman 20 Aug 2002 + * - Merged the nrv2b decompressor into crt0.base of coreboot + * Eric Biederman 26 Sept 2002 + */ + + +#include <arch/asm.h> +#include <arch/intel.h> +#include <console/loglevel.h> + +/* + * This is the entry code the code in .reset section + * jumps to this address. + * + */ +.section ".rom.data", "a", @progbits +.section ".rom.text", "ax", @progbits + + intel_chip_post_macro(0x01) /* delay for chipsets */ + Added: trunk/src/arch/i386/lib/walkcbfs.S =================================================================== --- trunk/src/arch/i386/lib/walkcbfs.S (rev 0) +++ trunk/src/arch/i386/lib/walkcbfs.S 2009-12-23 12:52:56 UTC (rev 4989) @@ -0,0 +1,94 @@ +#define CBFS_HEADER_PTR 0xfffffffc + +#define CBFS_HEADER_MAGIC 0 +#define CBFS_HEADER_VERSION (CBFS_HEADER_MAGIC + 4) +#define CBFS_HEADER_ROMSIZE (CBFS_HEADER_VERSION + 4) +#define CBFS_HEADER_BOOTBLOCKSIZE (CBFS_HEADER_ROMSIZE + 4) +#define CBFS_HEADER_ALIGN (CBFS_HEADER_BOOTBLOCKSIZE + 4) +#define CBFS_HEADER_OFFSET (CBFS_HEADER_ALIGN + 4) + +#define CBFS_FILE_MAGIC 0 +#define CBFS_FILE_LEN (CBFS_FILE_MAGIC + 8) +#define CBFS_FILE_TYPE (CBFS_FILE_LEN + 4) +#define CBFS_FILE_CHECKSUM (CBFS_FILE_TYPE + 4) +#define CBFS_FILE_OFFSET (CBFS_FILE_CHECKSUM + 4) + +#define CBFS_FILE_STRUCTSIZE (CBFS_FILE_OFFSET + 4) + +#define CBFS_STAGE_COMPRESSION 0 +#define CBFS_STAGE_ENTRY (CBFS_STAGE_COMPRESSION + 4) +#define CBFS_STAGE_LOAD (CBFS_STAGE_ENTRY + 8) +#define CBFS_STAGE_LEN (CBFS_STAGE_LOAD + 8) +#define CBFS_STAGE_MEMLEN (CBFS_STAGE_LEN + 4) + +/* + input %esi: filename + input %esp: return address (not pointer to return address!) + output %eax: entry point + clobbers %ebx, %ecx, %edx, %edi, %ebp +*/ +walkcbfs: + mov %esi, %ebp /* stash away filename pointer */ + mov $0, %edx +1: + cmpb $0, (%edx,%esi) + jz 2f + add $1, %edx + jmp 1b +2: + add $1, %edx + mov CBFS_HEADER_PTR, %eax + mov CBFS_HEADER_ROMSIZE(%eax), %ecx + bswap %ecx + mov $0, %ebx + sub %ecx, %ebx + mov CBFS_HEADER_OFFSET(%eax), %ecx + bswap %ecx + add %ecx, %ebx + mov CBFS_HEADER_ALIGN(%eax), %eax + bswap %eax + sub $1, %eax + +walker: + mov %ebp, %esi + mov %ebx, %edi + add $CBFS_FILE_STRUCTSIZE, %edi /* edi = address of first byte after struct cbfs_file */ + mov %edx, %ecx + repe cmpsb + # zero flag set if strings are equal + jnz tryharder + + # we found it! + mov CBFS_FILE_OFFSET(%ebx), %eax + bswap %eax + add %ebx, %eax + add $CBFS_STAGE_ENTRY, %eax /* eax = ((cbfs_stage* (cbfs_file* ebx)->offset)->entry) */ + mov 0(%eax), %eax + jmp *%esp + +tryharder: + mov CBFS_FILE_OFFSET(%ebx), %ecx + bswap %ecx + add %ebx, %ecx + mov CBFS_FILE_LEN(%ebx), %edi + bswap %edi + add %edi, %ecx + add %eax, %ecx + mov %eax, %edi + not %edi + and %edi, %ecx + mov %ecx, %ebx + + /* look if we should exit */ + mov CBFS_HEADER_PTR, %esi + mov CBFS_HEADER_ROMSIZE(%esi), %ecx + bswap %ecx + not %ecx + add $1, %ecx + + cmp %ebx, %ecx + /* if we're still inside the ROM area, jump back */ + jbe walker + + mov $0, %eax + jmp *%esp Modified: trunk/src/cpu/x86/32bit/entry32.lds =================================================================== --- trunk/src/cpu/x86/32bit/entry32.lds 2009-12-21 15:09:01 UTC (rev 4988) +++ trunk/src/cpu/x86/32bit/entry32.lds 2009-12-23 12:52:56 UTC (rev 4989) @@ -0,0 +1 @@ +ENTRY(protected_start) Modified: trunk/src/mainboard/emulation/qemu-x86/Kconfig =================================================================== --- trunk/src/mainboard/emulation/qemu-x86/Kconfig 2009-12-21 15:09:01 UTC (rev 4988) +++ trunk/src/mainboard/emulation/qemu-x86/Kconfig 2009-12-23 12:52:56 UTC (rev 4989) @@ -6,6 +6,7 @@ select HAVE_PIRQ_TABLE select BOARD_ROMSIZE_KB_256 select WARNINGS_ARE_ERRORS + select TINY_BOOTBLOCK config MAINBOARD_DIR string Modified: trunk/src/mainboard/emulation/qemu-x86/Makefile.inc =================================================================== --- trunk/src/mainboard/emulation/qemu-x86/Makefile.inc 2009-12-21 15:09:01 UTC (rev 4988) +++ trunk/src/mainboard/emulation/qemu-x86/Makefile.inc 2009-12-23 12:52:56 UTC (rev 4989) @@ -1,18 +1,12 @@ initobj-y += crt0.o -crt0-y += ../../../../src/cpu/x86/16bit/entry16.inc crt0-y += ../../../../src/cpu/x86/32bit/entry32.inc -crt0-y += ../../../../src/cpu/x86/16bit/reset16.inc -crt0-y += ../../../../src/arch/i386/lib/id.inc crt0-y += auto.inc obj-y += mainboard.o obj-$(CONFIG_GENERATE_PIRQ_TABLE) += irq_tables.o ldscript-y += ../../../../src/arch/i386/init/ldscript_fallback_cbfs.lb -ldscript-y += ../../../../src/cpu/x86/16bit/entry16.lds ldscript-y += ../../../../src/cpu/x86/32bit/entry32.lds -ldscript-y += ../../../../src/cpu/x86/16bit/reset16.lds -ldscript-y += ../../../../src/arch/i386/lib/id.lds ifdef POST_EVALUATION Modified: trunk/util/cbfstool/cbfs-mkstage.c =================================================================== --- trunk/util/cbfstool/cbfs-mkstage.c 2009-12-21 15:09:01 UTC (rev 4988) +++ trunk/util/cbfstool/cbfs-mkstage.c 2009-12-23 12:52:56 UTC (rev 4989) @@ -122,6 +122,10 @@ mem_end = mend; } + if (data_start < *location) { + data_start = *location; + } + /* allocate an intermediate buffer for the data */ buffer = calloc(data_end - data_start, 1); @@ -133,6 +137,7 @@ /* Copy the file data into the buffer */ for (i = 0; i < headers; i++) { + unsigned int l_start, l_offset = 0; if (elf32_to_native(phdr[i].p_type) != PT_LOAD) continue; @@ -140,9 +145,15 @@ if (elf32_to_native(phdr[i].p_memsz) == 0) continue; - memcpy(buffer + (elf32_to_native(phdr[i].p_paddr) - data_start), - &header[elf32_to_native(phdr[i].p_offset)], - elf32_to_native(phdr[i].p_filesz)); + l_start = elf32_to_native(phdr[i].p_paddr); + if (l_start < *location) { + l_offset = *location - l_start; + l_start = *location; + } + + memcpy(buffer + (l_start - data_start), + &header[elf32_to_native(phdr[i].p_offset)+l_offset], + elf32_to_native(phdr[i].p_filesz)-l_offset); } /* Now make the output buffer */

1 0

memtest failed (atom+945gse)
by Scott.Hsiao 23 Dec '09

23 Dec '09

coreboot ver: 4988 hw: atom + 945gse + ich7m + it8718 memory: 512M DDR2 SO-DIMM memtest86+ ver: v2.11 screen: =======begin====== Memtest86+ v2.11 Atom (0.045) 1600Mhz L1 cache: 24K 3125MB/s L2 cache: 512K 1860MB/s L3 cache: None Memory: 0K Chipset: 0K LinuxBIOS =======end====== complete log: http://sites.google.com/site/hipporepos/pan-duo-la/memtest_fail.txt?attredir ects=0 <http://sites.google.com/site/hipporepos/pan-duo-la/memtest_fail.txt?attredi rects=0&d=1> &d=1 problem: memtest hangs without any detected memory description: I see the DIMM is well configured and coreboot shows the right size of RAM but memtest cannot recognize they at all. I also try to launch the memtest from hdd throught seabios. The result is same. Where should I check? Thanks.

1 0

Fujitsu Siemens D2264-A1
by Bernhard Weiss 22 Dec '09

22 Dec '09

Hi, following the guidelines lined out in the coreboot FAQ the chipsets of this board seem to be supported. Just the board itself is unknown or not listed so far. Any advice which board to select or howto extend an existing board configuration would be helpful. Please find attached the listings of lspci -tvnn, superiotool -dV, flashrom -V and dmidecode. Base Board Information Manufacturer: FUJITSU SIEMENS Product Name: D2264-A1 Version: S26361-D2264-A1 Kind regards Bernhard ______________________________________________________ GRATIS für alle WEB.DE-Nutzer: Die maxdome Movie-FLAT! Jetzt freischalten unter http://movieflat.web.de

1 0

More SeaBIOS timings
by Kevin O'Connor 22 Dec '09

22 Dec '09

I've completed another round of improvements and timings on my epia-cn machine. From power-on to grub serial menu is now 750ms. For comparison, the same equipment with the factory bios takes 9.9s. (To be fair though, I needed to remove the 2.5s boot menu delay in SeaBIOS to get to 750ms.) More background info is available in the thread at: http://www.coreboot.org/pipermail/coreboot/2009-December/054561.html A breakdown of the 750ms reveals: * cpu appears to start running around 350ms * smbus power stabilizes around 400ms * 20ms to program ddr ram controller * 15ms to uncompress coreboot_ram (note flash access wasn't a factor - see below) * 10ms to run coreboot_ram * 35ms to read and uncompress seabios from flash * 40ms to read and uncompress via vga rom from flash * 200ms to run via vga option rom and turn on vga * 10ms for remaining hardware init (the hardware init runs in parallel with the 240ms for vga option rom - the 10ms is what remains after vga finishes). * 10ms time spent in grub (and in grub reads from disk) Changes since last time: * I'm using a SATA SSD (OCZ Vertex 30G) to store grub (and the OS). This device doesn't seem to require a "spin up" delay. * I've enhanced SeaBIOS to support ATA bus mastering DMA. I'll send a patch out separately with the details. This dramatically increases the speed of disk reads. * I've commented out the calls to wbinvd() in coreboot's mtrr cache_disable logic - those calls are expensive and the code seems to work without it. * While waiting for the smbus to power stabilize, I added reads to the flash to seed the cache with the bootblock and coreboot_ram. This eliminates the costly flash read time for that code. Also interesting is adding a gPXE rom (rtl8169) only added 50ms to the total SeaBIOS boot time (I set gPXE's BANNER_TIMEOUT to 0). -Kevin

4 4

KBuild Report [r4988]
by coresystems autobuild service 21 Dec '09

21 Dec '09

[1/116] a-trend/atc-6220 ok. Processing mainboard/a-trend/atc-6220 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_INTEL_SLOT_2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [2/116] a-trend/atc-6240 ok. Processing mainboard/a-trend/atc-6240 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_INTEL_SLOT_2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [3/116] abit/be6-ii_v2_0 ok. Processing mainboard/abit/be6-ii_v2_0 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_INTEL_SLOT_2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [4/116] advantech/pcm-5820 ok. Processing mainboard/advantech/pcm-5820 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_GX1 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x0 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WRITE_HIGH_TABLES = 0x1 +CONFIG_WRITE_HIGH_TABLES = 0x0 [5/116] amd/db800 ok. Processing mainboard/amd/db800 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_LX = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_IRQ_SLOT_COUNT = 0x4 +CONFIG_IRQ_SLOT_COUNT = 0x6 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [6/116] amd/dbm690t ok. Processing mainboard/amd/dbm690t (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-4988/targets/amd/dbm690t/Config-abuild.lb ok Creating builddir...ok -CONFIG_GFXUMA = 0x1 +CONFIG_GFXUMA = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_ROM_SIZE = 0x100000 +CONFIG_ROM_SIZE = 0x80000 [7/116] amd/norwich ok. Processing mainboard/amd/norwich (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_LX = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [8/116] amd/pistachio ok. Processing mainboard/amd/pistachio (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-4988/targets/amd/pistachio/Config-abuild.lb ok Creating builddir...ok -CONFIG_APIC_ID_OFFSET = 0x0 +CONFIG_APIC_ID_OFFSET = 0x8 -CONFIG_GFXUMA = 0x1 +CONFIG_GFXUMA = 0x0 +CONFIG_HAVE_ACPI_TABLES = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 -CONFIG_HAVE_MAINBOARD_RESOURCES = 0x1 +CONFIG_HAVE_MAINBOARD_RESOURCES = 0x0 +CONFIG_HAVE_MP_TABLE = 0x1 -CONFIG_HAVE_OPTION_TABLE = 0x0 +CONFIG_HAVE_OPTION_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x1 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x6 -CONFIG_HT_CHAIN_UNITID_BASE = 0x0 +CONFIG_HT_CHAIN_UNITID_BASE = 0xa -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_ROM_SIZE = 0x100000 +CONFIG_ROM_SIZE = 0x80000 -CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x1 +CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x2 -CONFIG_WAIT_BEFORE_CPUS_INIT = 0x0 +CONFIG_WAIT_BEFORE_CPUS_INIT = 0x1 [9/116] amd/rumba ok. Processing mainboard/amd/rumba (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_GX2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_HAVE_HIGH_TABLES = 0x0 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WRITE_HIGH_TABLES = 0x1 +CONFIG_WRITE_HIGH_TABLES = 0x0 [10/116] amd/serengeti_cheetah ok. Processing mainboard/amd/serengeti_cheetah (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-4988/targets/amd/serengeti_cheetah/Config-abuild.lb ok Creating builddir...ok -CONFIG_ACPI_SSDTX_NUM = 0x1 +CONFIG_ACPI_SSDTX_NUM = 0x0 +CONFIG_HAVE_ACPI_TABLES = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [11/116] amd/serengeti_cheetah_fam10 fail. [12/116] arima/hdama ok. Processing mainboard/arima/hdama (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-4988/targets/arima/hdama/Config-abuild.lb ok Creating builddir...ok -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DCACHE_RAM_BASE = 0xcf000 +CONFIG_DCACHE_RAM_BASE = 0xc8000 -CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0 +CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_DCACHE_RAM_SIZE = 0x8000 -CONFIG_DIMM_SUPPORT = 0x108 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0 +CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x0 +CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [13/116] artecgroup/dbe61 ok. Processing mainboard/artecgroup/dbe61 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_LX = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [14/116] asi/mb_5blgp ok. Processing mainboard/asi/mb_5blgp (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_GX1 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x0 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WRITE_HIGH_TABLES = 0x1 +CONFIG_WRITE_HIGH_TABLES = 0x0 [15/116] asi/mb_5blmp ok. Processing mainboard/asi/mb_5blmp (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_GX1 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_GENERATE_MP_TABLE = 0x0 +CONFIG_GX1_VIDEO = 0x1 +CONFIG_GX1_VIDEOMODE = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x0 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 +CONFIG_SPLASH_GRAPHIC = 0x1 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WRITE_HIGH_TABLES = 0x1 +CONFIG_WRITE_HIGH_TABLES = 0x0 [16/116] asus/a8n_e ok. Processing mainboard/asus/a8n_e (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-4988/targets/asus/a8n_e/Config-abuild.lb ok Creating builddir...ok -CONFIG_APIC_ID_OFFSET = 0x0 +CONFIG_APIC_ID_OFFSET = 0x10 -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DCACHE_RAM_BASE = 0xc8000 +CONFIG_DCACHE_RAM_BASE = 0xcf000 -CONFIG_DCACHE_RAM_SIZE = 0x8000 +CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DIMM_SUPPORT = 0x108 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x0 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [17/116] asus/a8v-e_se ok. Processing mainboard/asus/a8v-e_se (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DIMM_SUPPORT = 0x108 +CONFIG_EPIA_VT8237R_INIT = 0x0 +CONFIG_HAVE_ACPI_TABLES = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_IRQ_SLOT_COUNT = 0xd -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [18/116] asus/m2v-mx_se ok. Processing mainboard/asus/m2v-mx_se (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-4988/targets/asus/m2v-mx_se/Config-abuild.lb ok Creating builddir...ok -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_EPIA_VT8237R_INIT = 0x0 -CONFIG_HAVE_ACPI_RESUME = 0x1 +CONFIG_HAVE_ACPI_RESUME = 0x0 +CONFIG_HAVE_ACPI_TABLES = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 -CONFIG_HAVE_LOW_TABLES = 0x0 +CONFIG_HAVE_LOW_TABLES = 0x1 -CONFIG_HAVE_MAINBOARD_RESOURCES = 0x1 +CONFIG_HAVE_MAINBOARD_RESOURCES = 0x0 -CONFIG_HW_MEM_HOLE_SIZEK = 0x0 +CONFIG_HW_MEM_HOLE_SIZEK = 0x100000 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x1f00000 +CONFIG_RAMBASE = 0x100000 -CONFIG_RAMTOP = 0x2000000 +CONFIG_RAMTOP = 0x200000 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [19/116] asus/mew-am ok. Processing mainboard/asus/mew-am (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 +CONFIG_I810_VIDEO_MB_1MB = 0x1 +CONFIG_I810_VIDEO_MB_512KB = 0x0 +CONFIG_I810_VIDEO_MB_OFF = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 +CONFIG_MMX = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [20/116] asus/mew-vm ok. Processing mainboard/asus/mew-vm (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 -CONFIG_HAVE_OPTION_TABLE = 0x0 +CONFIG_HAVE_OPTION_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 +CONFIG_I810_VIDEO_MB_1MB = 0x1 +CONFIG_I810_VIDEO_MB_512KB = 0x0 +CONFIG_I810_VIDEO_MB_OFF = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 +CONFIG_MMX = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [21/116] asus/p2b-d ok. Processing mainboard/asus/p2b-d (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_INTEL_SLOT_2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [22/116] asus/p2b-ds ok. Processing mainboard/asus/p2b-ds (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_AGP_APERTURE_SIZE = 0x4000000 -CONFIG_APIC_ID_OFFSET = 0x0 +CONFIG_APIC_ID_OFFSET = 0x10 -CONFIG_CPU_ADDR_BITS = 0x24 +CONFIG_CPU_ADDR_BITS = 0x28 -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DCACHE_RAM_BASE = 0xc0000 +CONFIG_DCACHE_RAM_BASE = 0xcf000 -CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0 +CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 -CONFIG_DIMM_SUPPORT = 0x108 -CONFIG_HAVE_HARD_RESET = 0x0 +CONFIG_HAVE_HARD_RESET = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 -CONFIG_HAVE_MOVNTI = 0x0 +CONFIG_HAVE_MOVNTI = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 -CONFIG_HAVE_OPTION_TABLE = 0x0 +CONFIG_HAVE_OPTION_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x0 -CONFIG_HT_CHAIN_UNITID_BASE = 0x1 +CONFIG_HT_CHAIN_UNITID_BASE = 0x0 -CONFIG_HW_MEM_HOLE_SIZEK = 0x0 +CONFIG_HW_MEM_HOLE_SIZEK = 0x100000 -CONFIG_ID_SECTION_OFFSET = 0x10 +CONFIG_ID_SECTION_OFFSET = 0x80 -CONFIG_IRQ_SLOT_COUNT = 0x7 +CONFIG_IRQ_SLOT_COUNT = 0xd -CONFIG_LB_CKS_LOC = 0x7e +CONFIG_LB_CKS_LOC = 0x7b -CONFIG_LB_CKS_RANGE_END = 0x7d +CONFIG_LB_CKS_RANGE_END = 0x7a -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID = 0x0 +CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID = 0x815a -CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x0 +CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1043 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_MEM_TRAIN_SEQ = 0x0 +CONFIG_MEM_TRAIN_SEQ = 0x2 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_ROM_SIZE = 0x40000 +CONFIG_ROM_SIZE = 0x80000 -CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x0 +CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x2 -CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x1 +CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0 -CONFIG_UDELAY_TSC = 0x1 +CONFIG_UDELAY_TSC = 0x0 -CONFIG_USE_DCACHE_RAM = 0x0 +CONFIG_USE_DCACHE_RAM = 0x1 -CONFIG_USE_PRINTK_IN_CAR = 0x0 +CONFIG_USE_PRINTK_IN_CAR = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [23/116] asus/p2b-f ok. Processing mainboard/asus/p2b-f (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_INTEL_SLOT_2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [24/116] asus/p2b ok. Processing mainboard/asus/p2b (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_INTEL_SLOT_2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [25/116] asus/p3b-f ok. Processing mainboard/asus/p3b-f (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_INTEL_SLOT_2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [26/116] axus/tc320 ok. Processing mainboard/axus/tc320 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_GX1 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x6 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x0 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x6 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WRITE_HIGH_TABLES = 0x1 +CONFIG_WRITE_HIGH_TABLES = 0x0 [27/116] azza/pt-6ibd ok. Processing mainboard/azza/pt-6ibd (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_INTEL_SLOT_2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [28/116] bcom/winnet100 ok. Processing mainboard/bcom/winnet100 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_GX1 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x6 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x0 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x6 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WRITE_HIGH_TABLES = 0x1 +CONFIG_WRITE_HIGH_TABLES = 0x0 [29/116] bcom/winnetp680 ok. Processing mainboard/bcom/winnetp680 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-4988/targets/bcom/winnetp680/Config-abuild.lb ok Creating builddir...ok +CONFIG_CN700_VIDEO_MB_128MB = 0x0 +CONFIG_CN700_VIDEO_MB_16MB = 0x0 +CONFIG_CN700_VIDEO_MB_32MB = 0x1 +CONFIG_CN700_VIDEO_MB_64MB = 0x0 +CONFIG_CN700_VIDEO_MB_8MB = 0x0 +CONFIG_CN700_VIDEO_MB_OFF = 0x0 +CONFIG_CPU_VIA_C7 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x7 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_EPIA_VT8237R_INIT = 0x0 +CONFIG_FALLBACK_SIZE = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 [30/116] biostar/m6tba ok. Processing mainboard/biostar/m6tba (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_INTEL_SLOT_2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [31/116] broadcom/blast ok. Processing mainboard/broadcom/blast (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_APIC_ID_OFFSET = 0x0 +CONFIG_APIC_ID_OFFSET = 0x10 -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DIMM_SUPPORT = 0x108 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x1 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x0 -CONFIG_HT_CHAIN_UNITID_BASE = 0x6 +CONFIG_HT_CHAIN_UNITID_BASE = 0x0 -CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0 +CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x1 +CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x2 -CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x1 +CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [32/116] compaq/deskpro_en_sff_p600 ok. Processing mainboard/compaq/deskpro_en_sff_p600 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_INTEL_SLOT_2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [33/116] dell/s1850 ok. Processing mainboard/dell/s1850 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_HAVE_HARD_RESET = 0x1 +CONFIG_HAVE_HARD_RESET = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 -CONFIG_HAVE_MOVNTI = 0x1 +CONFIG_HAVE_MOVNTI = 0x0 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_IOAPIC = 0x1 +CONFIG_IOAPIC = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAX_CPUS = 0x4 +CONFIG_MAX_CPUS = 0x2 -CONFIG_MAX_PHYSICAL_CPUS = 0x1 +CONFIG_MAX_PHYSICAL_CPUS = 0x2 +CONFIG_MMX = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 +CONFIG_SSE = 0x1 -CONFIG_TTYS0_BAUD = 0x4b00 +CONFIG_TTYS0_BAUD = 0x1c200 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [34/116] digitallogic/adl855pc ok. Processing mainboard/digitallogic/adl855pc (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HARD_RESET = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 +CONFIG_MMX = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_SMP = 0x0 +CONFIG_SMP = 0x1 +CONFIG_SSE = 0x1 -CONFIG_UDELAY_IO = 0x1 +CONFIG_UDELAY_IO = 0x0 -CONFIG_UDELAY_TSC = 0x0 +CONFIG_UDELAY_TSC = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [35/116] digitallogic/msm586seg ok. Processing mainboard/digitallogic/msm586seg (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-4988/targets/digitallogic/msm586seg/Config-abuild.lb ok Creating builddir...ok +CONFIG_CPU_AMD_SC520 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x0 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_ROM_SIZE = 0x80000 +CONFIG_ROM_SIZE = 0x40000 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_UDELAY_LAPIC = 0x0 +CONFIG_UDELAY_TSC = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [36/116] digitallogic/msm800sev ok. Processing mainboard/digitallogic/msm800sev (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_LX = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_IRQ_SLOT_COUNT = 0x9 +CONFIG_IRQ_SLOT_COUNT = 0x7 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [37/116] eaglelion/5bcm ok. Processing mainboard/eaglelion/5bcm (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_GX1 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_GX1_VIDEO = 0x1 +CONFIG_GX1_VIDEOMODE = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x0 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 +CONFIG_SPLASH_GRAPHIC = 0x1 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WRITE_HIGH_TABLES = 0x1 +CONFIG_WRITE_HIGH_TABLES = 0x0 [38/116] emulation/qemu-x86 ok. Processing mainboard/emulation/qemu-x86 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-4988/targets/emulation/qemu-x86/Config-abuild.lb ok Creating builddir...ok +CONFIG_CPU_EMULATION_QEMU_X86 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0x8f000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_HAVE_HIGH_TABLES = 0x0 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_UDELAY_LAPIC = 0x0 +CONFIG_UDELAY_TSC = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WRITE_HIGH_TABLES = 0x1 +CONFIG_WRITE_HIGH_TABLES = 0x0 [39/116] gigabyte/ga-6bxc ok. Processing mainboard/gigabyte/ga-6bxc (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_INTEL_SLOT_2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_IRQ_SLOT_COUNT = 0x6 +CONFIG_IRQ_SLOT_COUNT = 0x5 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [40/116] gigabyte/ga_2761gxdk ok. Processing mainboard/gigabyte/ga_2761gxdk (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-4988/targets/gigabyte/ga_2761gxdk/Config-abuild.lb ok Creating builddir...ok -CONFIG_APIC_ID_OFFSET = 0x10 +CONFIG_APIC_ID_OFFSET = 0x16 -CONFIG_HAVE_FALLBACK_BOOT = 0x1 +CONFIG_HAVE_FALLBACK_BOOT = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x0 -CONFIG_MEM_TRAIN_SEQ = 0x2 +CONFIG_MEM_TRAIN_SEQ = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0 +CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x1 -CONFIG_SERIAL_CPU_INIT = 0x1 +CONFIG_SERIAL_CPU_INIT = 0x0 -CONFIG_SMP = 0x0 +CONFIG_SMP = 0x1 -CONFIG_USE_FALLBACK_IMAGE = 0x1 +CONFIG_USE_FALLBACK_IMAGE = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [41/116] gigabyte/m57sli ok. Processing mainboard/gigabyte/m57sli (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-4988/targets/gigabyte/m57sli/Config-abuild.lb ok Creating builddir...ok -CONFIG_APIC_ID_OFFSET = 0x10 +CONFIG_APIC_ID_OFFSET = 0x16 +CONFIG_HAVE_ACPI_TABLES = 0x1 -CONFIG_HAVE_FALLBACK_BOOT = 0x1 +CONFIG_HAVE_FALLBACK_BOOT = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x0 -CONFIG_MEM_TRAIN_SEQ = 0x2 +CONFIG_MEM_TRAIN_SEQ = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0 +CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x1 -CONFIG_SERIAL_CPU_INIT = 0x1 +CONFIG_SERIAL_CPU_INIT = 0x0 -CONFIG_SUPERIO_ITE_IT8716F_OVERRIDE_FANCTL = 0x1 -CONFIG_USE_FALLBACK_IMAGE = 0x1 +CONFIG_USE_FALLBACK_IMAGE = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [42/116] hp/dl145_g3 ok. Processing mainboard/hp/dl145_g3 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_APIC_ID_OFFSET = 0x8 +CONFIG_APIC_ID_OFFSET = 0x10 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x1 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x0 -CONFIG_HT_CHAIN_UNITID_BASE = 0x6 +CONFIG_HT_CHAIN_UNITID_BASE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x1 +CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0 -CONFIG_SERIAL_CPU_INIT = 0x0 +CONFIG_SERIAL_CPU_INIT = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [43/116] hp/e_vectra_p2706t ok. Processing mainboard/hp/e_vectra_p2706t (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 +CONFIG_I810_VIDEO_MB_1MB = 0x1 +CONFIG_I810_VIDEO_MB_512KB = 0x0 +CONFIG_I810_VIDEO_MB_OFF = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 +CONFIG_MMX = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 [44/116] ibm/e325 ok. Processing mainboard/ibm/e325 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_APIC_ID_OFFSET = 0x0 +CONFIG_APIC_ID_OFFSET = 0x8 -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DIMM_SUPPORT = 0x108 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x6 -CONFIG_HT_CHAIN_UNITID_BASE = 0x1 +CONFIG_HT_CHAIN_UNITID_BASE = 0xa -CONFIG_HW_MEM_HOLE_SIZEK = 0x0 +CONFIG_HW_MEM_HOLE_SIZEK = 0x100000 -CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0 +CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x0 +CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x2 -CONFIG_SERIAL_CPU_INIT = 0x1 +CONFIG_SERIAL_CPU_INIT = 0x0 -CONFIG_SMP = 0x1 +CONFIG_SMP = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WAIT_BEFORE_CPUS_INIT = 0x0 +CONFIG_WAIT_BEFORE_CPUS_INIT = 0x1 [45/116] ibm/e326 ok. Processing mainboard/ibm/e326 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-4988/targets/ibm/e326/Config-abuild.lb ok Creating builddir...ok -CONFIG_APIC_ID_OFFSET = 0x0 +CONFIG_APIC_ID_OFFSET = 0x8 -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DIMM_SUPPORT = 0x108 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x6 -CONFIG_HT_CHAIN_UNITID_BASE = 0x1 +CONFIG_HT_CHAIN_UNITID_BASE = 0xa -CONFIG_HW_MEM_HOLE_SIZEK = 0x0 +CONFIG_HW_MEM_HOLE_SIZEK = 0x100000 -CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0 +CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x0 +CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x2 -CONFIG_SERIAL_CPU_INIT = 0x1 +CONFIG_SERIAL_CPU_INIT = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WAIT_BEFORE_CPUS_INIT = 0x0 +CONFIG_WAIT_BEFORE_CPUS_INIT = 0x1 [46/116] iei/juki-511p ok. Processing mainboard/iei/juki-511p (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-4988/targets/iei/juki-511p/Config-abuild.lb ok Creating builddir...ok +CONFIG_CPU_AMD_GX1 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_GX1_VIDEO = 0x1 +CONFIG_GX1_VIDEOMODE = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x0 -CONFIG_HAVE_INIT_TIMER = 0x0 +CONFIG_HAVE_INIT_TIMER = 0x1 -CONFIG_HAVE_OPTION_TABLE = 0x0 +CONFIG_HAVE_OPTION_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 +CONFIG_SPLASH_GRAPHIC = 0x1 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_UDELAY_IO = 0x1 +CONFIG_UDELAY_IO = 0x0 -CONFIG_UDELAY_TSC = 0x0 +CONFIG_UDELAY_TSC = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WRITE_HIGH_TABLES = 0x1 +CONFIG_WRITE_HIGH_TABLES = 0x0 [47/116] iei/nova4899r ok. Processing mainboard/iei/nova4899r (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_GX1 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_GX1_VIDEO = 0x1 +CONFIG_GX1_VIDEOMODE = 0x0 -CONFIG_HAVE_FALLBACK_BOOT = 0x0 +CONFIG_HAVE_FALLBACK_BOOT = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x0 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 +CONFIG_SPLASH_GRAPHIC = 0x1 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WRITE_HIGH_TABLES = 0x1 +CONFIG_WRITE_HIGH_TABLES = 0x0 [48/116] iei/pcisa-lx-800-r10 ok. Processing mainboard/iei/pcisa-lx-800-r10 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_LX = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 -CONFIG_HAVE_INIT_TIMER = 0x0 +CONFIG_HAVE_INIT_TIMER = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_UDELAY_IO = 0x1 +CONFIG_UDELAY_IO = 0x0 -CONFIG_UDELAY_TSC = 0x0 +CONFIG_UDELAY_TSC = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [49/116] intel/d945gclf ok. Processing mainboard/intel/d945gclf (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-4988/targets/intel/d945gclf/Config-abuild.lb ok Creating builddir...ok +CONFIG_CPU_INTEL_CORE = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xffed8000 +CONFIG_DCACHE_RAM_BASE = 0xffdf8000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x5 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 -CONFIG_GENERATE_ACPI_TABLES = 0x1 +CONFIG_GENERATE_ACPI_TABLES = 0x0 -CONFIG_GFXUMA = 0x1 +CONFIG_GFXUMA = 0x0 -CONFIG_HAVE_ACPI_RESUME = 0x1 +CONFIG_HAVE_ACPI_RESUME = 0x0 -CONFIG_HAVE_HARD_RESET = 0x1 +CONFIG_HAVE_HARD_RESET = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 -CONFIG_HAVE_INIT_TIMER = 0x1 +CONFIG_HAVE_INIT_TIMER = 0x0 -CONFIG_HAVE_MAINBOARD_RESOURCES = 0x1 +CONFIG_HAVE_MAINBOARD_RESOURCES = 0x0 -CONFIG_HAVE_MOVNTI = 0x1 +CONFIG_HAVE_MOVNTI = 0x0 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HAVE_SMI_HANDLER = 0x1 +CONFIG_HAVE_SMI_HANDLER = 0x0 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_IOAPIC = 0x1 +CONFIG_IOAPIC = 0x0 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_MAX_CPUS = 0x4 +CONFIG_MAX_CPUS = 0x1 +CONFIG_MMX = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_ROM_SIZE = 0x80000 +CONFIG_ROM_SIZE = 0x100000 +CONFIG_SSE = 0x1 -CONFIG_USE_DCACHE_RAM = 0x1 +CONFIG_USE_DCACHE_RAM = 0x0 [50/116] intel/eagleheights ok. Processing mainboard/intel/eagleheights (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_INTEL_CORE2 = 0x1 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x7 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_ACPI_TABLES = 0x1 -CONFIG_HAVE_HARD_RESET = 0x1 +CONFIG_HAVE_HARD_RESET = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 -CONFIG_HAVE_MAINBOARD_RESOURCES = 0x1 +CONFIG_HAVE_MAINBOARD_RESOURCES = 0x0 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_IOAPIC = 0x1 +CONFIG_IOAPIC = 0x0 -CONFIG_IRQ_SLOT_COUNT = 0x9 +CONFIG_IRQ_SLOT_COUNT = 0x12 -CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x0 +CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x8086 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_MAX_CPUS = 0x4 +CONFIG_MAX_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_USE_DCACHE_RAM = 0x1 +CONFIG_USE_DCACHE_RAM = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [51/116] intel/jarrell ok. Processing mainboard/intel/jarrell (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_ATI_RAGE_XL = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_HAVE_HARD_RESET = 0x1 +CONFIG_HAVE_HARD_RESET = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 -CONFIG_HAVE_MOVNTI = 0x1 +CONFIG_HAVE_MOVNTI = 0x0 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_IOAPIC = 0x1 +CONFIG_IOAPIC = 0x0 -CONFIG_IRQ_SLOT_COUNT = 0x12 +CONFIG_IRQ_SLOT_COUNT = 0x9 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAX_REBOOT_CNT = 0x8 +CONFIG_MAX_REBOOT_CNT = 0x3 +CONFIG_MMX = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 +CONFIG_SSE = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [52/116] intel/mtarvon ok. Processing mainboard/intel/mtarvon (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x5 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 -CONFIG_HAVE_HARD_RESET = 0x1 +CONFIG_HAVE_HARD_RESET = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_IOAPIC = 0x1 +CONFIG_IOAPIC = 0x0 -CONFIG_LB_CKS_LOC = 0x7e +CONFIG_LB_CKS_LOC = 0x7b -CONFIG_LB_CKS_RANGE_END = 0x7d +CONFIG_LB_CKS_RANGE_END = 0x7a -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x5 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_MAX_CPUS = 0x4 +CONFIG_MAX_CPUS = 0x1 +CONFIG_MMX = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 +CONFIG_SSE = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [53/116] intel/truxton ok. Processing mainboard/intel/truxton (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_INTEL_EP80579 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x5 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 -CONFIG_HAVE_HARD_RESET = 0x1 +CONFIG_HAVE_HARD_RESET = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_IOAPIC = 0x1 +CONFIG_IOAPIC = 0x0 -CONFIG_LB_CKS_LOC = 0x7e +CONFIG_LB_CKS_LOC = 0x7b -CONFIG_LB_CKS_RANGE_END = 0x7d +CONFIG_LB_CKS_RANGE_END = 0x7a -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x5 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_MAX_CPUS = 0x4 +CONFIG_MAX_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_SMP = 0x1 +CONFIG_SMP = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [54/116] intel/xe7501devkit ok. Processing mainboard/intel/xe7501devkit (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEBUG = 0x1 +CONFIG_DEBUG = 0x0 +CONFIG_HAVE_ACPI_TABLES = 0x1 -CONFIG_HAVE_HARD_RESET = 0x1 +CONFIG_HAVE_HARD_RESET = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 -CONFIG_HAVE_MOVNTI = 0x1 +CONFIG_HAVE_MOVNTI = 0x0 +CONFIG_HAVE_MP_TABLE = 0x1 -CONFIG_HAVE_OPTION_TABLE = 0x0 +CONFIG_HAVE_OPTION_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_IOAPIC = 0x1 +CONFIG_IOAPIC = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_MMX = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 +CONFIG_SSE = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [55/116] iwill/dk8_htx ok. Processing mainboard/iwill/dk8_htx (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-4988/targets/iwill/dk8_htx/Config-abuild.lb ok Creating builddir...ok -CONFIG_ACPI_SSDTX_NUM = 0x3 +CONFIG_ACPI_SSDTX_NUM = 0x0 -CONFIG_APIC_ID_OFFSET = 0x10 +CONFIG_APIC_ID_OFFSET = 0x8 -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DCACHE_RAM_BASE = 0xc4000 +CONFIG_DCACHE_RAM_BASE = 0xc8000 -CONFIG_DCACHE_RAM_SIZE = 0xc000 +CONFIG_DCACHE_RAM_SIZE = 0x8000 -CONFIG_DIMM_SUPPORT = 0x108 +CONFIG_HAVE_ACPI_TABLES = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HW_MEM_HOLE_SIZEK = 0x80000 +CONFIG_HW_MEM_HOLE_SIZEK = 0x100000 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WAIT_BEFORE_CPUS_INIT = 0x0 +CONFIG_WAIT_BEFORE_CPUS_INIT = 0x1 [56/116] iwill/dk8s2 ok. Processing mainboard/iwill/dk8s2 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_APIC_ID_OFFSET = 0x0 +CONFIG_APIC_ID_OFFSET = 0x8 +CONFIG_ATI_RAGE_XL = 0x1 -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DCACHE_RAM_BASE = 0xcf000 +CONFIG_DCACHE_RAM_BASE = 0xc8000 -CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0 +CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_DCACHE_RAM_SIZE = 0x8000 -CONFIG_DIMM_SUPPORT = 0x108 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x6 -CONFIG_HT_CHAIN_UNITID_BASE = 0x1 +CONFIG_HT_CHAIN_UNITID_BASE = 0xa -CONFIG_HW_MEM_HOLE_SIZEK = 0x0 +CONFIG_HW_MEM_HOLE_SIZEK = 0x100000 -CONFIG_IRQ_SLOT_COUNT = 0xc +CONFIG_IRQ_SLOT_COUNT = 0xb -CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0 +CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAX_CPUS = 0x2 +CONFIG_MAX_CPUS = 0x4 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x0 +CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x2 -CONFIG_SERIAL_CPU_INIT = 0x1 +CONFIG_SERIAL_CPU_INIT = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WAIT_BEFORE_CPUS_INIT = 0x0 +CONFIG_WAIT_BEFORE_CPUS_INIT = 0x1 [57/116] iwill/dk8x ok. Processing mainboard/iwill/dk8x (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_APIC_ID_OFFSET = 0x0 +CONFIG_APIC_ID_OFFSET = 0x8 -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DCACHE_RAM_BASE = 0xcf000 +CONFIG_DCACHE_RAM_BASE = 0xc8000 -CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0 +CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_DCACHE_RAM_SIZE = 0x8000 -CONFIG_DIMM_SUPPORT = 0x108 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x6 -CONFIG_HT_CHAIN_UNITID_BASE = 0x1 +CONFIG_HT_CHAIN_UNITID_BASE = 0xa -CONFIG_HW_MEM_HOLE_SIZEK = 0x0 +CONFIG_HW_MEM_HOLE_SIZEK = 0x100000 -CONFIG_IRQ_SLOT_COUNT = 0x9 +CONFIG_IRQ_SLOT_COUNT = 0xb -CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0 +CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAX_CPUS = 0x2 +CONFIG_MAX_CPUS = 0x4 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x0 +CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x2 -CONFIG_SERIAL_CPU_INIT = 0x1 +CONFIG_SERIAL_CPU_INIT = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WAIT_BEFORE_CPUS_INIT = 0x0 +CONFIG_WAIT_BEFORE_CPUS_INIT = 0x1 [58/116] jetway/j7f24 ok. Processing mainboard/jetway/j7f24 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-4988/targets/jetway/j7f24/Config-abuild.lb ok Creating builddir...ok +CONFIG_CN700_VIDEO_MB_128MB = 0x0 +CONFIG_CN700_VIDEO_MB_16MB = 0x0 +CONFIG_CN700_VIDEO_MB_32MB = 0x1 +CONFIG_CN700_VIDEO_MB_64MB = 0x0 +CONFIG_CN700_VIDEO_MB_8MB = 0x0 +CONFIG_CN700_VIDEO_MB_OFF = 0x0 +CONFIG_CPU_VIA_C7 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x7 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_EPIA_VT8237R_INIT = 0x0 +CONFIG_FALLBACK_SIZE = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 -CONFIG_HAVE_OPTION_TABLE = 0x0 +CONFIG_HAVE_OPTION_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_UDELAY_TSC = 0x1 +CONFIG_UDELAY_TSC = 0x0 [59/116] kontron/986lcd-m ok. Processing mainboard/kontron/986lcd-m (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-4988/targets/kontron/986lcd-m/Config-abuild.lb ok Creating builddir...ok +CONFIG_CPU_INTEL_CORE = 0x1 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x5 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_ACPI_SLIC = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_MAX_CPUS = 0x4 +CONFIG_MAX_CPUS = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 [60/116] kontron/kt690 ok. Processing mainboard/kontron/kt690 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-4988/targets/kontron/kt690/Config-abuild.lb ok Creating builddir...ok +CONFIG_HAVE_ACPI_TABLES = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_ROM_SIZE = 0x100000 +CONFIG_ROM_SIZE = 0x80000 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [61/116] lippert/frontrunner ok. Processing mainboard/lippert/frontrunner (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_GX2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_HAVE_HIGH_TABLES = 0x0 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WRITE_HIGH_TABLES = 0x1 +CONFIG_WRITE_HIGH_TABLES = 0x0 [62/116] lippert/roadrunner-lx ok. Processing mainboard/lippert/roadrunner-lx (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_LX = 0x1 -CONFIG_DEBUG = 0x1 +CONFIG_DEBUG = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [63/116] lippert/spacerunner-lx ok. Processing mainboard/lippert/spacerunner-lx (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_LX = 0x1 -CONFIG_DEBUG = 0x1 +CONFIG_DEBUG = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [64/116] mitac/6513wu ok. Processing mainboard/mitac/6513wu (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x7 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 +CONFIG_I810_VIDEO_MB_1MB = 0x1 +CONFIG_I810_VIDEO_MB_512KB = 0x0 +CONFIG_I810_VIDEO_MB_OFF = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 +CONFIG_MMX = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [65/116] msi/ms6119 ok. Processing mainboard/msi/ms6119 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_INTEL_SLOT_2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x0 +CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1462 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [66/116] msi/ms6147 ok. Processing mainboard/msi/ms6147 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_INTEL_SLOT_2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x0 +CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1462 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [67/116] msi/ms6156 ok. Processing mainboard/msi/ms6156 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_INTEL_SLOT_2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x0 +CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1462 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [68/116] msi/ms6178 ok. Processing mainboard/msi/ms6178 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 +CONFIG_I810_VIDEO_MB_1MB = 0x1 +CONFIG_I810_VIDEO_MB_512KB = 0x0 +CONFIG_I810_VIDEO_MB_OFF = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x0 +CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1462 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 +CONFIG_MMX = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_UDELAY_IO = 0x0 +CONFIG_UDELAY_IO = 0x1 -CONFIG_UDELAY_TSC = 0x1 +CONFIG_UDELAY_TSC = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [69/116] msi/ms7135 ok. Processing mainboard/msi/ms7135 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-4988/targets/msi/ms7135/Config-abuild.lb ok Creating builddir...ok -CONFIG_APIC_ID_OFFSET = 0x0 +CONFIG_APIC_ID_OFFSET = 0x10 -CONFIG_DCACHE_RAM_BASE = 0xc8000 +CONFIG_DCACHE_RAM_BASE = 0xcf000 -CONFIG_DCACHE_RAM_SIZE = 0x8000 +CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DIMM_SUPPORT = 0x108 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_MEM_TRAIN_SEQ = 0x2 +CONFIG_MEM_TRAIN_SEQ = 0x0 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [70/116] msi/ms7260 ok. Processing mainboard/msi/ms7260 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-4988/targets/msi/ms7260/Config-abuild.lb ok Creating builddir...ok -CONFIG_APIC_ID_OFFSET = 0x10 +CONFIG_APIC_ID_OFFSET = 0x16 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 -CONFIG_HAVE_FALLBACK_BOOT = 0x1 +CONFIG_HAVE_FALLBACK_BOOT = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x0 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_MEM_TRAIN_SEQ = 0x2 +CONFIG_MEM_TRAIN_SEQ = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0 +CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x1 -CONFIG_SERIAL_CPU_INIT = 0x1 +CONFIG_SERIAL_CPU_INIT = 0x0 -CONFIG_USE_FALLBACK_IMAGE = 0x1 +CONFIG_USE_FALLBACK_IMAGE = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [71/116] msi/ms9185 ok. Processing mainboard/msi/ms9185 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-4988/targets/msi/ms9185/Config-abuild.lb ok Creating builddir...ok -CONFIG_APIC_ID_OFFSET = 0x8 +CONFIG_APIC_ID_OFFSET = 0x10 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x1 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x0 -CONFIG_HT_CHAIN_UNITID_BASE = 0x6 +CONFIG_HT_CHAIN_UNITID_BASE = 0x0 -CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1022 +CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1462 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x1 +CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0 -CONFIG_SERIAL_CPU_INIT = 0x0 +CONFIG_SERIAL_CPU_INIT = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [72/116] msi/ms9282 ok. Processing mainboard/msi/ms9282 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-4988/targets/msi/ms9282/Config-abuild.lb ok Creating builddir...ok -CONFIG_APIC_ID_OFFSET = 0x10 +CONFIG_APIC_ID_OFFSET = 0x16 -CONFIG_ENABLE_APIC_EXT_ID = 0x1 +CONFIG_ENABLE_APIC_EXT_ID = 0x0 -CONFIG_HAVE_FALLBACK_BOOT = 0x1 +CONFIG_HAVE_FALLBACK_BOOT = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x0 -CONFIG_HW_MEM_HOLE_SIZEK = 0x0 +CONFIG_HW_MEM_HOLE_SIZEK = 0x100000 -CONFIG_MAX_CPUS = 0x4 +CONFIG_MAX_CPUS = 0x2 -CONFIG_MAX_PHYSICAL_CPUS = 0x2 +CONFIG_MAX_PHYSICAL_CPUS = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x1 +CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x2 -CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0 +CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x1 -CONFIG_SERIAL_CPU_INIT = 0x1 +CONFIG_SERIAL_CPU_INIT = 0x0 -CONFIG_USE_FALLBACK_IMAGE = 0x1 +CONFIG_USE_FALLBACK_IMAGE = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [73/116] nec/powermate2000 ok. Processing mainboard/nec/powermate2000 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 +CONFIG_I810_VIDEO_MB_1MB = 0x1 +CONFIG_I810_VIDEO_MB_512KB = 0x0 +CONFIG_I810_VIDEO_MB_OFF = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 +CONFIG_MMX = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [74/116] newisys/khepri ok. Processing mainboard/newisys/khepri (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_APIC_ID_OFFSET = 0x0 +CONFIG_APIC_ID_OFFSET = 0x10 -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0 +CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000 -CONFIG_DIMM_SUPPORT = 0x108 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x0 -CONFIG_HT_CHAIN_UNITID_BASE = 0x1 +CONFIG_HT_CHAIN_UNITID_BASE = 0x0 -CONFIG_IRQ_SLOT_COUNT = 0x9 +CONFIG_IRQ_SLOT_COUNT = 0xb -CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0 +CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x0 +CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x2 -CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x1 +CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [75/116] nvidia/l1_2pvv ok. Processing mainboard/nvidia/l1_2pvv (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-4988/targets/nvidia/l1_2pvv/Config-abuild.lb ok Creating builddir...ok -CONFIG_APIC_ID_OFFSET = 0x10 +CONFIG_APIC_ID_OFFSET = 0x16 -CONFIG_HAVE_FALLBACK_BOOT = 0x1 +CONFIG_HAVE_FALLBACK_BOOT = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x0 -CONFIG_MAX_CPUS = 0x4 +CONFIG_MAX_CPUS = 0x2 -CONFIG_MAX_PHYSICAL_CPUS = 0x2 +CONFIG_MAX_PHYSICAL_CPUS = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0 +CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x1 -CONFIG_SERIAL_CPU_INIT = 0x1 +CONFIG_SERIAL_CPU_INIT = 0x0 -CONFIG_USE_FALLBACK_IMAGE = 0x1 +CONFIG_USE_FALLBACK_IMAGE = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WAIT_BEFORE_CPUS_INIT = 0x1 +CONFIG_WAIT_BEFORE_CPUS_INIT = 0x0 [76/116] olpc/btest ok. Processing mainboard/olpc/btest (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_GX2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_HAVE_HIGH_TABLES = 0x0 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WRITE_HIGH_TABLES = 0x1 +CONFIG_WRITE_HIGH_TABLES = 0x0 [77/116] olpc/rev_a ok. Processing mainboard/olpc/rev_a (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_GX2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_HAVE_HIGH_TABLES = 0x0 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WRITE_HIGH_TABLES = 0x1 +CONFIG_WRITE_HIGH_TABLES = 0x0 [78/116] pcengines/alix1c ok. Processing mainboard/pcengines/alix1c (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_LX = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [79/116] rca/rm4100 ok. Processing mainboard/rca/rm4100 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-4988/targets/rca/rm4100/Config-abuild.lb ok Creating builddir...ok -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HARD_RESET = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 +CONFIG_I830_VIDEO_MB_1MB = 0x0 +CONFIG_I830_VIDEO_MB_512KB = 0x0 +CONFIG_I830_VIDEO_MB_8MB = 0x1 +CONFIG_I830_VIDEO_MB_OFF = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 +CONFIG_MMX = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [80/116] soyo/sy-6ba-plus-iii ok. Processing mainboard/soyo/sy-6ba-plus-iii (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_INTEL_SLOT_2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [81/116] sunw/ultra40 ok. Processing mainboard/sunw/ultra40 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0 +CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000 -CONFIG_DIMM_SUPPORT = 0x108 -CONFIG_ENABLE_APIC_EXT_ID = 0x1 +CONFIG_ENABLE_APIC_EXT_ID = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x0 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [82/116] supermicro/h8dme ok. Processing mainboard/supermicro/h8dme (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-4988/targets/supermicro/h8dme/Config-abuild.lb ok Creating builddir...ok -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 -CONFIG_HAVE_LOW_TABLES = 0x0 +CONFIG_HAVE_LOW_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x0 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_SERIAL_CPU_INIT = 0x0 +CONFIG_SERIAL_CPU_INIT = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WAIT_BEFORE_CPUS_INIT = 0x1 +CONFIG_WAIT_BEFORE_CPUS_INIT = 0x0 [83/116] supermicro/h8dmr ok. Processing mainboard/supermicro/h8dmr (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-4988/targets/supermicro/h8dmr/Config-abuild.lb ok Creating builddir...ok +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x0 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_ROM_SIZE = 0x100000 +CONFIG_ROM_SIZE = 0x80000 -CONFIG_SERIAL_CPU_INIT = 0x0 +CONFIG_SERIAL_CPU_INIT = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WAIT_BEFORE_CPUS_INIT = 0x1 +CONFIG_WAIT_BEFORE_CPUS_INIT = 0x0 [84/116] supermicro/h8dmr_fam10 fail. [85/116] supermicro/x6dai_g ok. Processing mainboard/supermicro/x6dai_g (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_HAVE_HARD_RESET = 0x1 +CONFIG_HAVE_HARD_RESET = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 -CONFIG_HAVE_MOVNTI = 0x1 +CONFIG_HAVE_MOVNTI = 0x0 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_IOAPIC = 0x1 +CONFIG_IOAPIC = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_MMX = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 +CONFIG_SSE = 0x1 -CONFIG_UDELAY_TSC = 0x1 +CONFIG_UDELAY_TSC = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [86/116] supermicro/x6dhe_g ok. Processing mainboard/supermicro/x6dhe_g (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_HAVE_HARD_RESET = 0x1 +CONFIG_HAVE_HARD_RESET = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 -CONFIG_HAVE_MOVNTI = 0x1 +CONFIG_HAVE_MOVNTI = 0x0 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_IOAPIC = 0x1 +CONFIG_IOAPIC = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_MMX = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 +CONFIG_SSE = 0x1 -CONFIG_UDELAY_TSC = 0x1 +CONFIG_UDELAY_TSC = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [87/116] supermicro/x6dhe_g2 ok. Processing mainboard/supermicro/x6dhe_g2 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_HAVE_HARD_RESET = 0x1 +CONFIG_HAVE_HARD_RESET = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 -CONFIG_HAVE_MOVNTI = 0x1 +CONFIG_HAVE_MOVNTI = 0x0 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_IOAPIC = 0x1 +CONFIG_IOAPIC = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_MMX = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 +CONFIG_SSE = 0x1 -CONFIG_UDELAY_TSC = 0x1 +CONFIG_UDELAY_TSC = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [88/116] supermicro/x6dhr_ig ok. Processing mainboard/supermicro/x6dhr_ig (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_HAVE_HARD_RESET = 0x1 +CONFIG_HAVE_HARD_RESET = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 -CONFIG_HAVE_MOVNTI = 0x1 +CONFIG_HAVE_MOVNTI = 0x0 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_IOAPIC = 0x1 +CONFIG_IOAPIC = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_MMX = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 +CONFIG_SSE = 0x1 -CONFIG_UDELAY_TSC = 0x1 +CONFIG_UDELAY_TSC = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [89/116] supermicro/x6dhr_ig2 ok. Processing mainboard/supermicro/x6dhr_ig2 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_HAVE_HARD_RESET = 0x1 +CONFIG_HAVE_HARD_RESET = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 -CONFIG_HAVE_MOVNTI = 0x1 +CONFIG_HAVE_MOVNTI = 0x0 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_IOAPIC = 0x1 +CONFIG_IOAPIC = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_MMX = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 +CONFIG_SSE = 0x1 -CONFIG_UDELAY_TSC = 0x1 +CONFIG_UDELAY_TSC = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [90/116] technexion/tim5690 ok. Processing mainboard/technexion/tim5690 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-4988/targets/technexion/tim5690/Config-abuild.lb ok Creating builddir...ok +CONFIG_HAVE_ACPI_TABLES = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 [91/116] technexion/tim8690 ok. Processing mainboard/technexion/tim8690 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-4988/targets/technexion/tim8690/Config-abuild.lb ok Creating builddir...ok -CONFIG_APIC_ID_OFFSET = 0x0 +CONFIG_APIC_ID_OFFSET = 0x8 -CONFIG_GFXUMA = 0x1 +CONFIG_GFXUMA = 0x0 +CONFIG_HAVE_ACPI_TABLES = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 -CONFIG_HAVE_MAINBOARD_RESOURCES = 0x1 +CONFIG_HAVE_MAINBOARD_RESOURCES = 0x0 +CONFIG_HAVE_MP_TABLE = 0x1 -CONFIG_HAVE_OPTION_TABLE = 0x0 +CONFIG_HAVE_OPTION_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x1 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x6 -CONFIG_HT_CHAIN_UNITID_BASE = 0x0 +CONFIG_HT_CHAIN_UNITID_BASE = 0xa -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x1 +CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x2 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WAIT_BEFORE_CPUS_INIT = 0x0 +CONFIG_WAIT_BEFORE_CPUS_INIT = 0x1 [92/116] technologic/ts5300 ok. Processing mainboard/technologic/ts5300 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-4988/targets/technologic/ts5300/Config-abuild.lb ok Creating builddir...ok +CONFIG_CPU_AMD_SC520 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x0 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_ROM_SIZE = 0x20000 +CONFIG_ROM_SIZE = 0x40000 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 -CONFIG_TTYS0_BASE = 0x2f8 +CONFIG_TTYS0_BASE = 0x3f8 +CONFIG_UDELAY_LAPIC = 0x0 +CONFIG_UDELAY_TSC = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [93/116] televideo/tc7020 ok. Processing mainboard/televideo/tc7020 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_GX1 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x6 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x0 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x6 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WRITE_HIGH_TABLES = 0x1 +CONFIG_WRITE_HIGH_TABLES = 0x0 [94/116] thomson/ip1000 ok. Processing mainboard/thomson/ip1000 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-4988/targets/thomson/ip1000/Config-abuild.lb ok Creating builddir...ok -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HARD_RESET = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 +CONFIG_I830_VIDEO_MB_1MB = 0x0 +CONFIG_I830_VIDEO_MB_512KB = 0x0 +CONFIG_I830_VIDEO_MB_8MB = 0x1 +CONFIG_I830_VIDEO_MB_OFF = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 +CONFIG_MMX = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [95/116] tyan/s1846 ok. Processing mainboard/tyan/s1846 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_INTEL_SLOT_2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [96/116] tyan/s2735 ok. Processing mainboard/tyan/s2735 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_HAVE_HARD_RESET = 0x1 +CONFIG_HAVE_HARD_RESET = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 -CONFIG_HAVE_MOVNTI = 0x1 +CONFIG_HAVE_MOVNTI = 0x0 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_IOAPIC = 0x1 +CONFIG_IOAPIC = 0x0 +CONFIG_MMX = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_SERIAL_CPU_INIT = 0x0 +CONFIG_SERIAL_CPU_INIT = 0x1 +CONFIG_SSE = 0x1 -CONFIG_USE_PRINTK_IN_CAR = 0x1 +CONFIG_USE_PRINTK_IN_CAR = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [97/116] tyan/s2850 ok. Processing mainboard/tyan/s2850 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DCACHE_RAM_BASE = 0xcf000 +CONFIG_DCACHE_RAM_BASE = 0xc8000 -CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0 +CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_DCACHE_RAM_SIZE = 0x8000 -CONFIG_DIMM_SUPPORT = 0x108 -CONFIG_HAVE_HARD_RESET = 0x1 +CONFIG_HAVE_HARD_RESET = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_IOAPIC = 0x1 +CONFIG_IOAPIC = 0x0 -CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0 +CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [98/116] tyan/s2875 ok. Processing mainboard/tyan/s2875 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DCACHE_RAM_BASE = 0xcf000 +CONFIG_DCACHE_RAM_BASE = 0xc8000 -CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0 +CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_DCACHE_RAM_SIZE = 0x8000 -CONFIG_DIMM_SUPPORT = 0x108 -CONFIG_HAVE_HARD_RESET = 0x1 +CONFIG_HAVE_HARD_RESET = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0 +CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [99/116] tyan/s2880 ok. Processing mainboard/tyan/s2880 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_APIC_ID_OFFSET = 0x0 +CONFIG_APIC_ID_OFFSET = 0x10 -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DCACHE_RAM_BASE = 0xcf000 +CONFIG_DCACHE_RAM_BASE = 0xc8000 -CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0 +CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_DCACHE_RAM_SIZE = 0x8000 -CONFIG_DIMM_SUPPORT = 0x108 -CONFIG_HAVE_HARD_RESET = 0x1 +CONFIG_HAVE_HARD_RESET = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x6 -CONFIG_HT_CHAIN_UNITID_BASE = 0x1 +CONFIG_HT_CHAIN_UNITID_BASE = 0xa -CONFIG_IOAPIC = 0x1 +CONFIG_IOAPIC = 0x0 -CONFIG_IRQ_SLOT_COUNT = 0xd +CONFIG_IRQ_SLOT_COUNT = 0x9 -CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0 +CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAX_CPUS = 0x2 +CONFIG_MAX_CPUS = 0x4 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x0 +CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x2 -CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x1 +CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [100/116] tyan/s2881 ok. Processing mainboard/tyan/s2881 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_APIC_ID_OFFSET = 0x0 +CONFIG_APIC_ID_OFFSET = 0x10 -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DCACHE_RAM_BASE = 0xcf000 +CONFIG_DCACHE_RAM_BASE = 0xc8000 -CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0 +CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_DCACHE_RAM_SIZE = 0x8000 -CONFIG_DIMM_SUPPORT = 0x108 -CONFIG_HAVE_HARD_RESET = 0x1 +CONFIG_HAVE_HARD_RESET = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_IOAPIC = 0x1 +CONFIG_IOAPIC = 0x0 -CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0 +CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x0 +CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x2 -CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x1 +CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [101/116] tyan/s2882 ok. Processing mainboard/tyan/s2882 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_APIC_ID_OFFSET = 0x0 +CONFIG_APIC_ID_OFFSET = 0x10 -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DCACHE_RAM_BASE = 0xcf000 +CONFIG_DCACHE_RAM_BASE = 0xc8000 -CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0 +CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_DCACHE_RAM_SIZE = 0x8000 -CONFIG_DIMM_SUPPORT = 0x108 -CONFIG_HAVE_HARD_RESET = 0x1 +CONFIG_HAVE_HARD_RESET = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x6 -CONFIG_HT_CHAIN_UNITID_BASE = 0x1 +CONFIG_HT_CHAIN_UNITID_BASE = 0xa -CONFIG_IOAPIC = 0x1 +CONFIG_IOAPIC = 0x0 -CONFIG_IRQ_SLOT_COUNT = 0xf +CONFIG_IRQ_SLOT_COUNT = 0x9 -CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0 +CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x0 +CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x2 -CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x1 +CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [102/116] tyan/s2885 ok. Processing mainboard/tyan/s2885 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DCACHE_RAM_BASE = 0xcf000 +CONFIG_DCACHE_RAM_BASE = 0xc8000 -CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0 +CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_DCACHE_RAM_SIZE = 0x8000 -CONFIG_DIMM_SUPPORT = 0x108 -CONFIG_ENABLE_APIC_EXT_ID = 0x1 +CONFIG_ENABLE_APIC_EXT_ID = 0x0 -CONFIG_HAVE_HARD_RESET = 0x1 +CONFIG_HAVE_HARD_RESET = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_IOAPIC = 0x1 +CONFIG_IOAPIC = 0x0 -CONFIG_IRQ_SLOT_COUNT = 0xb +CONFIG_IRQ_SLOT_COUNT = 0x9 -CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0 +CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x1 +CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [103/116] tyan/s2891 ok. Processing mainboard/tyan/s2891 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-4988/targets/tyan/s2891/Config-abuild.lb ok Creating builddir...ok -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DCACHE_RAM_BASE = 0xcf000 +CONFIG_DCACHE_RAM_BASE = 0xc8000 -CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0 +CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_DCACHE_RAM_SIZE = 0x8000 -CONFIG_DIMM_SUPPORT = 0x108 +CONFIG_HAVE_ACPI_TABLES = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0 +CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_ROM_SIZE = 0x80000 +CONFIG_ROM_SIZE = 0x100000 -CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x1 +CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0 [104/116] tyan/s2892 ok. Processing mainboard/tyan/s2892 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-4988/targets/tyan/s2892/Config-abuild.lb ok Creating builddir...ok -CONFIG_APIC_ID_OFFSET = 0x0 +CONFIG_APIC_ID_OFFSET = 0x10 -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DCACHE_RAM_BASE = 0xcf000 +CONFIG_DCACHE_RAM_BASE = 0xc8000 -CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0 +CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_DCACHE_RAM_SIZE = 0x8000 -CONFIG_DIMM_SUPPORT = 0x108 +CONFIG_HAVE_ACPI_TABLES = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0 +CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 [105/116] tyan/s2895 ok. Processing mainboard/tyan/s2895 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-4988/targets/tyan/s2895/Config-abuild.lb ok Creating builddir...ok -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DCACHE_RAM_BASE = 0xcf000 +CONFIG_DCACHE_RAM_BASE = 0xc8000 -CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0 +CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_DCACHE_RAM_SIZE = 0x8000 -CONFIG_DIMM_SUPPORT = 0x108 +CONFIG_HAVE_ACPI_TABLES = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_SERIAL_CPU_INIT = 0x0 +CONFIG_SERIAL_CPU_INIT = 0x1 [106/116] tyan/s2912 ok. Processing mainboard/tyan/s2912 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-4988/targets/tyan/s2912/Config-abuild.lb ok Creating builddir...ok -CONFIG_ACPI_SSDTX_NUM = 0x3 +CONFIG_ACPI_SSDTX_NUM = 0x0 -CONFIG_APIC_ID_OFFSET = 0x10 +CONFIG_APIC_ID_OFFSET = 0x16 -CONFIG_HAVE_FALLBACK_BOOT = 0x1 +CONFIG_HAVE_FALLBACK_BOOT = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x0 -CONFIG_MAX_CPUS = 0x4 +CONFIG_MAX_CPUS = 0x2 -CONFIG_MAX_PHYSICAL_CPUS = 0x2 +CONFIG_MAX_PHYSICAL_CPUS = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0 +CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x1 -CONFIG_SERIAL_CPU_INIT = 0x1 +CONFIG_SERIAL_CPU_INIT = 0x0 -CONFIG_USE_FALLBACK_IMAGE = 0x1 +CONFIG_USE_FALLBACK_IMAGE = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WAIT_BEFORE_CPUS_INIT = 0x1 +CONFIG_WAIT_BEFORE_CPUS_INIT = 0x0 [107/116] tyan/s2912_fam10 fail. [108/116] tyan/s4880 ok. Processing mainboard/tyan/s4880 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0 +CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000 -CONFIG_DIMM_SUPPORT = 0x108 -CONFIG_ENABLE_APIC_EXT_ID = 0x1 +CONFIG_ENABLE_APIC_EXT_ID = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x0 -CONFIG_HT_CHAIN_UNITID_BASE = 0x1 +CONFIG_HT_CHAIN_UNITID_BASE = 0x0 -CONFIG_IRQ_SLOT_COUNT = 0x16 +CONFIG_IRQ_SLOT_COUNT = 0xb -CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0 +CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1 -CONFIG_MAX_CPUS = 0x8 +CONFIG_MAX_CPUS = 0x4 -CONFIG_MAX_PHYSICAL_CPUS = 0x4 +CONFIG_MAX_PHYSICAL_CPUS = 0x2 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x0 +CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x2 -CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x1 +CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [109/116] tyan/s4882 ok. Processing mainboard/tyan/s4882 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0 +CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000 -CONFIG_DIMM_SUPPORT = 0x108 -CONFIG_ENABLE_APIC_EXT_ID = 0x1 +CONFIG_ENABLE_APIC_EXT_ID = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x0 -CONFIG_HT_CHAIN_UNITID_BASE = 0x1 +CONFIG_HT_CHAIN_UNITID_BASE = 0x0 -CONFIG_IRQ_SLOT_COUNT = 0x16 +CONFIG_IRQ_SLOT_COUNT = 0xb -CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0 +CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1 -CONFIG_MAX_CPUS = 0x8 +CONFIG_MAX_CPUS = 0x4 -CONFIG_MAX_PHYSICAL_CPUS = 0x4 +CONFIG_MAX_PHYSICAL_CPUS = 0x2 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x2000 +CONFIG_RAMBASE = 0x100000 -CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x0 +CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x2 -CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x1 +CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [110/116] via/epia-cn ok. Processing mainboard/via/epia-cn (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-4988/targets/via/epia-cn/Config-abuild.lb ok Creating builddir...ok +CONFIG_CN700_VIDEO_MB_128MB = 0x0 +CONFIG_CN700_VIDEO_MB_16MB = 0x0 +CONFIG_CN700_VIDEO_MB_32MB = 0x1 +CONFIG_CN700_VIDEO_MB_64MB = 0x0 +CONFIG_CN700_VIDEO_MB_8MB = 0x0 +CONFIG_CN700_VIDEO_MB_OFF = 0x0 +CONFIG_CPU_VIA_C7 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x7 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_EPIA_VT8237R_INIT = 0x0 +CONFIG_FALLBACK_SIZE = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_UDELAY_TSC = 0x1 +CONFIG_UDELAY_TSC = 0x0 [111/116] via/epia-m ok. Processing mainboard/via/epia-m (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-4988/targets/via/epia-m/Config-abuild.lb ok Creating builddir...ok +CONFIG_CPU_VIA_C3 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_FALLBACK_SIZE = 0x0 +CONFIG_HAVE_ACPI_TABLES = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_UDELAY_TSC = 0x1 +CONFIG_UDELAY_TSC = 0x0 [112/116] via/epia-m700 ok. Processing mainboard/via/epia-m700 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-4988/targets/via/epia-m700/Config-abuild.lb ok Creating builddir...ok +CONFIG_CPU_VIA_C7 = 0x1 -CONFIG_DCACHE_RAM_SIZE = 0x2000 +CONFIG_DCACHE_RAM_SIZE = 0x8000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_FALLBACK_SIZE = 0x0 +CONFIG_HAVE_ACPI_TABLES = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x0 -CONFIG_HEAP_SIZE = 0x5000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_IOAPIC = 0x1 +CONFIG_IOAPIC = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x0 +CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1019 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_UDELAY_TSC = 0x1 +CONFIG_UDELAY_TSC = 0x0 -CONFIG_USE_DCACHE_RAM = 0x1 +CONFIG_USE_DCACHE_RAM = 0x0 [113/116] via/epia-n ok. Processing mainboard/via/epia-n (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-4988/targets/via/epia-n/Config-abuild.lb ok Creating builddir...ok +CONFIG_CN400_VIDEO_MB_128MB = 0x0 +CONFIG_CN400_VIDEO_MB_16MB = 0x0 +CONFIG_CN400_VIDEO_MB_32MB = 0x1 +CONFIG_CN400_VIDEO_MB_64MB = 0x0 +CONFIG_CN400_VIDEO_MB_8MB = 0x0 +CONFIG_CN400_VIDEO_MB_OFF = 0x0 +CONFIG_CPU_VIA_C3 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x7 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_FALLBACK_SIZE = 0x0 +CONFIG_HAVE_ACPI_TABLES = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x0 -CONFIG_HAVE_MAINBOARD_RESOURCES = 0x1 +CONFIG_HAVE_MAINBOARD_RESOURCES = 0x0 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_IOAPIC = 0x1 +CONFIG_IOAPIC = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_SMP = 0x1 +CONFIG_SMP = 0x0 -CONFIG_UDELAY_TSC = 0x1 +CONFIG_UDELAY_TSC = 0x0 -CONFIG_WRITE_HIGH_TABLES = 0x1 +CONFIG_WRITE_HIGH_TABLES = 0x0 [114/116] via/epia ok. Processing mainboard/via/epia (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_VIA_C3 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x7 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_FALLBACK_SIZE = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 -CONFIG_HAVE_INIT_TIMER = 0x0 +CONFIG_HAVE_INIT_TIMER = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_UDELAY_IO = 0x1 +CONFIG_UDELAY_IO = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [115/116] via/pc2500e ok. Processing mainboard/via/pc2500e (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-4988/targets/via/pc2500e/Config-abuild.lb ok Creating builddir...ok +CONFIG_CN700_VIDEO_MB_128MB = 0x0 +CONFIG_CN700_VIDEO_MB_16MB = 0x0 +CONFIG_CN700_VIDEO_MB_32MB = 0x1 +CONFIG_CN700_VIDEO_MB_64MB = 0x0 +CONFIG_CN700_VIDEO_MB_8MB = 0x0 +CONFIG_CN700_VIDEO_MB_OFF = 0x0 +CONFIG_CPU_VIA_C7 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_EPIA_VT8237R_INIT = 0x0 +CONFIG_FALLBACK_SIZE = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_USE_OPTION_TABLE = 0x1 +CONFIG_USE_OPTION_TABLE = 0x0 [116/116] via/vt8454c ok. Processing mainboard/via/vt8454c (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-4988/targets/via/vt8454c/Config-abuild.lb ok Creating builddir...ok +CONFIG_CPU_VIA_C7 = 0x1 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x5 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_ACPI_TABLES = 0x1 -CONFIG_HAVE_HARD_RESET = 0x1 +CONFIG_HAVE_HARD_RESET = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x0 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_IOAPIC = 0x1 +CONFIG_IOAPIC = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x0 +CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1019 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x5 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_ROM_SIZE = 0x80000 +CONFIG_ROM_SIZE = 0x100000 -CONFIG_SMP = 0x1 +CONFIG_SMP = 0x0 -CONFIG_UDELAY_TSC = 0x1 +CONFIG_UDELAY_TSC = 0x0 -CONFIG_USE_DCACHE_RAM = 0x1 +CONFIG_USE_DCACHE_RAM = 0x0 -CONFIG_WRITE_HIGH_TABLES = 0x1 +CONFIG_WRITE_HIGH_TABLES = 0x0

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coreboot December 2009