attached patch eliminates some noise in the output of compareboard
(which will show up every couple commits on this list now).
Some variables do not exist in kconfig if they're irrelevant to the
configuration at hands.
The patch hides AMD K8/Fam10h-specific variables on non-K8/Fam10h
boards. Currently they appear as "only in oldstyle build".
There's more to do, this is just the first step.
Once the remaining differences in configuration are done away with,
Kconfig and newconfig should be functionally equivalent on working boards.
Signed-off-by: Patrick Georgi <patrick.georgi(a)coresystems.de>
Sorry for troubles caused by my ldscript patch that triggered slightly
misbehaviour resulting in 4GB image files in abuild. I didn't noticed
such behaviour on my machine and thats why i send it to ML.
I created separated from ld way to reuse space in top 64k not used by bootblock
patch in attachment. Only missing thing in this patch would be option to enable
firing script that calculates size that can be claimed and adjusting gapsize
so it might be disabled by default.
Signed-off: Maciej Pijanka <maciej.pijanka(a)gmail.com>
(or should i add Blames-To: also?)
reg. Linux user #133161
On 11/30/2009 09:39 PM, Scott.Hsiao wrote:
> Hello! Joseph,
> Yes, the process stopped at same place everytime.
> Completed log is attatched.
> Scott Hsiao
> -----Original Message-----
> From: Joseph Smith [mailto:firstname.lastname@example.org]
> Sent: Tuesday, December 01, 2009 10:31 AM
> To: Scott.Hsiao
> Cc: coreboot(a)coreboot.org
> Subject: Re: [coreboot] Atom platform porting problem.
> On 11/30/2009 03:29 AM, Scott.Hsiao wrote:
>> I am porting coreboot to a Intel Atom based mainboard which
>> incorperate atom (N270) + 945GSE + it8718f.
>> The initial progress of north bridge seems okay but I got error in the
>> "dev_initialize" function.
>> Here are the partial output:
>> Initializing devices...
>> Root Device init
>> APIC_CLUSTER: 0 init
>> malloc Enter, size 91, free_mem_ptr 0013b998 malloc 0013b998
>> start_eip=0x0000a000, offset=0x00100000, code_size=0x0000005b
>> Initializing SMM handler... ... pmbase = 0x0500
>> SMI_STS: PM1
>> PM1_STS: WAK PWRBTN TMROF
>> ... raise SMI#
>> Initializing CPU #0
>> CPU: vendor Intel device 106c2
>> CPU: family 06, model 1c, stepping 02
>> Using generic cpu ops (good)
>> Enabling cache
>> microcode_info: sig = 0x000106c2 pf=0x00000004 rev = 0x00000000
>> CPU: Intel(R) Core(TM) CPU N270 @ 1.60GHz.
>> Setting fixed MTRRs(0-88) Type: UC
>> Setting fixed MTRRs(0-16) Type: WB
>> Setting fixed MTRRs(24-88) Type: WB
>> DONE fixed MTRRs
>> call enable_fixed_mtrr()
>> Setting variable MTRR 0, base: 0MB, range: 512MB, type WB
>> ADDRESS_MASK_HIGH=0xf Unexpected Exception: 13 @ 10:001025e9 - Halting
>> Code: 0 eflags: 00010002
>> eax: e0000800 ebx: 0000000f ecx: 00000201 edx: 0000000f
>> edi: e0000000 esi: 00000000 ebp: 0000000f esp: 00139df4
> Hello Scott,
> Could you send me your whole boot log?
> Are you getting the Unexpected Exception errors in the same place every
> boot? Or, is it in a different spot each time?
Wow it looks like you are getting pretty far in the boot process,
congrats :-) I think there may be something wrong with how the MTRRs
are setup. I think you are supposed to have more than one variable MTRR?
My suggestion would be to get inteltool working on the board, and then
you can tell what the MTRRs look like with the vender bios and compare
it with your code. I hope that helps.