coreboot December 2009

coreboot@coreboot.org

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[commit] r4975 - trunk/util/cbfstool
by svn＠coreboot.org 06 Dec '09

06 Dec '09

Author: stuge Date: 2009-12-06 13:14:39 +0100 (Sun, 06 Dec 2009) New Revision: 4975 Modified: trunk/util/cbfstool/common.c Log: cbfstool: Fill memory allocated in create_cbfs_file() with 0xff This should improve programming speed a bit. Signed-off-by: Peter Stuge <peter(a)stuge.se> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/util/cbfstool/common.c =================================================================== --- trunk/util/cbfstool/common.c 2009-12-02 21:11:12 UTC (rev 4974) +++ trunk/util/cbfstool/common.c 2009-12-06 12:14:39 UTC (rev 4975) @@ -279,6 +279,7 @@ headersize); exit(1); } + memset(newdata, 0xff, *datasize + headersize); struct cbfs_file *nextfile = (struct cbfs_file *)newdata; strncpy(nextfile->magic, "LARCHIVE", 8); nextfile->len = htonl(*datasize);

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Some SeaBIOS timings
by Kevin O'Connor 05 Dec '09

05 Dec '09

I decided to rerun some timing tests on my epia-cn. With some hacking, I've gotten the time from power-on to SeaBIOS boot menu down to 850ms. Of this time, 530ms is coreboot, 210ms is via vga rom, 60ms is usb init (and other hardware probes), and 30ms is time to copy and decompress vga rom from flash. This rom is pretty small too (under 128K) - 20K for bootblock, 30K for coreboot_ram, 33K for seabios, and 36K for via vga rom. To get to these numbers I had to disconnect my ATA drive - it's spinup time dominates startup otherwise (9 seconds from power on). I'm hopeful the times shown would be representative if I had an SSD drive. I also needed to hack coreboot to improve caching. I modified entry16.inc to turn on caching of the rom as soon as possible, I modified auto.c to make sure ram was cached prior to decompressing coreboot_ram, and finally I modified the permanent mtrr setup to leave the rom cached for seabios. As an aside, I think coreboot could improve in this area. It seems as if each board is tasked with setting up caching - I'm sure epia-cn is not the exception with unoptimized caches. I'm attaching the serial output below. The timing numbers quoted above are from a program that times the serial responses. This program also takes into account the cost to send serial messages and subtracts that time from the reports. I believe the numbers shown are representative of times had debugging been disabled. My epia-cn seems to write a null byte to the serial port when I press the power button - I'm using that to time the rest of the boot. I suspect much of the 400ms to the first coreboot message is due to power stabilization prior to cpu execution. -Kevin ======================= 00.000: <00> 00.008: <00> 00.399: 0 00.400: 00.401: coreboot-2.0.0-r4967M-epiacn Wed Dec 2 20:01:30 EST 2009 starting... 00.426: Stage: loading fallback/coreboot_ram @ 0x4000 (114688 bytes), entry @ 0x4000 00.459: coreboot-2.0.0-r4967M-epiacn Wed Dec 2 20:01:30 EST 2009 booting... 00.479: clocks_per_usec: 1501 00.481: Enumerating buses... 00.481: Finding PCI configuration type. 00.484: done 00.483: Allocating resources... 00.481: Reading resources... 00.487: PNP: 002e.b missing read_resources 00.485: APIC: 00 missing read_resources 00.485: Done reading resources. 00.488: skipping PNP: 002e.1@74 fixed resource, size=0! 00.484: skipping PNP: 002e.b@60 fixed resource, size=0! 00.489: Setting resources... 00.488: ERROR: PNP: 002e.3 74 drq size: 0x0000000001 not assigned 00.491: PNP: 002e.b missing set_resources 00.488: ERROR: PNP: 002e.4 60 io size: 0x0000000008 not assigned 00.491: ERROR: PNP: 002e.4 70 irq size: 0x0000000001 not assigned 00.489: ERROR: PNP: 002e.6 70 irq size: 0x0000000001 not assigned 00.490: Done setting resources. 00.490: Done allocating resources. 00.494: Enabling resources... 00.492: PCI: 00:00.3 missing enable_resources 00.491: PNP: 002e.b missing enable_resources 00.494: done. 00.493: Initializing devices... 00.493: Primary IDE interface enabled 00.497: Secondary IDE interface enabled 00.494: Initializing CPU #0 00.494: Detected VIA Model D C7-D 00.499: Voltage: 1084mV (min 1084mV; max 1084mV) 00.496: CPU multiplier: 15x (min 15x; max 15x) 00.495: Current voltage: 1084mV 00.500: Current CPU multiplier: 15x 00.497: Enabling cache 00.498: Running out of variable MTRRs! 00.501: Disabling local apic...done. 00.500: CPU #0 initialized 00.505: Devices initialized 00.503: Copying Interrupt Routing Table to 0x000f0000... done. 00.502: Copying Interrupt Routing Table to 0x3dff0400... done. 00.505: ACPI: Writing ACPI tables at 3dff1400... 00.503: ACPI: done. 00.503: Multiboot Information structure has been written. 00.537: Start bios (version pre-0.4.3-20091202_003935-morn.localdomain) 00.539: Found mainboard via epia-cn 00.540: Found CBFS header at 0xffffaae0 00.542: Ram Size=0x3dff0000 00.542: CPU Mhz=1501 00.543: No apic - only the main cpu is present. 00.545: Copying ACPI RSDP from 0x3dff1400 to 0x000fdc00 00.543: SMBIOS ptr=0x000fdbe0 table=0x3dfef800 00.548: Scan for VGA option rom 00.579: Running option rom at c000:0003 00.581: fail handle_155fXX:23(86): 00.582: a=00005f0b b=00010100 c=00000044 d=00000110 ds=0000 es=f000 ss=0000 00.583: si=0000ab66 di=00000044 bp=00000000 sp=00006e82 cs=c000 ip=c996 f=0006 00.582: fail handle_155fXX:23(86): 00.584: a=00005f01 b=00010100 c=00000044 d=00000110 ds=0000 es=f000 ss=0000 00.585: si=0000ab66 di=00000044 bp=00000000 sp=00006e68 cs=c000 ip=c8c6 f=0002 00.768: fail handle_155fXX:23(86): 00.770: a=00005f02 b=00010001 c=00000000 d=000003c2 ds=0000 es=f000 ss=0000 00.769: si=00000001 di=00000044 bp=00000000 sp=00006e96 cs=c000 ip=c8f9 f=0002 00.773: fail handle_155fXX:23(86): 00.771: a=00005f18 b=00010200 c=00000044 d=000003c2 ds=0000 es=f000 ss=0000 00.773: si=00000000 di=00000044 bp=00000000 sp=00006e9c cs=c000 ip=ca89 f=0006 00.784: Turning on vga console 00.790: Starting SeaBIOS (version pre-0.4.3-20091202_003935-morn.localdomain) 00.790: 00.790: ebda moved from 9f400 to 9f000 00.790: Found 1 lpt ports 00.794: Found 2 serial ports 00.792: ATA controller 0 at 24a0/24b0 (dev 78 prog_if 8f) 00.792: ATA controller 1 at 24a8/24b4 (dev 78 prog_if 8f) 00.792: ATA controller 2 at 1f0/3f0 (dev 79 prog_if 8a) 00.796: Got ps2 nak (status=d1); continuing 00.793: ATA controller 3 at 170/370 (dev 79 prog_if 8a) 00.827: config_usb: 0x000fdf94 1 00.851: Scan for option roms 00.853: Press F12 for boot menu. 00.854: 03.390: Returned 28672 bytes of ZoneHigh 03.393: e820 map has 5 items: 03.394: 0: 0000000000000000 - 000000000009f000 = 1 03.394: 1: 000000000009f000 - 00000000000a0000 = 2 03.396: 2: 00000000000f0000 - 0000000000100000 = 2 03.396: 3: 0000000000100000 - 000000003dfe7000 = 1 03.397: 4: 000000003dfe7000 - 000000003e000000 = 2 03.398: enter handle_19: 03.398: NULL ======================= coreboot.final.rom: 1024 kB, bootblocksize 21248, romsize 1048576, offset 0x0 Alignment: 64 bytes Name Offset Type Size fallback/payload 0x0 payload 33364 fallback/coreboot_ram 0x82c0 stage 30820 pci1106,3344.rom.lzma 0xfb80 optionrom 36368 0x18a00 null 926392

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Serial Debugging.
by David Houston 05 Dec '09

05 Dec '09

Hi! I have finally got round to making myself a IDC Serial header for debugging purposes. http://www.maplin.co.uk/Module.aspx?ModuleNo=29968 <--- would it be ok to get a male to female converter for this adapter and will it still work ok with coreboot? Cheer guys Dave ------------- root(a)crankyadmin.net cranky(a)archlinux.us

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Re: [coreboot] GeodeLX RAM initialisation issue
by Daniel Mack 04 Dec '09

04 Dec '09

(sorry I can't post a proper reply message, I picked that up from the archives) Nathan Williams <nathan at traverse.com.au> wrote: > I am suspicious that the reset problem only occurs when I'm using a > laptop hard drive off the 44pin IDE connector on our board. I have tried > booting with a 3.5" drive and external 12V, but I can't replicate the > problem. With the 3.5" drive, a reboot from fsck works fine. Hopefully > the next PCB revision should perform better because we've moved the 5V > plane further away from the DDR tracks. > > I don't know if I mentioned another problem that has similar symptoms. > Some RAM causes the same cache disable problem, even if there are no > IDE devices connected. This happens from power-up, so it's not a reset > issue. I'm facing a very similar issue here on an ALIX.2D board which is based on the same chipset. The problem happens to occur only sometimes, just like you described it, and resetting from Linux gives a higher change of provoking it. However, I also have once out of 20 power-up cycles as well. What's really strange about that is the fact that sometimes, not even power cycling will fix it - coreboot will always ever stop at the same point (from what I've traced, exactly at the same instructions that you pointed out). Powering off and waiting for ~10 minutes likely brings the board back to life. Connecting or disconnecting extern IDE44 drives does not appear to affect the probability, though. One more thing that bring some awareness is that the effect is harder to trigger when booting from an external LPC flash emulator (in contrast to coreboot flashed to the internal LPC). I urgently need to resolve that and would appreciate any more hints about where to add more code for flushing caches and the like. I also suspect the reset vector to not properly flush the hardware, but I'm somewhat lost in this codebase I must admit, and Geode is also nothing I'm terribly familiar with. Thanks, Daniel

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Coreboot fails to initialize on ASUS A8V-E SE
by Jonathan Rogers 04 Dec '09

04 Dec '09

I just built coreboot from SVN using the kconfig system for my ASUS A8V-E SE. However, I never get anything after the "now booting... fallback" message on the serial port. Also, the hard drive activity light stays on solid. I had coreboot working fine on this exact board over a year ago. Then, I had to use the manual build method. Back then, even when the video card didn't initialize, I got a lot more output on the serial port. What should I try next? Do I still need to use the manual build method for this board? -- Jonathan Rogers

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Re: [coreboot] howto build qemu bios image with VGA console support?
by Myles Watson 04 Dec '09

04 Dec '09

> Please give me some directions to enable the VGA outout. The best way is to use Kconfig. 1. make menuconfig 2. Select [*] Use VGA console once initialized in the Console Options menu 3. make clean 4. make Thanks, Myles

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Re: [coreboot] Coreboot fails to initialize on ASUS A8V-E SE
by Myles Watson 03 Dec '09

03 Dec '09

> Thanks. I tried this patch and built it with kconfig, but it still hangs. I'm assuming that it hangs in the same spot, right? Since I don't have the board, I can only suggest narrowing down where it hangs. You could insert more print statements liberally, etc. You could try commenting out enumerate_ht_chain() in cache_as_ram_auto.c, and see if that gets you farther. Sorry it's broken. Myles

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AMD ASB1 Package L325 & L625
by Libra Li 03 Dec '09

03 Dec '09

Hello, Can the coreboot support AMD CPU L325 & L625 on version 2? Can it working on L325+RS690 & L625+RS690? Thanks.

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Biostar M6TLD and Lzma decompress error
by Maciej Pijanka 03 Dec '09

03 Dec '09

Hello I just enabled LZMA compression, and bootlog looks like one attached (and its looping over jump to boot code at 0x100000 endlessly until i power down) best regards Maciej -- Maciej Pijanka reg. Linux user #133161

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Biostar M6TLD
by Maciej Pijanka 03 Dec '09

03 Dec '09

Hello I have biostar M6TLD, it survives already raminit, patch is in attachment, also log from boot and config. Payload is uncompressed since i had problems with error in decompression from lzma, and current payload is coreinfo. Machine reboots at point indicated in log but only difference between next loops is like that one below, diff between two restarts from same log. Jumping to image. coreboot-2.3 Thu Dec 3 00:30:36 CET 2009 booting... Calibrating delay loop... -end 1ee10434f, start 1c570413d +end 2c5cfc8a0, start 29d2fc6b1 32-bit delta 650 calibrate_tsc 32-bit result is 650 clocks_per_usec: 650 Anyone has idea how to debug why it restarts? I am not placing signed off yet as it don't work unless producing endless stream of coreboot attempts to start is working. best regards Maciej -- Maciej Pijanka reg. Linux user #133161

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coreboot December 2009