On 11/30/2009 09:39 PM, Scott.Hsiao wrote:
Hello! Joseph, Yes, the process stopped at same place everytime. Completed log is attatched.
Scott Hsiao
-----Original Message----- From: Joseph Smith [mailto:joe@settoplinux.org] Sent: Tuesday, December 01, 2009 10:31 AM To: Scott.Hsiao Cc: coreboot@coreboot.org Subject: Re: [coreboot] Atom platform porting problem.
On 11/30/2009 03:29 AM, Scott.Hsiao wrote:
I am porting coreboot to a Intel Atom based mainboard which incorperate atom (N270) + 945GSE + it8718f. The initial progress of north bridge seems okay but I got error in the "dev_initialize" function. Here are the partial output: .... Initializing devices... Root Device init APIC_CLUSTER: 0 init malloc Enter, size 91, free_mem_ptr 0013b998 malloc 0013b998 start_eip=0x0000a000, offset=0x00100000, code_size=0x0000005b Initializing SMM handler... ... pmbase = 0x0500 SMI_STS: PM1 PM1_STS: WAK PWRBTN TMROF GPE0_STS: TCO_STS: ... raise SMI# Initializing CPU #0 CPU: vendor Intel device 106c2 CPU: family 06, model 1c, stepping 02 Using generic cpu ops (good) Enabling cache microcode_info: sig = 0x000106c2 pf=0x00000004 rev = 0x00000000 CPU: Intel(R) Core(TM) CPU N270 @ 1.60GHz. Setting fixed MTRRs(0-88) Type: UC Setting fixed MTRRs(0-16) Type: WB Setting fixed MTRRs(24-88) Type: WB DONE fixed MTRRs call enable_fixed_mtrr() Setting variable MTRR 0, base: 0MB, range: 512MB, type WB ADDRESS_MASK_HIGH=0xf Unexpected Exception: 13 @ 10:001025e9 - Halting Code: 0 eflags: 00010002 eax: e0000800 ebx: 0000000f ecx: 00000201 edx: 0000000f edi: e0000000 esi: 00000000 ebp: 0000000f esp: 00139df4
Hello Scott, Could you send me your whole boot log?
Are you getting the Unexpected Exception errors in the same place every boot? Or, is it in a different spot each time?
Wow it looks like you are getting pretty far in the boot process, congrats :-) I think there may be something wrong with how the MTRRs are setup. I think you are supposed to have more than one variable MTRR?
My suggestion would be to get inteltool working on the board, and then you can tell what the MTRRs look like with the vender bios and compare it with your code. I hope that helps.
DONE fixed MTRRs call enable_fixed_mtrr() Setting variable MTRR 0, base: 0MB, range: 512MB, type WB ADDRESS_MASK_HIGH=0xf Unexpected Exception: 13 @ 10:001025e9 - Halting Code: 0 eflags: 00010002 eax: e0000800 ebx: 0000000f ecx: 00000201 edx: 0000000f edi: e0000000 esi: 00000000 ebp: 0000000f esp: 00139df4
The register contents look like they are from setting the MTRR, so I'd think the problem was there.
It seems like some processors don't like having too many bits of the MTRRs set. I would suggest hacking it so that it doesn't set the upper bits to see if that makes a difference.
Thanks, Myles
Hi Scott,
I am also working on Intel atom based platform. I got the same problem Please try to change the following line /* Setup MTRRs */ x86_setup_mtrrs(36);
to
/* Setup MTRRs */ x86_setup_mtrrs(32);
Atom support only 32 bit address lines
-----Original Message----- From: coreboot-bounces@coreboot.org [mailto:coreboot-bounces@coreboot.org] On Behalf Of Myles Watson Sent: Tuesday, December 01, 2009 9:04 AM To: 'Scott.Hsiao'; 'coreboot' Subject: Re: [coreboot] Atom platform porting problem.
DONE fixed MTRRs call enable_fixed_mtrr() Setting variable MTRR 0, base: 0MB, range: 512MB, type WB ADDRESS_MASK_HIGH=0xf Unexpected Exception: 13 @ 10:001025e9 -
Halting
Code: 0 eflags: 00010002 eax: e0000800 ebx: 0000000f ecx: 00000201 edx: 0000000f edi: e0000000 esi: 00000000 ebp: 0000000f esp: 00139df4
The register contents look like they are from setting the MTRR, so I'd think the problem was there.
It seems like some processors don't like having too many bits of the MTRRs set. I would suggest hacking it so that it doesn't set the upper bits to see if that makes a difference.
Thanks, Myles
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Hi! Mansoor, It works after adding your patch. Now coreboot can go on to load the payload (and die XD) and this is just a second time trial build. Seems like I have more work to do now.
Thank you to everyone.
Scott Hsiao
-----Original Message----- From: Mansoor [mailto:mansoor@iwavesystems.com] Sent: Tuesday, December 01, 2009 1:37 PM To: 'Myles Watson'; 'Scott.Hsiao'; 'coreboot' Subject: RE: [coreboot] Atom platform porting problem.
Hi Scott,
I am also working on Intel atom based platform. I got the same problem Please try to change the following line /* Setup MTRRs */ x86_setup_mtrrs(36);
to
/* Setup MTRRs */ x86_setup_mtrrs(32);
Atom support only 32 bit address lines
-----Original Message----- From: coreboot-bounces@coreboot.org [mailto:coreboot-bounces@coreboot.org] On Behalf Of Myles Watson Sent: Tuesday, December 01, 2009 9:04 AM To: 'Scott.Hsiao'; 'coreboot' Subject: Re: [coreboot] Atom platform porting problem.
DONE fixed MTRRs call enable_fixed_mtrr() Setting variable MTRR 0, base: 0MB, range: 512MB, type WB ADDRESS_MASK_HIGH=0xf Unexpected Exception: 13 @ 10:001025e9 -
Halting
Code: 0 eflags: 00010002 eax: e0000800 ebx: 0000000f ecx: 00000201 edx: 0000000f edi: e0000000 esi: 00000000 ebp: 0000000f esp: 00139df4
The register contents look like they are from setting the MTRR, so I'd think the problem was there.
It seems like some processors don't like having too many bits of the MTRRs set. I would suggest hacking it so that it doesn't set the upper bits to see if that makes a difference.
Thanks, Myles
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DISCLAIMER: This e-mail and any attachment (s) is for authorised use by the intended recipient (s) only. It may contain proprietary material, confidential information and/or be subject to the legal privilege of iWave Systems Technologies Private Limited. If you have received this message in error, please notify the originator immediately. If you are not the intended recipient, you are notified that you are strictly prohibited from retaining, using, copying, alerting or disclosing the content of this message. Thank you for your co-operation.
---------------------------------------------------------------------------- --- DISCLAIMER: This e-mail and any attachment (s) is for authorised use by the intended recipient (s) only. It may contain proprietary material, confidential information and/or be subject to the legal privilege of iWave Systems Technologies Private Limited. If you have received this message in error, please notify the originator immediately. If you are not the intended recipient, you are notified that you are strictly prohibited from retaining, using, copying, alerting or disclosing the content of this message. Thank you for your co-operation. ---------------------------------------------------------------------------- --
-
Joseph Smith -
Mansoor -
Myles Watson -
Scott.Hsiao