coreboot January 2009

coreboot@coreboot.org

66 participants
320 discussions

Question about dual operating systems
by Matt Johnson 09 Jan '09

09 Jan '09

I was wondering, let's say I install linux using Wubi (so it isn't a separate partition) and want to use coreboot to boot to linux. Will cause problems? Thanks, Matt

2 1

r1112 - coreboot-v3/device
by svn＠coreboot.org 09 Jan '09

09 Jan '09

Author: myles Date: 2009-01-09 15:17:06 +0100 (Fri, 09 Jan 2009) New Revision: 1112 Modified: coreboot-v3/device/device.c Log: This patch adds the domain's resources and all links to the tree traversal for constraining resources. Build and boot tested on qemu, serengeti, and alix2c3. Signed-off-by: Myles Watson <mylesgw(a)gmail.com> Acked-by: Ward Vandewege <ward(a)gnu.org> Modified: coreboot-v3/device/device.c =================================================================== --- coreboot-v3/device/device.c 2009-01-08 20:07:21 UTC (rev 1111) +++ coreboot-v3/device/device.c 2009-01-09 14:17:06 UTC (rev 1112) @@ -705,41 +705,42 @@ #define MEM_TYPE (IORESOURCE_MEM) #define IO_TYPE (IORESOURCE_IO) - /* Descend into every child and look for fixed resources. */ - for (child=dev->link[0].children; child; child = child->sibling) { - constrain_resources(child, limits); - for (i = 0; i<child->resources; i++) { - res = &child->resource[i]; - if (!(res->flags & IORESOURCE_FIXED)) - continue; + /* Constrain limits based on the fixed resources of this device. */ + for (i = 0; i<dev->resources; i++) { + res = &dev->resource[i]; + if (!(res->flags & IORESOURCE_FIXED)) + continue; - /* PREFETCH, MEM, or I/O - skip any others. */ - if ((res->flags & MEM_MASK) == PREF_TYPE) - lim = &limits->pref; - else if ((res->flags & MEM_MASK) == MEM_TYPE) - lim = &limits->mem; - else if ((res->flags & IO_MASK) == IO_TYPE) - lim = &limits->io; - else - continue; + /* PREFETCH, MEM, or I/O - skip any others. */ + if ((res->flags & MEM_MASK) == PREF_TYPE) + lim = &limits->pref; + else if ((res->flags & MEM_MASK) == MEM_TYPE) + lim = &limits->mem; + else if ((res->flags & IO_MASK) == IO_TYPE) + lim = &limits->io; + else + continue; - /* Is it already outside the limits? */ - if (res->size && - (((res->base + res->size -1) < lim->base) || - (res->base > lim->limit))) - continue; + /* Is it already outside the limits? */ + if (res->size && (((res->base + res->size -1) < lim->base) || + (res->base > lim->limit))) + continue; - /* Choose to be above or below fixed resources. This - * check is signed so that "negative" amounts of space - * are handled correctly. - */ - if ((s64)(lim->limit - (res->base + res->size -1)) > - (s64)(res->base - lim->base)) - lim->base = res->base + res->size; - else - lim->limit = res->base -1; - } + /* Choose to be above or below fixed resources. This + * check is signed so that "negative" amounts of space + * are handled correctly. + */ + if ((s64)(lim->limit - (res->base + res->size -1)) > + (s64)(res->base - lim->base)) + lim->base = res->base + res->size; + else + lim->limit = res->base -1; } + + /* Descend into every child and look for fixed resources. */ + for (i = 0; i< dev->links; i++) + for (child=dev->link[i].children; child; child = child->sibling) + constrain_resources(child, limits); } static void avoid_fixed_resources(struct device *dev)

1 0

[flashrom]: AAI program supported?
by Bao, Zheng 09 Jan '09

09 Jan '09

Hi, all, I am trying to add AAI command support in flashrom. We know that some chips support AAI while others don't. I want to add a member in struct flashchip to indicate whether this chip support AAI. AAI programming improves the speed of writing. Does anyone give some advice? Do you guys think it makes sense? Zheng

2 1

[PATCH] flashrom: Add erase and write functions to Atmel AT25* and AT26*
by Carl-Daniel Hailfinger 09 Jan '09

09 Jan '09

Add erase and write functions to the following chip definitions: AT25DF021 AT25DF041A AT25DF081 AT25DF161 AT25DF321 AT25DF321A AT25DF641 AT25F512B AT25FS010 AT25FS040 AT26DF081A AT26DF161 AT26DF161A AT26DF321 AT26F004 Straight from the data sheets, untested because I lack the hardware. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: flashrom-atmel_readerasewrite/flashchips.c =================================================================== --- flashrom-atmel_readerasewrite/flashchips.c (Revision 3852) +++ flashrom-atmel_readerasewrite/flashchips.c (Arbeitskopie) @@ -123,8 +123,8 @@ .page_size = 256, .tested = TEST_UNTESTED, .probe = probe_spi_rdid, - .erase = NULL, - .write = NULL, + .erase = spi_chip_erase_60_c7, + .write = spi_chip_write, .read = spi_chip_read, }, @@ -137,8 +137,8 @@ .page_size = 256, .tested = TEST_UNTESTED, .probe = probe_spi_rdid, - .erase = NULL, - .write = NULL, + .erase = spi_chip_erase_60_c7, + .write = spi_chip_write, .read = spi_chip_read, }, @@ -151,8 +151,8 @@ .page_size = 256, .tested = TEST_UNTESTED, .probe = probe_spi_rdid, - .erase = NULL, - .write = NULL, + .erase = spi_chip_erase_60_c7, + .write = spi_chip_write, .read = spi_chip_read, }, @@ -165,8 +165,8 @@ .page_size = 256, .tested = TEST_UNTESTED, .probe = probe_spi_rdid, - .erase = NULL, - .write = NULL, + .erase = spi_chip_erase_60_c7, + .write = spi_chip_write, .read = spi_chip_read, }, @@ -179,7 +179,7 @@ .page_size = 256, .tested = TEST_OK_PREW, .probe = probe_spi_rdid, - .erase = spi_chip_erase_c7, + .erase = spi_chip_erase_60_c7, .write = spi_chip_write, .read = spi_chip_read, }, @@ -193,8 +193,8 @@ .page_size = 256, .tested = TEST_UNTESTED, .probe = probe_spi_rdid, - .erase = NULL, - .write = NULL, + .erase = spi_chip_erase_60_c7, + .write = spi_chip_write, .read = spi_chip_read, }, @@ -207,8 +207,8 @@ .page_size = 256, .tested = TEST_UNTESTED, .probe = probe_spi_rdid, - .erase = NULL, - .write = NULL, + .erase = spi_chip_erase_60_c7, + .write = spi_chip_write, .read = spi_chip_read, }, @@ -221,8 +221,8 @@ .page_size = 256, .tested = TEST_UNTESTED, .probe = probe_spi_rdid, - .erase = NULL, - .write = NULL, + .erase = spi_chip_erase_60_c7, + .write = spi_chip_write, .read = spi_chip_read, }, @@ -235,8 +235,8 @@ .page_size = 256, .tested = TEST_UNTESTED, .probe = probe_spi_rdid, - .erase = NULL, - .write = NULL, + .erase = spi_chip_erase_60_c7, + .write = spi_chip_write, .read = spi_chip_read, }, @@ -249,8 +249,8 @@ .page_size = 256, .tested = TEST_UNTESTED, .probe = probe_spi_rdid, - .erase = NULL, - .write = NULL, + .erase = spi_chip_erase_60_c7, + .write = spi_chip_write, .read = spi_chip_read, }, @@ -277,8 +277,8 @@ .page_size = 256, .tested = TEST_UNTESTED, .probe = probe_spi_rdid, - .erase = NULL, - .write = NULL, + .erase = spi_chip_erase_60_c7, + .write = spi_chip_write, .read = spi_chip_read, }, @@ -291,8 +291,8 @@ .page_size = 256, .tested = TEST_UNTESTED, .probe = probe_spi_rdid, - .erase = NULL, - .write = NULL, + .erase = spi_chip_erase_60_c7, + .write = spi_chip_write, .read = spi_chip_read, }, @@ -305,8 +305,8 @@ .page_size = 256, .tested = TEST_UNTESTED, .probe = probe_spi_rdid, - .erase = NULL, - .write = NULL, + .erase = spi_chip_erase_60_c7, + .write = spi_chip_write, .read = spi_chip_read, }, @@ -320,7 +320,7 @@ .page_size = 256, .tested = TEST_UNTESTED, .probe = probe_spi_rdid, - .erase = spi_chip_erase_c7, + .erase = spi_chip_erase_60_c7, .write = spi_chip_write, .read = spi_chip_read, },*/ @@ -334,7 +334,7 @@ .page_size = 256, .tested = TEST_UNTESTED, .probe = probe_spi_rdid, - .erase = NULL, + .erase = spi_chip_erase_60_c7, .write = NULL /* Incompatible Page write */, .read = spi_chip_read, }, -- http://www.hailfinger.org/

3 6

[patch] Proposed patch for FIDVID question
by Dan Lykowski 09 Jan '09

09 Jan '09

Marc, I have narrowed the reset to the first msr = rdmsr(0xc0010042); line in cache_as_ram.c. I assume the second would do the same thing if it ever made it there. Booting with the orig bios, linux reports ts ttp tm stc 100mhzsteps as the available power options. It is missing fid vid. Based on the lack of cpuinfo bits and the documentation the says the processor will do exactly what it is doing, I propose the included patch. I made the changes to pistachio and norwich also but they are untested. With this patch I make it here: coreboot-2.0.0 Wed Jan 7 17:09:38 PST 2009 starting... bsp_apicid=0x0 Enabling routing table for node 00 done. Enabling UP settings Disabling read/write/fill probes for UP... done. coherent_ht_finalize done core0 started: SBLink=00 NC node|link=00 rs690_early_setup() get_cpu_rev EAX=0x60fc2. CPU Rev is K8_G0. NB Revision is A12. k8_optimization() rs690_por_init sb600_early_setup() sb600_devices_por_init() sb600_devices_por_init(): SMBus Device, BDF:0-20-0 SMBus controller enabled, sb revision is 0x13 sb600_devices_por_init(): IDE Device, BDF:0-20-1 sb600_devices_por_init(): LPC Device, BDF:0-20-3 sb600_devices_por_init(): P2P Bridge, BDF:0-20-4 sb600_devices_por_init(): SATA Device, BDF:0-18-0 sb600_pmio_por_init() Changing FIDVID not supported entering optimize_link_incoherent_ht sysinfo->link_pair_num=0x1 entering ht_optimize_link pos=0x8a, unfiltered freq_cap=0x8035 pos=0x8a, filtered freq_cap=0x35 pos=0xd2, unfiltered freq_cap=0x65 pos=0xd2, filtered freq_cap=0x65 freq_cap1=0x35, freq_cap2=0x65 dev1 old_freq=0x5, freq=0x5, needs_reset=0x0 dev2 old_freq=0x5, freq=0x5, needs_reset=0x0 width_cap1=0x11, width_cap2=0x11 dev1 input ln_width1=0x4, ln_width2=0x4 dev1 input width=0x1 dev1 output ln_width1=0x4, ln_width2=0x4 dev1 input|output width=0x11 old dev1 input|output width=0x11 dev2 input|output width=0x11 old dev2 input|output width=0x11 after ht_optimize_link for link pair 0, reset_needed=0x0 after optimize_link_read_pointers_chain, reset_needed=0x0 rs690_htinit k8_ht_freq=5. rs690_htinit NB_CFG_Q_F1000_800=0 needs_reset=0x0 sysinfo->nodes: 1 sysinfo->ctrl: cf188 spd_addr: ffffae98 Ram1.00 setting up CPU00 northbridge registers done. Ram2.00 Enable 64MuxMode & BurstLength32 Unbuffered 333Mhz 333Mhz Thanks, Dan Lykowski Signed-off-by: Dan Lykowski <lykowdk(a)gmail.com> --- On Thu, 1/8/09, Marc Jones <marcj303(a)gmail.com> wrote: From: Marc Jones <marcj303(a)gmail.com> Subject: Re: [coreboot] FIDVID question To: r.marek(a)assembler.cz Cc: "Dan Lykowski" <engineerguy3737(a)yahoo.com>, "Coreboot" <coreboot(a)coreboot.org> Date: Thursday, January 8, 2009, 12:10 PM -----Inline Attachment Follows----- On Thu, Jan 8, 2009 at 1:45 AM, <r.marek(a)assembler.cz> wrote: > Hi, > > if you check your CPUID, does it support FIDVID? > > If yes, then there is another problem. Perhaps you are hit by > some errata which says first is needed not HT reset (LDTSTOP) but PCI reset. > I don't have a code at my hand right now, but is HT reset stuff done > _before_ the fidvid? > I think that all the revf/g processors support fidvid even if it can't be changed. The S1G1 socket means revf and above and checking for support really isn't needed. I think it is safe for a platform to make some assumptions like that. Have you narrowed the reset to the fidvid code? After fidvid setup there should be a ht reset as Rudolf noted. You can skip fidvid setup for now. It just means that the processor will run at min frequency. Marc -- coreboot mailing list: coreboot(a)coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

3 2

[RFC] Netbook Support
by bari 08 Jan '09

08 Jan '09

coreboot support for netbooks has come back up again. The VIA vx700 and vx800 chipsets have recently become popular in many netbook designs. Most of these netbooks are being produced by Quanta for several different OEM's. VIA has recently released open documentation for the vx700 and vx800 chipsets at the VIA Download Portal: http://linux.via.com.tw/support/downloadFiles.action and open documentation for the latest Unichrome graphics controllers: http://www.x.org/docs/via/ VIA has also released a binary unichrome driver for ubuntu 8.04 and 8.10 VIA is currently developing coreboot support for the vx800 chipset. Release should be along very soon! openChrome support is also in the works for many new chipsets including the vx700 and vx800: http://www.openchrome.org/ The openChrome developers can also use lots of help. irc.freenode.net #unichrome The remaining issue with supporting these and other similar netbooks is open firmware support for the Embedded Controller (EC). The most common EC's in these netbooks are the KB9110 or KB3886 from ENE Technology. The ENE EC's are 8051 based and are used to support keyboard scan, lid open/closed, battery charging, power management, etc. There are also several AMD 690/600 laptops still available that may be candidates as well. Let see what we can do to get this working! For a list of netbook candidates and progress updates: http://www.coreboot.org/Laptop -Bari

7 16

[PATCH] flashrom: add SST49LF020 support
by Sven Schnelle 08 Jan '09

08 Jan '09

Hi List, i've added support for the SST 49LF020 Flash chip to flashrom. Basically only the device Id differs, the programming algorithm seems to be the same as for SST 49LF020A. I've only tested read so far, i'm a bit reluctant to test erase/programming without a backup BIOS chip :) Index: flash.h =================================================================== --- flash.h (revision 3845) +++ flash.h (working copy) @@ -356,6 +356,7 @@ #define SST_39VF040 0xD7 #define SST_49LF040B 0x50 #define SST_49LF040 0x51 +#define SST_49LF020 0x61 #define SST_49LF020A 0x52 #define SST_49LF080A 0x5B #define SST_49LF002A 0x57 Index: flashchips.c =================================================================== --- flashchips.c (revision 3845) +++ flashchips.c (working copy) @@ -626,6 +626,12 @@ probe_49lfxxxc, erase_49lfxxxc, write_49lfxxxc }, + {"SST", "SST49LF020", SST_ID, SST_49LF020, + 256, 16 * 1024, + TEST_UNTESTED, + probe_jedec, erase_49lf040, write_49lf040 + }, + {"SST", "SST49LF020A", SST_ID, SST_49LF020A, 256, 16 * 1024, TEST_UNTESTED,

3 7

r1111 - coreboot-v3/northbridge/amd/geodelx
by svn＠coreboot.org 08 Jan '09

08 Jan '09

Author: myles Date: 2009-01-08 21:07:21 +0100 (Thu, 08 Jan 2009) New Revision: 1111 Modified: coreboot-v3/northbridge/amd/geodelx/geodelx.c Log: This patch adds reserved regions to the geode northbridge for the ROM and IOAPIC. Signed-off-by: Myles Watson <mylesgw(a)gmail.com> Acked-by: Marc Jones <marcj303(a)gmail.com> Modified: coreboot-v3/northbridge/amd/geodelx/geodelx.c =================================================================== --- coreboot-v3/northbridge/amd/geodelx/geodelx.c 2009-01-08 17:21:37 UTC (rev 1110) +++ coreboot-v3/northbridge/amd/geodelx/geodelx.c 2009-01-08 20:07:21 UTC (rev 1111) @@ -149,8 +149,27 @@ */ static void geodelx_pci_domain_read_resources(struct device *dev) { + struct resource *res; + /* If the domain has any specific resources, read them here. */ pci_domain_read_resources(dev); + + /* Reserve space for the IOAPIC. This should be in the Southbridge, + * but I couldn't tell which device to put it in. */ + res = new_resource(dev, 2); + res->base = 0xfec00000UL; + res->size = 0x100000UL; + res->limit = 0xffffffffUL; + res->flags = IORESOURCE_MEM | IORESOURCE_FIXED | IORESOURCE_STORED | + IORESOURCE_ASSIGNED; + + /* Reserve space for the ROM. */ + res = new_resource(dev, 3); + res->base = 0xfff00000UL; + res->size = 0x100000UL; + res->limit = 0xffffffffUL; + res->flags = IORESOURCE_MEM | IORESOURCE_FIXED | IORESOURCE_STORED | + IORESOURCE_ASSIGNED; } /**

1 0

[PATCH] cs5536: Add a NAND device and do the IDE PCI header disabling on time.
by Mart Raudsepp 08 Jan '09

08 Jan '09

This implements a nand device, akin to the ide device to follow the coreboot-v3 device tree design better. It allows us to do the IDE PCI header early enough in a clean way - the hide_vpci was called way too late before - in phase6 of southbridge device, but we need the Flash header active instead of IDE in the VSA2 before bus scans happen, or the PCI device gets disabled in coreboot understanding by the time we get it enabled in VSA2. It makes NAND setup work better, but still not completely. There is a VSA2 bug for which I made a patch, but waiting on a new binary to test if after that everything works or not. A quick hack to workaround the VSA2 bug suggests something further will still need fixing. There are also more potential opportunities to shuffle NAND code around to match v3 approach better, but that's a next step for me after NAND setup actually works right in the current form. Also corrected the documentation of ide_init() to match current reality. Signed-off-by: Mart Raudsepp <mart.raudsepp(a)artecdesign.ee> --- mainboard/artecgroup/dbe61/dts | 3 ++ mainboard/artecgroup/dbe62/dts | 3 ++ southbridge/amd/cs5536/cs5536.c | 49 +++++++++++++++++++++++++------------- southbridge/amd/cs5536/nand | 23 ++++++++++++++++++ 4 files changed, 61 insertions(+), 17 deletions(-) create mode 100644 southbridge/amd/cs5536/nand diff --git a/mainboard/artecgroup/dbe61/dts b/mainboard/artecgroup/dbe61/dts index b443533..48df288 100644 --- a/mainboard/artecgroup/dbe61/dts +++ b/mainboard/artecgroup/dbe61/dts @@ -109,6 +109,9 @@ end /* USB Port Power Handling setting. */ pph = "0xf5"; }; + pci@f,1 { + /config/("southbridge/amd/cs5536/nand"); + }; pci@f,2 { /config/("southbridge/amd/cs5536/ide"); }; diff --git a/mainboard/artecgroup/dbe62/dts b/mainboard/artecgroup/dbe62/dts index 213c397..3cbe0ff 100644 --- a/mainboard/artecgroup/dbe62/dts +++ b/mainboard/artecgroup/dbe62/dts @@ -63,6 +63,9 @@ /* USB Port Power Handling setting. */ pph = "0xf5"; }; + pci@f,1 { + /config/("southbridge/amd/cs5536/nand"); + }; pci@f,2 { /config/("southbridge/amd/cs5536/ide"); }; diff --git a/southbridge/amd/cs5536/cs5536.c b/southbridge/amd/cs5536/cs5536.c index 89d64d6..057400f 100644 --- a/southbridge/amd/cs5536/cs5536.c +++ b/southbridge/amd/cs5536/cs5536.c @@ -98,6 +98,23 @@ static void hide_vpci(u32 vpci_devid) } /** + * Enables the FLASH PCI header when NAND device existing in mainboard device + * tree. Used when the mainboard has a FLASH part instead of an IDE drive and + * that fact is expressed in the mainboard device tree. + * Must be called after VSA init but before PCI scans to enable the flash + * PCI device header early enough - that is .phase2_fixup of the device. + * + * @param dev The device. + */ +static void nand_phase2(struct device *dev) +{ + if (dev->enabled) { + /* Tell VSA to use FLASH PCI header. Not IDE header. */ + hide_vpci(0x800079C4); + } +} + +/** * Power button setup. * * Setup GPIO24, it is the external signal for CS5536 vsb_work_aux which @@ -170,16 +187,6 @@ static void chipset_flash_setup(struct southbridge_amd_cs5536_dts_config *sb) printk(BIOS_DEBUG, "chipset_flash_setup: Finish\n"); } -/** - * Use this in the event that you have a FLASH part instead of an IDE drive. - * Run after VSA init to enable the flash PCI device header. - */ -static void enable_ide_nand_flash_header(void) -{ - /* Tell VSA to use FLASH PCI header. Not IDE header. */ - hide_vpci(0x800079C4); -} - #define RTC_CENTURY 0x32 #define RTC_DOMA 0x3D #define RTC_MONA 0x3E @@ -601,8 +608,8 @@ void chipsetinit(void) #define IDE_ETC 0x50 /** - * Enabled the IDE. This is code that is optionally run if the ide_enable is set - * in the mainboard dts. + * Enables the IDE. This is code that is run if there is an ide device in the mainboard + * device tree and it has set non-zero "enable_ide". * * @param dev The device */ @@ -658,11 +665,6 @@ static void southbridge_init(struct device *dev) printk(BIOS_SPEW, "cs5536: done second call vr_write\n"); } - printk(BIOS_ERR, "cs5536: %s: enable_ide_nand_flash is %d\n", - __FUNCTION__, sb->enable_ide_nand_flash); - if (sb->enable_ide_nand_flash != 0) - enable_ide_nand_flash_header(); - enable_USB_port4(sb); /* disable unwanted virtual PCI devices */ @@ -733,3 +735,16 @@ struct device_operations cs5536_ide = { .ops_pci = &pci_dev_ops_pci, }; +struct device_operations cs5536_nand = { + .id = {.type = DEVICE_ID_PCI, + {.pci = {.vendor = PCI_VENDOR_ID_AMD, + .device = PCI_DEVICE_ID_AMD_CS5536_FLASH}}}, + .constructor = default_device_constructor, + .phase2_fixup = nand_phase2, + .phase3_scan = 0, + .phase4_read_resources = pci_dev_read_resources, + .phase4_set_resources = pci_set_resources, + .phase5_enable_resources = pci_dev_enable_resources, + .phase6_init = 0, /* No Option ROMs */ + .ops_pci = &pci_dev_ops_pci, +}; diff --git a/southbridge/amd/cs5536/nand b/southbridge/amd/cs5536/nand new file mode 100644 index 0000000..69f4fa4 --- /dev/null +++ b/southbridge/amd/cs5536/nand @@ -0,0 +1,23 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2009 Mart Raudsepp <mart.raudsepp(a)artecdesign.ee> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +{ + device_operations = "cs5536_nand"; +}; -- 1.6.0.4 --=-1xTwwUBL3x7eRC+hClPJ--

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r1110 - in coreboot-v3: arch/x86 device include/arch/x86
by svn＠coreboot.org 08 Jan '09

08 Jan '09

Author: mraudsepp Date: 2009-01-08 18:21:37 +0100 (Thu, 08 Jan 2009) New Revision: 1110 Removed: coreboot-v3/include/arch/x86/pciconf.h Modified: coreboot-v3/arch/x86/pci_ops_auto.c coreboot-v3/arch/x86/pci_ops_conf1.c coreboot-v3/arch/x86/pci_ops_mmconf.c coreboot-v3/device/pci_ops.c Log: Remove unused pciconf.h header with constants that everyone uses by value instead per convention Signed-off-by: Mart Raudsepp <mart.raudsepp(a)artecdesign.ee> Acked-by: Peter Stuge <peter(a)stuge.se> Modified: coreboot-v3/arch/x86/pci_ops_auto.c =================================================================== --- coreboot-v3/arch/x86/pci_ops_auto.c 2009-01-08 16:22:39 UTC (rev 1109) +++ coreboot-v3/arch/x86/pci_ops_auto.c 2009-01-08 17:21:37 UTC (rev 1110) @@ -1,6 +1,5 @@ #include <console.h> #include <device/device.h> -#include <pciconf.h> #include <device/pci.h> #include <device/pci_ids.h> #include <device/pci_ops.h> Modified: coreboot-v3/arch/x86/pci_ops_conf1.c =================================================================== --- coreboot-v3/arch/x86/pci_ops_conf1.c 2009-01-08 16:22:39 UTC (rev 1109) +++ coreboot-v3/arch/x86/pci_ops_conf1.c 2009-01-08 17:21:37 UTC (rev 1110) @@ -1,6 +1,5 @@ #include <console.h> #include <device/device.h> -#include <pciconf.h> #include <device/pci.h> #include <device/pci_ids.h> #include <device/pci_ops.h> Modified: coreboot-v3/arch/x86/pci_ops_mmconf.c =================================================================== --- coreboot-v3/arch/x86/pci_ops_mmconf.c 2009-01-08 16:22:39 UTC (rev 1109) +++ coreboot-v3/arch/x86/pci_ops_mmconf.c 2009-01-08 17:21:37 UTC (rev 1110) @@ -1,6 +1,5 @@ #include <console.h> #include <device/device.h> -#include <pciconf.h> #include <device/pci.h> #include <device/pci_ids.h> #include <device/pci_ops.h> Modified: coreboot-v3/device/pci_ops.c =================================================================== --- coreboot-v3/device/pci_ops.c 2009-01-08 16:22:39 UTC (rev 1109) +++ coreboot-v3/device/pci_ops.c 2009-01-08 17:21:37 UTC (rev 1110) @@ -20,7 +20,6 @@ #include <console.h> #include <device/device.h> -#include <pciconf.h> #include <device/pci.h> #include <device/pci_ids.h> #include <device/pci_ops.h> Deleted: coreboot-v3/include/arch/x86/pciconf.h =================================================================== --- coreboot-v3/include/arch/x86/pciconf.h 2009-01-08 16:22:39 UTC (rev 1109) +++ coreboot-v3/include/arch/x86/pciconf.h 2009-01-08 17:21:37 UTC (rev 1110) @@ -1,13 +0,0 @@ -#ifndef ARCH_X86_PCICONF_H -#define ARCH_X86_PCICONF_H - -#ifndef PCI_CONF_REG_INDEX - -// These are defined in the PCI spec, and hence are theoretically -// inclusive of ANYTHING that uses a PCI bus. -#define PCI_CONF_REG_INDEX 0xcf8 -#define PCI_CONF_REG_DATA 0xcfc - -#endif - -#endif /* ARCH_X86_PCICONF_H */

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coreboot January 2009