coreboot January 2009

coreboot@coreboot.org

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320 discussions

[PATCH] There's a pciconf.h with PCI conf constants - lets actually use it
by Mart Raudsepp 08 Jan '09

08 Jan '09

In case it's a good idea to use these constants from that header, here's the proposed commit log and patch: There's a pciconf.h with PCI conf constants - lets actually use it PCI_CONF_REG_{INDEX,DATA} constants instead of 0xCF8 and 0xCFF everywhere. Not touching YABEL as I'm not sure it would want to include that header. Signed-off-by: Mart Raudsepp <mart.raudsepp(a)artecdesign.ee> --- arch/x86/pci_ops_conf1.c | 24 ++++++++++++------------ southbridge/amd/cs5536/cs5536.c | 5 +++-- 2 files changed, 15 insertions(+), 14 deletions(-) diff --git a/arch/x86/pci_ops_conf1.c b/arch/x86/pci_ops_conf1.c index a9a7fea..757b6c2 100644 --- a/arch/x86/pci_ops_conf1.c +++ b/arch/x86/pci_ops_conf1.c @@ -58,38 +58,38 @@ u8 pci_conf1_read_config8(u32 bdf, int where) { - outl(CONFIG_CMD(bdf, where), 0xCF8); - return inb(0xCFC + (where & 3)); + outl(CONFIG_CMD(bdf, where), PCI_CONF_REG_INDEX); + return inb(PCI_CONF_REG_DATA + (where & 3)); } u16 pci_conf1_read_config16(u32 bdf, int where) { - outl(CONFIG_CMD(bdf, where), 0xCF8); - return inw(0xCFC + (where & 2)); + outl(CONFIG_CMD(bdf, where), PCI_CONF_REG_INDEX); + return inw(PCI_CONF_REG_DATA + (where & 2)); } u32 pci_conf1_read_config32(u32 bdf, int where) { - outl(CONFIG_CMD(bdf, where), 0xCF8); - return inl(0xCFC); + outl(CONFIG_CMD(bdf, where), PCI_CONF_REG_INDEX); + return inl(PCI_CONF_REG_DATA); } void pci_conf1_write_config8(u32 bdf, int where, u8 value) { - outl(CONFIG_CMD(bdf, where), 0xCF8); - outb(value, 0xCFC + (where & 3)); + outl(CONFIG_CMD(bdf, where), PCI_CONF_REG_INDEX); + outb(value, PCI_CONF_REG_DATA + (where & 3)); } void pci_conf1_write_config16(u32 bdf, int where, u16 value) { - outl(CONFIG_CMD(bdf, where), 0xCF8); - outw(value, 0xCFC + (where & 2)); + outl(CONFIG_CMD(bdf, where), PCI_CONF_REG_INDEX); + outw(value, PCI_CONF_REG_DATA + (where & 2)); } void pci_conf1_write_config32(u32 bdf, int where, u32 value) { - outl(CONFIG_CMD(bdf, where), 0xCF8); - outl(value, 0xCFC); + outl(CONFIG_CMD(bdf, where), PCI_CONF_REG_INDEX); + outl(value, PCI_CONF_REG_DATA); } /** diff --git a/southbridge/amd/cs5536/cs5536.c b/southbridge/amd/cs5536/cs5536.c index 89d64d6..dacf5c3 100644 --- a/southbridge/amd/cs5536/cs5536.c +++ b/southbridge/amd/cs5536/cs5536.c @@ -20,6 +20,7 @@ #include <types.h> #include <lib.h> #include <console.h> +#include <pciconf.h> #include <device/pci.h> #include <msr.h> #include <amd_geodelx.h> @@ -93,8 +94,8 @@ static void hide_vpci(u32 vpci_devid) printk(BIOS_DEBUG, "Hiding VPCI device: 0x%08X (%02x:%02x.%01x)\n", vpci_devid, (vpci_devid >> 16) & 0xff, (vpci_devid >> 11) & 0x1f, (vpci_devid >> 8) & 0x7); - outl(vpci_devid + 0x7C, 0xCF8); - outl(0xDEADBEEF, 0xCFC); + outl(vpci_devid + 0x7C, PCI_CONF_REG_INDEX); + outl(0xDEADBEEF, PCI_CONF_REG_DATA); } /** -- 1.6.0.4

4 5

FIDVID question
by Dan Lykowski 08 Jan '09

08 Jan '09

I have narrowed the resetting of my board to: Referring to real_main in cache_as_ram.c for dbm690t and pistachio. msr=rdmsr(0xc0010042); ( Reading the FIDVID_STAUS register ) According to the docs, trying to read this register on a processor that doesn't support FID/VID changes will cause a GP#. I was under the assumption that all mobile 0Fh processors had this capability. Would calling enable_fid_change() before the rdmsr call enable the MSR? ( I am skeptical because the code is working for other processors. ) Would it be appropriate to add a check around the FIDVID sections? struct cpuid_result cpuid1; cpuid1 = cpuid(0x8000007); if( (cpuid1.edx & 0x06) == 0x06 ) { } S1G1 Sempron 2100+ 9W 1Ghz Thanks, Dan Lykowski

3 2

r3853 - trunk/util/flashrom
by svn＠coreboot.org 08 Jan '09

08 Jan '09

Author: hailfinger Date: 2009-01-08 17:53:13 +0100 (Thu, 08 Jan 2009) New Revision: 3853 Modified: trunk/util/flashrom/flashchips.c Log: Add erase and write functions to the following chip definitions: AT25DF021 AT25DF041A AT25DF081 AT25DF161 AT25DF321 AT25DF321A AT25DF641 AT25F512B AT25FS010 AT25FS040 AT26DF081A AT26DF161 AT26DF161A AT26DF321 AT26F004 Straight from the data sheets, untested because I lack the hardware. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Peter Stuge <peter(a)stuge.se> Modified: trunk/util/flashrom/flashchips.c =================================================================== --- trunk/util/flashrom/flashchips.c 2009-01-08 04:56:59 UTC (rev 3852) +++ trunk/util/flashrom/flashchips.c 2009-01-08 16:53:13 UTC (rev 3853) @@ -123,8 +123,8 @@ .page_size = 256, .tested = TEST_UNTESTED, .probe = probe_spi_rdid, - .erase = NULL, - .write = NULL, + .erase = spi_chip_erase_60_c7, + .write = spi_chip_write, .read = spi_chip_read, }, @@ -137,8 +137,8 @@ .page_size = 256, .tested = TEST_UNTESTED, .probe = probe_spi_rdid, - .erase = NULL, - .write = NULL, + .erase = spi_chip_erase_60_c7, + .write = spi_chip_write, .read = spi_chip_read, }, @@ -151,8 +151,8 @@ .page_size = 256, .tested = TEST_UNTESTED, .probe = probe_spi_rdid, - .erase = NULL, - .write = NULL, + .erase = spi_chip_erase_60_c7, + .write = spi_chip_write, .read = spi_chip_read, }, @@ -165,8 +165,8 @@ .page_size = 256, .tested = TEST_UNTESTED, .probe = probe_spi_rdid, - .erase = NULL, - .write = NULL, + .erase = spi_chip_erase_60_c7, + .write = spi_chip_write, .read = spi_chip_read, }, @@ -179,7 +179,7 @@ .page_size = 256, .tested = TEST_OK_PREW, .probe = probe_spi_rdid, - .erase = spi_chip_erase_c7, + .erase = spi_chip_erase_60_c7, .write = spi_chip_write, .read = spi_chip_read, }, @@ -193,8 +193,8 @@ .page_size = 256, .tested = TEST_UNTESTED, .probe = probe_spi_rdid, - .erase = NULL, - .write = NULL, + .erase = spi_chip_erase_60_c7, + .write = spi_chip_write, .read = spi_chip_read, }, @@ -207,8 +207,8 @@ .page_size = 256, .tested = TEST_UNTESTED, .probe = probe_spi_rdid, - .erase = NULL, - .write = NULL, + .erase = spi_chip_erase_60_c7, + .write = spi_chip_write, .read = spi_chip_read, }, @@ -221,8 +221,8 @@ .page_size = 256, .tested = TEST_UNTESTED, .probe = probe_spi_rdid, - .erase = NULL, - .write = NULL, + .erase = spi_chip_erase_60_c7, + .write = spi_chip_write, .read = spi_chip_read, }, @@ -235,8 +235,8 @@ .page_size = 256, .tested = TEST_UNTESTED, .probe = probe_spi_rdid, - .erase = NULL, - .write = NULL, + .erase = spi_chip_erase_60_c7, + .write = spi_chip_write, .read = spi_chip_read, }, @@ -249,8 +249,8 @@ .page_size = 256, .tested = TEST_UNTESTED, .probe = probe_spi_rdid, - .erase = NULL, - .write = NULL, + .erase = spi_chip_erase_60_c7, + .write = spi_chip_write, .read = spi_chip_read, }, @@ -277,8 +277,8 @@ .page_size = 256, .tested = TEST_UNTESTED, .probe = probe_spi_rdid, - .erase = NULL, - .write = NULL, + .erase = spi_chip_erase_60_c7, + .write = spi_chip_write, .read = spi_chip_read, }, @@ -291,8 +291,8 @@ .page_size = 256, .tested = TEST_UNTESTED, .probe = probe_spi_rdid, - .erase = NULL, - .write = NULL, + .erase = spi_chip_erase_60_c7, + .write = spi_chip_write, .read = spi_chip_read, }, @@ -305,8 +305,8 @@ .page_size = 256, .tested = TEST_UNTESTED, .probe = probe_spi_rdid, - .erase = NULL, - .write = NULL, + .erase = spi_chip_erase_60_c7, + .write = spi_chip_write, .read = spi_chip_read, }, @@ -320,7 +320,7 @@ .page_size = 256, .tested = TEST_UNTESTED, .probe = probe_spi_rdid, - .erase = spi_chip_erase_c7, + .erase = spi_chip_erase_60_c7, .write = spi_chip_write, .read = spi_chip_read, },*/ @@ -334,7 +334,7 @@ .page_size = 256, .tested = TEST_UNTESTED, .probe = probe_spi_rdid, - .erase = NULL, + .erase = spi_chip_erase_60_c7, .write = NULL /* Incompatible Page write */, .read = spi_chip_read, },

1 0

K8 HT and dts fixups
by Myles Watson 08 Jan '09

08 Jan '09

This is a small HT fixup until HT links get figured out better. It removes processors from the list of devices on the domain's bus so that pci_scan_bus won't disable them, then scans for them, then puts them back. There are lots of other ways to do this, but this one seemed minimally invasive and ends up with a correct tree. The dts fixups I should have put in with the other K8 patch for the new resource allocator. I went to the v2 Config.lb files and tried to get them as complete as possible. Signed-off-by: Myles Watson <mylesgw(a)gmail.com> Thanks, Myles

2 3

r1109 - in coreboot-v3: mainboard/amd/dbm690t mainboard/amd/serengeti mainboard/gigabyte/m57sli northbridge/amd/k8
by svn＠coreboot.org 08 Jan '09

08 Jan '09

Author: myles Date: 2009-01-08 17:22:39 +0100 (Thu, 08 Jan 2009) New Revision: 1109 Modified: coreboot-v3/mainboard/amd/dbm690t/dts coreboot-v3/mainboard/amd/serengeti/dts coreboot-v3/mainboard/gigabyte/m57sli/dts coreboot-v3/northbridge/amd/k8/domain.c Log: This is a small HT fixup until HT links get figured out better. It removes processors from the list of devices on the domain's bus so that pci_scan_bus won't disable them, then scans for them, then puts them back. There are lots of other ways to do this, but this one seemed minimally invasive and ends up with a correct tree. The dts fixups I should have put in with the other K8 patch for the new resource allocator. I went to the v2 Config.lb files and tried to get them as complete as possible. Signed-off-by: Myles Watson <mylesgw(a)gmail.com> Acked-by: Peter Stuge <peter(a)stuge.se> Modified: coreboot-v3/mainboard/amd/dbm690t/dts =================================================================== --- coreboot-v3/mainboard/amd/dbm690t/dts 2009-01-08 16:19:51 UTC (rev 1108) +++ coreboot-v3/mainboard/amd/dbm690t/dts 2009-01-08 16:22:39 UTC (rev 1109) @@ -66,52 +66,75 @@ /{ device_operations="dbm690t"; mainboard_vendor = "AMD"; - mainboard_name = "Serengeti"; + mainboard_name = "dbm690t"; cpus { }; apic@0 { }; domain@0 { /config/("northbridge/amd/k8/domain"); - pci@1,0{ + /* Make sure that the HT device is first; if it isn't found, + * the rest of the devices won't be found. + */ + pci@0 { + /config/("southbridge/amd/rs690/ht.dts"); }; - /* guesses; we need a real lspci */ - pci0@18,0 { - /config/("northbridge/amd/k8/pci"); - /* make sure that the ht device is first, as it controls many other things. */ - pci0 { - /config/("southbridge/amd/rs690/ht.dts"); - }; - pci1{ + pci@1{ + /config/("southbridge/amd/sb600/pci.dts"); + pci@5{ /config/("southbridge/amd/rs690/gfx.dts"); }; - pci2{ - /config/("southbridge/amd/rs690/pcie.dts"); + }; + pci@6{ /* Port 2 */ + /config/("southbridge/amd/rs690/pcie.dts"); + }; + pci@7{ /* Port 3 */ + /config/("southbridge/amd/rs690/pcie.dts"); + }; + pci@12{ + /config/("southbridge/amd/sb600/hda.dts"); + }; + pci@13,0{ + /config/("southbridge/amd/sb600/usb.dts"); + }; + pci@13,1{ + /config/("southbridge/amd/sb600/usb.dts"); + }; + pci@13,2{ + /config/("southbridge/amd/sb600/usb.dts"); + }; + pci@13,3{ + /config/("southbridge/amd/sb600/usb.dts"); + }; + pci@13,4{ + /config/("southbridge/amd/sb600/usb.dts"); + }; + pci@13,5{ + /config/("southbridge/amd/sb600/usb2.dts"); + }; + pci@14,0{ + /config/("southbridge/amd/sb600/sm.dts"); + }; + pci@14,1{ + /config/("southbridge/amd/sb600/ide.dts"); + }; + pci@14,2{ + /config/("southbridge/amd/sb600/ac97audio.dts"); + }; + pci@14,3{ + /config/("southbridge/amd/sb600/lpc.dts"); + ioport@2e { + /config/("superio/ite/it8712f/dts"); + com1enable = "1"; }; - pci4{ - /config/("southbridge/amd/sb600/hda.dts"); - }; - pci5{ - /config/("southbridge/amd/sb600/usb.dts"); - }; - pci6{ - /config/("southbridge/amd/sb600/usb2.dts"); - }; }; - pci1@18,0 { - /config/("northbridge/amd/k8/pci"); + pci@14,4{ + /config/("southbridge/amd/sb600/pci.dts"); }; - pci2@18,0 { + pci@18,0 { /config/("northbridge/amd/k8/pci"); - /* just for illustrating link #2 */ - pci@2,0{ - }; }; pci@18,1 {}; pci@18,2 {}; pci@18,3 {}; - ioport@2e { - /config/("superio/ite/it8712f/dts"); - com1enable = "1"; - }; }; }; Modified: coreboot-v3/mainboard/amd/serengeti/dts =================================================================== --- coreboot-v3/mainboard/amd/serengeti/dts 2009-01-08 16:19:51 UTC (rev 1108) +++ coreboot-v3/mainboard/amd/serengeti/dts 2009-01-08 16:22:39 UTC (rev 1109) @@ -22,76 +22,82 @@ device_operations="serengeti"; mainboard_vendor = "AMD"; mainboard_name = "Serengeti"; - subsystem_vendor = "PCI_VENDOR_ID_AMD"; - subsystem_device = "0x2b80"; + mainboard_pci_subsystem_vendor = "PCI_VENDOR_ID_AMD"; + mainboard_pci_subsystem_device = "0x2b80"; cpus { }; apic@0 { /config/("northbridge/amd/k8/apic"); }; domain@0 { /config/("northbridge/amd/k8/domain"); - pci@18,0 { - /config/("northbridge/amd/k8/pci"); - pci_a@0,0 { - /config/("southbridge/amd/amd8132/pcix.dts"); - }; - pci_a@0,1 { - /config/("southbridge/amd/amd8132/apic.dts"); - }; - pci_a@1,0 { - /config/("southbridge/amd/amd8132/pcix.dts"); - }; - pci_a@1,1 { - /config/("southbridge/amd/amd8132/apic.dts"); - }; - pci@0,0 { - /config/("southbridge/amd/amd8111/pci.dts"); - pci@0,0{ - /config/("southbridge/amd/amd8111/usb.dts"); - }; - pci@0,1{ - /config/("southbridge/amd/amd8111/usb.dts"); - }; - pci@0,2{ - /config/("southbridge/amd/amd8111/usb2.dts"); - disabled; - }; - pci@1,0{ - /config/("southbridge/amd/amd8111/nic.dts"); - disabled; - }; + pci_a@0,0 { + /config/("southbridge/amd/amd8132/pcix.dts"); }; - pci@1,0 { - /config/("southbridge/amd/amd8111/lpc.dts"); - ioport@2e { - /config/("superio/winbond/w83627hf/dts"); - kbenable = "1"; - com1enable = "1"; - hwmenable = "1"; - }; + pci_a@0,1 { + /config/("southbridge/amd/amd8132/apic.dts"); }; - pci@1,1 { - /config/("southbridge/amd/amd8111/ide.dts"); - ide0_enable = "1"; - ide1_enable = "1"; + pci_a@1,0 { + /config/("southbridge/amd/amd8132/pcix.dts"); }; - pci@1,2 { - /config/("southbridge/amd/amd8111/smbus.dts"); + pci_a@1,1 { + /config/("southbridge/amd/amd8132/apic.dts"); }; - pci@1,3 { - /config/("southbridge/amd/amd8111/acpi.dts"); + pci@0,0 { + /config/("southbridge/amd/amd8111/pci.dts"); + pci@0,0{ + /config/("southbridge/amd/amd8111/usb.dts"); }; - pci@1,5 { - /config/("southbridge/amd/amd8111/ac97audio.dts"); + pci@0,1{ + /config/("southbridge/amd/amd8111/usb.dts"); + }; + pci@0,2{ + /config/("southbridge/amd/amd8111/usb2.dts"); disabled; }; - pci@1,6 { - /config/("southbridge/amd/amd8111/ac97modem.dts"); + pci@1,0{ + /config/("southbridge/amd/amd8111/nic.dts"); disabled; }; - pci@1,7 { + }; + pci@1,0 { + /config/("southbridge/amd/amd8111/lpc.dts"); + ioport@2e { + /config/("superio/winbond/w83627hf/dts"); + kbenable = "1"; + com1enable = "1"; + hwmenable = "1"; }; }; + pci@1,1 { + /config/("southbridge/amd/amd8111/ide.dts"); + ide0_enable = "1"; + ide1_enable = "1"; + }; + pci@1,2 { + /config/("southbridge/amd/amd8111/smbus.dts"); + }; + pci@1,3 { + /config/("southbridge/amd/amd8111/acpi.dts"); + }; + pci@1,5 { + /config/("southbridge/amd/amd8111/ac97audio.dts"); + disabled; + }; + pci@1,6 { + /config/("southbridge/amd/amd8111/ac97modem.dts"); + disabled; + }; + pci@1,7 { + }; + pci_8@0,0 { + /config/("southbridge/amd/amd8151/agpbridge.dts"); + }; + pci_8@1,0 { + /config/("southbridge/amd/amd8151/agpdev.dts"); + }; + pci@18,0 { + /config/("northbridge/amd/k8/pci"); + }; pci@18,1 {}; pci@18,2 {}; pci@18,3 { @@ -101,12 +107,6 @@ /config/("northbridge/amd/k8/pci"); }; pci@19,1 { - pci@0,0 { - /config/("southbridge/amd/amd8151/agpbridge.dts"); - }; - pci@1,0 { - /config/("southbridge/amd/amd8151/agpdev.dts"); - }; }; pci@19,2 {}; pci@19,3 { Modified: coreboot-v3/mainboard/gigabyte/m57sli/dts =================================================================== --- coreboot-v3/mainboard/gigabyte/m57sli/dts 2009-01-08 16:19:51 UTC (rev 1108) +++ coreboot-v3/mainboard/gigabyte/m57sli/dts 2009-01-08 16:22:39 UTC (rev 1109) @@ -44,20 +44,58 @@ apic@0 { }; domain@0 { - pci@1,0{ + pci@0,0 { /* MCP55 RAM? */ }; + pci@1,0 { + /config/("southbridge/nvidia/mcp55/lpc.dts"); + ioport@2e { + /config/("superio/ite/it8716f/dts"); + com1enable = "1"; + ecenable = "1"; + kbenable = "1"; + mouseenable = "1"; + gpioenable = "1"; + }; + }; + pci@1,1 { /* smbus */ + }; + pci@2,0 { /* usb */ + }; + pci@2,1 { /* usb */ + }; + pci@4,0 { + /config/("southbridge/nvidia/mcp55/ide.dts"); + ide0_enable = "1"; + }; + pci@5,0 { + /config/("southbridge/nvidia/mcp55/sata.dts"); + sata0_enable = "1"; + }; + pci@5,1 { + /config/("southbridge/nvidia/mcp55/sata.dts"); + sata1_enable = "1"; + }; + pci@6,0 { /* PCI */ + }; + pci@6,1 { + /*/config/("southbridge/nvidia/mcp55/audio.dts"); */ + }; + pci@8,0 { + /* + /config/("southbridge/nvidia/mcp55/nic.dts"); + mac_eeprom_smbus = "3"; + mac_eeprom_addr = "0x51"; + */ + }; + pci@f,0 { /* PCIe */ + }; pci@18,0 { /config/("northbridge/amd/k8/pci"); - pci@0,0 { - /config/("southbridge/nvidia/mcp55/ide.dts"); - }; - pci@0,1 { - /config/("southbridge/nvidia/mcp55/sata.dts"); - }; }; - ioport@2e { - /config/("superio/ite/it8716f/dts"); - com1enable = "1"; + pci@18,1 {}; + pci@18,2 {}; + pci@18,3 { + /config/("northbridge/amd/k8/mcf3"); }; }; }; Modified: coreboot-v3/northbridge/amd/k8/domain.c =================================================================== --- coreboot-v3/northbridge/amd/k8/domain.c 2009-01-08 16:19:51 UTC (rev 1108) +++ coreboot-v3/northbridge/amd/k8/domain.c 2009-01-08 16:22:39 UTC (rev 1109) @@ -717,6 +717,7 @@ { unsigned reg; int i; + struct device *last_dev, *children; printk(BIOS_DEBUG, "%s: %s \n", __func__, dev->dtsname); @@ -746,8 +747,31 @@ } } + /* Take processors off the list; we always know what link they're on. */ + for (last_dev = dev->link[0].children; last_dev; + last_dev = last_dev->sibling) + if (last_dev && last_dev->sibling == __f0_dev[0]) + last_dev->sibling = NULL; + max = amdk8_scan_chains(dev, __f0_dev[0], max); + /* Save non-processor children. */ + children = dev->link[0].children; + + /* Probe for processors and disable those that don't respond. */ + dev->link[0].children = __f0_dev[0]; + pci_scan_bus(&dev->link[0], PCI_DEVFN(0x18,0), 0xff, 0); + + /* Add them back to the new end of the list. */ + for (last_dev = children; last_dev && last_dev->sibling; + last_dev = last_dev->sibling); + + if (last_dev) { + last_dev->sibling = __f0_dev[0]; + dev->link[0].children = children; + } else + dev->link[0].children = __f0_dev[0]; + return max; }

1 0

r1108 - coreboot-v3/device
by svn＠coreboot.org 08 Jan '09

08 Jan '09

Author: myles Date: 2009-01-08 17:19:51 +0100 (Thu, 08 Jan 2009) New Revision: 1108 Modified: coreboot-v3/device/device.c Log: This patch implements preorder traversal for Phase 2 and Phase 6, and prints a warning that Phase 1 is obsolete if anyone implements one. The only difference between the Phase 2 and Phase 6 implementations is that phase2_fixup is always called if it's defined, but phase6_init is only called if the device is enabled. Note that any devices not found in the tree will not have their init functions called with this patch. I think that's a good thing, but it will require some dts fixes. Signed-off-by: Myles Watson <mylesgw(a)gmail.com> Acked-by: Peter Stuge <peter(a)stuge.se> Modified: coreboot-v3/device/device.c =================================================================== --- coreboot-v3/device/device.c 2009-01-08 16:14:12 UTC (rev 1107) +++ coreboot-v3/device/device.c 2009-01-08 16:19:51 UTC (rev 1108) @@ -989,6 +989,7 @@ printk(BIOS_DEBUG, "Phase 1: Very early setup...\n"); for (dev = all_devices; dev; dev = dev->next) { if (dev->ops && dev->ops->phase1_set_device_operations) { + printk(BIOS_WARNING, "Phase 1 is obsolete...\n"); dev->ops->phase1_set_device_operations(dev); } } @@ -997,32 +998,38 @@ post_code(POST_STAGE2_PHASE1_EXIT); } +/* + * Starting at the root device, walk the tree and call the device's phase2() + * method to do early setup. It's done parents before children in case there + * are dependencies. + */ +void phase2_tree(struct device *root) +{ + struct device *child; + unsigned link; + + if (root->ops && root->ops->phase2_fixup) { + printk(BIOS_DEBUG, "Phase 2: %s fixup.\n", dev_path(root)); + root->ops->phase2_fixup(root); + } + for (link = 0; link < root->links; link++) { + for (child = root->link[link].children; child; + child = child->sibling) { + phase2_tree(child); + } + } +} + /** - * Do early setup for all devices in the global device list. - * - * Starting at the first device on the global device link list, - * walk the list and call the device's phase2() method to do - * early setup. + * Do early setup for all devices in the global device tree. */ void dev_phase2(void) { - struct device *dev; - post_code(POST_STAGE2_PHASE2_ENTER); printk(BIOS_DEBUG, "Phase 2: Early setup...\n"); - for (dev = all_devices; dev; dev = dev->next) { - printk(BIOS_SPEW, - "%s: dev %s: ops %sNULL ops->phase2_fixup %s\n", - __FUNCTION__, dev->dtsname, dev->ops ? "NOT " : "", - dev->ops ? (dev->ops->phase2_fixup ? "NOT NULL" : "NULL") - : "N/A"); - if (dev->ops && dev->ops->phase2_fixup) { - printk(BIOS_SPEW, "Calling phase2 phase2_fixup...\n"); - dev->ops->phase2_fixup(dev); - printk(BIOS_SPEW, "phase2_fixup done\n"); - } - } + phase2_tree(&dev_root); + post_code(POST_STAGE2_PHASE2_DONE); printk(BIOS_DEBUG, "Phase 2: Done.\n"); post_code(POST_STAGE2_PHASE2_EXIT); @@ -1321,28 +1328,36 @@ printk(BIOS_INFO, "Phase 5: Done.\n"); } +/* + * Walk the device tree and call the device's phase6_init() method. It's done + * preorder (parents before children) in case there are dependencies. + */ +void phase6_tree(struct device *root) +{ + struct device *child; + unsigned link; + + if (root->enabled && root->ops && root->ops->phase6_init) { + printk(BIOS_DEBUG, "Phase 6: %s init.\n", dev_path(root)); + root->ops->phase6_init(root); + } + for (link = 0; link < root->links; link++) { + for (child = root->link[link].children; child; + child = child->sibling) { + phase6_tree(child); + } + } +} + /** - * Initialize all devices in the global device list. - * - * Starting at the first device on the global device link list, walk the list - * and call the device's init() method to do device specific setup. + * Initialize all devices in the device tree. */ void dev_phase6(void) { - struct device *dev; + printk(BIOS_INFO, "Phase 6: Initializing devices...\n"); - printk(BIOS_INFO, "Phase 6: Initializing devices...\n"); - for (dev = all_devices; dev; dev = dev->next) { - if (dev->enabled && dev->ops && dev->ops->phase6_init) { - if (dev->path.type == DEVICE_PATH_I2C) { - printk(BIOS_DEBUG, "Phase 6: smbus: %s[%d]->", - dev_path(dev->bus->dev), dev->bus->link); - } - printk(BIOS_DEBUG, "Phase 6: %s init.\n", - dev_path(dev)); - dev->ops->phase6_init(dev); - } - } + phase6_tree(&dev_root); + printk(BIOS_INFO, "Phase 6: Devices initialized.\n"); }

1 0

r1107 - in coreboot-v3: northbridge/intel/i945 southbridge/intel/i82801gx
by svn＠coreboot.org 08 Jan '09

08 Jan '09

Author: uwe Date: 2009-01-08 17:14:12 +0100 (Thu, 08 Jan 2009) New Revision: 1107 Modified: coreboot-v3/northbridge/intel/i945/ich7.h coreboot-v3/southbridge/intel/i82801gx/i82801gx.h coreboot-v3/southbridge/intel/i82801gx/lpc.c Log: Port r3747, r3732, r3733 from v2 to v3 (build-tested on v3): src/northbridge/intel/i945/ich7.h: Thanks to Uwe Hermann for spotting this typo. src/southbridge/intel/i82801gx/i82801gx_lpc.c: The enable_hpet() code in intel/i82801gx will not work with the ICH7 southbridge (but it might work with ICH4/ICH5 or so). The ICH7 needs a different init code. Drop the non-working code for now. src/southbridge/intel/i82801gx/i82801gx.h: Drop #defines for registers that are not existant on the ICH7. Also, fix BIOS_CNTL, which is 0xdc on ICH7. Build-tested with kontron/986lcd-m. Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Modified: coreboot-v3/northbridge/intel/i945/ich7.h =================================================================== --- coreboot-v3/northbridge/intel/i945/ich7.h 2009-01-08 16:01:25 UTC (rev 1106) +++ coreboot-v3/northbridge/intel/i945/ich7.h 2009-01-08 16:14:12 UTC (rev 1107) @@ -60,7 +60,7 @@ #define RP2D 0x0130 /* 32bit */ #define RP2BA 0x0138 /* 64bit */ #define RP3D 0x0140 /* 32bit */ -#define RP3BA 0x0138 /* 64bit */ +#define RP3BA 0x0148 /* 64bit */ #define RP4D 0x0150 /* 32bit */ #define RP4BA 0x0158 /* 64bit */ #define HDD 0x0160 /* 32bit */ Modified: coreboot-v3/southbridge/intel/i82801gx/i82801gx.h =================================================================== --- coreboot-v3/southbridge/intel/i82801gx/i82801gx.h 2009-01-08 16:01:25 UTC (rev 1106) +++ coreboot-v3/southbridge/intel/i82801gx/i82801gx.h 2009-01-08 16:14:12 UTC (rev 1107) @@ -22,18 +22,20 @@ #define SOUTHBRIDGE_INTEL_I82801GX_I82801GX_H /* warning: included in stage1 and stage2 */ -#define PCI_DMA_CFG 0x90 #define SERIRQ_CNTL 0x64 -#define GEN_CNTL 0xd0 -#define GEN_STS 0xd4 -#define RTC_CONF 0xd8 + #define GEN_PMCON_1 0xa0 #define GEN_PMCON_2 0xa2 #define GEN_PMCON_3 0xa4 +/* GEN_PMCON_3 bits */ +#define RTC_BATTERY_DEAD (1 << 2) +#define RTC_POWER_FAILED (1 << 1) +#define SLEEP_AFTER_POWER_FAIL (1 << 0) + #define PMBASE 0x40 #define ACPI_CNTL 0x44 -#define BIOS_CNTL 0x4E +#define BIOS_CNTL 0xDC #define GPIO_BASE 0x48 /* LPC GPIO Base Address Register */ #define GPIO_CNTL 0x4C /* LPC GPIO Control Register */ @@ -46,28 +48,10 @@ #define PIRQG_ROUT 0x6A #define PIRQH_ROUT 0x6B -#define FUNC_DIS 0xF2 - #define LPC_IO_DEC 0x80 /* IO Decode Ranges Register */ #define LPC_EN 0x82 /* LPC IF Enables Register */ -#define SBUS_NUM 0x19 -#define SUB_BUS_NUM 0x1A -#define SMLT 0x1B -#define IOBASE 0x1C -#define IOLIM 0x1D -#define MEMBASE 0x20 -#define MEMLIM 0x22 -#define CNF 0x50 -#define MTT 0x70 -#define PCI_MAST_STS 0x82 - -/* GEN_PMCON_3 bits */ -#define RTC_BATTERY_DEAD (1 << 2) -#define RTC_POWER_FAILED (1 << 1) -#define SLEEP_AFTER_POWER_FAIL (1 << 0) - -/* PCI Configuration Space (D31:F1) */ +/* PCI Configuration Space (D31:F1): IDE */ #define INTR_LN 0x3c #define IDE_TIM_PRI 0x40 /* IDE timings, primary */ #define IDE_DECODE_ENABLE (1 << 15) @@ -82,7 +66,7 @@ #define PCB1 (1 << 1) #define PCB0 (1 << 0) -/* PCI Configuration Space (D31:F3) */ +/* PCI Configuration Space (D31:F3): SMBus */ #define SMB_BASE 0x20 #define HOSTC 0x40 Modified: coreboot-v3/southbridge/intel/i82801gx/lpc.c =================================================================== --- coreboot-v3/southbridge/intel/i82801gx/lpc.c 2009-01-08 16:01:25 UTC (rev 1106) +++ coreboot-v3/southbridge/intel/i82801gx/lpc.c 2009-01-08 16:14:12 UTC (rev 1107) @@ -201,22 +201,7 @@ static void enable_hpet(struct device *dev) { - u32 reg32; - u32 code = (0 & 0x3); - - reg32 = pci_read_config32(dev, GEN_CNTL); - reg32 |= (1 << 17); /* Enable HPET. */ - /* - * Bits [16:15] Memory Address Range - * 00 FED0_0000h - FED0_03FFh - * 01 FED0_1000h - FED0_13FFh - * 10 FED0_2000h - FED0_23FFh - * 11 FED0_3000h - FED0_33FFh - */ - reg32 &= ~(3 << 15); /* Clear it */ - reg32 |= (code << 15); - /* TODO: reg32 is never written to anywhere? */ - printk(BIOS_DEBUG, "Enabling HPET @0x%x\n", HPET_ADDR | (code << 12)); + /* TODO */ } static void i82801gx_lock_smm(struct device *dev)

1 0

r1106 - coreboot-v3/northbridge/intel/i945
by svn＠coreboot.org 08 Jan '09

08 Jan '09

Author: uwe Date: 2009-01-08 17:01:25 +0100 (Thu, 08 Jan 2009) New Revision: 1106 Modified: coreboot-v3/northbridge/intel/i945/i945.h coreboot-v3/northbridge/intel/i945/raminit.c coreboot-v3/northbridge/intel/i945/rcven.c Log: Port relevant parts of r3741 from v2 to v3 (build-tested on v3): Merge some parts of the i945 review (trivial): * fix \r\n occurence in i945 code * drop early TOLUD write * fix 16bit BCTRL1 access Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Modified: coreboot-v3/northbridge/intel/i945/i945.h =================================================================== --- coreboot-v3/northbridge/intel/i945/i945.h 2009-01-08 15:44:56 UTC (rev 1105) +++ coreboot-v3/northbridge/intel/i945/i945.h 2009-01-08 16:01:25 UTC (rev 1106) @@ -67,7 +67,7 @@ /* Device 0:1.0 PCI configuration space (PCI Express) */ -#define BCTRL1 0x3e /* 8bit */ +#define BCTRL1 0x3e /* 16bit */ /* Device 0:2.0 PCI configuration space (Graphics Device) */ Modified: coreboot-v3/northbridge/intel/i945/raminit.c =================================================================== --- coreboot-v3/northbridge/intel/i945/raminit.c 2009-01-08 15:44:56 UTC (rev 1105) +++ coreboot-v3/northbridge/intel/i945/raminit.c 2009-01-08 16:01:25 UTC (rev 1106) @@ -1158,7 +1158,7 @@ static int i945_silicon_revision(void) { - return pci_conf1_read_config8(PCI_BDF(0, 0x00, 0), 8); + return pci_conf1_read_config8(PCI_BDF(0, 0x00, 0), PCI_CLASS_REVISION); } static void sdram_force_rcomp(void) @@ -1435,11 +1435,15 @@ tolud = (cum0 + cum1) << 1; else tolud = (cum1 ? cum1 : cum0) << 1; - pci_conf1_write_config16(PCI_BDF(0,0,0), TOLUD, tolud); - + + /* Some extra checks needed. See 4.1.26 in the + * 82945G MCH datasheet (30750203) + */ + pci_conf1_write_config8(PCI_BDF(0,0,0), TOLUD, tolud); + printk(BIOS_DEBUG, "C0DRB = 0x%08x\n", MCHBAR32(C0DRB0)); printk(BIOS_DEBUG, "C1DRB = 0x%08x\n", MCHBAR32(C1DRB0)); - printk(BIOS_DEBUG, "TOLUD = 0x%04x\n", tolud); + printk(BIOS_DEBUG, "TOLUD = 0x%02x\n", tolud); pci_conf1_write_config16(PCI_BDF(0,0,0), TOM, tolud>>3); @@ -2837,8 +2841,6 @@ pci_conf1_write_config8(PCI_BDF(0, 0x00, 0), PAM5, 0x33); pci_conf1_write_config8(PCI_BDF(0, 0x00, 0), PAM6, 0x33); - pci_conf1_write_config8(PCI_BDF(0, 0x00, 0), TOLUD, 0x40); /* 1G XXX dynamic! */ - pci_conf1_write_config32(PCI_BDF(0, 0x00, 0), SKPAD, 0xcafebabe); printk(BIOS_DEBUG, " done.\n"); @@ -3141,24 +3143,23 @@ u32 timeout; u32 reg32; u16 reg16; - u8 reg8; /* For now we just disable the x16 link */ printk(BIOS_DEBUG, "Disabling PCI Express x16 Link\n"); MCHBAR16(UPMC1) |= (1 << 5) | (1 << 0); - reg8 = pcie_read_config8(PCI_BDF(0, 0x01, 0), BCTRL1); - reg8 |= (1 << 6); - pcie_write_config8(PCI_BDF(0, 0x01, 0), BCTRL1, reg8); + reg16 = pcie_read_config16(PCI_BDF(0, 0x01, 0), BCTRL1); + reg16 |= (1 << 6); + pcie_write_config16(PCI_BDF(0, 0x01, 0), BCTRL1, reg16); reg32 = pcie_read_config32(PCI_BDF(0, 0x01, 0), 0x224); reg32 |= (1 << 8); pcie_write_config32(PCI_BDF(0, 0x01, 0), 0x224, reg32); - reg8 = pcie_read_config8(PCI_BDF(0, 0x01, 0), BCTRL1); - reg8 &= ~(1 << 6); - pcie_write_config8(PCI_BDF(0, 0x01, 0), BCTRL1, reg8); + reg16 = pcie_read_config16(PCI_BDF(0, 0x01, 0), BCTRL1); + reg16 &= ~(1 << 6); + pcie_write_config16(PCI_BDF(0, 0x01, 0), BCTRL1, reg16); printk(BIOS_DEBUG, "Wait for link to enter detect state... "); timeout = 0x7fffff; Modified: coreboot-v3/northbridge/intel/i945/rcven.c =================================================================== --- coreboot-v3/northbridge/intel/i945/rcven.c 2009-01-08 15:44:56 UTC (rev 1105) +++ coreboot-v3/northbridge/intel/i945/rcven.c 2009-01-08 16:01:25 UTC (rev 1106) @@ -82,7 +82,7 @@ { u32 reg32; - printk(BIOS_SPEW, " set_receive_enable() medium=0x%x, coarse=0x%x\r\n", medium, coarse); + printk(BIOS_SPEW, " set_receive_enable() medium=0x%x, coarse=0x%x\n", medium, coarse); reg32 = MCHBAR32(C0DRT1 + channel_offset); reg32 &= 0xf0ffffff; @@ -116,7 +116,7 @@ static int normalize(int channel_offset, u8 * mediumcoarse, u8 * fine) { - printk(BIOS_SPEW, " normalize()\r\n"); + printk(BIOS_SPEW, " normalize()\n"); if (*fine < 0x80) return 0; @@ -125,7 +125,7 @@ *mediumcoarse += 1; if (*mediumcoarse >= 0x40) { - printk(BIOS_DEBUG, "Normalize Error\r\n"); + printk(BIOS_DEBUG, "Normalize Error\n"); return -1; } @@ -143,12 +143,12 @@ /* find start of the data phase */ u32 reg32; - printk(BIOS_SPEW, " find_preamble()\r\n"); + printk(BIOS_SPEW, " find_preamble()\n"); do { if (*mediumcoarse < 4) { - printk(BIOS_DEBUG, "No Preamble found.\r\n"); + printk(BIOS_DEBUG, "No Preamble found.\n"); return -1; } *mediumcoarse -= 4; @@ -162,7 +162,7 @@ if (!(reg32 & (1 << 18))) { - printk(BIOS_DEBUG, "No Preamble found (neither high nor low).\r\n"); + printk(BIOS_DEBUG, "No Preamble found (neither high nor low).\n"); return -1; } @@ -175,14 +175,14 @@ static int add_quarter_clock(int channel_offset, u8 * mediumcoarse, u8 * fine) { - printk(BIOS_SPEW, " add_quarter_clock() mediumcoarse=%02x fine=%02x\r\n", + printk(BIOS_SPEW, " add_quarter_clock() mediumcoarse=%02x fine=%02x\n", *mediumcoarse, *fine); if (*fine >= 0x80) { *fine -= 0x80; *mediumcoarse += 2; if (*mediumcoarse >= 0x40) { - printk(BIOS_DEBUG, "clocks at max.\r\n"); + printk(BIOS_DEBUG, "clocks at max.\n"); return -1; } @@ -202,7 +202,7 @@ { u32 rcvenmt; - printk(BIOS_SPEW, " find_strobes_low()\r\n"); + printk(BIOS_SPEW, " find_strobes_low()\n"); for (;;) { MCHBAR8(C0WL0REOST + channel_offset) = *fine; @@ -228,7 +228,7 @@ } - printk(BIOS_DEBUG, "Could not find low strobe\r\n"); + printk(BIOS_DEBUG, "Could not find low strobe\n"); return 0; } @@ -238,7 +238,7 @@ int counter; u32 rcvenmt; - printk(BIOS_SPEW, " find_strobes_edge()\r\n"); + printk(BIOS_SPEW, " find_strobes_edge()\n"); counter = 8; set_receive_enable(channel_offset, *mediumcoarse & 3, @@ -273,7 +273,7 @@ continue; } - printk(BIOS_DEBUG, "could not find rising edge.\r\n"); + printk(BIOS_DEBUG, "could not find rising edge.\n"); return -1; } @@ -302,7 +302,7 @@ u8 mediumcoarse; u8 fine; - printk(BIOS_SPEW, "receive_enable_autoconfig() for channel %d\r\n", + printk(BIOS_SPEW, "receive_enable_autoconfig() for channel %d\n", channel_offset ? 1 : 0); /* Set initial values */

1 0

r1105 - coreboot-v3/northbridge/intel/i945
by svn＠coreboot.org 08 Jan '09

08 Jan '09

Author: uwe Date: 2009-01-08 16:44:56 +0100 (Thu, 08 Jan 2009) New Revision: 1105 Modified: coreboot-v3/northbridge/intel/i945/i945.h Log: Port r3738 from v2 to v3 (build-tested in v3): 945.h: Add some more comments, align data for better readability (trivial). Also, add missing C1DRA2 #define (as per public datasheet). Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Modified: coreboot-v3/northbridge/intel/i945/i945.h =================================================================== --- coreboot-v3/northbridge/intel/i945/i945.h 2009-01-07 18:37:21 UTC (rev 1104) +++ coreboot-v3/northbridge/intel/i945/i945.h 2009-01-08 15:44:56 UTC (rev 1105) @@ -31,15 +31,15 @@ #define X60BAR 0x60 /* Northbridge BARs */ -#define DEFAULT_PCIEXBAR 0xf0000000 +#define DEFAULT_PCIEXBAR 0xf0000000 /* 4 KB per PCIe device */ #define DEFAULT_X60BAR 0xfed13000 -#define DEFAULT_MCHBAR 0xfed14000 -#define DEFAULT_DMIBAR 0xfed18000 -#define DEFAULT_EPBAR 0xfed19000 +#define DEFAULT_MCHBAR 0xfed14000 /* 16 KB */ +#define DEFAULT_DMIBAR 0xfed18000 /* 4 KB */ +#define DEFAULT_EPBAR 0xfed19000 /* 4 KB */ -#define GGC 0x52 +#define GGC 0x52 /* GMCH Graphics Control */ -#define DEVEN 0x54 +#define DEVEN 0x54 /* Device Enable */ #define DEVEN_D0F0 (1 << 0) #define DEVEN_D1F0 (1 << 1) #define DEVEN_D2F0 (1 << 3) @@ -48,22 +48,22 @@ #define BOARD_DEVEN ( DEVEN_D0F0 | DEVEN_D2F0 | DEVEN_D2F1 ) #endif -#define PAM0 0x90 -#define PAM1 0x91 -#define PAM2 0x92 -#define PAM3 0x93 -#define PAM4 0x94 -#define PAM5 0x95 -#define PAM6 0x96 +#define PAM0 0x90 +#define PAM1 0x91 +#define PAM2 0x92 +#define PAM3 0x93 +#define PAM4 0x94 +#define PAM5 0x95 +#define PAM6 0x96 -#define LAC 0x97 /* Legacy Access Control */ -#define TOLUD 0x9c /* Top of Low Used Memory */ -#define SMRAM 0x9d -#define ESMRAM 0x9e +#define LAC 0x97 /* Legacy Access Control */ +#define TOLUD 0x9c /* Top of Low Used Memory */ +#define SMRAM 0x9d /* System Management RAM Control */ +#define ESMRAM 0x9e /* Extended System Management RAM Control */ -#define TOM 0xa0 +#define TOM 0xa0 -#define SKPAD 0xdc /* Scratchpad */ +#define SKPAD 0xdc /* Scratchpad Data */ /* Device 0:1.0 PCI configuration space (PCI Express) */ @@ -72,7 +72,7 @@ /* Device 0:2.0 PCI configuration space (Graphics Device) */ -#define GCFC 0xf0 /* Graphics Clock Frequency and Gating Control */ +#define GCFC 0xf0 /* Graphics Clock Frequency & Gating Control */ /* @@ -119,6 +119,7 @@ #define C1DRB2 0x182 /* 8bit */ #define C1DRB3 0x183 /* 8bit */ #define C1DRA0 0x188 /* 8bit */ +#define C1DRA2 0x189 /* 8bit */ #define C1DCLKDIS 0x18c /* 8bit */ #define C1BNKARC 0x18e /* 16bit */ #define C1DRT0 0x190 /* 32bit */ @@ -152,7 +153,7 @@ #define DQSMT 0x2f4 /* 16bit */ #define RCVENMT 0x2f8 /* 32bit */ -#define C0R0B00DQST 0x300 /* 64bit */ +#define C0R0B00DQST 0x300 /* 64bit */ #define C0WL0REOST 0x340 /* 8bit */ #define C0WL1REOST 0x341 /* 8bit */ @@ -162,7 +163,7 @@ #define C0WDLLCMC 0x36c /* 32bit */ #define C0HCTC 0x37c /* 8bit */ -#define C1R0B00DQST 0x380 /* 64bit */ +#define C1R0B00DQST 0x380 /* 64bit */ #define C1WL0REOST 0x3c0 /* 8bit */ #define C1WL1REOST 0x3c1 /* 8bit */

1 0

how to add some constant bytes into .rom file in coreboot v2 and v3?
by JasonZhao＠viatech.com.cn 08 Jan '09

08 Jan '09

To support VIA's ROMSIP I need to add the bellow constant into .rom file. How should I do to achieve this? The data I need add include: At ffffffd0, a 4byte pointer (pointto a address X (e.g. 0xffffff70)) At X, 32byte ROMSIP data Thank you! -jasonzhao

2 1

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coreboot January 2009